reg (reference) in projects: linux-4.4.14

Searched refs:reg (Results 1 – 200 of 7387) sorted by relevance

/linux-4.4.14/arch/mips/include/asm/
D	asm-eva.h	18 #define kernel_ll(reg, addr) "ll " reg ", " addr "\n" argument 19 #define kernel_sc(reg, addr) "sc " reg ", " addr "\n" argument 20 #define kernel_lw(reg, addr) "lw " reg ", " addr "\n" argument 21 #define kernel_lwl(reg, addr) "lwl " reg ", " addr "\n" argument 22 #define kernel_lwr(reg, addr) "lwr " reg ", " addr "\n" argument 23 #define kernel_lh(reg, addr) "lh " reg ", " addr "\n" argument 24 #define kernel_lb(reg, addr) "lb " reg ", " addr "\n" argument 25 #define kernel_lbu(reg, addr) "lbu " reg ", " addr "\n" argument 26 #define kernel_sw(reg, addr) "sw " reg ", " addr "\n" argument 27 #define kernel_swl(reg, addr) "swl " reg ", " addr "\n" argument [all …]
/linux-4.4.14/arch/parisc/include/asm/
D	asmregs.h	`24 rp: .reg %r2 25 arg3: .reg %r23 26 arg2: .reg %r24 27 arg1: .reg %r25 28 arg0: .reg %r26 29 dp: .reg %r27 30 ret0: .reg %r28 31 ret1: .reg %r29 32 sl: .reg %r29 33 sp: .reg %r30 [all …]`
/linux-4.4.14/drivers/gpu/drm/exynos/
D	exynos_dp_reg.c	29 u32 reg; in exynos_dp_enable_video_mute() local 32 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1); in exynos_dp_enable_video_mute() 33 reg \|= HDCP_VIDEO_MUTE; in exynos_dp_enable_video_mute() 34 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1); in exynos_dp_enable_video_mute() 36 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1); in exynos_dp_enable_video_mute() 37 reg &= ~HDCP_VIDEO_MUTE; in exynos_dp_enable_video_mute() 38 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1); in exynos_dp_enable_video_mute() 44 u32 reg; in exynos_dp_stop_video() local 46 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1); in exynos_dp_stop_video() 47 reg &= ~VIDEO_EN; in exynos_dp_stop_video() [all …]
D	exynos_drm_mic.c	98 void __iomem *reg; member 141 writel(MIC_SW_RST, mic->reg + MIC_OP); in mic_sw_reset() 144 ret = readl(mic->reg + MIC_OP); in mic_sw_reset() 157 u32 reg; in mic_set_porch_timing() local 159 reg = MIC_V_PULSE_WIDTH(vm.vsync_len) + in mic_set_porch_timing() 162 writel(reg, mic->reg + MIC_V_TIMING_0); in mic_set_porch_timing() 164 reg = MIC_VBP_SIZE(vm.vback_porch) + in mic_set_porch_timing() 166 writel(reg, mic->reg + MIC_V_TIMING_1); in mic_set_porch_timing() 168 reg = MIC_V_PULSE_WIDTH(vm.hsync_len) + in mic_set_porch_timing() 171 writel(reg, mic->reg + MIC_INPUT_TIMING_0); in mic_set_porch_timing() [all …]
/linux-4.4.14/drivers/media/platform/s5p-jpeg/
D	jpeg-hw-s5p.c	22 unsigned long reg; in s5p_jpeg_reset() local 25 reg = readl(regs + S5P_JPG_SW_RESET); in s5p_jpeg_reset() 27 while (reg != 0) { in s5p_jpeg_reset() 29 reg = readl(regs + S5P_JPG_SW_RESET); in s5p_jpeg_reset() 40 unsigned long reg, m; in s5p_jpeg_input_raw_mode() local 48 reg = readl(regs + S5P_JPGCMOD); in s5p_jpeg_input_raw_mode() 49 reg &= ~S5P_MOD_SEL_MASK; in s5p_jpeg_input_raw_mode() 50 reg \|= m; in s5p_jpeg_input_raw_mode() 51 writel(reg, regs + S5P_JPGCMOD); in s5p_jpeg_input_raw_mode() 56 unsigned long reg, m; in s5p_jpeg_proc_mode() local [all …]
D	jpeg-hw-exynos4.c	21 unsigned int reg; in exynos4_jpeg_sw_reset() local 23 reg = readl(base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_sw_reset() 24 writel(reg & ~EXYNOS4_SOFT_RESET_HI, base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_sw_reset() 28 writel(reg \| EXYNOS4_SOFT_RESET_HI, base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_sw_reset() 33 unsigned int reg; in exynos4_jpeg_set_enc_dec_mode() local 35 reg = readl(base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_set_enc_dec_mode() 38 writel((reg & EXYNOS4_ENC_DEC_MODE_MASK) \| in exynos4_jpeg_set_enc_dec_mode() 42 writel((reg & EXYNOS4_ENC_DEC_MODE_MASK) \| in exynos4_jpeg_set_enc_dec_mode() 51 unsigned int reg; in __exynos4_jpeg_set_img_fmt() local 63 reg = readl(base + EXYNOS4_IMG_FMT_REG) & in __exynos4_jpeg_set_img_fmt() [all …]
D	jpeg-hw-exynos3250.c	23 u32 reg = 1; in exynos3250_jpeg_reset() local 28 while (reg != 0 && --count > 0) { in exynos3250_jpeg_reset() 31 reg = readl(regs + EXYNOS3250_SW_RESET); in exynos3250_jpeg_reset() 34 reg = 0; in exynos3250_jpeg_reset() 37 while (reg != 1 && --count > 0) { in exynos3250_jpeg_reset() 41 reg = readl(regs + EXYNOS3250_JPGDRI); in exynos3250_jpeg_reset() 65 u32 reg; in exynos3250_jpeg_clk_set() local 67 reg = readl(base + EXYNOS3250_JPGCMOD) & ~EXYNOS3250_HALF_EN_MASK; in exynos3250_jpeg_clk_set() 69 writel(reg \| EXYNOS3250_HALF_EN, base + EXYNOS3250_JPGCMOD); in exynos3250_jpeg_clk_set() 74 u32 reg; in exynos3250_jpeg_input_raw_fmt() local [all …]
/linux-4.4.14/drivers/video/fbdev/exynos/
D	exynos_mipi_dsi_lowlevel.c	34 unsigned int reg; in exynos_mipi_dsi_func_reset() local 36 reg = readl(dsim->reg_base + EXYNOS_DSIM_SWRST); in exynos_mipi_dsi_func_reset() 38 reg \|= DSIM_FUNCRST; in exynos_mipi_dsi_func_reset() 40 writel(reg, dsim->reg_base + EXYNOS_DSIM_SWRST); in exynos_mipi_dsi_func_reset() 45 unsigned int reg; in exynos_mipi_dsi_sw_reset() local 47 reg = readl(dsim->reg_base + EXYNOS_DSIM_SWRST); in exynos_mipi_dsi_sw_reset() 49 reg \|= DSIM_SWRST; in exynos_mipi_dsi_sw_reset() 51 writel(reg, dsim->reg_base + EXYNOS_DSIM_SWRST); in exynos_mipi_dsi_sw_reset() 56 unsigned int reg; in exynos_mipi_dsi_sw_reset_release() local 58 reg = readl(dsim->reg_base + EXYNOS_DSIM_INTSRC); in exynos_mipi_dsi_sw_reset_release() [all …]
/linux-4.4.14/drivers/memory/tegra/
D	tegra210.c	`28 .reg = 0x228, 32 .reg = 0x2e8, 42 .reg = 0x228, 46 .reg = 0x2f4, 56 .reg = 0x228, 60 .reg = 0x2e8, 70 .reg = 0x228, 74 .reg = 0x2f4, 84 .reg = 0x228, 88 .reg = 0x2ec, [all …]`
D	tegra114.c	`26 .reg = 0x228, 30 .reg = 0x2e8, 40 .reg = 0x228, 44 .reg = 0x2f4, 54 .reg = 0x228, 58 .reg = 0x2e8, 68 .reg = 0x228, 72 .reg = 0x2f4, 82 .reg = 0x228, 86 .reg = 0x2ec, [all …]`
D	tegra124.c	`68 .reg = 0x228, 72 .reg = 0x2e8, 82 .reg = 0x228, 86 .reg = 0x2f4, 96 .reg = 0x228, 100 .reg = 0x2e8, 110 .reg = 0x228, 114 .reg = 0x2f4, 124 .reg = 0x228, 128 .reg = 0x2ec, [all …]`
D	tegra30.c	`26 .reg = 0x228, 30 .reg = 0x2e8, 40 .reg = 0x228, 44 .reg = 0x2f4, 54 .reg = 0x228, 58 .reg = 0x2e8, 68 .reg = 0x228, 72 .reg = 0x2f4, 82 .reg = 0x228, 86 .reg = 0x2ec, [all …]`
/linux-4.4.14/drivers/scsi/qla2xxx/
D	qla_dbg.c	121 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; in qla27xx_dump_mpi_ram() local 128 WRT_REG_WORD(&reg->mailbox0, MBC_LOAD_DUMP_MPI_RAM); in qla27xx_dump_mpi_ram() 137 WRT_REG_WORD(&reg->mailbox1, LSW(addr)); in qla27xx_dump_mpi_ram() 138 WRT_REG_WORD(&reg->mailbox8, MSW(addr)); in qla27xx_dump_mpi_ram() 140 WRT_REG_WORD(&reg->mailbox2, MSW(dump_dma)); in qla27xx_dump_mpi_ram() 141 WRT_REG_WORD(&reg->mailbox3, LSW(dump_dma)); in qla27xx_dump_mpi_ram() 142 WRT_REG_WORD(&reg->mailbox6, MSW(MSD(dump_dma))); in qla27xx_dump_mpi_ram() 143 WRT_REG_WORD(&reg->mailbox7, LSW(MSD(dump_dma))); in qla27xx_dump_mpi_ram() 145 WRT_REG_WORD(&reg->mailbox4, MSW(dwords)); in qla27xx_dump_mpi_ram() 146 WRT_REG_WORD(&reg->mailbox5, LSW(dwords)); in qla27xx_dump_mpi_ram() [all …]
/linux-4.4.14/arch/m32r/kernel/
D	entry.S	`84 #define R4(reg) @reg argument 85 #define R5(reg) @(0x04,reg) argument 86 #define R6(reg) @(0x08,reg) argument 87 #define PTREGS(reg) @(0x0C,reg) argument 88 #define R0(reg) @(0x10,reg) argument 89 #define R1(reg) @(0x14,reg) argument 90 #define R2(reg) @(0x18,reg) argument 91 #define R3(reg) @(0x1C,reg) argument 92 #define R7(reg) @(0x20,reg) argument 93 #define R8(reg) @(0x24,reg) argument [all …]`
/linux-4.4.14/drivers/video/fbdev/riva/
D	nvreg.h	44 #define DEVICE_ACCESS(device,reg) \ argument 45 nvCONTROL[(NV_##device##_##reg)/4] 47 #define DEVICE_WRITE(device,reg,value) DEVICE_ACCESS(device,reg)=(value) argument 48 #define DEVICE_READ(device,reg) DEVICE_ACCESS(device,reg) argument 49 #define DEVICE_PRINT(device,reg) \ argument 50 ErrorF("NV_"#device"_"#reg"=#%08lx\n",DEVICE_ACCESS(device,reg)) 56 #define PDAC_Write(reg,value) DEVICE_WRITE(PDAC,reg,value) argument 57 #define PDAC_Read(reg) DEVICE_READ(PDAC,reg) argument 58 #define PDAC_Print(reg) DEVICE_PRINT(PDAC,reg) argument 63 #define PFB_Write(reg,value) DEVICE_WRITE(PFB,reg,value) argument [all …]
/linux-4.4.14/drivers/media/pci/cx23885/
D	cx23885-ioctl.c	42 struct v4l2_dbg_register reg) in cx23417_g_register() argument 49 if ((reg->reg & 0x3) != 0 \|\| reg->reg >= 0x10000) in cx23417_g_register() 52 if (mc417_register_read(dev, (u16) reg->reg, &value)) in cx23417_g_register() 55 reg->size = 4; in cx23417_g_register() 56 reg->val = value; in cx23417_g_register() 61 struct v4l2_dbg_register reg) in cx23885_g_register() argument 65 if (reg->match.addr > 1) in cx23885_g_register() 67 if (reg->match.addr) in cx23885_g_register() 68 return cx23417_g_register(dev, reg); in cx23885_g_register() 70 if ((reg->reg & 0x3) != 0 \|\| reg->reg >= pci_resource_len(dev->pci, 0)) in cx23885_g_register() [all …]
/linux-4.4.14/drivers/net/ethernet/intel/ixgbe/
D	ixgbe_dcb_82598.c	46 u32 reg = 0; in ixgbe_dcb_config_rx_arbiter_82598() local 51 reg = IXGBE_READ_REG(hw, IXGBE_RUPPBMR) \| IXGBE_RUPPBMR_MQA; in ixgbe_dcb_config_rx_arbiter_82598() 52 IXGBE_WRITE_REG(hw, IXGBE_RUPPBMR, reg); in ixgbe_dcb_config_rx_arbiter_82598() 54 reg = IXGBE_READ_REG(hw, IXGBE_RMCS); in ixgbe_dcb_config_rx_arbiter_82598() 56 reg &= ~IXGBE_RMCS_ARBDIS; in ixgbe_dcb_config_rx_arbiter_82598() 58 reg \|= IXGBE_RMCS_RRM; in ixgbe_dcb_config_rx_arbiter_82598() 60 reg \|= IXGBE_RMCS_DFP; in ixgbe_dcb_config_rx_arbiter_82598() 62 IXGBE_WRITE_REG(hw, IXGBE_RMCS, reg); in ixgbe_dcb_config_rx_arbiter_82598() 69 reg = credit_refill \| (credit_max << IXGBE_RT2CR_MCL_SHIFT); in ixgbe_dcb_config_rx_arbiter_82598() 72 reg \|= IXGBE_RT2CR_LSP; in ixgbe_dcb_config_rx_arbiter_82598() [all …]
D	ixgbe_dcb_82599.c	51 u32 reg = 0; in ixgbe_dcb_config_rx_arbiter_82599() local 60 reg = IXGBE_RTRPCS_RRM \| IXGBE_RTRPCS_RAC \| IXGBE_RTRPCS_ARBDIS; in ixgbe_dcb_config_rx_arbiter_82599() 61 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg); in ixgbe_dcb_config_rx_arbiter_82599() 64 reg = 0; in ixgbe_dcb_config_rx_arbiter_82599() 66 reg \|= (prio_tc[i] << (i * IXGBE_RTRUP2TC_UP_SHIFT)); in ixgbe_dcb_config_rx_arbiter_82599() 67 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg); in ixgbe_dcb_config_rx_arbiter_82599() 73 reg = credit_refill \| (credit_max << IXGBE_RTRPT4C_MCL_SHIFT); in ixgbe_dcb_config_rx_arbiter_82599() 75 reg \|= (u32)(bwg_id[i]) << IXGBE_RTRPT4C_BWG_SHIFT; in ixgbe_dcb_config_rx_arbiter_82599() 78 reg \|= IXGBE_RTRPT4C_LSP; in ixgbe_dcb_config_rx_arbiter_82599() 80 IXGBE_WRITE_REG(hw, IXGBE_RTRPT4C(i), reg); in ixgbe_dcb_config_rx_arbiter_82599() [all …]
/linux-4.4.14/drivers/net/ethernet/microchip/
D	encx24j600-regmap.c	66 static int regmap_encx24j600_sfr_read(void context, u8 reg, u8 val, in regmap_encx24j600_sfr_read() argument 70 u8 banked_reg = reg & ADDR_MASK; in regmap_encx24j600_sfr_read() 71 u8 bank = ((reg & BANK_MASK) >> BANK_SHIFT); in regmap_encx24j600_sfr_read() 77 if (reg < 0x80) { in regmap_encx24j600_sfr_read() 87 switch (reg) { in regmap_encx24j600_sfr_read() 110 tx_buf[i++] = reg; in regmap_encx24j600_sfr_read() 118 u8 reg, u8 *val, size_t len, in regmap_encx24j600_sfr_update() argument 121 u8 banked_reg = reg & ADDR_MASK; in regmap_encx24j600_sfr_update() 122 u8 bank = ((reg & BANK_MASK) >> BANK_SHIFT); in regmap_encx24j600_sfr_update() 126 { .tx_buf = &reg, .len = sizeof(reg), }, in regmap_encx24j600_sfr_update() [all …]
/linux-4.4.14/arch/mips/include/asm/octeon/
D	cvmx-fau.h	129 static inline uint64_t __cvmx_fau_store_address(uint64_t noadd, uint64_t reg) in __cvmx_fau_store_address() argument 133 cvmx_build_bits(CVMX_FAU_BITS_REGISTER, reg); in __cvmx_fau_store_address() 152 static inline uint64_t __cvmx_fau_atomic_address(uint64_t tagwait, uint64_t reg, in __cvmx_fau_atomic_address() argument 158 cvmx_build_bits(CVMX_FAU_BITS_REGISTER, reg); in __cvmx_fau_atomic_address() 170 static inline int64_t cvmx_fau_fetch_and_add64(cvmx_fau_reg_64_t reg, in cvmx_fau_fetch_and_add64() argument 173 return cvmx_read64_int64(__cvmx_fau_atomic_address(0, reg, value)); in cvmx_fau_fetch_and_add64() 185 static inline int32_t cvmx_fau_fetch_and_add32(cvmx_fau_reg_32_t reg, in cvmx_fau_fetch_and_add32() argument 188 reg ^= SWIZZLE_32; in cvmx_fau_fetch_and_add32() 189 return cvmx_read64_int32(__cvmx_fau_atomic_address(0, reg, value)); in cvmx_fau_fetch_and_add32() 200 static inline int16_t cvmx_fau_fetch_and_add16(cvmx_fau_reg_16_t reg, in cvmx_fau_fetch_and_add16() argument [all …]
/linux-4.4.14/drivers/mfd/
D	tps65912-irq.c	45 u8 reg; in tps65912_irq() local 49 tps65912->read(tps65912, TPS65912_INT_STS, 1, &reg); in tps65912_irq() 50 irq_sts = reg; in tps65912_irq() 51 tps65912->read(tps65912, TPS65912_INT_STS2, 1, &reg); in tps65912_irq() 52 irq_sts \|= reg << 8; in tps65912_irq() 53 tps65912->read(tps65912, TPS65912_INT_STS3, 1, &reg); in tps65912_irq() 54 irq_sts \|= reg << 16; in tps65912_irq() 55 tps65912->read(tps65912, TPS65912_INT_STS4, 1, &reg); in tps65912_irq() 56 irq_sts \|= reg << 24; in tps65912_irq() 58 tps65912->read(tps65912, TPS65912_INT_MSK, 1, &reg); in tps65912_irq() [all …]
D	rtsx_pcr.h	61 #define rtsx_vendor_setting_valid(reg) (!((reg) & 0x1000000)) argument 62 #define rts5209_vendor_setting1_valid(reg) (!((reg) & 0x80)) argument 63 #define rts5209_vendor_setting2_valid(reg) ((reg) & 0x80) argument 65 #define rtsx_reg_to_aspm(reg) (((reg) >> 28) & 0x03) argument 66 #define rtsx_reg_to_sd30_drive_sel_1v8(reg) (((reg) >> 26) & 0x03) argument 67 #define rtsx_reg_to_sd30_drive_sel_3v3(reg) (((reg) >> 5) & 0x03) argument 68 #define rtsx_reg_to_card_drive_sel(reg) ((((reg) >> 25) & 0x01) << 6) argument 69 #define rtsx_reg_check_reverse_socket(reg) ((reg) & 0x4000) argument 70 #define rts5209_reg_to_aspm(reg) (((reg) >> 5) & 0x03) argument 71 #define rts5209_reg_check_ms_pmos(reg) (!((reg) & 0x08)) argument [all …]
D	wm8350-irq.c	`41 int reg; member 49 .reg = WM8350_OVER_CURRENT_INT_OFFSET, 55 .reg = WM8350_UNDER_VOLTAGE_INT_OFFSET, 60 .reg = WM8350_UNDER_VOLTAGE_INT_OFFSET, 65 .reg = WM8350_UNDER_VOLTAGE_INT_OFFSET, 70 .reg = WM8350_UNDER_VOLTAGE_INT_OFFSET, 75 .reg = WM8350_UNDER_VOLTAGE_INT_OFFSET, 80 .reg = WM8350_UNDER_VOLTAGE_INT_OFFSET, 85 .reg = WM8350_UNDER_VOLTAGE_INT_OFFSET, 90 .reg = WM8350_UNDER_VOLTAGE_INT_OFFSET, [all …]`
D	wm831x-irq.c	`32 int reg; member 39 .reg = 1, 44 .reg = 5, 49 .reg = 5, 54 .reg = 5, 59 .reg = 5, 64 .reg = 5, 69 .reg = 5, 74 .reg = 5, 79 .reg = 5, [all …]`
D	wm8350-gpio.c	52 u16 reg; in gpio_set_func() local 57 reg = wm8350_reg_read(wm8350, WM8350_GPIO_FUNCTION_SELECT_1) in gpio_set_func() 60 reg \| ((func & 0xf) << 0)); in gpio_set_func() 63 reg = wm8350_reg_read(wm8350, WM8350_GPIO_FUNCTION_SELECT_1) in gpio_set_func() 66 reg \| ((func & 0xf) << 4)); in gpio_set_func() 69 reg = wm8350_reg_read(wm8350, WM8350_GPIO_FUNCTION_SELECT_1) in gpio_set_func() 72 reg \| ((func & 0xf) << 8)); in gpio_set_func() 75 reg = wm8350_reg_read(wm8350, WM8350_GPIO_FUNCTION_SELECT_1) in gpio_set_func() 78 reg \| ((func & 0xf) << 12)); in gpio_set_func() 81 reg = wm8350_reg_read(wm8350, WM8350_GPIO_FUNCTION_SELECT_2) in gpio_set_func() [all …]
D	max77686.c	53 unsigned int reg) in max77802_pmic_is_accessible_reg() argument 55 return reg < MAX77802_REG_PMIC_END; in max77802_pmic_is_accessible_reg() 59 unsigned int reg) in max77802_rtc_is_accessible_reg() argument 61 return (reg >= MAX77802_RTC_INT && reg < MAX77802_RTC_END); in max77802_rtc_is_accessible_reg() 64 static bool max77802_is_accessible_reg(struct device dev, unsigned int reg) in max77802_is_accessible_reg() argument 66 return (max77802_pmic_is_accessible_reg(dev, reg) \|\| in max77802_is_accessible_reg() 67 max77802_rtc_is_accessible_reg(dev, reg)); in max77802_is_accessible_reg() 70 static bool max77802_pmic_is_precious_reg(struct device dev, unsigned int reg) in max77802_pmic_is_precious_reg() argument 72 return (reg == MAX77802_REG_INTSRC \|\| reg == MAX77802_REG_INT1 \|\| in max77802_pmic_is_precious_reg() 73 reg == MAX77802_REG_INT2); in max77802_pmic_is_precious_reg() [all …]
/linux-4.4.14/drivers/net/wireless/rt2x00/
D	rt2400pci.c	59 u32 reg; in rt2400pci_bbp_write() local 67 if (WAIT_FOR_BBP(rt2x00dev, &reg)) { in rt2400pci_bbp_write() 68 reg = 0; in rt2400pci_bbp_write() 69 rt2x00_set_field32(&reg, BBPCSR_VALUE, value); in rt2400pci_bbp_write() 70 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word); in rt2400pci_bbp_write() 71 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1); in rt2400pci_bbp_write() 72 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1); in rt2400pci_bbp_write() 74 rt2x00mmio_register_write(rt2x00dev, BBPCSR, reg); in rt2400pci_bbp_write() 83 u32 reg; in rt2400pci_bbp_read() local 95 if (WAIT_FOR_BBP(rt2x00dev, &reg)) { in rt2400pci_bbp_read() [all …]
D	rt2500pci.c	59 u32 reg; in rt2500pci_bbp_write() local 67 if (WAIT_FOR_BBP(rt2x00dev, &reg)) { in rt2500pci_bbp_write() 68 reg = 0; in rt2500pci_bbp_write() 69 rt2x00_set_field32(&reg, BBPCSR_VALUE, value); in rt2500pci_bbp_write() 70 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word); in rt2500pci_bbp_write() 71 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1); in rt2500pci_bbp_write() 72 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1); in rt2500pci_bbp_write() 74 rt2x00mmio_register_write(rt2x00dev, BBPCSR, reg); in rt2500pci_bbp_write() 83 u32 reg; in rt2500pci_bbp_read() local 95 if (WAIT_FOR_BBP(rt2x00dev, &reg)) { in rt2500pci_bbp_read() [all …]
D	rt61pci.c	68 u32 reg; in rt61pci_bbp_write() local 76 if (WAIT_FOR_BBP(rt2x00dev, &reg)) { in rt61pci_bbp_write() 77 reg = 0; in rt61pci_bbp_write() 78 rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value); in rt61pci_bbp_write() 79 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word); in rt61pci_bbp_write() 80 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1); in rt61pci_bbp_write() 81 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0); in rt61pci_bbp_write() 83 rt2x00mmio_register_write(rt2x00dev, PHY_CSR3, reg); in rt61pci_bbp_write() 92 u32 reg; in rt61pci_bbp_read() local 104 if (WAIT_FOR_BBP(rt2x00dev, &reg)) { in rt61pci_bbp_read() [all …]
D	rt2500usb.c	62 __le16 reg; in rt2500usb_register_read() local 65 &reg, sizeof(reg)); in rt2500usb_register_read() 66 value = le16_to_cpu(reg); in rt2500usb_register_read() 73 __le16 reg; in rt2500usb_register_read_lock() local 76 &reg, sizeof(reg), REGISTER_TIMEOUT); in rt2500usb_register_read_lock() 77 value = le16_to_cpu(reg); in rt2500usb_register_read_lock() 93 __le16 reg = cpu_to_le16(value); in rt2500usb_register_write() local 96 &reg, sizeof(reg)); in rt2500usb_register_write() 103 __le16 reg = cpu_to_le16(value); in rt2500usb_register_write_lock() local 106 &reg, sizeof(reg), REGISTER_TIMEOUT); in rt2500usb_register_write_lock() [all …]
D	rt73usb.c	66 u32 reg; in rt73usb_bbp_write() local 74 if (WAIT_FOR_BBP(rt2x00dev, &reg)) { in rt73usb_bbp_write() 75 reg = 0; in rt73usb_bbp_write() 76 rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value); in rt73usb_bbp_write() 77 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word); in rt73usb_bbp_write() 78 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1); in rt73usb_bbp_write() 79 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0); in rt73usb_bbp_write() 81 rt2x00usb_register_write_lock(rt2x00dev, PHY_CSR3, reg); in rt73usb_bbp_write() 90 u32 reg; in rt73usb_bbp_read() local 102 if (WAIT_FOR_BBP(rt2x00dev, &reg)) { in rt73usb_bbp_read() [all …]
D	rt2800lib.c	88 u32 reg; in rt2800_bbp_write() local 96 if (WAIT_FOR_BBP(rt2x00dev, &reg)) { in rt2800_bbp_write() 97 reg = 0; in rt2800_bbp_write() 98 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value); in rt2800_bbp_write() 99 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word); in rt2800_bbp_write() 100 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1); in rt2800_bbp_write() 101 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0); in rt2800_bbp_write() 102 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1); in rt2800_bbp_write() 104 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg); in rt2800_bbp_write() 113 u32 reg; in rt2800_bbp_read() local [all …]
D	rt2800mmio.c	327 u32 reg; in rt2800mmio_enable_interrupt() local 334 rt2x00mmio_register_read(rt2x00dev, INT_MASK_CSR, &reg); in rt2800mmio_enable_interrupt() 335 rt2x00_set_field32(&reg, irq_field, 1); in rt2800mmio_enable_interrupt() 336 rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg); in rt2800mmio_enable_interrupt() 367 u32 reg; in rt2800mmio_tbtt_tasklet() local 379 rt2x00mmio_register_read(rt2x00dev, BCN_TIME_CFG, &reg); in rt2800mmio_tbtt_tasklet() 380 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, in rt2800mmio_tbtt_tasklet() 382 rt2x00mmio_register_write(rt2x00dev, BCN_TIME_CFG, reg); in rt2800mmio_tbtt_tasklet() 384 rt2x00mmio_register_read(rt2x00dev, BCN_TIME_CFG, &reg); in rt2800mmio_tbtt_tasklet() 385 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, in rt2800mmio_tbtt_tasklet() [all …]
/linux-4.4.14/drivers/net/ethernet/sfc/
D	io.h	83 unsigned int reg) in _efx_writeq() argument 85 __raw_writeq((__force u64)value, efx->membase + reg); in _efx_writeq() 87 static inline __le64 _efx_readq(struct efx_nic efx, unsigned int reg) in _efx_readq() argument 89 return (__force __le64)__raw_readq(efx->membase + reg); in _efx_readq() 94 unsigned int reg) in _efx_writed() argument 96 __raw_writel((__force u32)value, efx->membase + reg); in _efx_writed() 98 static inline __le32 _efx_readd(struct efx_nic efx, unsigned int reg) in _efx_readd() argument 100 return (__force __le32)__raw_readl(efx->membase + reg); in _efx_readd() 105 unsigned int reg) in efx_writeo() argument 110 "writing register %x with " EFX_OWORD_FMT "\n", reg, in efx_writeo() [all …]
/linux-4.4.14/drivers/clk/
D	clk-highbank.c	51 void __iomem *reg; member 59 u32 reg; in clk_pll_prepare() local 61 reg = readl(hbclk->reg); in clk_pll_prepare() 62 reg &= ~HB_PLL_RESET; in clk_pll_prepare() 63 writel(reg, hbclk->reg); in clk_pll_prepare() 65 while ((readl(hbclk->reg) & HB_PLL_LOCK) == 0) in clk_pll_prepare() 67 while ((readl(hbclk->reg) & HB_PLL_LOCK_500) == 0) in clk_pll_prepare() 76 u32 reg; in clk_pll_unprepare() local 78 reg = readl(hbclk->reg); in clk_pll_unprepare() 79 reg \|= HB_PLL_RESET; in clk_pll_unprepare() [all …]
/linux-4.4.14/arch/ia64/include/asm/native/
D	inst.h	`25 #define MOV_FROM_IFA(reg) \ argument 26 mov reg = cr.ifa 28 #define MOV_FROM_ITIR(reg) \ argument 29 mov reg = cr.itir 31 #define MOV_FROM_ISR(reg) \ argument 32 mov reg = cr.isr 34 #define MOV_FROM_IHA(reg) \ argument 35 mov reg = cr.iha 37 #define MOV_FROM_IPSR(pred, reg) \ argument 38 (pred) mov reg = cr.ipsr [all …]`
/linux-4.4.14/sound/hda/
D	hdac_regmap.c	32 #define get_verb(reg) (((reg) >> 8) & 0xfff) argument 34 static bool hda_volatile_reg(struct device dev, unsigned int reg) in hda_volatile_reg() argument 37 unsigned int verb = get_verb(reg); in hda_volatile_reg() 61 static bool hda_writeable_reg(struct device dev, unsigned int reg) in hda_writeable_reg() argument 64 unsigned int verb = get_verb(reg); in hda_writeable_reg() 110 static bool hda_readable_reg(struct device *dev, unsigned int reg) in hda_readable_reg() argument 113 unsigned int verb = get_verb(reg); in hda_readable_reg() 132 return hda_writeable_reg(dev, reg); in hda_readable_reg() 143 static bool is_stereo_amp_verb(unsigned int reg) in is_stereo_amp_verb() argument 145 if (((reg >> 8) & 0x700) != AC_VERB_SET_AMP_GAIN_MUTE) in is_stereo_amp_verb() [all …]
/linux-4.4.14/drivers/staging/rtl8188eu/hal/
D	bb_cfg.c	597 struct bb_reg_def *reg[4]; in rtl88e_phy_init_bb_rf_register_definition() local 599 reg[RF_PATH_A] = &hal_data->PHYRegDef[RF_PATH_A]; in rtl88e_phy_init_bb_rf_register_definition() 600 reg[RF_PATH_B] = &hal_data->PHYRegDef[RF_PATH_B]; in rtl88e_phy_init_bb_rf_register_definition() 601 reg[RF_PATH_C] = &hal_data->PHYRegDef[RF_PATH_C]; in rtl88e_phy_init_bb_rf_register_definition() 602 reg[RF_PATH_D] = &hal_data->PHYRegDef[RF_PATH_D]; in rtl88e_phy_init_bb_rf_register_definition() 604 reg[RF_PATH_A]->rfintfs = rFPGA0_XAB_RFInterfaceSW; in rtl88e_phy_init_bb_rf_register_definition() 605 reg[RF_PATH_B]->rfintfs = rFPGA0_XAB_RFInterfaceSW; in rtl88e_phy_init_bb_rf_register_definition() 606 reg[RF_PATH_C]->rfintfs = rFPGA0_XCD_RFInterfaceSW; in rtl88e_phy_init_bb_rf_register_definition() 607 reg[RF_PATH_D]->rfintfs = rFPGA0_XCD_RFInterfaceSW; in rtl88e_phy_init_bb_rf_register_definition() 609 reg[RF_PATH_A]->rfintfi = rFPGA0_XAB_RFInterfaceRB; in rtl88e_phy_init_bb_rf_register_definition() [all …]
/linux-4.4.14/include/video/
D	vga.h	212 static inline void vga_io_w_fast (unsigned short port, unsigned char reg, in vga_io_w_fast() argument 215 outw(VGA_OUT16VAL (val, reg), port); in vga_io_w_fast() 229 unsigned char reg, unsigned char val) in vga_mm_w_fast() argument 231 writew (VGA_OUT16VAL (val, reg), regbase + port); in vga_mm_w_fast() 252 unsigned char reg, unsigned char val) in vga_w_fast() argument 255 vga_mm_w_fast (regbase, port, reg, val); in vga_w_fast() 257 vga_io_w_fast (port, reg, val); in vga_w_fast() 265 static inline unsigned char vga_rcrt (void __iomem regbase, unsigned char reg) in vga_rcrt() argument 267 vga_w (regbase, VGA_CRT_IC, reg); in vga_rcrt() 271 static inline void vga_wcrt (void __iomem regbase, unsigned char reg, unsigned char val) in vga_wcrt() argument [all …]
/linux-4.4.14/fs/ocfs2/cluster/
D	heartbeat.c	291 struct o2hb_region reg = in o2hb_write_timeout() local 296 "milliseconds\n", reg->hr_dev_name, in o2hb_write_timeout() 297 jiffies_to_msecs(jiffies - reg->hr_last_timeout_start)); in o2hb_write_timeout() 301 if (test_bit(reg->hr_region_num, o2hb_quorum_region_bitmap)) in o2hb_write_timeout() 302 set_bit(reg->hr_region_num, o2hb_failed_region_bitmap); in o2hb_write_timeout() 323 static void o2hb_arm_write_timeout(struct o2hb_region reg) in o2hb_arm_write_timeout() argument 326 if (atomic_read(&reg->hr_steady_iterations) != 0) in o2hb_arm_write_timeout() 334 clear_bit(reg->hr_region_num, o2hb_failed_region_bitmap); in o2hb_arm_write_timeout() 337 cancel_delayed_work(&reg->hr_write_timeout_work); in o2hb_arm_write_timeout() 338 reg->hr_last_timeout_start = jiffies; in o2hb_arm_write_timeout() [all …]
/linux-4.4.14/drivers/net/ethernet/intel/e1000/
D	e1000_osdep.h	54 #define er32(reg) \ argument 56 ? E1000_##reg : E1000_82542_##reg))) 58 #define ew32(reg, value) \ argument 60 ? E1000_##reg : E1000_82542_##reg)))) 62 #define E1000_WRITE_REG_ARRAY(a, reg, offset, value) ( \ argument 64 (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \ 67 #define E1000_READ_REG_ARRAY(a, reg, offset) ( \ argument 69 (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \ 75 #define E1000_WRITE_REG_ARRAY_WORD(a, reg, offset, value) ( \ argument 77 (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \ [all …]
/linux-4.4.14/drivers/net/ethernet/mellanox/mlxsw/
D	reg.h	74 MLXSW_ITEM32(reg, sgcr, llb, 0x04, 0, 1); 100 MLXSW_ITEM_BUF(reg, spad, base_mac, 0x02, 6); 124 MLXSW_ITEM32(reg, sspr, m, 0x00, 31, 1); 131 MLXSW_ITEM32(reg, sspr, local_port, 0x00, 16, 8); 139 MLXSW_ITEM32(reg, sspr, sub_port, 0x00, 8, 8); 149 MLXSW_ITEM32(reg, sspr, system_port, 0x04, 0, 16); 177 MLXSW_ITEM32(reg, sfdat, swid, 0x00, 24, 8); 186 MLXSW_ITEM32(reg, sfdat, age_time, 0x04, 0, 20); 218 MLXSW_ITEM32(reg, sfd, swid, 0x00, 24, 8); 252 MLXSW_ITEM32(reg, sfd, op, 0x04, 30, 2); [all …]
/linux-4.4.14/drivers/net/wireless/ath/
D	regd.c	26 static int __ath_regd_init(struct ath_regulatory reg); 117 static bool dynamic_country_user_possible(struct ath_regulatory reg) in dynamic_country_user_possible() argument 122 switch (reg->country_code) { in dynamic_country_user_possible() 189 static bool ath_reg_dyn_country_user_allow(struct ath_regulatory reg) in ath_reg_dyn_country_user_allow() argument 193 if (!dynamic_country_user_possible(reg)) in ath_reg_dyn_country_user_allow() 205 static u16 ath_regd_get_eepromRD(struct ath_regulatory reg) in ath_regd_get_eepromRD() argument 207 return reg->current_rd & ~WORLDWIDE_ROAMING_FLAG; in ath_regd_get_eepromRD() 210 bool ath_is_world_regd(struct ath_regulatory reg) in ath_is_world_regd() argument 212 return is_wwr_sku(ath_regd_get_eepromRD(reg)); in ath_is_world_regd() 223 ieee80211_regdomain ath_world_regdomain(struct ath_regulatory *reg) in ath_world_regdomain() argument [all …]
/linux-4.4.14/drivers/scsi/
D	dtc.h	34 #define DTC_address(reg) (base + DTC_5380_OFFSET + reg) argument 36 #define dbNCR5380_read(reg) \ argument 37 (rval=readb(DTC_address(reg)), \ 39 , (reg), DTC_address(reg), rval)), rval ) ) 41 #define dbNCR5380_write(reg, value) do { \ argument 43 (value), (reg), DTC_address(reg)); \ 44 writeb(value, DTC_address(reg));} while(0) 48 #define NCR5380_read(reg) (readb(DTC_address(reg))) argument 49 #define NCR5380_write(reg, value) (writeb(value, DTC_address(reg))) argument 51 #define NCR5380_read(reg) (readb(DTC_address(reg))) argument [all …]
D	t128.h	`93 #define T128_address(reg) (base + T_5380_OFFSET + ((reg) * 0x20)) argument 96 #define NCR5380_read(reg) readb(T128_address(reg)) argument 97 #define NCR5380_write(reg, value) writeb((value),(T128_address(reg))) argument 99 #define NCR5380_read(reg) \ argument 101 , instance->hostno, (reg), T128_address(reg))), readb(T128_address(reg))) 103 #define NCR5380_write(reg, value) { \ argument 105 instance->hostno, (value), (reg), T128_address(reg)); \ 106 writeb((value), (T128_address(reg))); \`
D	nsp32_io.h	119 unsigned int reg) in nsp32_index_read1() argument 121 outb(reg, base + INDEX_REG); in nsp32_index_read1() 126 unsigned int reg, in nsp32_index_write1() argument 129 outb(reg, base + INDEX_REG ); in nsp32_index_write1() 134 unsigned int reg) in nsp32_index_read2() argument 136 outb(reg, base + INDEX_REG); in nsp32_index_read2() 141 unsigned int reg, in nsp32_index_write2() argument 144 outb(reg, base + INDEX_REG ); in nsp32_index_write2() 149 unsigned int reg) in nsp32_index_read4() argument 153 outb(reg, base + INDEX_REG); in nsp32_index_read4() [all …]
/linux-4.4.14/arch/cris/include/arch-v32/arch/hwregs/
D	marb_defs.h	`18 #define REG_RD( scope, inst, reg ) \ argument 19 REG_READ( reg_##scope##_##reg, \ 20 (inst) + REG_RD_ADDR_##scope##_##reg ) 24 #define REG_WR( scope, inst, reg, val ) \ argument 25 REG_WRITE( reg_##scope##_##reg, \ 26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) 30 #define REG_RD_VECT( scope, inst, reg, index ) \ argument 31 REG_READ( reg_##scope##_##reg, \ 32 (inst) + REG_RD_ADDR_##scope##_##reg + \ 33 (index) * STRIDE_##scope##_##reg ) [all …]`
D	irq_nmi_defs.h	`18 #define REG_RD( scope, inst, reg ) \ argument 19 REG_READ( reg_##scope##_##reg, \ 20 (inst) + REG_RD_ADDR_##scope##_##reg ) 24 #define REG_WR( scope, inst, reg, val ) \ argument 25 REG_WRITE( reg_##scope##_##reg, \ 26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) 30 #define REG_RD_VECT( scope, inst, reg, index ) \ argument 31 REG_READ( reg_##scope##_##reg, \ 32 (inst) + REG_RD_ADDR_##scope##_##reg + \ 33 (index) * STRIDE_##scope##_##reg ) [all …]`
D	strcop_defs.h	`18 #define REG_RD( scope, inst, reg ) \ argument 19 REG_READ( reg_##scope##_##reg, \ 20 (inst) + REG_RD_ADDR_##scope##_##reg ) 24 #define REG_WR( scope, inst, reg, val ) \ argument 25 REG_WRITE( reg_##scope##_##reg, \ 26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) 30 #define REG_RD_VECT( scope, inst, reg, index ) \ argument 31 REG_READ( reg_##scope##_##reg, \ 32 (inst) + REG_RD_ADDR_##scope##_##reg + \ 33 (index) * STRIDE_##scope##_##reg ) [all …]`
D	config_defs.h	`18 #define REG_RD( scope, inst, reg ) \ argument 19 REG_READ( reg_##scope##_##reg, \ 20 (inst) + REG_RD_ADDR_##scope##_##reg ) 24 #define REG_WR( scope, inst, reg, val ) \ argument 25 REG_WRITE( reg_##scope##_##reg, \ 26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) 30 #define REG_RD_VECT( scope, inst, reg, index ) \ argument 31 REG_READ( reg_##scope##_##reg, \ 32 (inst) + REG_RD_ADDR_##scope##_##reg + \ 33 (index) * STRIDE_##scope##_##reg ) [all …]`
D	rt_trace_defs.h	`18 #define REG_RD( scope, inst, reg ) \ argument 19 REG_READ( reg_##scope##_##reg, \ 20 (inst) + REG_RD_ADDR_##scope##_##reg ) 24 #define REG_WR( scope, inst, reg, val ) \ argument 25 REG_WRITE( reg_##scope##_##reg, \ 26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) 30 #define REG_RD_VECT( scope, inst, reg, index ) \ argument 31 REG_READ( reg_##scope##_##reg, \ 32 (inst) + REG_RD_ADDR_##scope##_##reg + \ 33 (index) * STRIDE_##scope##_##reg ) [all …]`
D	ata_defs.h	`18 #define REG_RD( scope, inst, reg ) \ argument 19 REG_READ( reg_##scope##_##reg, \ 20 (inst) + REG_RD_ADDR_##scope##_##reg ) 24 #define REG_WR( scope, inst, reg, val ) \ argument 25 REG_WRITE( reg_##scope##_##reg, \ 26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) 30 #define REG_RD_VECT( scope, inst, reg, index ) \ argument 31 REG_READ( reg_##scope##_##reg, \ 32 (inst) + REG_RD_ADDR_##scope##_##reg + \ 33 (index) * STRIDE_##scope##_##reg ) [all …]`
D	bif_slave_defs.h	`18 #define REG_RD( scope, inst, reg ) \ argument 19 REG_READ( reg_##scope##_##reg, \ 20 (inst) + REG_RD_ADDR_##scope##_##reg ) 24 #define REG_WR( scope, inst, reg, val ) \ argument 25 REG_WRITE( reg_##scope##_##reg, \ 26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) 30 #define REG_RD_VECT( scope, inst, reg, index ) \ argument 31 REG_READ( reg_##scope##_##reg, \ 32 (inst) + REG_RD_ADDR_##scope##_##reg + \ 33 (index) * STRIDE_##scope##_##reg ) [all …]`
D	marb_bp_defs.h	`18 #define REG_RD( scope, inst, reg ) \ argument 19 REG_READ( reg_##scope##_##reg, \ 20 (inst) + REG_RD_ADDR_##scope##_##reg ) 24 #define REG_WR( scope, inst, reg, val ) \ argument 25 REG_WRITE( reg_##scope##_##reg, \ 26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) 30 #define REG_RD_VECT( scope, inst, reg, index ) \ argument 31 REG_READ( reg_##scope##_##reg, \ 32 (inst) + REG_RD_ADDR_##scope##_##reg + \ 33 (index) * STRIDE_##scope##_##reg ) [all …]`
D	ser_defs.h	`18 #define REG_RD( scope, inst, reg ) \ argument 19 REG_READ( reg_##scope##_##reg, \ 20 (inst) + REG_RD_ADDR_##scope##_##reg ) 24 #define REG_WR( scope, inst, reg, val ) \ argument 25 REG_WRITE( reg_##scope##_##reg, \ 26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) 30 #define REG_RD_VECT( scope, inst, reg, index ) \ argument 31 REG_READ( reg_##scope##_##reg, \ 32 (inst) + REG_RD_ADDR_##scope##_##reg + \ 33 (index) * STRIDE_##scope##_##reg ) [all …]`
D	bif_core_defs.h	`18 #define REG_RD( scope, inst, reg ) \ argument 19 REG_READ( reg_##scope##_##reg, \ 20 (inst) + REG_RD_ADDR_##scope##_##reg ) 24 #define REG_WR( scope, inst, reg, val ) \ argument 25 REG_WRITE( reg_##scope##_##reg, \ 26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) 30 #define REG_RD_VECT( scope, inst, reg, index ) \ argument 31 REG_READ( reg_##scope##_##reg, \ 32 (inst) + REG_RD_ADDR_##scope##_##reg + \ 33 (index) * STRIDE_##scope##_##reg ) [all …]`
D	eth_defs.h	`18 #define REG_RD( scope, inst, reg ) \ argument 19 REG_READ( reg_##scope##_##reg, \ 20 (inst) + REG_RD_ADDR_##scope##_##reg ) 24 #define REG_WR( scope, inst, reg, val ) \ argument 25 REG_WRITE( reg_##scope##_##reg, \ 26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) 30 #define REG_RD_VECT( scope, inst, reg, index ) \ argument 31 REG_READ( reg_##scope##_##reg, \ 32 (inst) + REG_RD_ADDR_##scope##_##reg + \ 33 (index) * STRIDE_##scope##_##reg ) [all …]`
D	sser_defs.h	`18 #define REG_RD( scope, inst, reg ) \ argument 19 REG_READ( reg_##scope##_##reg, \ 20 (inst) + REG_RD_ADDR_##scope##_##reg ) 24 #define REG_WR( scope, inst, reg, val ) \ argument 25 REG_WRITE( reg_##scope##_##reg, \ 26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) 30 #define REG_RD_VECT( scope, inst, reg, index ) \ argument 31 REG_READ( reg_##scope##_##reg, \ 32 (inst) + REG_RD_ADDR_##scope##_##reg + \ 33 (index) * STRIDE_##scope##_##reg ) [all …]`
D	dma_defs.h	`18 #define REG_RD( scope, inst, reg ) \ argument 19 REG_READ( reg_##scope##_##reg, \ 20 (inst) + REG_RD_ADDR_##scope##_##reg ) 24 #define REG_WR( scope, inst, reg, val ) \ argument 25 REG_WRITE( reg_##scope##_##reg, \ 26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) 30 #define REG_RD_VECT( scope, inst, reg, index ) \ argument 31 REG_READ( reg_##scope##_##reg, \ 32 (inst) + REG_RD_ADDR_##scope##_##reg + \ 33 (index) * STRIDE_##scope##_##reg ) [all …]`
D	extmem_defs.h	`18 #define REG_RD( scope, inst, reg ) \ argument 19 REG_READ( reg_##scope##_##reg, \ 20 (inst) + REG_RD_ADDR_##scope##_##reg ) 24 #define REG_WR( scope, inst, reg, val ) \ argument 25 REG_WRITE( reg_##scope##_##reg, \ 26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) 30 #define REG_RD_VECT( scope, inst, reg, index ) \ argument 31 REG_READ( reg_##scope##_##reg, \ 32 (inst) + REG_RD_ADDR_##scope##_##reg + \ 33 (index) * STRIDE_##scope##_##reg ) [all …]`
/linux-4.4.14/arch/cris/include/arch-v32/mach-fs/mach/hwregs/
D	marb_defs.h	`18 #define REG_RD( scope, inst, reg ) \ argument 19 REG_READ( reg_##scope##_##reg, \ 20 (inst) + REG_RD_ADDR_##scope##_##reg ) 24 #define REG_WR( scope, inst, reg, val ) \ argument 25 REG_WRITE( reg_##scope##_##reg, \ 26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) 30 #define REG_RD_VECT( scope, inst, reg, index ) \ argument 31 REG_READ( reg_##scope##_##reg, \ 32 (inst) + REG_RD_ADDR_##scope##_##reg + \ 33 (index) * STRIDE_##scope##_##reg ) [all …]`
D	strmux_defs.h	`18 #define REG_RD( scope, inst, reg ) \ argument 19 REG_READ( reg_##scope##_##reg, \ 20 (inst) + REG_RD_ADDR_##scope##_##reg ) 24 #define REG_WR( scope, inst, reg, val ) \ argument 25 REG_WRITE( reg_##scope##_##reg, \ 26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) 30 #define REG_RD_VECT( scope, inst, reg, index ) \ argument 31 REG_READ( reg_##scope##_##reg, \ 32 (inst) + REG_RD_ADDR_##scope##_##reg + \ 33 (index) * STRIDE_##scope##_##reg ) [all …]`
D	config_defs.h	`18 #define REG_RD( scope, inst, reg ) \ argument 19 REG_READ( reg_##scope##_##reg, \ 20 (inst) + REG_RD_ADDR_##scope##_##reg ) 24 #define REG_WR( scope, inst, reg, val ) \ argument 25 REG_WRITE( reg_##scope##_##reg, \ 26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) 30 #define REG_RD_VECT( scope, inst, reg, index ) \ argument 31 REG_READ( reg_##scope##_##reg, \ 32 (inst) + REG_RD_ADDR_##scope##_##reg + \ 33 (index) * STRIDE_##scope##_##reg ) [all …]`
D	timer_defs.h	`18 #define REG_RD( scope, inst, reg ) \ argument 19 REG_READ( reg_##scope##_##reg, \ 20 (inst) + REG_RD_ADDR_##scope##_##reg ) 24 #define REG_WR( scope, inst, reg, val ) \ argument 25 REG_WRITE( reg_##scope##_##reg, \ 26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) 30 #define REG_RD_VECT( scope, inst, reg, index ) \ argument 31 REG_READ( reg_##scope##_##reg, \ 32 (inst) + REG_RD_ADDR_##scope##_##reg + \ 33 (index) * STRIDE_##scope##_##reg ) [all …]`
D	intr_vect_defs.h	`18 #define REG_RD( scope, inst, reg ) \ argument 19 REG_READ( reg_##scope##_##reg, \ 20 (inst) + REG_RD_ADDR_##scope##_##reg ) 24 #define REG_WR( scope, inst, reg, val ) \ argument 25 REG_WRITE( reg_##scope##_##reg, \ 26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) 30 #define REG_RD_VECT( scope, inst, reg, index ) \ argument 31 REG_READ( reg_##scope##_##reg, \ 32 (inst) + REG_RD_ADDR_##scope##_##reg + \ 33 (index) * STRIDE_##scope##_##reg ) [all …]`
D	bif_slave_defs.h	`18 #define REG_RD( scope, inst, reg ) \ argument 19 REG_READ( reg_##scope##_##reg, \ 20 (inst) + REG_RD_ADDR_##scope##_##reg ) 24 #define REG_WR( scope, inst, reg, val ) \ argument 25 REG_WRITE( reg_##scope##_##reg, \ 26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) 30 #define REG_RD_VECT( scope, inst, reg, index ) \ argument 31 REG_READ( reg_##scope##_##reg, \ 32 (inst) + REG_RD_ADDR_##scope##_##reg + \ 33 (index) * STRIDE_##scope##_##reg ) [all …]`
D	gio_defs.h	`18 #define REG_RD( scope, inst, reg ) \ argument 19 REG_READ( reg_##scope##_##reg, \ 20 (inst) + REG_RD_ADDR_##scope##_##reg ) 24 #define REG_WR( scope, inst, reg, val ) \ argument 25 REG_WRITE( reg_##scope##_##reg, \ 26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) 30 #define REG_RD_VECT( scope, inst, reg, index ) \ argument 31 REG_READ( reg_##scope##_##reg, \ 32 (inst) + REG_RD_ADDR_##scope##_##reg + \ 33 (index) * STRIDE_##scope##_##reg ) [all …]`
D	marb_bp_defs.h	`18 #define REG_RD( scope, inst, reg ) \ argument 19 REG_READ( reg_##scope##_##reg, \ 20 (inst) + REG_RD_ADDR_##scope##_##reg ) 24 #define REG_WR( scope, inst, reg, val ) \ argument 25 REG_WRITE( reg_##scope##_##reg, \ 26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) 30 #define REG_RD_VECT( scope, inst, reg, index ) \ argument 31 REG_READ( reg_##scope##_##reg, \ 32 (inst) + REG_RD_ADDR_##scope##_##reg + \ 33 (index) * STRIDE_##scope##_##reg ) [all …]`
D	bif_core_defs.h	`18 #define REG_RD( scope, inst, reg ) \ argument 19 REG_READ( reg_##scope##_##reg, \ 20 (inst) + REG_RD_ADDR_##scope##_##reg ) 24 #define REG_WR( scope, inst, reg, val ) \ argument 25 REG_WRITE( reg_##scope##_##reg, \ 26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) 30 #define REG_RD_VECT( scope, inst, reg, index ) \ argument 31 REG_READ( reg_##scope##_##reg, \ 32 (inst) + REG_RD_ADDR_##scope##_##reg + \ 33 (index) * STRIDE_##scope##_##reg ) [all …]`
D	pinmux_defs.h	`18 #define REG_RD( scope, inst, reg ) \ argument 19 REG_READ( reg_##scope##_##reg, \ 20 (inst) + REG_RD_ADDR_##scope##_##reg ) 24 #define REG_WR( scope, inst, reg, val ) \ argument 25 REG_WRITE( reg_##scope##_##reg, \ 26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) 30 #define REG_RD_VECT( scope, inst, reg, index ) \ argument 31 REG_READ( reg_##scope##_##reg, \ 32 (inst) + REG_RD_ADDR_##scope##_##reg + \ 33 (index) * STRIDE_##scope##_##reg ) [all …]`
/linux-4.4.14/arch/cris/include/arch-v32/mach-a3/mach/hwregs/
D	marb_bar_defs.h	`15 #define REG_RD( scope, inst, reg ) \ argument 16 REG_READ( reg_##scope##_##reg, \ 17 (inst) + REG_RD_ADDR_##scope##_##reg ) 21 #define REG_WR( scope, inst, reg, val ) \ argument 22 REG_WRITE( reg_##scope##_##reg, \ 23 (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) 27 #define REG_RD_VECT( scope, inst, reg, index ) \ argument 28 REG_READ( reg_##scope##_##reg, \ 29 (inst) + REG_RD_ADDR_##scope##_##reg + \ 30 (index) * STRIDE_##scope##_##reg ) [all …]`
D	strmux_defs.h	`15 #define REG_RD( scope, inst, reg ) \ argument 16 REG_READ( reg_##scope##_##reg, \ 17 (inst) + REG_RD_ADDR_##scope##_##reg ) 21 #define REG_WR( scope, inst, reg, val ) \ argument 22 REG_WRITE( reg_##scope##_##reg, \ 23 (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) 27 #define REG_RD_VECT( scope, inst, reg, index ) \ argument 28 REG_READ( reg_##scope##_##reg, \ 29 (inst) + REG_RD_ADDR_##scope##_##reg + \ 30 (index) * STRIDE_##scope##_##reg ) [all …]`
D	l2cache_defs.h	`15 #define REG_RD( scope, inst, reg ) \ argument 16 REG_READ( reg_##scope##_##reg, \ 17 (inst) + REG_RD_ADDR_##scope##_##reg ) 21 #define REG_WR( scope, inst, reg, val ) \ argument 22 REG_WRITE( reg_##scope##_##reg, \ 23 (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) 27 #define REG_RD_VECT( scope, inst, reg, index ) \ argument 28 REG_READ( reg_##scope##_##reg, \ 29 (inst) + REG_RD_ADDR_##scope##_##reg + \ 30 (index) * STRIDE_##scope##_##reg ) [all …]`
D	clkgen_defs.h	`15 #define REG_RD( scope, inst, reg ) \ argument 16 REG_READ( reg_##scope##_##reg, \ 17 (inst) + REG_RD_ADDR_##scope##_##reg ) 21 #define REG_WR( scope, inst, reg, val ) \ argument 22 REG_WRITE( reg_##scope##_##reg, \ 23 (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) 27 #define REG_RD_VECT( scope, inst, reg, index ) \ argument 28 REG_READ( reg_##scope##_##reg, \ 29 (inst) + REG_RD_ADDR_##scope##_##reg + \ 30 (index) * STRIDE_##scope##_##reg ) [all …]`
D	marb_foo_defs.h	`15 #define REG_RD( scope, inst, reg ) \ argument 16 REG_READ( reg_##scope##_##reg, \ 17 (inst) + REG_RD_ADDR_##scope##_##reg ) 21 #define REG_WR( scope, inst, reg, val ) \ argument 22 REG_WRITE( reg_##scope##_##reg, \ 23 (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) 27 #define REG_RD_VECT( scope, inst, reg, index ) \ argument 28 REG_READ( reg_##scope##_##reg, \ 29 (inst) + REG_RD_ADDR_##scope##_##reg + \ 30 (index) * STRIDE_##scope##_##reg ) [all …]`
D	timer_defs.h	`15 #define REG_RD( scope, inst, reg ) \ argument 16 REG_READ( reg_##scope##_##reg, \ 17 (inst) + REG_RD_ADDR_##scope##_##reg ) 21 #define REG_WR( scope, inst, reg, val ) \ argument 22 REG_WRITE( reg_##scope##_##reg, \ 23 (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) 27 #define REG_RD_VECT( scope, inst, reg, index ) \ argument 28 REG_READ( reg_##scope##_##reg, \ 29 (inst) + REG_RD_ADDR_##scope##_##reg + \ 30 (index) * STRIDE_##scope##_##reg ) [all …]`
D	ddr2_defs.h	`15 #define REG_RD( scope, inst, reg ) \ argument 16 REG_READ( reg_##scope##_##reg, \ 17 (inst) + REG_RD_ADDR_##scope##_##reg ) 21 #define REG_WR( scope, inst, reg, val ) \ argument 22 REG_WRITE( reg_##scope##_##reg, \ 23 (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) 27 #define REG_RD_VECT( scope, inst, reg, index ) \ argument 28 REG_READ( reg_##scope##_##reg, \ 29 (inst) + REG_RD_ADDR_##scope##_##reg + \ 30 (index) * STRIDE_##scope##_##reg ) [all …]`
D	pinmux_defs.h	`15 #define REG_RD( scope, inst, reg ) \ argument 16 REG_READ( reg_##scope##_##reg, \ 17 (inst) + REG_RD_ADDR_##scope##_##reg ) 21 #define REG_WR( scope, inst, reg, val ) \ argument 22 REG_WRITE( reg_##scope##_##reg, \ 23 (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) 27 #define REG_RD_VECT( scope, inst, reg, index ) \ argument 28 REG_READ( reg_##scope##_##reg, \ 29 (inst) + REG_RD_ADDR_##scope##_##reg + \ 30 (index) * STRIDE_##scope##_##reg ) [all …]`
D	pio_defs.h	`15 #define REG_RD( scope, inst, reg ) \ argument 16 REG_READ( reg_##scope##_##reg, \ 17 (inst) + REG_RD_ADDR_##scope##_##reg ) 21 #define REG_WR( scope, inst, reg, val ) \ argument 22 REG_WRITE( reg_##scope##_##reg, \ 23 (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) 27 #define REG_RD_VECT( scope, inst, reg, index ) \ argument 28 REG_READ( reg_##scope##_##reg, \ 29 (inst) + REG_RD_ADDR_##scope##_##reg + \ 30 (index) * STRIDE_##scope##_##reg ) [all …]`
D	intr_vect_defs.h	`15 #define REG_RD( scope, inst, reg ) \ argument 16 REG_READ( reg_##scope##_##reg, \ 17 (inst) + REG_RD_ADDR_##scope##_##reg ) 21 #define REG_WR( scope, inst, reg, val ) \ argument 22 REG_WRITE( reg_##scope##_##reg, \ 23 (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) 27 #define REG_RD_VECT( scope, inst, reg, index ) \ argument 28 REG_READ( reg_##scope##_##reg, \ 29 (inst) + REG_RD_ADDR_##scope##_##reg + \ 30 (index) * STRIDE_##scope##_##reg ) [all …]`
/linux-4.4.14/drivers/scsi/aic94xx/
D	aic94xx_reg.c	128 u32 reg) \ 131 u32 map_offs = (reg - io_handle->ww##_base) + asd_mem_offs_##ww();\ 137 u32 reg, type val) \ 140 u32 map_offs = (reg - io_handle->ww##_base) + asd_mem_offs_##ww();\ 188 static void asd_move_swb(struct asd_ha_struct asd_ha, u32 reg) in asd_move_swb() argument 190 u32 base = reg & ~(MBAR0_SWB_SIZE-1); in asd_move_swb() 195 static void __asd_write_reg_byte(struct asd_ha_struct asd_ha, u32 reg, u8 val) in __asd_write_reg_byte() argument 198 BUG_ON(reg >= 0xC0000000 \|\| reg < ALL_BASE_ADDR); in __asd_write_reg_byte() 199 if (io_handle->swa_base <= reg in __asd_write_reg_byte() 200 && reg < io_handle->swa_base + MBAR0_SWA_SIZE) in __asd_write_reg_byte() [all …]
/linux-4.4.14/arch/m68k/math-emu/
D	multi_arith.h	22 static inline void fp_denormalize(struct fp_ext *reg, unsigned int cnt) in fp_denormalize() argument 24 reg->exp += cnt; in fp_denormalize() 28 reg->lowmant = reg->mant.m32[1] << (8 - cnt); in fp_denormalize() 29 reg->mant.m32[1] = (reg->mant.m32[1] >> cnt) \| in fp_denormalize() 30 (reg->mant.m32[0] << (32 - cnt)); in fp_denormalize() 31 reg->mant.m32[0] = reg->mant.m32[0] >> cnt; in fp_denormalize() 34 reg->lowmant = reg->mant.m32[1] >> (cnt - 8); in fp_denormalize() 35 if (reg->mant.m32[1] << (40 - cnt)) in fp_denormalize() 36 reg->lowmant \|= 1; in fp_denormalize() 37 reg->mant.m32[1] = (reg->mant.m32[1] >> cnt) \| in fp_denormalize() [all …]
/linux-4.4.14/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/
D	iop_version_defs.h	`15 #define REG_RD( scope, inst, reg ) \ argument 16 REG_READ( reg_##scope##_##reg, \ 17 (inst) + REG_RD_ADDR_##scope##_##reg ) 21 #define REG_WR( scope, inst, reg, val ) \ argument 22 REG_WRITE( reg_##scope##_##reg, \ 23 (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) 27 #define REG_RD_VECT( scope, inst, reg, index ) \ argument 28 REG_READ( reg_##scope##_##reg, \ 29 (inst) + REG_RD_ADDR_##scope##_##reg + \ 30 (index) * STRIDE_##scope##_##reg ) [all …]`
D	iop_sap_in_defs.h	`15 #define REG_RD( scope, inst, reg ) \ argument 16 REG_READ( reg_##scope##_##reg, \ 17 (inst) + REG_RD_ADDR_##scope##_##reg ) 21 #define REG_WR( scope, inst, reg, val ) \ argument 22 REG_WRITE( reg_##scope##_##reg, \ 23 (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) 27 #define REG_RD_VECT( scope, inst, reg, index ) \ argument 28 REG_READ( reg_##scope##_##reg, \ 29 (inst) + REG_RD_ADDR_##scope##_##reg + \ 30 (index) * STRIDE_##scope##_##reg ) [all …]`
D	iop_sap_out_defs.h	`15 #define REG_RD( scope, inst, reg ) \ argument 16 REG_READ( reg_##scope##_##reg, \ 17 (inst) + REG_RD_ADDR_##scope##_##reg ) 21 #define REG_WR( scope, inst, reg, val ) \ argument 22 REG_WRITE( reg_##scope##_##reg, \ 23 (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) 27 #define REG_RD_VECT( scope, inst, reg, index ) \ argument 28 REG_READ( reg_##scope##_##reg, \ 29 (inst) + REG_RD_ADDR_##scope##_##reg + \ 30 (index) * STRIDE_##scope##_##reg ) [all …]`
D	iop_sw_spu_defs.h	`15 #define REG_RD( scope, inst, reg ) \ argument 16 REG_READ( reg_##scope##_##reg, \ 17 (inst) + REG_RD_ADDR_##scope##_##reg ) 21 #define REG_WR( scope, inst, reg, val ) \ argument 22 REG_WRITE( reg_##scope##_##reg, \ 23 (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) 27 #define REG_RD_VECT( scope, inst, reg, index ) \ argument 28 REG_READ( reg_##scope##_##reg, \ 29 (inst) + REG_RD_ADDR_##scope##_##reg + \ 30 (index) * STRIDE_##scope##_##reg ) [all …]`
/linux-4.4.14/arch/cris/include/arch-v32/arch/hwregs/iop/
D	iop_version_defs.h	`18 #define REG_RD( scope, inst, reg ) \ argument 19 REG_READ( reg_##scope##_##reg, \ 20 (inst) + REG_RD_ADDR_##scope##_##reg ) 24 #define REG_WR( scope, inst, reg, val ) \ argument 25 REG_WRITE( reg_##scope##_##reg, \ 26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) 30 #define REG_RD_VECT( scope, inst, reg, index ) \ argument 31 REG_READ( reg_##scope##_##reg, \ 32 (inst) + REG_RD_ADDR_##scope##_##reg + \ 33 (index) * STRIDE_##scope##_##reg ) [all …]`
D	iop_scrc_in_defs.h	`18 #define REG_RD( scope, inst, reg ) \ argument 19 REG_READ( reg_##scope##_##reg, \ 20 (inst) + REG_RD_ADDR_##scope##_##reg ) 24 #define REG_WR( scope, inst, reg, val ) \ argument 25 REG_WRITE( reg_##scope##_##reg, \ 26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) 30 #define REG_RD_VECT( scope, inst, reg, index ) \ argument 31 REG_READ( reg_##scope##_##reg, \ 32 (inst) + REG_RD_ADDR_##scope##_##reg + \ 33 (index) * STRIDE_##scope##_##reg ) [all …]`
D	iop_scrc_out_defs.h	`18 #define REG_RD( scope, inst, reg ) \ argument 19 REG_READ( reg_##scope##_##reg, \ 20 (inst) + REG_RD_ADDR_##scope##_##reg ) 24 #define REG_WR( scope, inst, reg, val ) \ argument 25 REG_WRITE( reg_##scope##_##reg, \ 26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) 30 #define REG_RD_VECT( scope, inst, reg, index ) \ argument 31 REG_READ( reg_##scope##_##reg, \ 32 (inst) + REG_RD_ADDR_##scope##_##reg + \ 33 (index) * STRIDE_##scope##_##reg ) [all …]`
D	iop_trigger_grp_defs.h	`18 #define REG_RD( scope, inst, reg ) \ argument 19 REG_READ( reg_##scope##_##reg, \ 20 (inst) + REG_RD_ADDR_##scope##_##reg ) 24 #define REG_WR( scope, inst, reg, val ) \ argument 25 REG_WRITE( reg_##scope##_##reg, \ 26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) 30 #define REG_RD_VECT( scope, inst, reg, index ) \ argument 31 REG_READ( reg_##scope##_##reg, \ 32 (inst) + REG_RD_ADDR_##scope##_##reg + \ 33 (index) * STRIDE_##scope##_##reg ) [all …]`
D	iop_fifo_in_extra_defs.h	`18 #define REG_RD( scope, inst, reg ) \ argument 19 REG_READ( reg_##scope##_##reg, \ 20 (inst) + REG_RD_ADDR_##scope##_##reg ) 24 #define REG_WR( scope, inst, reg, val ) \ argument 25 REG_WRITE( reg_##scope##_##reg, \ 26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) 30 #define REG_RD_VECT( scope, inst, reg, index ) \ argument 31 REG_READ( reg_##scope##_##reg, \ 32 (inst) + REG_RD_ADDR_##scope##_##reg + \ 33 (index) * STRIDE_##scope##_##reg ) [all …]`
D	iop_fifo_out_extra_defs.h	`18 #define REG_RD( scope, inst, reg ) \ argument 19 REG_READ( reg_##scope##_##reg, \ 20 (inst) + REG_RD_ADDR_##scope##_##reg ) 24 #define REG_WR( scope, inst, reg, val ) \ argument 25 REG_WRITE( reg_##scope##_##reg, \ 26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) 30 #define REG_RD_VECT( scope, inst, reg, index ) \ argument 31 REG_READ( reg_##scope##_##reg, \ 32 (inst) + REG_RD_ADDR_##scope##_##reg + \ 33 (index) * STRIDE_##scope##_##reg ) [all …]`
D	iop_sap_in_defs.h	`18 #define REG_RD( scope, inst, reg ) \ argument 19 REG_READ( reg_##scope##_##reg, \ 20 (inst) + REG_RD_ADDR_##scope##_##reg ) 24 #define REG_WR( scope, inst, reg, val ) \ argument 25 REG_WRITE( reg_##scope##_##reg, \ 26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) 30 #define REG_RD_VECT( scope, inst, reg, index ) \ argument 31 REG_READ( reg_##scope##_##reg, \ 32 (inst) + REG_RD_ADDR_##scope##_##reg + \ 33 (index) * STRIDE_##scope##_##reg ) [all …]`
D	iop_mpu_defs.h	`18 #define REG_RD( scope, inst, reg ) \ argument 19 REG_READ( reg_##scope##_##reg, \ 20 (inst) + REG_RD_ADDR_##scope##_##reg ) 24 #define REG_WR( scope, inst, reg, val ) \ argument 25 REG_WRITE( reg_##scope##_##reg, \ 26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) 30 #define REG_RD_VECT( scope, inst, reg, index ) \ argument 31 REG_READ( reg_##scope##_##reg, \ 32 (inst) + REG_RD_ADDR_##scope##_##reg + \ 33 (index) * STRIDE_##scope##_##reg ) [all …]`
D	iop_crc_par_defs.h	`18 #define REG_RD( scope, inst, reg ) \ argument 19 REG_READ( reg_##scope##_##reg, \ 20 (inst) + REG_RD_ADDR_##scope##_##reg ) 24 #define REG_WR( scope, inst, reg, val ) \ argument 25 REG_WRITE( reg_##scope##_##reg, \ 26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) 30 #define REG_RD_VECT( scope, inst, reg, index ) \ argument 31 REG_READ( reg_##scope##_##reg, \ 32 (inst) + REG_RD_ADDR_##scope##_##reg + \ 33 (index) * STRIDE_##scope##_##reg ) [all …]`
D	iop_fifo_in_defs.h	`18 #define REG_RD( scope, inst, reg ) \ argument 19 REG_READ( reg_##scope##_##reg, \ 20 (inst) + REG_RD_ADDR_##scope##_##reg ) 24 #define REG_WR( scope, inst, reg, val ) \ argument 25 REG_WRITE( reg_##scope##_##reg, \ 26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) 30 #define REG_RD_VECT( scope, inst, reg, index ) \ argument 31 REG_READ( reg_##scope##_##reg, \ 32 (inst) + REG_RD_ADDR_##scope##_##reg + \ 33 (index) * STRIDE_##scope##_##reg ) [all …]`
D	iop_timer_grp_defs.h	`18 #define REG_RD( scope, inst, reg ) \ argument 19 REG_READ( reg_##scope##_##reg, \ 20 (inst) + REG_RD_ADDR_##scope##_##reg ) 24 #define REG_WR( scope, inst, reg, val ) \ argument 25 REG_WRITE( reg_##scope##_##reg, \ 26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) 30 #define REG_RD_VECT( scope, inst, reg, index ) \ argument 31 REG_READ( reg_##scope##_##reg, \ 32 (inst) + REG_RD_ADDR_##scope##_##reg + \ 33 (index) * STRIDE_##scope##_##reg ) [all …]`
D	iop_fifo_out_defs.h	`18 #define REG_RD( scope, inst, reg ) \ argument 19 REG_READ( reg_##scope##_##reg, \ 20 (inst) + REG_RD_ADDR_##scope##_##reg ) 24 #define REG_WR( scope, inst, reg, val ) \ argument 25 REG_WRITE( reg_##scope##_##reg, \ 26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) 30 #define REG_RD_VECT( scope, inst, reg, index ) \ argument 31 REG_READ( reg_##scope##_##reg, \ 32 (inst) + REG_RD_ADDR_##scope##_##reg + \ 33 (index) * STRIDE_##scope##_##reg ) [all …]`
D	iop_sap_out_defs.h	`18 #define REG_RD( scope, inst, reg ) \ argument 19 REG_READ( reg_##scope##_##reg, \ 20 (inst) + REG_RD_ADDR_##scope##_##reg ) 24 #define REG_WR( scope, inst, reg, val ) \ argument 25 REG_WRITE( reg_##scope##_##reg, \ 26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) 30 #define REG_RD_VECT( scope, inst, reg, index ) \ argument 31 REG_READ( reg_##scope##_##reg, \ 32 (inst) + REG_RD_ADDR_##scope##_##reg + \ 33 (index) * STRIDE_##scope##_##reg ) [all …]`
D	iop_dmc_out_defs.h	`18 #define REG_RD( scope, inst, reg ) \ argument 19 REG_READ( reg_##scope##_##reg, \ 20 (inst) + REG_RD_ADDR_##scope##_##reg ) 24 #define REG_WR( scope, inst, reg, val ) \ argument 25 REG_WRITE( reg_##scope##_##reg, \ 26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) 30 #define REG_RD_VECT( scope, inst, reg, index ) \ argument 31 REG_READ( reg_##scope##_##reg, \ 32 (inst) + REG_RD_ADDR_##scope##_##reg + \ 33 (index) * STRIDE_##scope##_##reg ) [all …]`
D	iop_dmc_in_defs.h	`18 #define REG_RD( scope, inst, reg ) \ argument 19 REG_READ( reg_##scope##_##reg, \ 20 (inst) + REG_RD_ADDR_##scope##_##reg ) 24 #define REG_WR( scope, inst, reg, val ) \ argument 25 REG_WRITE( reg_##scope##_##reg, \ 26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) 30 #define REG_RD_VECT( scope, inst, reg, index ) \ argument 31 REG_READ( reg_##scope##_##reg, \ 32 (inst) + REG_RD_ADDR_##scope##_##reg + \ 33 (index) * STRIDE_##scope##_##reg ) [all …]`
/linux-4.4.14/arch/blackfin/kernel/
D	pseudodbg.c	23 static const char get_allreg_name(int grp, int reg) in get_allreg_name() argument 25 return greg_names[(grp << 3) \| reg]; in get_allreg_name() 40 static bool fix_up_reg(struct pt_regs fp, long value, int grp, int reg) in fix_up_reg() argument 47 (grp == 4 && (reg == 4 \|\| reg == 5)) \|\| in fix_up_reg() 51 if (grp == 0 \|\| (grp == 1 && reg < 6)) in fix_up_reg() 52 val -= (reg + 8 grp); in fix_up_reg() 53 else if (grp == 1 && reg == 6) in fix_up_reg() 55 else if (grp == 1 && reg == 7) in fix_up_reg() 59 val -= reg; in fix_up_reg() 60 } else if (grp == 3 && reg >= 4) { in fix_up_reg() [all …]
/linux-4.4.14/drivers/md/
D	dm-region-hash.c	134 void dm_rh_region_context(struct dm_region reg) in dm_rh_region_context() argument 136 return reg->rh->context; in dm_rh_region_context() 140 region_t dm_rh_get_region_key(struct dm_region reg) in dm_rh_get_region_key() argument 142 return reg->key; in dm_rh_get_region_key() 238 struct dm_region reg, nreg; in dm_region_hash_destroy() local 242 list_for_each_entry_safe(reg, nreg, rh->buckets + h, in dm_region_hash_destroy() 244 BUG_ON(atomic_read(&reg->pending)); in dm_region_hash_destroy() 245 mempool_free(reg, rh->region_pool); in dm_region_hash_destroy() 271 struct dm_region reg; in __rh_lookup() local 274 list_for_each_entry(reg, bucket, hash_list) in __rh_lookup() [all …]
/linux-4.4.14/arch/x86/include/asm/
D	xor_avx.h	43 #define BLOCK(i, reg) \ in xor_avx_2() argument 45 asm volatile("vmovdqa %0, %%ymm" #reg : : "m" (p1[i / sizeof(p1)])); \ in xor_avx_2() 46 asm volatile("vxorps %0, %%ymm" #reg ", %%ymm" #reg : : \ in xor_avx_2() 48 asm volatile("vmovdqa %%ymm" #reg ", %0" : \ in xor_avx_2() 70 #define BLOCK(i, reg) \ in xor_avx_3() argument 72 asm volatile("vmovdqa %0, %%ymm" #reg : : "m" (p2[i / sizeof(p2)])); \ in xor_avx_3() 73 asm volatile("vxorps %0, %%ymm" #reg ", %%ymm" #reg : : \ in xor_avx_3() 75 asm volatile("vxorps %0, %%ymm" #reg ", %%ymm" #reg : : \ in xor_avx_3() 77 asm volatile("vmovdqa %%ymm" #reg ", %0" : \ in xor_avx_3() 100 #define BLOCK(i, reg) \ in xor_avx_4() argument [all …]
/linux-4.4.14/drivers/clk/berlin/
D	berlin2-avpll.c	127 u32 reg; in berlin2_avpll_vco_is_enabled() local 129 reg = readl_relaxed(vco->base + VCO_CTRL0); in berlin2_avpll_vco_is_enabled() 131 reg >>= 4; in berlin2_avpll_vco_is_enabled() 133 return !!(reg & VCO_POWERUP); in berlin2_avpll_vco_is_enabled() 139 u32 reg; in berlin2_avpll_vco_enable() local 141 reg = readl_relaxed(vco->base + VCO_CTRL0); in berlin2_avpll_vco_enable() 143 reg \|= VCO_POWERUP << 4; in berlin2_avpll_vco_enable() 145 reg \|= VCO_POWERUP; in berlin2_avpll_vco_enable() 146 writel_relaxed(reg, vco->base + VCO_CTRL0); in berlin2_avpll_vco_enable() 154 u32 reg; in berlin2_avpll_vco_disable() local [all …]
D	berlin2-div.c	79 u32 reg; in berlin2_div_is_enabled() local 84 reg = readl_relaxed(div->base + map->gate_offs); in berlin2_div_is_enabled() 85 reg >>= map->gate_shift; in berlin2_div_is_enabled() 90 return (reg & 0x1); in berlin2_div_is_enabled() 97 u32 reg; in berlin2_div_enable() local 102 reg = readl_relaxed(div->base + map->gate_offs); in berlin2_div_enable() 103 reg \|= BIT(map->gate_shift); in berlin2_div_enable() 104 writel_relaxed(reg, div->base + map->gate_offs); in berlin2_div_enable() 116 u32 reg; in berlin2_div_disable() local 121 reg = readl_relaxed(div->base + map->gate_offs); in berlin2_div_disable() [all …]
/linux-4.4.14/sound/firewire/tascam/
D	tascam-stream.c	`16 __be32 reg; in get_clock() local 21 &reg, sizeof(reg), 0); in get_clock() 23 *data = be32_to_cpu(reg); in get_clock() 32 __be32 reg; in set_clock() local 63 reg = cpu_to_be32(data); in set_clock() 67 &reg, sizeof(reg), 0); in set_clock() 72 reg = cpu_to_be32(0x0000001a); in set_clock() 74 reg = cpu_to_be32(0x0000000d); in set_clock() 78 &reg, sizeof(reg), 0); in set_clock() 130 __be32 reg; in enable_data_channels() local [all …]`
/linux-4.4.14/drivers/acpi/pmic/
D	intel_pmic_crc.c	`30 .reg = 0x66, 35 .reg = 0x5d, 43 .reg = 0x75 47 .reg = 0x95 51 .reg = 0x97 55 .reg = 0x77 59 .reg = 0x9a 63 .reg = 0x9c 67 .reg = 0x79 71 .reg = 0x9f [all …]`
D	intel_pmic_xpower.c	`29 .reg = 0x13, 34 .reg = 0x13, 39 .reg = 0x13, 44 .reg = 0x12, 49 .reg = 0x12, 54 .reg = 0x12, 59 .reg = 0x12, 64 .reg = 0x12, 69 .reg = 0x12, 74 .reg = 0x12, [all …]`
/linux-4.4.14/drivers/net/ethernet/intel/ixgb/
D	ixgb_ethtool.c	225 u32 reg = p; in ixgb_get_regs() local 226 u32 reg_start = reg; in ixgb_get_regs() 235 reg++ = IXGB_READ_REG(hw, CTRL0); / 0 / in ixgb_get_regs() 236 reg++ = IXGB_READ_REG(hw, CTRL1); /* 1 / in ixgb_get_regs() 237 reg++ = IXGB_READ_REG(hw, STATUS); /* 2 / in ixgb_get_regs() 238 reg++ = IXGB_READ_REG(hw, EECD); /* 3 / in ixgb_get_regs() 239 reg++ = IXGB_READ_REG(hw, MFS); /* 4 / in ixgb_get_regs() 242 reg++ = IXGB_READ_REG(hw, ICR); /* 5 / in ixgb_get_regs() 243 reg++ = IXGB_READ_REG(hw, ICS); /* 6 / in ixgb_get_regs() 244 reg++ = IXGB_READ_REG(hw, IMS); /* 7 */ in ixgb_get_regs() [all …]
/linux-4.4.14/drivers/net/ethernet/broadcom/genet/
D	bcmgenet_wol.c	47 u32 reg; in bcmgenet_get_wol() local 54 reg = bcmgenet_umac_readl(priv, UMAC_MPD_PW_MS); in bcmgenet_get_wol() 55 put_unaligned_be16(reg, &wol->sopass[0]); in bcmgenet_get_wol() 56 reg = bcmgenet_umac_readl(priv, UMAC_MPD_PW_LS); in bcmgenet_get_wol() 57 put_unaligned_be32(reg, &wol->sopass[2]); in bcmgenet_get_wol() 68 u32 reg; in bcmgenet_set_wol() local 76 reg = bcmgenet_umac_readl(priv, UMAC_MPD_CTRL); in bcmgenet_set_wol() 82 reg \|= MPD_PW_EN; in bcmgenet_set_wol() 84 reg &= ~MPD_PW_EN; in bcmgenet_set_wol() 86 bcmgenet_umac_writel(priv, reg, UMAC_MPD_CTRL); in bcmgenet_set_wol() [all …]
/linux-4.4.14/arch/arm/mach-tegra/
D	flowctrl.c	76 unsigned int reg; in flowctrl_cpu_suspend_enter() local 79 reg = flowctrl_read_cpu_csr(cpuid); in flowctrl_cpu_suspend_enter() 83 reg &= ~TEGRA20_FLOW_CTRL_CSR_WFE_BITMAP; in flowctrl_cpu_suspend_enter() 85 reg &= ~TEGRA20_FLOW_CTRL_CSR_WFI_BITMAP; in flowctrl_cpu_suspend_enter() 87 reg \|= TEGRA20_FLOW_CTRL_CSR_WFE_CPU0 << cpuid; in flowctrl_cpu_suspend_enter() 93 reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP; in flowctrl_cpu_suspend_enter() 95 reg &= ~TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP; in flowctrl_cpu_suspend_enter() 97 reg \|= TEGRA30_FLOW_CTRL_CSR_WFI_CPU0 << cpuid; in flowctrl_cpu_suspend_enter() 100 reg \|= FLOW_CTRL_CSR_INTR_FLAG; /* clear intr flag / in flowctrl_cpu_suspend_enter() 101 reg \|= FLOW_CTRL_CSR_EVENT_FLAG; / clear event flag */ in flowctrl_cpu_suspend_enter() [all …]
/linux-4.4.14/drivers/cpufreq/
D	s5pv210-cpufreq.c	201 void __iomem *reg = NULL; in s5pv210_set_refresh() local 204 reg = (dmc_base[0] + 0x30); in s5pv210_set_refresh() 206 reg = (dmc_base[1] + 0x30); in s5pv210_set_refresh() 221 __raw_writel(tmp1, reg); in s5pv210_set_refresh() 226 unsigned long reg; in s5pv210_target() local 302 reg = __raw_readl(S5P_CLK_DIV2); in s5pv210_target() 303 reg &= ~(S5P_CLKDIV2_G3D_MASK \| S5P_CLKDIV2_MFC_MASK); in s5pv210_target() 304 reg \|= (3 << S5P_CLKDIV2_G3D_SHIFT) \| in s5pv210_target() 306 __raw_writel(reg, S5P_CLK_DIV2); in s5pv210_target() 310 reg = __raw_readl(S5P_CLKDIV_STAT0); in s5pv210_target() [all …]
/linux-4.4.14/drivers/video/fbdev/savage/
D	savagefb_driver.c	117 static void vgaHWRestore(struct savagefb_par par, struct savage_reg reg) in vgaHWRestore() argument 121 VGAwMISC(reg->MiscOutReg, par); in vgaHWRestore() 124 VGAwSEQ(i, reg->Sequencer[i], par); in vgaHWRestore() 128 VGAwCR(17, reg->CRTC[17] & ~0x80, par); in vgaHWRestore() 131 VGAwCR(i, reg->CRTC[i], par); in vgaHWRestore() 134 VGAwGR(i, reg->Graphics[i], par); in vgaHWRestore() 139 VGAwATTR(i, reg->Attribute[i], par); in vgaHWRestore() 147 struct savage_reg *reg) in vgaHWInit() argument 149 reg->MiscOutReg = 0x23; in vgaHWInit() 152 reg->MiscOutReg \|= 0x40; in vgaHWInit() [all …]
/linux-4.4.14/drivers/thermal/
D	armada_thermal.c	76 unsigned long reg; in armadaxp_init_sensor() local 78 reg = readl_relaxed(priv->control); in armadaxp_init_sensor() 79 reg \|= PMU_TDC0_OTF_CAL_MASK; in armadaxp_init_sensor() 80 writel(reg, priv->control); in armadaxp_init_sensor() 83 reg &= ~PMU_TDC0_REF_CAL_CNT_MASK; in armadaxp_init_sensor() 84 reg \|= (0xf1 << PMU_TDC0_REF_CAL_CNT_OFFS); in armadaxp_init_sensor() 85 writel(reg, priv->control); in armadaxp_init_sensor() 88 reg = readl_relaxed(priv->control); in armadaxp_init_sensor() 89 writel((reg \| PMU_TDC0_SW_RST_MASK), priv->control); in armadaxp_init_sensor() 91 writel(reg, priv->control); in armadaxp_init_sensor() [all …]
D	dove_thermal.c	53 u32 reg; in dove_init_sensor() local 57 reg = readl_relaxed(priv->control); in dove_init_sensor() 60 reg &= ~PMU_TDC0_AVG_NUM_MASK; in dove_init_sensor() 61 reg \|= (0x1 << PMU_TDC0_AVG_NUM_OFFS); in dove_init_sensor() 64 reg &= ~PMU_TDC0_REF_CAL_CNT_MASK; in dove_init_sensor() 65 reg \|= (0x0F1 << PMU_TDC0_REF_CAL_CNT_OFFS); in dove_init_sensor() 68 reg &= ~PMU_TDC0_SEL_VCAL_MASK; in dove_init_sensor() 69 reg \|= (0x2 << PMU_TDC0_SEL_VCAL_OFFS); in dove_init_sensor() 70 writel(reg, priv->control); in dove_init_sensor() 73 reg = readl_relaxed(priv->control); in dove_init_sensor() [all …]
/linux-4.4.14/drivers/net/dsa/
D	bcm_sf2.c	121 offset = s->reg + CORE_P_MIB_OFFSET(port); in bcm_sf2_sw_get_ethtool_stats() 147 u32 reg; in bcm_sf2_imp_vlan_setup() local 157 reg = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(i)); in bcm_sf2_imp_vlan_setup() 158 reg \|= (1 << cpu_port); in bcm_sf2_imp_vlan_setup() 159 core_writel(priv, reg, CORE_PORT_VLAN_CTL_PORT(i)); in bcm_sf2_imp_vlan_setup() 166 u32 reg, val; in bcm_sf2_imp_setup() local 169 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL); in bcm_sf2_imp_setup() 170 reg &= ~P_TXQ_PSM_VDD(port); in bcm_sf2_imp_setup() 171 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL); in bcm_sf2_imp_setup() 174 reg = core_readl(priv, CORE_IMP_CTL); in bcm_sf2_imp_setup() [all …]
/linux-4.4.14/arch/arm/boot/dts/
D	k2hk-clocks.dtsi	`17 reg = <0x02620370 4>; 18 reg-names = "control"; 25 reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>; 26 reg-names = "control", "multiplier", "post-divider"; 34 reg = <0x02620358 4>; 35 reg-names = "control"; 43 reg = <0x02620360 4>; 44 reg-names = "control"; 52 reg = <0x02620368 4>; 53 reg-names = "control"; [all …]`
D	k2l-clocks.dtsi	`17 reg = <0x02620370 4>; 18 reg-names = "control"; 25 reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>; 26 reg-names = "control", "multiplier", "post-divider"; 34 reg = <0x02620358 4>; 35 reg-names = "control"; 43 reg = <0x02620360 4>; 44 reg-names = "control"; 52 reg-names = "control", "domain"; 53 reg = <0x02350004 0xb00>, <0x02350000 0x400>; [all …]`
D	hip04.dtsi	`93 reg = <0>; 98 reg = <1>; 103 reg = <2>; 108 reg = <3>; 113 reg = <0x100>; 118 reg = <0x101>; 123 reg = <0x102>; 128 reg = <0x103>; 133 reg = <0x200>; 138 reg = <0x201>; [all …]`
D	wm8750.dtsi	`45 reg = <0xd8140000 0x10000>; 54 reg = <0xD8150000 0x10000>; 60 reg = <0xd8110000 0x10000>; 69 reg = <0xd8130000 0x1000>; 91 reg = <0x200>; 98 reg = <0x204>; 105 reg = <0x208>; 112 reg = <0x20C>; 119 reg = <0x210>; 126 divisor-reg = <0x300>; [all …]`
D	wm8850.dtsi	`21 reg = <0x0>; 42 reg = <0xd8140000 0x10000>; 51 reg = <0xD8150000 0x10000>; 57 reg = <0xd8110000 0x10000>; 66 reg = <0xd8130000 0x1000>; 88 reg = <0x200>; 95 reg = <0x204>; 102 reg = <0x208>; 109 reg = <0x20c>; 116 reg = <0x210>; [all …]`
D	sama5d2.dtsi	`70 reg = <0>; 76 reg = <0x20000000 0x20000000>; 101 reg = <0x00200000 0x20000>; 114 reg = <0x00300000 0x100000 122 reg = <0>; 128 reg = <1>; 136 reg = <2>; 144 reg = <3>; 152 reg = <4>; 160 reg = <5>; [all …]`
D	omap44xx-clocks.dtsi	`28 reg = <0x0108>; 54 reg = <0x0108>; 139 reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>; 146 reg = <0x01f0>; 155 reg = <0x01f0>; 173 reg = <0x0108>; 183 reg = <0x0528>; 192 reg = <0x01f4>; 202 reg = <0x012c>; 209 reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>; [all …]`
/linux-4.4.14/drivers/media/dvb-frontends/
D	stv090x.c	695 static int stv090x_read_reg(struct stv090x_state state, unsigned int reg) in stv090x_read_reg() argument 700 u8 b0[] = { reg >> 8, reg & 0xff }; in stv090x_read_reg() 713 reg, ret); in stv090x_read_reg() 719 reg, buf); in stv090x_read_reg() 724 static int stv090x_write_regs(struct stv090x_state state, unsigned int reg, u8 *data, u32 count) in stv090x_write_regs() argument 734 KBUILD_MODNAME, reg, count); in stv090x_write_regs() 738 buf[0] = reg >> 8; in stv090x_write_regs() 739 buf[1] = reg & 0xff; in stv090x_write_regs() 745 printk(KERN_DEBUG "%s [0x%04x]:", __func__, reg); in stv090x_write_regs() 755 reg, data[0], count, ret); in stv090x_write_regs() [all …]
D	stb0899_algo.c	178 u8 reg; in stb0899_check_tmg() local 184 reg = stb0899_read_reg(state, STB0899_TLIR); in stb0899_check_tmg() 185 lock = STB0899_GETFIELD(TLIR_TMG_LOCK_IND, reg); in stb0899_check_tmg() 253 u8 reg; in stb0899_check_carrier() local 257 reg = stb0899_read_reg(state, STB0899_CFD); in stb0899_check_carrier() 258 STB0899_SETFIELD_VAL(CFD_ON, reg, 1); in stb0899_check_carrier() 259 stb0899_write_reg(state, STB0899_CFD, reg); in stb0899_check_carrier() 261 reg = stb0899_read_reg(state, STB0899_DSTATUS); in stb0899_check_carrier() 262 dprintk(state->verbose, FE_DEBUG, 1, "--------------------> STB0899_DSTATUS=[0x%02x]", reg); in stb0899_check_carrier() 263 if (STB0899_GETFIELD(CARRIER_FOUND, reg)) { in stb0899_check_carrier() [all …]
D	stb0899_drv.c	225 static int _stb0899_read_reg(struct stb0899_state state, unsigned int reg) in _stb0899_read_reg() argument 229 u8 b0[] = { reg >> 8, reg & 0xff }; in _stb0899_read_reg() 251 reg, ret); in _stb0899_read_reg() 257 reg, buf); in _stb0899_read_reg() 262 int stb0899_read_reg(struct stb0899_state state, unsigned int reg) in stb0899_read_reg() argument 266 result = _stb0899_read_reg(state, reg); in stb0899_read_reg() 272 if ((reg != 0xf2ff) && (reg != 0xf6ff) && in stb0899_read_reg() 273 (((reg & 0xff00) == 0xf200) \|\| ((reg & 0xff00) == 0xf600))) in stb0899_read_reg() 274 _stb0899_read_reg(state, (reg \| 0x00ff)); in stb0899_read_reg() 452 int stb0899_read_regs(struct stb0899_state state, unsigned int reg, u8 buf, u32 count) in stb0899_read_regs() argument [all …]
D	m88rs2000.c	64 u8 reg, u8 data) in m88rs2000_writereg() argument 67 u8 buf[] = { reg, data }; in m88rs2000_writereg() 79 "ret == %i)\n", __func__, reg, data, ret); in m88rs2000_writereg() 84 static u8 m88rs2000_readreg(struct m88rs2000_state *state, u8 reg) in m88rs2000_readreg() argument 87 u8 b0[] = { reg }; in m88rs2000_readreg() 108 __func__, reg, ret); in m88rs2000_readreg() 117 u8 reg; in m88rs2000_get_mclk() local 119 reg = m88rs2000_readreg(state, 0x86); in m88rs2000_get_mclk() 120 if (!reg \|\| reg == 0xff) in m88rs2000_get_mclk() 123 reg /= 2; in m88rs2000_get_mclk() [all …]
/linux-4.4.14/arch/mips/include/asm/mach-pnx833x/
D	pnx833x.h	33 #define PNX833X_BIT(val, reg, field) ((val) & PNX833X_##reg##_##field) argument 34 #define PNX833X_REGBIT(reg, field) PNX833X_BIT(PNX833X_##reg, reg, field) argument 37 #define PNX_FIELD(cpu, val, reg, field) \ argument 38 (((val) & PNX##cpu##_##reg##_##field##_MASK) >> \ 39 PNX##cpu##_##reg##_##field##_SHIFT) 40 #define PNX833X_FIELD(val, reg, field) PNX_FIELD(833X, val, reg, field) argument 41 #define PNX8330_FIELD(val, reg, field) PNX_FIELD(8330, val, reg, field) argument 42 #define PNX8335_FIELD(val, reg, field) PNX_FIELD(8335, val, reg, field) argument 45 #define PNX833X_REGFIELD(reg, field) PNX833X_FIELD(PNX833X_##reg, reg, field) argument 46 #define PNX8330_REGFIELD(reg, field) PNX8330_FIELD(PNX8330_##reg, reg, field) argument [all …]
/linux-4.4.14/drivers/usb/gadget/udc/
D	fusb300_udc.c	42 u32 reg = ioread32(fusb300->reg + offset); in fusb300_enable_bit() local 44 reg \|= value; in fusb300_enable_bit() 45 iowrite32(reg, fusb300->reg + offset); in fusb300_enable_bit() 51 u32 reg = ioread32(fusb300->reg + offset); in fusb300_disable_bit() local 53 reg &= ~value; in fusb300_disable_bit() 54 iowrite32(reg, fusb300->reg + offset); in fusb300_disable_bit() 78 u32 val = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET1(ep)); in fusb300_set_fifo_entry() 82 iowrite32(val, fusb300->reg + FUSB300_OFFSET_EPSET1(ep)); in fusb300_set_fifo_entry() 88 u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET1(ep)); in fusb300_set_start_entry() local 91 reg &= ~FUSB300_EPSET1_START_ENTRY_MSK ; in fusb300_set_start_entry() [all …]
D	fotg210-udc.c	33 u32 value = ioread32(ep->fotg210->reg + FOTG210_DMISGR1); in fotg210_disable_fifo_int() 39 iowrite32(value, ep->fotg210->reg + FOTG210_DMISGR1); in fotg210_disable_fifo_int() 44 u32 value = ioread32(ep->fotg210->reg + FOTG210_DMISGR1); in fotg210_enable_fifo_int() 50 iowrite32(value, ep->fotg210->reg + FOTG210_DMISGR1); in fotg210_enable_fifo_int() 55 u32 value = ioread32(fotg210->reg + FOTG210_DCFESR); in fotg210_set_cxdone() 58 iowrite32(value, fotg210->reg + FOTG210_DCFESR); in fotg210_set_cxdone() 95 val = ioread32(fotg210->reg + FOTG210_EPMAP); in fotg210_fifo_ep_mapping() 98 iowrite32(val, fotg210->reg + FOTG210_EPMAP); in fotg210_fifo_ep_mapping() 101 val = ioread32(fotg210->reg + FOTG210_FIFOMAP); in fotg210_fifo_ep_mapping() 104 iowrite32(val, fotg210->reg + FOTG210_FIFOMAP); in fotg210_fifo_ep_mapping() [all …]
/linux-4.4.14/arch/arm/mach-cns3xxx/
D	pm.c	20 u32 reg = __raw_readl(PM_CLK_GATE_REG); in cns3xxx_pwr_clk_en() local 22 reg \|= (block & PM_CLK_GATE_REG_MASK); in cns3xxx_pwr_clk_en() 23 __raw_writel(reg, PM_CLK_GATE_REG); in cns3xxx_pwr_clk_en() 29 u32 reg = __raw_readl(PM_CLK_GATE_REG); in cns3xxx_pwr_clk_dis() local 31 reg &= ~(block & PM_CLK_GATE_REG_MASK); in cns3xxx_pwr_clk_dis() 32 __raw_writel(reg, PM_CLK_GATE_REG); in cns3xxx_pwr_clk_dis() 38 u32 reg = __raw_readl(PM_PLL_HM_PD_CTRL_REG); in cns3xxx_pwr_power_up() local 40 reg &= ~(block & CNS3XXX_PWR_PLL_ALL); in cns3xxx_pwr_power_up() 41 __raw_writel(reg, PM_PLL_HM_PD_CTRL_REG); in cns3xxx_pwr_power_up() 50 u32 reg = __raw_readl(PM_PLL_HM_PD_CTRL_REG); in cns3xxx_pwr_power_down() local [all …]
/linux-4.4.14/arch/sh/include/mach-common/mach/
D	magicpanelr2.h	22 #define SETBITS_OUTB(mask, reg) __raw_writeb(__raw_readb(reg) \| mask, reg) argument 23 #define SETBITS_OUTW(mask, reg) __raw_writew(__raw_readw(reg) \| mask, reg) argument 24 #define SETBITS_OUTL(mask, reg) __raw_writel(__raw_readl(reg) \| mask, reg) argument 25 #define CLRBITS_OUTB(mask, reg) __raw_writeb(__raw_readb(reg) & ~mask, reg) argument 26 #define CLRBITS_OUTW(mask, reg) __raw_writew(__raw_readw(reg) & ~mask, reg) argument 27 #define CLRBITS_OUTL(mask, reg) __raw_writel(__raw_readl(reg) & ~mask, reg) argument
/linux-4.4.14/drivers/regulator/
D	vexpress.c	34 struct vexpress_regulator reg = rdev_get_drvdata(regdev); in vexpress_regulator_get_voltage() local 36 int err = regmap_read(reg->regmap, 0, &uV); in vexpress_regulator_get_voltage() 44 struct vexpress_regulator reg = rdev_get_drvdata(regdev); in vexpress_regulator_set_voltage() local 46 return regmap_write(reg->regmap, 0, min_uV); in vexpress_regulator_set_voltage() 60 struct vexpress_regulator reg; in vexpress_regulator_probe() local 64 reg = devm_kzalloc(&pdev->dev, sizeof(reg), GFP_KERNEL); in vexpress_regulator_probe() 65 if (!reg) in vexpress_regulator_probe() 68 reg->regmap = devm_regmap_init_vexpress_config(&pdev->dev); in vexpress_regulator_probe() 69 if (IS_ERR(reg->regmap)) in vexpress_regulator_probe() 70 return PTR_ERR(reg->regmap); in vexpress_regulator_probe() [all …]
/linux-4.4.14/arch/arm/mach-omap2/
D	sdrc.h	27 #define OMAP_SDRC_REGADDR(reg) (omap2_sdrc_base + (reg)) argument 28 #define OMAP_SMS_REGADDR(reg) (omap2_sms_base + (reg)) argument 32 static inline void sdrc_write_reg(u32 val, u16 reg) in sdrc_write_reg() argument 34 writel_relaxed(val, OMAP_SDRC_REGADDR(reg)); in sdrc_write_reg() 37 static inline u32 sdrc_read_reg(u16 reg) in sdrc_read_reg() argument 39 return readl_relaxed(OMAP_SDRC_REGADDR(reg)); in sdrc_read_reg() 44 static inline void sms_write_reg(u32 val, u16 reg) in sms_write_reg() argument 46 writel_relaxed(val, OMAP_SMS_REGADDR(reg)); in sms_write_reg() 49 static inline u32 sms_read_reg(u16 reg) in sms_read_reg() argument 51 return readl_relaxed(OMAP_SMS_REGADDR(reg)); in sms_read_reg() [all …]
/linux-4.4.14/arch/x86/pci/
D	ce4100.c	47 int reg; member 48 void (init)(struct sim_dev_reg reg); 49 void (read)(struct sim_dev_reg reg, u32 value); 50 void (write)(struct sim_dev_reg reg, u32 value); 55 void (init)(struct sim_dev_reg reg); 56 void (read)(struct sim_dev_reg reg, u32 value); 57 void (write)(struct sim_dev_reg reg, u32 value); 68 static void reg_init(struct sim_dev_reg reg) in reg_init() argument 70 pci_direct_conf1.read(0, 1, reg->dev_func, reg->reg, 4, in reg_init() 71 &reg->sim_reg.value); in reg_init() [all …]
D	olpc.c	183 static uint32_t hdr_addr(const uint32_t hdr, int reg) in hdr_addr() argument 198 addr = (uint32_t)hdr + reg + (bar_probing ? -0x10 : 0x20); in hdr_addr() 205 unsigned int devfn, int reg, int len, uint32_t *value) in pci_olpc_read() argument 213 return pci_direct_conf1.read(seg, bus, devfn, reg, len, value); in pci_olpc_read() 219 if (reg >= 0x70) in pci_olpc_read() 224 addr = hdr_addr(is_lx ? lxnb_hdr : gxnb_hdr, reg); in pci_olpc_read() 227 addr = hdr_addr(is_lx ? lxfb_hdr : gxfb_hdr, reg); in pci_olpc_read() 230 addr = is_lx ? hdr_addr(aes_hdr, reg) : &ff_loc; in pci_olpc_read() 233 addr = hdr_addr(isa_hdr, reg); in pci_olpc_read() 236 addr = hdr_addr(ac97_hdr, reg); in pci_olpc_read() [all …]
D	direct.c	16 #define PCI_CONF1_ADDRESS(bus, devfn, reg) \ argument 17 (0x80000000 \| ((reg & 0xF00) << 16) \| (bus << 16) \ 18 \| (devfn << 8) \| (reg & 0xFC)) 21 unsigned int devfn, int reg, int len, u32 value) in pci_conf1_read() argument 25 if (seg \|\| (bus > 255) \|\| (devfn > 255) \|\| (reg > 4095)) { in pci_conf1_read() 32 outl(PCI_CONF1_ADDRESS(bus, devfn, reg), 0xCF8); in pci_conf1_read() 36 value = inb(0xCFC + (reg & 3)); in pci_conf1_read() 39 *value = inw(0xCFC + (reg & 2)); in pci_conf1_read() 52 unsigned int devfn, int reg, int len, u32 value) in pci_conf1_write() argument 56 if (seg \|\| (bus > 255) \|\| (devfn > 255) \|\| (reg > 4095)) in pci_conf1_write() [all …]
/linux-4.4.14/drivers/media/tuners/
D	fc0012.c	24 static int fc0012_writereg(struct fc0012_priv priv, u8 reg, u8 val) in fc0012_writereg() argument 26 u8 buf[2] = {reg, val}; in fc0012_writereg() 34 KBUILD_MODNAME, reg, val); in fc0012_writereg() 40 static int fc0012_readreg(struct fc0012_priv priv, u8 reg, u8 *val) in fc0012_readreg() argument 44 .buf = &reg, .len = 1 }, in fc0012_readreg() 52 KBUILD_MODNAME, reg); in fc0012_readreg() 69 unsigned char reg[] = { in fc0012_init() local 100 reg[0x07] \|= 0x20; in fc0012_init() 108 reg[0x0c] \|= 0x02; in fc0012_init() 111 reg[0x09] \|= 0x01; in fc0012_init() [all …]
D	fc0013.c	27 static int fc0013_writereg(struct fc0013_priv priv, u8 reg, u8 val) in fc0013_writereg() argument 29 u8 buf[2] = {reg, val}; in fc0013_writereg() 35 err("I2C write reg failed, reg: %02x, val: %02x", reg, val); in fc0013_writereg() 41 static int fc0013_readreg(struct fc0013_priv priv, u8 reg, u8 *val) in fc0013_readreg() argument 44 { .addr = priv->addr, .flags = 0, .buf = &reg, .len = 1 }, in fc0013_readreg() 49 err("I2C read reg failed, reg: %02x", reg); in fc0013_readreg() 66 unsigned char reg[] = { in fc0013_init() local 96 reg[0x07] \|= 0x20; in fc0013_init() 104 reg[0x0c] \|= 0x02; in fc0013_init() 109 for (i = 1; i < sizeof(reg); i++) { in fc0013_init() [all …]
/linux-4.4.14/arch/mips/pci/
D	ops-sni.c	24 static int set_config_address(unsigned int busno, unsigned int devfn, int reg) in set_config_address() argument 26 if ((devfn > 255) \|\| (reg > 255)) in set_config_address() 35 (reg & 0xfc); in set_config_address() 40 static int pcimt_read(struct pci_bus bus, unsigned int devfn, int reg, in pcimt_read() argument 45 if ((res = set_config_address(bus->number, devfn, reg))) in pcimt_read() 50 val = inb(PCIMT_CONFIG_DATA + (reg & 3)); in pcimt_read() 53 val = inw(PCIMT_CONFIG_DATA + (reg & 2)); in pcimt_read() 63 static int pcimt_write(struct pci_bus bus, unsigned int devfn, int reg, in pcimt_write() argument 68 if ((res = set_config_address(bus->number, devfn, reg))) in pcimt_write() 73 outb(val, PCIMT_CONFIG_DATA + (reg & 3)); in pcimt_write() [all …]
/linux-4.4.14/sound/soc/
D	soc-io.c	29 unsigned int reg, unsigned int val) in snd_soc_component_read() argument 34 ret = regmap_read(component->regmap, reg, val); in snd_soc_component_read() 36 ret = component->read(component, reg, val); in snd_soc_component_read() 53 unsigned int reg, unsigned int val) in snd_soc_component_write() argument 56 return regmap_write(component->regmap, reg, val); in snd_soc_component_write() 58 return component->write(component, reg, val); in snd_soc_component_write() 65 struct snd_soc_component component, unsigned int reg, in snd_soc_component_update_bits_legacy() argument 76 ret = component->read(component, reg, &old); in snd_soc_component_update_bits_legacy() 83 ret = component->write(component, reg, new); in snd_soc_component_update_bits_legacy() 102 unsigned int reg, unsigned int mask, unsigned int val) in snd_soc_component_update_bits() argument [all …]
/linux-4.4.14/arch/arm/mach-mvebu/
D	pmsu.c	210 u32 reg; in mvebu_v7_pmsu_enable_l2_powerdown_onidle() local 216 reg = readl(pmsu_mp_base + L2C_NFABRIC_PM_CTL); in mvebu_v7_pmsu_enable_l2_powerdown_onidle() 217 reg \|= L2C_NFABRIC_PM_CTL_PWR_DOWN; in mvebu_v7_pmsu_enable_l2_powerdown_onidle() 218 writel(reg, pmsu_mp_base + L2C_NFABRIC_PM_CTL); in mvebu_v7_pmsu_enable_l2_powerdown_onidle() 231 u32 reg; in mvebu_v7_pmsu_idle_prepare() local 241 reg = readl(pmsu_mp_base + PMSU_STATUS_AND_MASK(hw_cpu)); in mvebu_v7_pmsu_idle_prepare() 242 reg \|= PMSU_STATUS_AND_MASK_CPU_IDLE_WAIT \| in mvebu_v7_pmsu_idle_prepare() 248 writel(reg, pmsu_mp_base + PMSU_STATUS_AND_MASK(hw_cpu)); in mvebu_v7_pmsu_idle_prepare() 250 reg = readl(pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu)); in mvebu_v7_pmsu_idle_prepare() 253 reg \|= PMSU_CONTROL_AND_CONFIG_L2_PWDDN; in mvebu_v7_pmsu_idle_prepare() [all …]
/linux-4.4.14/drivers/phy/
D	phy-qcom-ipq806x-sata.c	64 u32 reg; in qcom_ipq806x_sata_phy_init() local 67 reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM3); in qcom_ipq806x_sata_phy_init() 68 reg = reg \| SATA_PHY_SSC_EN; in qcom_ipq806x_sata_phy_init() 69 writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM3); in qcom_ipq806x_sata_phy_init() 71 reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM0) & in qcom_ipq806x_sata_phy_init() 75 reg \|= SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN3(0xf); in qcom_ipq806x_sata_phy_init() 76 writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM0); in qcom_ipq806x_sata_phy_init() 78 reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM1) & in qcom_ipq806x_sata_phy_init() 82 reg \|= SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN3(0x55) \| in qcom_ipq806x_sata_phy_init() 85 writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM1); in qcom_ipq806x_sata_phy_init() [all …]
D	phy-exynos5-usbdrd.c	197 static unsigned int exynos5_rate_to_clk(unsigned long rate, u32 reg) in exynos5_rate_to_clk() argument 203 reg = EXYNOS5_FSEL_9MHZ6; in exynos5_rate_to_clk() 206 reg = EXYNOS5_FSEL_10MHZ; in exynos5_rate_to_clk() 209 reg = EXYNOS5_FSEL_12MHZ; in exynos5_rate_to_clk() 212 reg = EXYNOS5_FSEL_19MHZ2; in exynos5_rate_to_clk() 215 reg = EXYNOS5_FSEL_20MHZ; in exynos5_rate_to_clk() 218 reg = EXYNOS5_FSEL_24MHZ; in exynos5_rate_to_clk() 221 reg = EXYNOS5_FSEL_50MHZ; in exynos5_rate_to_clk() 252 static u32 reg; in exynos5_usbdrd_pipe3_set_refclk() local 256 reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST); in exynos5_usbdrd_pipe3_set_refclk() [all …]
/linux-4.4.14/arch/mips/bcm63xx/
D	timer.c	58 u32 reg; in bcm63xx_timer_enable() local 66 reg = bcm_timer_readl(TIMER_CTLx_REG(id)); in bcm63xx_timer_enable() 67 reg \|= TIMER_CTL_ENABLE_MASK; in bcm63xx_timer_enable() 68 bcm_timer_writel(reg, TIMER_CTLx_REG(id)); in bcm63xx_timer_enable() 70 reg = bcm_timer_readl(TIMER_IRQSTAT_REG); in bcm63xx_timer_enable() 71 reg \|= TIMER_IRQSTAT_TIMER_IR_EN(id); in bcm63xx_timer_enable() 72 bcm_timer_writel(reg, TIMER_IRQSTAT_REG); in bcm63xx_timer_enable() 82 u32 reg; in bcm63xx_timer_disable() local 90 reg = bcm_timer_readl(TIMER_CTLx_REG(id)); in bcm63xx_timer_disable() 91 reg &= ~TIMER_CTL_ENABLE_MASK; in bcm63xx_timer_disable() [all …]
D	setup.c	34 u32 reg; in bcm6348_a1_reboot() local 38 reg = bcm_perf_readl(PERF_SOFTRESET_REG); in bcm6348_a1_reboot() 39 reg &= ~SOFTRESET_6348_ALL; in bcm6348_a1_reboot() 40 bcm_perf_writel(reg, PERF_SOFTRESET_REG); in bcm6348_a1_reboot() 43 reg = bcm_perf_readl(PERF_SOFTRESET_REG); in bcm6348_a1_reboot() 44 reg \|= SOFTRESET_6348_ALL; in bcm6348_a1_reboot() 45 bcm_perf_writel(reg, PERF_SOFTRESET_REG); in bcm6348_a1_reboot() 67 u32 reg, perf_regs[2] = { 0, 0 }; in bcm63xx_machine_reboot() local 99 reg = bcm_perf_readl(perf_regs[i]); in bcm63xx_machine_reboot() 101 reg &= ~EXTIRQ_CFG_MASK_ALL_6348; in bcm63xx_machine_reboot() [all …]
/linux-4.4.14/sound/pci/
D	ad1889.c	81 u16 reg; /* reg setup / member 110 ad1889_readw(struct snd_ad1889 chip, unsigned reg) in ad1889_readw() argument 112 return readw(chip->iobase + reg); in ad1889_readw() 116 ad1889_writew(struct snd_ad1889 chip, unsigned reg, u16 val) in ad1889_writew() argument 118 writew(val, chip->iobase + reg); in ad1889_writew() 122 ad1889_readl(struct snd_ad1889 chip, unsigned reg) in ad1889_readl() argument 124 return readl(chip->iobase + reg); in ad1889_readl() 128 ad1889_writel(struct snd_ad1889 *chip, unsigned reg, u32 val) in ad1889_writel() argument 130 writel(val, chip->iobase + reg); in ad1889_writel() 197 u16 reg; in ad1889_channel_reset() local [all …]
D	azt3328.c	334 snd_azf3328_io_reg_setb(unsigned reg, u8 mask, bool do_set) in snd_azf3328_io_reg_setb() argument 339 u8 prev = inb(reg), new; in snd_azf3328_io_reg_setb() 344 outb(new, reg); in snd_azf3328_io_reg_setb() 353 unsigned reg, in snd_azf3328_codec_outb() argument 357 outb(value, codec->io_base + reg); in snd_azf3328_codec_outb() 361 snd_azf3328_codec_inb(const struct snd_azf3328_codec_data codec, unsigned reg) in snd_azf3328_codec_inb() argument 363 return inb(codec->io_base + reg); in snd_azf3328_codec_inb() 368 unsigned reg, in snd_azf3328_codec_outw() argument 372 outw(value, codec->io_base + reg); in snd_azf3328_codec_outw() 376 snd_azf3328_codec_inw(const struct snd_azf3328_codec_data codec, unsigned reg) in snd_azf3328_codec_inw() argument [all …]
/linux-4.4.14/sound/soc/codecs/
D	rl6347a.c	19 int rl6347a_hw_write(void context, unsigned int reg, unsigned int value) in rl6347a_hw_write() argument 27 if (reg <= 0xff) { in rl6347a_hw_write() 28 rl6347a_hw_write(client, RL6347A_COEF_INDEX, reg); in rl6347a_hw_write() 30 if (reg == rl6347a->index_cache[i].reg) { in rl6347a_hw_write() 36 reg = RL6347A_PROC_COEF; in rl6347a_hw_write() 39 data[0] = (reg >> 24) & 0xff; in rl6347a_hw_write() 40 data[1] = (reg >> 16) & 0xff; in rl6347a_hw_write() 46 data[2] = ((reg >> 8) & 0xff) \| ((value >> 8) & 0xff); in rl6347a_hw_write() 62 int rl6347a_hw_read(void context, unsigned int reg, unsigned int *value) in rl6347a_hw_read() argument 71 if (reg <= 0xff) { in rl6347a_hw_read() [all …]
D	wm8961.c	113 static bool wm8961_volatile(struct device dev, unsigned int reg) in wm8961_volatile() argument 115 switch (reg) { in wm8961_volatile() 126 static bool wm8961_readable(struct device dev, unsigned int reg) in wm8961_readable() argument 128 switch (reg) { in wm8961_readable() 511 u16 reg; in wm8961_hw_params() local 527 reg = snd_soc_read(codec, WM8961_ADDITIONAL_CONTROL_3); in wm8961_hw_params() 528 reg &= ~WM8961_SAMPLE_RATE_MASK; in wm8961_hw_params() 529 reg \|= wm8961_srate[best].val; in wm8961_hw_params() 530 snd_soc_write(codec, WM8961_ADDITIONAL_CONTROL_3, reg); in wm8961_hw_params() 560 reg = snd_soc_read(codec, WM8961_CLOCKING_4); in wm8961_hw_params() [all …]
D	wm9713.c	43 unsigned int reg); 45 unsigned int reg, unsigned int val); 281 update.reg = wm9713_mixer_mute_regs[shift]; in wm9713_hp_mixer_put() 678 unsigned int reg) in ac97_read() argument 683 if (reg == AC97_RESET \|\| reg == AC97_GPIO_STATUS \|\| in ac97_read() 684 reg == AC97_VENDOR_ID1 \|\| reg == AC97_VENDOR_ID2 \|\| in ac97_read() 685 reg == AC97_CD) in ac97_read() 686 return soc_ac97_ops->read(wm9713->ac97, reg); in ac97_read() 688 reg = reg >> 1; in ac97_read() 690 if (reg >= (ARRAY_SIZE(wm9713_reg))) in ac97_read() [all …]
/linux-4.4.14/arch/arm/kvm/
D	guest.c	49 static int get_core_reg(struct kvm_vcpu vcpu, const struct kvm_one_reg reg) in get_core_reg() argument 51 u32 __user uaddr = (u32 __user )(long)reg->addr; in get_core_reg() 55 if (KVM_REG_SIZE(reg->id) != 4) in get_core_reg() 59 off = core_reg_offset_from_id(reg->id); in get_core_reg() 60 if (off >= sizeof(regs) / KVM_REG_SIZE(reg->id)) in get_core_reg() 66 static int set_core_reg(struct kvm_vcpu vcpu, const struct kvm_one_reg reg) in set_core_reg() argument 68 u32 __user uaddr = (u32 __user )(long)reg->addr; in set_core_reg() 72 if (KVM_REG_SIZE(reg->id) != 4) in set_core_reg() 76 off = core_reg_offset_from_id(reg->id); in set_core_reg() 77 if (off >= sizeof(regs) / KVM_REG_SIZE(reg->id)) in set_core_reg() [all …]
/linux-4.4.14/drivers/media/i2c/
D	adv7183.c	84 static inline int adv7183_read(struct v4l2_subdev sd, unsigned char reg) in adv7183_read() argument 88 return i2c_smbus_read_byte_data(client, reg); in adv7183_read() 91 static inline int adv7183_write(struct v4l2_subdev sd, unsigned char reg, in adv7183_write() argument 96 return i2c_smbus_write_byte_data(client, reg, value); in adv7183_write() 102 unsigned char reg, data; in adv7183_writeregs() local 111 reg = *regs++; in adv7183_writeregs() 115 adv7183_write(sd, reg, data); in adv7183_writeregs() 212 int reg; in adv7183_s_std() local 214 reg = adv7183_read(sd, ADV7183_IN_CTRL) & 0xF; in adv7183_s_std() 216 reg \|= 0x60; in adv7183_s_std() [all …]
/linux-4.4.14/drivers/staging/lustre/lustre/libcfs/
D	kernel_user_comm.c	115 struct kkuc_reg reg; in libcfs_kkuc_group_add() local 127 reg = kmalloc(sizeof(reg), 0); in libcfs_kkuc_group_add() 128 if (reg == NULL) in libcfs_kkuc_group_add() 131 reg->kr_fp = filp; in libcfs_kkuc_group_add() 132 reg->kr_uid = uid; in libcfs_kkuc_group_add() 133 reg->kr_data = data; in libcfs_kkuc_group_add() 138 list_add(&reg->kr_chain, &kkuc_groups[group]); in libcfs_kkuc_group_add() 149 struct kkuc_reg reg, next; in libcfs_kkuc_group_rem() local 166 list_for_each_entry_safe(reg, next, &kkuc_groups[group], kr_chain) { in libcfs_kkuc_group_rem() 167 if ((uid == 0) \|\| (uid == reg->kr_uid)) { in libcfs_kkuc_group_rem() [all …]
/linux-4.4.14/drivers/gpu/drm/i915/
D	intel_uncore.c	528 #define NEEDS_FORCE_WAKE(reg) \ argument 529 ((reg) < 0x40000 && (reg) != FORCEWAKE) 531 #define REG_RANGE(reg, start, end) ((reg) >= (start) && (reg) < (end)) argument 533 #define FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg) \ argument 534 (REG_RANGE((reg), 0x2000, 0x4000) \|\| \ 535 REG_RANGE((reg), 0x5000, 0x8000) \|\| \ 536 REG_RANGE((reg), 0xB000, 0x12000) \|\| \ 537 REG_RANGE((reg), 0x2E000, 0x30000)) 539 #define FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg) \ argument 540 (REG_RANGE((reg), 0x12000, 0x14000) \|\| \ [all …]
D	intel_sideband.c	102 u32 vlv_bunit_read(struct drm_i915_private dev_priv, u32 reg) in vlv_bunit_read() argument 107 SB_CRRDDA_NP, reg, &val); in vlv_bunit_read() 112 void vlv_bunit_write(struct drm_i915_private dev_priv, u32 reg, u32 val) in vlv_bunit_write() argument 115 SB_CRWRDA_NP, reg, &val); in vlv_bunit_write() 132 u32 vlv_gpio_nc_read(struct drm_i915_private dev_priv, u32 reg) in vlv_gpio_nc_read() argument 136 SB_CRRDDA_NP, reg, &val); in vlv_gpio_nc_read() 140 void vlv_gpio_nc_write(struct drm_i915_private dev_priv, u32 reg, u32 val) in vlv_gpio_nc_write() argument 143 SB_CRWRDA_NP, reg, &val); in vlv_gpio_nc_write() 146 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg) in vlv_cck_read() argument 150 SB_CRRDDA_NP, reg, &val); in vlv_cck_read() [all …]
/linux-4.4.14/sound/pci/oxygen/
D	oxygen_io.c	28 u8 oxygen_read8(struct oxygen chip, unsigned int reg) in oxygen_read8() argument 30 return inb(chip->addr + reg); in oxygen_read8() 34 u16 oxygen_read16(struct oxygen chip, unsigned int reg) in oxygen_read16() argument 36 return inw(chip->addr + reg); in oxygen_read16() 40 u32 oxygen_read32(struct oxygen chip, unsigned int reg) in oxygen_read32() argument 42 return inl(chip->addr + reg); in oxygen_read32() 46 void oxygen_write8(struct oxygen chip, unsigned int reg, u8 value) in oxygen_write8() argument 48 outb(value, chip->addr + reg); in oxygen_write8() 49 chip->saved_registers._8[reg] = value; in oxygen_write8() 53 void oxygen_write16(struct oxygen *chip, unsigned int reg, u16 value) in oxygen_write16() argument [all …]
/linux-4.4.14/drivers/clk/imx/
D	clk-gate2.c	32 void __iomem reg; member 44 u32 reg; in clk_gate2_enable() local 52 reg = readl(gate->reg); in clk_gate2_enable() 53 reg \|= 3 << gate->bit_idx; in clk_gate2_enable() 54 writel(reg, gate->reg); in clk_gate2_enable() 65 u32 reg; in clk_gate2_disable() local 77 reg = readl(gate->reg); in clk_gate2_disable() 78 reg &= ~(3 << gate->bit_idx); in clk_gate2_disable() 79 writel(reg, gate->reg); in clk_gate2_disable() 85 static int clk_gate2_reg_is_enabled(void __iomem reg, u8 bit_idx) in clk_gate2_reg_is_enabled() argument [all …]
/linux-4.4.14/drivers/media/platform/blackfin/
D	ppi.c	56 struct bfin_ppi_regs reg = info->base; in ppi_irq_err() local 62 status = bfin_read16(&reg->status); in ppi_irq_err() 65 bfin_write16(&reg->status, 0xff00); in ppi_irq_err() 70 struct bfin_eppi_regs reg = info->base; in ppi_irq_err() local 73 status = bfin_read16(&reg->status); in ppi_irq_err() 76 bfin_write16(&reg->status, 0xffff); in ppi_irq_err() 81 struct bfin_eppi3_regs reg = info->base; in ppi_irq_err() local 84 stat = bfin_read32(&reg->stat); in ppi_irq_err() 87 bfin_write32(&reg->stat, 0xc0ff); in ppi_irq_err() 141 struct bfin_ppi_regs reg = info->base; in ppi_start() local [all …]
/linux-4.4.14/drivers/media/platform/s5p-mfc/
D	s5p_mfc_opr_v6.c	640 unsigned int reg = 0; in s5p_mfc_set_enc_params() local 657 reg = 0; in s5p_mfc_set_enc_params() 658 reg \|= p->gop_size & 0xFFFF; in s5p_mfc_set_enc_params() 659 writel(reg, mfc_regs->e_gop_config); in s5p_mfc_set_enc_params() 664 reg = 0; in s5p_mfc_set_enc_params() 666 reg \|= (0x1 << 3); in s5p_mfc_set_enc_params() 667 writel(reg, mfc_regs->e_enc_options); in s5p_mfc_set_enc_params() 670 reg \|= (0x1 << 3); in s5p_mfc_set_enc_params() 671 writel(reg, mfc_regs->e_enc_options); in s5p_mfc_set_enc_params() 674 reg &= ~(0x1 << 3); in s5p_mfc_set_enc_params() [all …]
/linux-4.4.14/sound/soc/tegra/
D	tegra30_ahub.c	36 static inline void tegra30_apbif_write(u32 reg, u32 val) in tegra30_apbif_write() argument 38 regmap_write(ahub->regmap_apbif, reg, val); in tegra30_apbif_write() 41 static inline u32 tegra30_apbif_read(u32 reg) in tegra30_apbif_read() argument 44 regmap_read(ahub->regmap_apbif, reg, &val); in tegra30_apbif_read() 48 static inline void tegra30_audio_write(u32 reg, u32 val) in tegra30_audio_write() argument 50 regmap_write(ahub->regmap_ahub, reg, val); in tegra30_audio_write() 102 u32 reg, val; in tegra30_ahub_allocate_rx_fifo() local 119 reg = TEGRA30_AHUB_CHANNEL_CTRL + in tegra30_ahub_allocate_rx_fifo() 121 val = tegra30_apbif_read(reg); in tegra30_ahub_allocate_rx_fifo() 127 tegra30_apbif_write(reg, val); in tegra30_ahub_allocate_rx_fifo() [all …]
/linux-4.4.14/arch/arm64/kvm/
D	guest.c	51 static int get_core_reg(struct kvm_vcpu vcpu, const struct kvm_one_reg reg) in get_core_reg() argument 59 __u32 __user uaddr = (__u32 __user )(unsigned long)reg->addr; in get_core_reg() 65 off = core_reg_offset_from_id(reg->id); in get_core_reg() 67 (off + (KVM_REG_SIZE(reg->id) / sizeof(__u32))) >= nr_regs) in get_core_reg() 70 if (copy_to_user(uaddr, ((u32 )regs) + off, KVM_REG_SIZE(reg->id))) in get_core_reg() 76 static int set_core_reg(struct kvm_vcpu vcpu, const struct kvm_one_reg reg) in set_core_reg() argument 78 __u32 __user uaddr = (__u32 __user *)(unsigned long)reg->addr; in set_core_reg() 87 off = core_reg_offset_from_id(reg->id); in set_core_reg() 89 (off + (KVM_REG_SIZE(reg->id) / sizeof(__u32))) >= nr_regs) in set_core_reg() 92 if (KVM_REG_SIZE(reg->id) > sizeof(tmp)) in set_core_reg() [all …]
/linux-4.4.14/drivers/pwm/
D	pwm-pca9685.c	96 unsigned int reg; in pca9685_pwm_config() local 141 reg = PCA9685_ALL_LED_OFF_H; in pca9685_pwm_config() 143 reg = LED_N_OFF_H(pwm->hwpwm); in pca9685_pwm_config() 145 regmap_write(pca->regmap, reg, LED_FULL); in pca9685_pwm_config() 153 reg = PCA9685_ALL_LED_OFF_L; in pca9685_pwm_config() 155 reg = LED_N_OFF_L(pwm->hwpwm); in pca9685_pwm_config() 157 regmap_write(pca->regmap, reg, 0x0); in pca9685_pwm_config() 160 reg = PCA9685_ALL_LED_OFF_H; in pca9685_pwm_config() 162 reg = LED_N_OFF_H(pwm->hwpwm); in pca9685_pwm_config() 164 regmap_write(pca->regmap, reg, 0x0); in pca9685_pwm_config() [all …]
/linux-4.4.14/drivers/clk/mvebu/
D	clk-corediv.c	57 void __iomem *reg; member 83 return !!(readl(corediv->reg) & enable_mask); in clk_corediv_is_enabled() 92 u32 reg; in clk_corediv_enable() local 96 reg = readl(corediv->reg); in clk_corediv_enable() 97 reg \|= (BIT(desc->fieldbit) << soc_desc->enable_bit_offset); in clk_corediv_enable() 98 writel(reg, corediv->reg); in clk_corediv_enable() 111 u32 reg; in clk_corediv_disable() local 115 reg = readl(corediv->reg); in clk_corediv_disable() 116 reg &= ~(BIT(desc->fieldbit) << soc_desc->enable_bit_offset); in clk_corediv_disable() 117 writel(reg, corediv->reg); in clk_corediv_disable() [all …]
/linux-4.4.14/drivers/staging/sm750fb/
D	ddk750_display.c	183 unsigned int reg; in swPanelPowerSequence() local 186 reg = PEEK32(PANEL_DISPLAY_CTRL); in swPanelPowerSequence() 187 reg = FIELD_VALUE(reg, PANEL_DISPLAY_CTRL, FPEN, disp); in swPanelPowerSequence() 188 POKE32(PANEL_DISPLAY_CTRL, reg); in swPanelPowerSequence() 191 reg = PEEK32(PANEL_DISPLAY_CTRL); in swPanelPowerSequence() 192 reg = FIELD_VALUE(reg, PANEL_DISPLAY_CTRL, DATA, disp); in swPanelPowerSequence() 193 POKE32(PANEL_DISPLAY_CTRL, reg); in swPanelPowerSequence() 196 reg = PEEK32(PANEL_DISPLAY_CTRL); in swPanelPowerSequence() 197 reg = FIELD_VALUE(reg, PANEL_DISPLAY_CTRL, VBIASEN, disp); in swPanelPowerSequence() 198 POKE32(PANEL_DISPLAY_CTRL, reg); in swPanelPowerSequence() [all …]
/linux-4.4.14/arch/mips/ath79/
D	common.c	59 void ath79_ddr_wb_flush(u32 reg) in ath79_ddr_wb_flush() argument 61 void __iomem *flush_reg = ath79_ddr_wb_flush_base + reg; in ath79_ddr_wb_flush() 93 u32 reg; in ath79_device_reset_set() local 97 reg = AR71XX_RESET_REG_RESET_MODULE; in ath79_device_reset_set() 99 reg = AR724X_RESET_REG_RESET_MODULE; in ath79_device_reset_set() 101 reg = AR913X_RESET_REG_RESET_MODULE; in ath79_device_reset_set() 103 reg = AR933X_RESET_REG_RESET_MODULE; in ath79_device_reset_set() 105 reg = AR934X_RESET_REG_RESET_MODULE; in ath79_device_reset_set() 107 reg = QCA955X_RESET_REG_RESET_MODULE; in ath79_device_reset_set() 112 t = ath79_reset_rr(reg); in ath79_device_reset_set() [all …]
/linux-4.4.14/drivers/net/phy/
D	broadcom.c	180 int reg, err; in bcm54xx_config_init() local 182 reg = phy_read(phydev, MII_BCM54XX_ECR); in bcm54xx_config_init() 183 if (reg < 0) in bcm54xx_config_init() 184 return reg; in bcm54xx_config_init() 187 reg \|= MII_BCM54XX_ECR_IM; in bcm54xx_config_init() 188 err = phy_write(phydev, MII_BCM54XX_ECR, reg); in bcm54xx_config_init() 193 reg = ~(MII_BCM54XX_INT_DUPLEX \| in bcm54xx_config_init() 196 err = phy_write(phydev, MII_BCM54XX_IMR, reg); in bcm54xx_config_init() 217 int err, reg; in bcm5482_config_init() local 225 reg = bcm_phy_read_shadow(phydev, BCM5482_SHD_SSD); in bcm5482_config_init() [all …]
/linux-4.4.14/arch/mips/oprofile/
D	op_model_loongson3.c	51 } reg; variable 67 reg.reset_counter1 = 0; in loongson3_reg_setup() 68 reg.reset_counter2 = 0; in loongson3_reg_setup() 78 reg.reset_counter1 = 0x8000000000000000ULL - ctr[0].count; in loongson3_reg_setup() 88 reg.reset_counter2 = 0x8000000000000000ULL - ctr[1].count; in loongson3_reg_setup() 96 reg.control1 = control1; in loongson3_reg_setup() 97 reg.control2 = control2; in loongson3_reg_setup() 98 reg.ctr1_enable = ctr[0].enabled; in loongson3_reg_setup() 99 reg.ctr2_enable = ctr[1].enabled; in loongson3_reg_setup() 107 perfcount1 = reg.reset_counter1; in loongson3_cpu_setup() [all …]
D	op_model_loongson2.c	41 } reg; variable 56 reg.reset_counter1 = 0; in loongson2_reg_setup() 57 reg.reset_counter2 = 0; in loongson2_reg_setup() 65 reg.reset_counter1 = 0x80000000ULL - cfg[0].count; in loongson2_reg_setup() 70 reg.reset_counter2 = 0x80000000ULL - cfg[1].count; in loongson2_reg_setup() 81 reg.ctrl = ctrl; in loongson2_reg_setup() 83 reg.cnt1_enabled = cfg[0].enabled; in loongson2_reg_setup() 84 reg.cnt2_enabled = cfg[1].enabled; in loongson2_reg_setup() 89 write_c0_perfcnt((reg.reset_counter2 << 32) \| reg.reset_counter1); in loongson2_cpu_setup() 95 if (reg.cnt1_enabled \|\| reg.cnt2_enabled) in loongson2_cpu_start() [all …]
/linux-4.4.14/arch/cris/include/uapi/arch-v10/arch/
D	sv_addr_ag.h	28 #define IO_MASK(reg, field) IO_MASK_ (reg##_, field##_) argument 34 #define IO_STATE(reg, field, state) IO_STATE_ (reg##_, field##_, _##state) argument 40 #define IO_EXTRACT(reg, field, val) IO_EXTRACT_ (reg##_, field##_, val) argument 46 #define IO_STATE_VALUE(reg, field, state) \ argument 47 IO_STATE_VALUE_ (reg##_, field##_, _##state) 52 #define IO_FIELD(reg, field, val) IO_FIELD_ (reg##_, field##_, val) argument 57 #define IO_BITNR(reg, field) IO_BITNR_ (reg##_, field##_) argument 61 #define IO_WIDTH(reg, field) IO_WIDTH_ (reg##_, field##_) argument 67 #define IO_RD(reg) ((volatile u32)(reg)) argument 68 #define IO_RD_B(reg) ((volatile u8)(reg)) argument [all …]
/linux-4.4.14/include/linux/mtd/
D	sh_flctl.h	`30 #define FLCMNCR(f) (f->reg + 0x0) 31 #define FLCMDCR(f) (f->reg + 0x4) 32 #define FLCMCDR(f) (f->reg + 0x8) 33 #define FLADR(f) (f->reg + 0xC) 34 #define FLADR2(f) (f->reg + 0x3C) 35 #define FLDATAR(f) (f->reg + 0x10) 36 #define FLDTCNTR(f) (f->reg + 0x14) 37 #define FLINTDMACR(f) (f->reg + 0x18) 38 #define FLBSYTMR(f) (f->reg + 0x1C) 39 #define FLBSYCNT(f) (f->reg + 0x20) [all …]`
/linux-4.4.14/arch/mips/boot/dts/cavium-octeon/
D	octeon_68xx.dts	`30 reg = <0x10701 0x00000000 0x0 0x4000000>; 36 reg = <0x10700 0x00000800 0x0 0x100>; 58 reg = <0x11800 0x00003800 0x0 0x40>; 62 marvell,reg-init = 69 reg = <6>; 74 reg = <1>; 76 marvell,reg-init = <3 0x10 0 0x5777>, 83 reg = <2>; 85 marvell,reg-init = <3 0x10 0 0x5777>, 92 reg = <3>; [all …]`
D	octeon_3xxx.dts	`29 reg = <0x10700 0x00000000 0x0 0x7000>; 35 reg = <0x10700 0x00000800 0x0 0x100>; 57 reg = <0x11800 0x00001800 0x0 0x40>; 61 marvell,reg-init = 68 reg = <0>; 73 marvell,reg-init = 80 reg = <1>; 84 reg = <2>; 86 marvell,reg-init = <3 0x10 0 0x5777>, 92 reg = <3>; [all …]`
/linux-4.4.14/drivers/media/pci/tw68/
D	tw68.h	178 #define tw_readl(reg) readl(dev->lmmio + ((reg) >> 2)) argument 179 #define tw_readb(reg) readb(dev->bmmio + (reg)) argument 180 #define tw_writel(reg, value) writel((value), dev->lmmio + ((reg) >> 2)) argument 181 #define tw_writeb(reg, value) writeb((value), dev->bmmio + (reg)) argument 183 #define tw_andorl(reg, mask, value) \ argument 184 writel((readl(dev->lmmio+((reg)>>2)) & ~(mask)) \|\ 185 ((value) & (mask)), dev->lmmio+((reg)>>2)) 186 #define tw_andorb(reg, mask, value) \ argument 187 writeb((readb(dev->bmmio + (reg)) & ~(mask)) \|\ 188 ((value) & (mask)), dev->bmmio+(reg)) [all …]
/linux-4.4.14/drivers/mmc/host/
D	sdhci-iproc.c	37 #define REG_OFFSET_IN_BITS(reg) ((reg) << 3 & 0x18) argument 39 static inline u32 sdhci_iproc_readl(struct sdhci_host host, int reg) in sdhci_iproc_readl() argument 41 u32 val = readl(host->ioaddr + reg); in sdhci_iproc_readl() 44 mmc_hostname(host->mmc), reg, val); in sdhci_iproc_readl() 48 static u16 sdhci_iproc_readw(struct sdhci_host host, int reg) in sdhci_iproc_readw() argument 50 u32 val = sdhci_iproc_readl(host, (reg & ~3)); in sdhci_iproc_readw() 51 u16 word = val >> REG_OFFSET_IN_BITS(reg) & 0xffff; in sdhci_iproc_readw() 55 static u8 sdhci_iproc_readb(struct sdhci_host *host, int reg) in sdhci_iproc_readb() argument 57 u32 val = sdhci_iproc_readl(host, (reg & ~3)); in sdhci_iproc_readb() 58 u8 byte = val >> REG_OFFSET_IN_BITS(reg) & 0xff; in sdhci_iproc_readb() [all …]
/linux-4.4.14/drivers/base/regmap/
D	trace.h	`17 TP_PROTO(struct regmap map, unsigned int reg, 20 TP_ARGS(map, reg, val), 24 __field( unsigned int, reg ) 30 __entry->reg = reg; 35 (unsigned int)__entry->reg, 41 TP_PROTO(struct regmap map, unsigned int reg, 44 TP_ARGS(map, reg, val) 50 TP_PROTO(struct regmap map, unsigned int reg, 53 TP_ARGS(map, reg, val) 59 TP_PROTO(struct regmap map, unsigned int reg, [all …]`
/linux-4.4.14/drivers/misc/mei/
D	hw-me.c	91 u32 reg; in mei_me_mecsr_read() local 93 reg = mei_me_reg_read(to_me_hw(dev), ME_CSR_HA); in mei_me_mecsr_read() 94 trace_mei_reg_read(dev->dev, "ME_CSR_HA", ME_CSR_HA, reg); in mei_me_mecsr_read() 96 return reg; in mei_me_mecsr_read() 108 u32 reg; in mei_hcsr_read() local 110 reg = mei_me_reg_read(to_me_hw(dev), H_CSR); in mei_hcsr_read() 111 trace_mei_reg_read(dev->dev, "H_CSR", H_CSR, reg); in mei_hcsr_read() 113 return reg; in mei_hcsr_read() 122 static inline void mei_hcsr_write(struct mei_device *dev, u32 reg) in mei_hcsr_write() argument 124 trace_mei_reg_write(dev->dev, "H_CSR", H_CSR, reg); in mei_hcsr_write() [all …]
/linux-4.4.14/arch/sh/kernel/cpu/irq/
D	intc-sh5.c	84 unsigned long reg; in enable_intc_irq() local 91 reg = INTC_INTENB_0; in enable_intc_irq() 94 reg = INTC_INTENB_1; in enable_intc_irq() 98 __raw_writel(bitmask, reg); in enable_intc_irq() 104 unsigned long reg; in disable_intc_irq() local 108 reg = INTC_INTDSB_0; in disable_intc_irq() 111 reg = INTC_INTDSB_1; in disable_intc_irq() 115 __raw_writel(bitmask, reg); in disable_intc_irq() 127 unsigned long reg; in plat_irq_setup() local 145 for (reg = INTC_INTPRI_0, i = 0; i < INTC_INTPRI_PREGS; i++, reg += 8) in plat_irq_setup() [all …]
/linux-4.4.14/drivers/clk/sunxi/
D	clk-factors.c	39 #define FACTOR_GET(bit, len, reg) (((reg) & SETMASK(len, bit)) >> (bit)) argument 41 #define FACTOR_SET(bit, len, reg, val) \ argument 42 (((reg) & CLRMASK(len, bit)) \| (val << (bit))) 48 u32 reg; in clk_factors_recalc_rate() local 54 reg = readl(factors->reg); in clk_factors_recalc_rate() 58 n = FACTOR_GET(config->nshift, config->nwidth, reg); in clk_factors_recalc_rate() 60 k = FACTOR_GET(config->kshift, config->kwidth, reg); in clk_factors_recalc_rate() 62 m = FACTOR_GET(config->mshift, config->mwidth, reg); in clk_factors_recalc_rate() 64 p = FACTOR_GET(config->pshift, config->pwidth, reg); in clk_factors_recalc_rate() 124 u32 reg; in clk_factors_set_rate() local [all …]
/linux-4.4.14/arch/mips/boot/dts/netlogic/
D	xlp_svp.dts	`22 reg = <0 0x30100 0xa00>; 23 reg-shift = <2>; 24 reg-io-width = <4>; 32 reg = <0 0x31100 0xa00>; 33 reg-shift = <2>; 34 reg-io-width = <4>; 43 reg = <0 0x32100 0xa00>; 44 reg-shift = <2>; 45 reg-io-width = <4>; 54 reg = <0 0x33100 0xa00>; [all …]`
D	xlp_fvp.dts	`22 reg = <0 0x30100 0xa00>; 23 reg-shift = <2>; 24 reg-io-width = <4>; 32 reg = <0 0x31100 0xa00>; 33 reg-shift = <2>; 34 reg-io-width = <4>; 43 reg = <0 0x37100 0x20>; 44 reg-shift = <2>; 45 reg-io-width = <4>; 54 reg = <0 0x37120 0x20>; [all …]`
D	xlp_evp.dts	`22 reg = <0 0x30100 0xa00>; 23 reg-shift = <2>; 24 reg-io-width = <4>; 32 reg = <0 0x31100 0xa00>; 33 reg-shift = <2>; 34 reg-io-width = <4>; 43 reg = <0 0x32100 0xa00>; 44 reg-shift = <2>; 45 reg-io-width = <4>; 54 reg = <0 0x33100 0xa00>; [all …]`
/linux-4.4.14/arch/powerpc/kernel/
D	udbg_16550.c	46 static u8 (udbg_uart_in)(unsigned int reg); 47 static void (udbg_uart_out)(unsigned int reg, u8 data); 169 static u8 udbg_uart_in_pio(unsigned int reg) in udbg_uart_in_pio() argument 171 return inb(udbg_uart.pio_base + (reg * udbg_uart_stride)); in udbg_uart_in_pio() 174 static void udbg_uart_out_pio(unsigned int reg, u8 data) in udbg_uart_out_pio() argument 176 outb(data, udbg_uart.pio_base + (reg * udbg_uart_stride)); in udbg_uart_out_pio() 190 static u8 udbg_uart_in_mmio(unsigned int reg) in udbg_uart_in_mmio() argument 192 return in_8(udbg_uart.mmio_base + (reg * udbg_uart_stride)); in udbg_uart_in_mmio() 195 static void udbg_uart_out_mmio(unsigned int reg, u8 data) in udbg_uart_out_mmio() argument 197 out_8(udbg_uart.mmio_base + (reg * udbg_uart_stride), data); in udbg_uart_out_mmio() [all …]
/linux-4.4.14/arch/powerpc/include/asm/
D	dcr-native.h	44 extern void __mtdcr(unsigned int reg, unsigned int val); 45 extern unsigned int __mfdcr(unsigned int reg); 50 static inline unsigned int mfdcrx(unsigned int reg) in mfdcrx() argument 54 : "=r" (ret) : "r" (reg)); in mfdcrx() 58 static inline void mtdcrx(unsigned int reg, unsigned int val) in mtdcrx() argument 61 : : "r" (val), "r" (reg)); in mtdcrx() 89 static inline unsigned __mfdcri(int base_addr, int base_data, int reg) in __mfdcri() argument 96 mtdcrx(base_addr, reg); in __mfdcri() 99 __mtdcr(base_addr, reg); in __mfdcri() 106 static inline void __mtdcri(int base_addr, int base_data, int reg, in __mtdcri() argument [all …]
/linux-4.4.14/arch/mips/emma/markeins/
D	irq.c	79 u32 reg; in emma2rh_sw_irq_enable() local 81 reg = emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN); in emma2rh_sw_irq_enable() 82 reg \|= 1 << irq; in emma2rh_sw_irq_enable() 83 emma2rh_out32(EMMA2RH_BHIF_SW_INT_EN, reg); in emma2rh_sw_irq_enable() 89 u32 reg; in emma2rh_sw_irq_disable() local 91 reg = emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN); in emma2rh_sw_irq_disable() 92 reg &= ~(1 << irq); in emma2rh_sw_irq_disable() 93 emma2rh_out32(EMMA2RH_BHIF_SW_INT_EN, reg); in emma2rh_sw_irq_disable() 115 u32 reg; in emma2rh_gpio_irq_enable() local 117 reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK); in emma2rh_gpio_irq_enable() [all …]
D	setup.c	65 u32 reg; in detect_bus_frequency() local 68 reg = emma2rh_in32(EMMA2RH_BHIF_STRAP_0); in detect_bus_frequency() 69 reg = (reg >> 4) & 0x3; in detect_bus_frequency() 71 return emma2rh_clock[reg]; in detect_bus_frequency() 76 u32 reg; in plat_time_init() local 80 reg = emma2rh_in32(EMMA2RH_BHIF_STRAP_0); in plat_time_init() 81 if ((reg & 0x3) == 0) in plat_time_init() 82 reg = (reg >> 6) & 0x3; in plat_time_init() 84 reg = emma2rh_in32(EMMA2RH_BHIF_MAIN_CTRL); in plat_time_init() 85 reg = (reg >> 4) & 0x3; in plat_time_init() [all …]
/linux-4.4.14/drivers/misc/
D	ad525x_dpot.c	102 static inline int dpot_read_r8d8(struct dpot_data dpot, u8 reg) in dpot_read_r8d8() argument 104 return dpot->bdata.bops->read_r8d8(dpot->bdata.client, reg); in dpot_read_r8d8() 107 static inline int dpot_read_r8d16(struct dpot_data dpot, u8 reg) in dpot_read_r8d16() argument 109 return dpot->bdata.bops->read_r8d16(dpot->bdata.client, reg); in dpot_read_r8d16() 117 static inline int dpot_write_r8d8(struct dpot_data dpot, u8 reg, u16 val) in dpot_write_r8d8() argument 119 return dpot->bdata.bops->write_r8d8(dpot->bdata.client, reg, val); in dpot_write_r8d8() 122 static inline int dpot_write_r8d16(struct dpot_data dpot, u8 reg, u16 val) in dpot_write_r8d16() argument 124 return dpot->bdata.bops->write_r8d16(dpot->bdata.client, reg, val); in dpot_write_r8d16() 127 static s32 dpot_read_spi(struct dpot_data *dpot, u8 reg) in dpot_read_spi() argument 132 if (!(reg & (DPOT_ADDR_EEPROM \| DPOT_ADDR_CMD))) { in dpot_read_spi() [all …]
/linux-4.4.14/sound/synth/emux/
D	emux_proc.c	67 vp->reg.parm.moddelay, in snd_emux_proc_info_read() 68 vp->reg.parm.modatkhld, in snd_emux_proc_info_read() 69 vp->reg.parm.moddcysus, in snd_emux_proc_info_read() 70 vp->reg.parm.modrelease); in snd_emux_proc_info_read() 72 vp->reg.parm.voldelay, in snd_emux_proc_info_read() 73 vp->reg.parm.volatkhld, in snd_emux_proc_info_read() 74 vp->reg.parm.voldcysus, in snd_emux_proc_info_read() 75 vp->reg.parm.volrelease); in snd_emux_proc_info_read() 77 vp->reg.parm.lfo1delay, in snd_emux_proc_info_read() 78 vp->reg.parm.lfo2delay, in snd_emux_proc_info_read() [all …]
/linux-4.4.14/arch/x86/platform/ce4100/
D	falconfalls.dts	`24 reg = <0>; 39 reg = <0xfec00000 0x1000>; 44 reg = <0xfed00000 0x200>; 49 reg = <0xfee00000 0x1000>; 67 reg = <0x100 0x0 0x0 0x0 0x0>; 77 reg = <0x0800 0x0 0x0 0x0 0x0>; 88 reg = <0x11000 0x0 0x0 0x0 0x0>; 98 reg = <0x11800 0x0 0x0 0x0 0x0>; 108 reg = <0x12000 0x0 0x0 0x0 0x0>; 118 reg = <0x12100 0x0 0x0 0x0 0x0>; [all …]`
/linux-4.4.14/arch/powerpc/boot/dts/
D	c2k.dts	`36 reg = <0>; 49 reg = <0x00000000 0x40000000>; /* 1GB */ 58 reg = <0xd8000000 0x00010000>; 59 virtual-reg = <0xd8000000>; 74 reg = <0x2000 4>; 78 reg = <0>; 83 reg = <1>; 88 reg = <2>; 96 reg = <0x2000 0x2000>; 100 reg = <0>; [all …]`
D	lite5200.dts	`28 reg = <0>; 41 reg = <0x00000000 0x04000000>; // 64MB 49 reg = <0xf0000000 0x00000100>; 55 reg = <0x200 0x38>; 63 reg = <0x500 0x80>; 68 reg = <0x600 0x10>; 75 reg = <0x610 0x10>; 81 reg = <0x620 0x10>; 87 reg = <0x630 0x10>; 93 reg = <0x640 0x10>; [all …]`
/linux-4.4.14/drivers/pinctrl/spear/
D	pinctrl-spear320.c	`36 .reg = MODE_CONFIG_REG, 44 .reg = MODE_CONFIG_REG, 52 .reg = MODE_CONFIG_REG, 60 .reg = MODE_CONFIG_REG, 68 .reg = MODE_EXT_CONFIG_REG, 465 .reg = IP_SEL_PAD_60_69_REG, 469 .reg = IP_SEL_PAD_70_79_REG, 477 .reg = IP_SEL_PAD_80_89_REG, 483 .reg = IP_SEL_PAD_90_99_REG, 522 .reg = PMX_CONFIG_REG, [all …]`
/linux-4.4.14/drivers/net/can/
D	bfin_can.c	174 struct bfin_can_regs __iomem reg = priv->membase; in bfin_can_set_bittiming() local 189 writew(clk, &reg->clock); in bfin_can_set_bittiming() 190 writew(timing, &reg->timing); in bfin_can_set_bittiming() 200 struct bfin_can_regs __iomem reg = priv->membase; in bfin_can_set_reset_mode() local 205 writew(0, &reg->mbim1); in bfin_can_set_reset_mode() 206 writew(0, &reg->mbim2); in bfin_can_set_reset_mode() 207 writew(0, &reg->gim); in bfin_can_set_reset_mode() 210 writew(SRS \| CCR, &reg->control); in bfin_can_set_reset_mode() 211 writew(CCR, &reg->control); in bfin_can_set_reset_mode() 212 while (!(readw(&reg->control) & CCA)) { in bfin_can_set_reset_mode() [all …]
/linux-4.4.14/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/
D	iop_version_defs_asm.h	15 #define REG_FIELD( scope, reg, field, value ) \ argument 16 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) 21 #define REG_STATE( scope, reg, field, symbolic_value ) \ argument 22 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) 27 #define REG_MASK( scope, reg, field ) \ argument 28 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) 33 #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb argument 37 #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit argument 41 #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) argument 46 #define REG_ADDR_VECT( scope, inst, reg, index ) \ argument [all …]
/linux-4.4.14/arch/cris/include/arch-v32/arch/hwregs/iop/asm/
D	iop_version_defs_asm.h	18 #define REG_FIELD( scope, reg, field, value ) \ argument 19 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) 24 #define REG_STATE( scope, reg, field, symbolic_value ) \ argument 25 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) 30 #define REG_MASK( scope, reg, field ) \ argument 31 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) 36 #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb argument 40 #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit argument 44 #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) argument 49 #define REG_ADDR_VECT( scope, inst, reg, index ) \ argument [all …]
/linux-4.4.14/arch/mips/boot/dts/brcm/
D	bcm7346.dtsi	`15 reg = <0>; 21 reg = <1>; 56 reg = <0x411400 0x30>, <0x411600 0x30>; 67 reg = <0x403000 0x30>; 76 reg = <0x400000 0xdc>; 88 reg = <0x406780 0x8>; 103 reg = <0x408b80 0x8>; 120 reg = <0x404000 0x51c>; 131 reg = <0x406900 0x20>; 132 reg-io-width = <0x4>; [all …]`
/linux-4.4.14/net/netfilter/
D	core.c	66 const struct nf_hook_ops reg) in nf_find_hook_list() argument 70 if (reg->pf != NFPROTO_NETDEV) in nf_find_hook_list() 71 hook_list = &net->nf.hooks[reg->pf][reg->hooknum]; in nf_find_hook_list() 72 else if (reg->hooknum == NF_NETDEV_INGRESS) { in nf_find_hook_list() 74 if (reg->dev && dev_net(reg->dev) == net) in nf_find_hook_list() 75 hook_list = &reg->dev->nf_hooks_ingress; in nf_find_hook_list() 86 int nf_register_net_hook(struct net net, const struct nf_hook_ops reg) in nf_register_net_hook() argument 96 entry->orig_ops = reg; in nf_register_net_hook() 97 entry->ops = reg; in nf_register_net_hook() 99 hook_list = nf_find_hook_list(net, reg); in nf_register_net_hook() [all …]
/linux-4.4.14/drivers/media/pci/zoran/
D	zr36060.c	77 u16 reg) in zr36060_read() argument 84 reg)) & 0xff; in zr36060_read() 97 u16 reg, in zr36060_write() argument 101 dprintk(4, "0x%02x @0x%04x\n", value, reg); in zr36060_write() 105 ptr->codec->master_data->writereg(ptr->codec, reg, value); in zr36060_write() 600 u32 reg; in zr36060_set_video() local 619 reg = (!pol->vsync_pol ? ZR060_VPR_VSPol : 0) in zr36060_set_video() 627 zr36060_write(ptr, ZR060_VPR, reg); in zr36060_set_video() 629 reg = 0; in zr36060_set_video() 636 reg \|= ZR060_SR_HScale2; in zr36060_set_video() [all …]
/linux-4.4.14/arch/alpha/lib/
D	fpreg.c	8 #define STT(reg,val) asm volatile ("ftoit $f"#reg",%0" : "=r"(val)); argument 10 #define STT(reg,val) asm volatile ("stt $f"#reg",%0" : "=m"(val)); argument 14 alpha_read_fp_reg (unsigned long reg) in alpha_read_fp_reg() argument 18 switch (reg) { in alpha_read_fp_reg() 57 #define LDT(reg,val) asm volatile ("itoft %0,$f"#reg : : "r"(val)); argument 59 #define LDT(reg,val) asm volatile ("ldt $f"#reg",%0" : : "m"(val)); argument 63 alpha_write_fp_reg (unsigned long reg, unsigned long val) in alpha_write_fp_reg() argument 65 switch (reg) { in alpha_write_fp_reg() 102 #define STS(reg,val) asm volatile ("ftois $f"#reg",%0" : "=r"(val)); argument 104 #define STS(reg,val) asm volatile ("sts $f"#reg",%0" : "=m"(val)); argument [all …]

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