174 	struct bfin_can_regs __iomem *reg = priv->membase;  in bfin_can_set_bittiming()  local
189 	writew(clk, &reg->clock);  in bfin_can_set_bittiming()
190 	writew(timing, &reg->timing);  in bfin_can_set_bittiming()
200 	struct bfin_can_regs __iomem *reg = priv->membase;  in bfin_can_set_reset_mode()  local
205 	writew(0, &reg->mbim1);  in bfin_can_set_reset_mode()
206 	writew(0, &reg->mbim2);  in bfin_can_set_reset_mode()
207 	writew(0, &reg->gim);  in bfin_can_set_reset_mode()
210 	writew(SRS | CCR, &reg->control);  in bfin_can_set_reset_mode()
211 	writew(CCR, &reg->control);  in bfin_can_set_reset_mode()
212 	while (!(readw(&reg->control) & CCA)) {  in bfin_can_set_reset_mode()
225 	writew(0, &reg->mc1);  in bfin_can_set_reset_mode()
226 	writew(0, &reg->mc2);  in bfin_can_set_reset_mode()
229 	writew(0xFFFF, &reg->md1);   /* mailbox 1-16 are RX */  in bfin_can_set_reset_mode()
230 	writew(0, &reg->md2);   /* mailbox 17-32 are TX */  in bfin_can_set_reset_mode()
234 		writew(0, &reg->chl[RECEIVE_STD_CHL + i].id0);  in bfin_can_set_reset_mode()
235 		writew(AME, &reg->chl[RECEIVE_STD_CHL + i].id1);  in bfin_can_set_reset_mode()
236 		writew(0, &reg->chl[RECEIVE_STD_CHL + i].dlc);  in bfin_can_set_reset_mode()
237 		writew(0x1FFF, &reg->msk[RECEIVE_STD_CHL + i].amh);  in bfin_can_set_reset_mode()
238 		writew(0xFFFF, &reg->msk[RECEIVE_STD_CHL + i].aml);  in bfin_can_set_reset_mode()
243 		writew(0, &reg->chl[RECEIVE_EXT_CHL + i].id0);  in bfin_can_set_reset_mode()
244 		writew(AME | IDE, &reg->chl[RECEIVE_EXT_CHL + i].id1);  in bfin_can_set_reset_mode()
245 		writew(0, &reg->chl[RECEIVE_EXT_CHL + i].dlc);  in bfin_can_set_reset_mode()
246 		writew(0x1FFF, &reg->msk[RECEIVE_EXT_CHL + i].amh);  in bfin_can_set_reset_mode()
247 		writew(0xFFFF, &reg->msk[RECEIVE_EXT_CHL + i].aml);  in bfin_can_set_reset_mode()
250 	writew(BIT(TRANSMIT_CHL - 16), &reg->mc2);  in bfin_can_set_reset_mode()
251 	writew(BIT(RECEIVE_STD_CHL) + BIT(RECEIVE_EXT_CHL), &reg->mc1);  in bfin_can_set_reset_mode()
259 	struct bfin_can_regs __iomem *reg = priv->membase;  in bfin_can_set_normal_mode()  local
265 	writew(readw(&reg->control) & ~CCR, &reg->control);  in bfin_can_set_normal_mode()
267 	while (readw(&reg->status) & CCA) {  in bfin_can_set_normal_mode()
278 	writew(0xFFFF, &reg->mbtif1);  in bfin_can_set_normal_mode()
279 	writew(0xFFFF, &reg->mbtif2);  in bfin_can_set_normal_mode()
280 	writew(0xFFFF, &reg->mbrif1);  in bfin_can_set_normal_mode()
281 	writew(0xFFFF, &reg->mbrif2);  in bfin_can_set_normal_mode()
286 	writew(0x7FF, &reg->gis); /* overwrites with '1' */  in bfin_can_set_normal_mode()
293 	writew(BIT(RECEIVE_STD_CHL) + BIT(RECEIVE_EXT_CHL), &reg->mbim1);  in bfin_can_set_normal_mode()
294 	writew(BIT(TRANSMIT_CHL - 16), &reg->mbim2);  in bfin_can_set_normal_mode()
296 	writew(EPIM | BOIM | RMLIM, &reg->gim);  in bfin_can_set_normal_mode()
331 	struct bfin_can_regs __iomem *reg = priv->membase;  in bfin_can_get_berr_counter()  local
333 	u16 cec = readw(&reg->cec);  in bfin_can_get_berr_counter()
344 	struct bfin_can_regs __iomem *reg = priv->membase;  in bfin_can_start_xmit()  local
359 		writew(id, &reg->chl[TRANSMIT_CHL].id0);  in bfin_can_start_xmit()
365 	writew(val | AME, &reg->chl[TRANSMIT_CHL].id1);  in bfin_can_start_xmit()
371 		writew(val, &reg->chl[TRANSMIT_CHL].data[i]);  in bfin_can_start_xmit()
375 	writew(dlc, &reg->chl[TRANSMIT_CHL].dlc);  in bfin_can_start_xmit()
380 	writew(BIT(TRANSMIT_CHL - 16), &reg->trs2);  in bfin_can_start_xmit()
389 	struct bfin_can_regs __iomem *reg = priv->membase;  in bfin_can_rx()  local
403 		cf->can_id = ((readw(&reg->chl[RECEIVE_EXT_CHL].id1)  in bfin_can_rx()
405 			     + readw(&reg->chl[RECEIVE_EXT_CHL].id0);  in bfin_can_rx()
410 		cf->can_id = (readw(&reg->chl[RECEIVE_STD_CHL].id1)  in bfin_can_rx()
414 	if (readw(&reg->chl[obj].id1) & RTR)  in bfin_can_rx()
418 	cf->can_dlc = get_can_dlc(readw(&reg->chl[obj].dlc) & 0xF);  in bfin_can_rx()
422 		val = readw(&reg->chl[obj].data[i]);  in bfin_can_rx()
435 	struct bfin_can_regs __iomem *reg = priv->membase;  in bfin_can_err()  local
475 		u16 cec = readw(&reg->cec);  in bfin_can_err()
519 	struct bfin_can_regs __iomem *reg = priv->membase;  in bfin_can_interrupt()  local
523 	if ((irq == priv->tx_irq) && readw(&reg->mbtif2)) {  in bfin_can_interrupt()
525 		writew(0xFFFF, &reg->mbtif2);  in bfin_can_interrupt()
527 		stats->tx_bytes += readw(&reg->chl[TRANSMIT_CHL].dlc);  in bfin_can_interrupt()
530 	} else if ((irq == priv->rx_irq) && readw(&reg->mbrif1)) {  in bfin_can_interrupt()
532 		isrc = readw(&reg->mbrif1);  in bfin_can_interrupt()
533 		writew(0xFFFF, &reg->mbrif1);  in bfin_can_interrupt()
535 	} else if ((irq == priv->err_irq) && readw(&reg->gis)) {  in bfin_can_interrupt()
537 		isrc = readw(&reg->gis);  in bfin_can_interrupt()
538 		status = readw(&reg->esr);  in bfin_can_interrupt()
539 		writew(0x7FF, &reg->gis);  in bfin_can_interrupt()
733 	struct bfin_can_regs __iomem *reg = priv->membase;  in bfin_can_suspend()  local
738 		writew(readw(&reg->control) | SMR, &reg->control);  in bfin_can_suspend()
739 		while (!(readw(&reg->intr) & SMACK)) {  in bfin_can_suspend()
755 	struct bfin_can_regs __iomem *reg = priv->membase;  in bfin_can_resume()  local
759 		writew(0, &reg->intr);  in bfin_can_resume()