210 	u32 reg;  in mvebu_v7_pmsu_enable_l2_powerdown_onidle()  local
216 	reg = readl(pmsu_mp_base + L2C_NFABRIC_PM_CTL);  in mvebu_v7_pmsu_enable_l2_powerdown_onidle()
217 	reg |= L2C_NFABRIC_PM_CTL_PWR_DOWN;  in mvebu_v7_pmsu_enable_l2_powerdown_onidle()
218 	writel(reg, pmsu_mp_base + L2C_NFABRIC_PM_CTL);  in mvebu_v7_pmsu_enable_l2_powerdown_onidle()
231 	u32 reg;  in mvebu_v7_pmsu_idle_prepare()  local
241 	reg = readl(pmsu_mp_base + PMSU_STATUS_AND_MASK(hw_cpu));  in mvebu_v7_pmsu_idle_prepare()
242 	reg |= PMSU_STATUS_AND_MASK_CPU_IDLE_WAIT    |  in mvebu_v7_pmsu_idle_prepare()
248 	writel(reg, pmsu_mp_base + PMSU_STATUS_AND_MASK(hw_cpu));  in mvebu_v7_pmsu_idle_prepare()
250 	reg = readl(pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu));  in mvebu_v7_pmsu_idle_prepare()
253 		reg |= PMSU_CONTROL_AND_CONFIG_L2_PWDDN;  in mvebu_v7_pmsu_idle_prepare()
256 	reg |= PMSU_CONTROL_AND_CONFIG_PWDDN_REQ;  in mvebu_v7_pmsu_idle_prepare()
257 	writel(reg, pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu));  in mvebu_v7_pmsu_idle_prepare()
261 		reg = readl(pmsu_mp_base + PMSU_CPU_POWER_DOWN_CONTROL(hw_cpu));  in mvebu_v7_pmsu_idle_prepare()
262 		reg |= PMSU_CPU_POWER_DOWN_DIS_SNP_Q_SKIP;  in mvebu_v7_pmsu_idle_prepare()
263 		writel(reg, pmsu_mp_base + PMSU_CPU_POWER_DOWN_CONTROL(hw_cpu));  in mvebu_v7_pmsu_idle_prepare()
345 	u32 reg;  in mvebu_v7_pmsu_idle_exit()  local
350 	reg = readl(pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu));  in mvebu_v7_pmsu_idle_exit()
351 	reg &= ~PMSU_CONTROL_AND_CONFIG_L2_PWDDN;  in mvebu_v7_pmsu_idle_exit()
352 	writel(reg, pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu));  in mvebu_v7_pmsu_idle_exit()
355 	reg = readl(pmsu_mp_base + PMSU_STATUS_AND_MASK(hw_cpu));  in mvebu_v7_pmsu_idle_exit()
356 	reg &= ~(PMSU_STATUS_AND_MASK_IRQ_WAKEUP | PMSU_STATUS_AND_MASK_FIQ_WAKEUP);  in mvebu_v7_pmsu_idle_exit()
357 	reg &= ~PMSU_STATUS_AND_MASK_CPU_IDLE_WAIT;  in mvebu_v7_pmsu_idle_exit()
358 	reg &= ~PMSU_STATUS_AND_MASK_SNP_Q_EMPTY_WAIT;  in mvebu_v7_pmsu_idle_exit()
359 	reg &= ~(PMSU_STATUS_AND_MASK_IRQ_MASK | PMSU_STATUS_AND_MASK_FIQ_MASK);  in mvebu_v7_pmsu_idle_exit()
360 	writel(reg, pmsu_mp_base + PMSU_STATUS_AND_MASK(hw_cpu));  in mvebu_v7_pmsu_idle_exit()
430 	u32 reg;  in armada_38x_cpuidle_init()  local
453 	reg = readl(mpsoc_base + MPCORE_RESET_CTL);  in armada_38x_cpuidle_init()
454 	reg |= MPCORE_RESET_CTL_L2;  in armada_38x_cpuidle_init()
455 	reg |= MPCORE_RESET_CTL_DEBUG;  in armada_38x_cpuidle_init()
456 	writel(reg, mpsoc_base + MPCORE_RESET_CTL);  in armada_38x_cpuidle_init()
460 	reg = readl(pmsu_mp_base + PMSU_POWERDOWN_DELAY);  in armada_38x_cpuidle_init()
461 	reg &= ~PMSU_POWERDOWN_DELAY_MASK;  in armada_38x_cpuidle_init()
462 	reg |= PMSU_DFLT_ARMADA38X_DELAY;  in armada_38x_cpuidle_init()
463 	reg |= PMSU_POWERDOWN_DELAY_PMU;  in armada_38x_cpuidle_init()
464 	writel(reg, pmsu_mp_base + PMSU_POWERDOWN_DELAY);  in armada_38x_cpuidle_init()
540 	u32 reg;  in mvebu_pmsu_dfs_request_local()  local
547 	reg = readl(pmsu_mp_base + PMSU_STATUS_AND_MASK(cpu));  in mvebu_pmsu_dfs_request_local()
548 	reg |= PMSU_STATUS_AND_MASK_CPU_IDLE_WAIT |  in mvebu_pmsu_dfs_request_local()
551 	writel(reg, pmsu_mp_base + PMSU_STATUS_AND_MASK(cpu));  in mvebu_pmsu_dfs_request_local()
554 	reg = readl(pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(cpu));  in mvebu_pmsu_dfs_request_local()
555 	reg |= PMSU_CONTROL_AND_CONFIG_DFS_REQ;  in mvebu_pmsu_dfs_request_local()
556 	writel(reg, pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(cpu));  in mvebu_pmsu_dfs_request_local()
565 	reg = readl(pmsu_mp_base + PMSU_STATUS_AND_MASK(cpu));  in mvebu_pmsu_dfs_request_local()
566 	reg &= ~PMSU_STATUS_AND_MASK_CPU_IDLE_WAIT;  in mvebu_pmsu_dfs_request_local()
567 	writel(reg, pmsu_mp_base + PMSU_STATUS_AND_MASK(cpu));  in mvebu_pmsu_dfs_request_local()
576 	u32 reg;  in mvebu_pmsu_dfs_request()  local
579 	reg = readl(pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu));  in mvebu_pmsu_dfs_request()
580 	reg &= ~PMSU_EVENT_STATUS_AND_MASK_DFS_DONE;  in mvebu_pmsu_dfs_request()
581 	writel(reg, pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu));  in mvebu_pmsu_dfs_request()
584 	reg = readl(pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu));  in mvebu_pmsu_dfs_request()
585 	reg |= PMSU_EVENT_STATUS_AND_MASK_DFS_DONE_MASK;  in mvebu_pmsu_dfs_request()
586 	writel(reg, pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu));  in mvebu_pmsu_dfs_request()
595 		reg = readl(pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu));  in mvebu_pmsu_dfs_request()
596 		if (reg & PMSU_EVENT_STATUS_AND_MASK_DFS_DONE)  in mvebu_pmsu_dfs_request()
605 	reg = readl(pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu));  in mvebu_pmsu_dfs_request()
606 	reg &= ~PMSU_EVENT_STATUS_AND_MASK_DFS_DONE_MASK;  in mvebu_pmsu_dfs_request()
607 	writel(reg, pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu));  in mvebu_pmsu_dfs_request()