197 static unsigned int exynos5_rate_to_clk(unsigned long rate, u32 *reg)  in exynos5_rate_to_clk()  argument
203 		*reg = EXYNOS5_FSEL_9MHZ6;  in exynos5_rate_to_clk()
206 		*reg = EXYNOS5_FSEL_10MHZ;  in exynos5_rate_to_clk()
209 		*reg = EXYNOS5_FSEL_12MHZ;  in exynos5_rate_to_clk()
212 		*reg = EXYNOS5_FSEL_19MHZ2;  in exynos5_rate_to_clk()
215 		*reg = EXYNOS5_FSEL_20MHZ;  in exynos5_rate_to_clk()
218 		*reg = EXYNOS5_FSEL_24MHZ;  in exynos5_rate_to_clk()
221 		*reg = EXYNOS5_FSEL_50MHZ;  in exynos5_rate_to_clk()
252 	static u32 reg;  in exynos5_usbdrd_pipe3_set_refclk()  local
256 	reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST);  in exynos5_usbdrd_pipe3_set_refclk()
259 	reg &= ~PHYCLKRST_REFCLKSEL_MASK;  in exynos5_usbdrd_pipe3_set_refclk()
260 	reg |=	PHYCLKRST_REFCLKSEL_EXT_REFCLK;  in exynos5_usbdrd_pipe3_set_refclk()
263 	reg &= ~PHYCLKRST_FSEL_PIPE_MASK |  in exynos5_usbdrd_pipe3_set_refclk()
268 		reg |= (PHYCLKRST_MPLL_MULTIPLIER_50M_REF |  in exynos5_usbdrd_pipe3_set_refclk()
272 		reg |= (PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF |  in exynos5_usbdrd_pipe3_set_refclk()
276 		reg |= (PHYCLKRST_MPLL_MULTIPLIER_20MHZ_REF |  in exynos5_usbdrd_pipe3_set_refclk()
280 		reg |= (PHYCLKRST_MPLL_MULTIPLIER_19200KHZ_REF |  in exynos5_usbdrd_pipe3_set_refclk()
288 	return reg;  in exynos5_usbdrd_pipe3_set_refclk()
298 	static u32 reg;  in exynos5_usbdrd_utmi_set_refclk()  local
302 	reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST);  in exynos5_usbdrd_utmi_set_refclk()
304 	reg &= ~PHYCLKRST_REFCLKSEL_MASK;  in exynos5_usbdrd_utmi_set_refclk()
305 	reg |=	PHYCLKRST_REFCLKSEL_EXT_REFCLK;  in exynos5_usbdrd_utmi_set_refclk()
307 	reg &= ~PHYCLKRST_FSEL_UTMI_MASK |  in exynos5_usbdrd_utmi_set_refclk()
310 	reg |= PHYCLKRST_FSEL(phy_drd->extrefclk);  in exynos5_usbdrd_utmi_set_refclk()
312 	return reg;  in exynos5_usbdrd_utmi_set_refclk()
317 	u32 reg;  in exynos5_usbdrd_pipe3_init()  local
319 	reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM1);  in exynos5_usbdrd_pipe3_init()
321 	reg &= ~PHYPARAM1_PCS_TXDEEMPH_MASK;  in exynos5_usbdrd_pipe3_init()
322 	reg |=	PHYPARAM1_PCS_TXDEEMPH;  in exynos5_usbdrd_pipe3_init()
323 	writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM1);  in exynos5_usbdrd_pipe3_init()
325 	reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST);  in exynos5_usbdrd_pipe3_init()
326 	reg &= ~PHYTEST_POWERDOWN_SSP;  in exynos5_usbdrd_pipe3_init()
327 	writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST);  in exynos5_usbdrd_pipe3_init()
332 	u32 reg;  in exynos5_usbdrd_utmi_init()  local
334 	reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM0);  in exynos5_usbdrd_utmi_init()
336 	reg &= ~PHYPARAM0_REF_LOSLEVEL_MASK;  in exynos5_usbdrd_utmi_init()
337 	reg |=	PHYPARAM0_REF_LOSLEVEL;  in exynos5_usbdrd_utmi_init()
338 	writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM0);  in exynos5_usbdrd_utmi_init()
340 	reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM1);  in exynos5_usbdrd_utmi_init()
342 	reg &= ~PHYPARAM1_PCS_TXDEEMPH_MASK;  in exynos5_usbdrd_utmi_init()
343 	reg |=	PHYPARAM1_PCS_TXDEEMPH;  in exynos5_usbdrd_utmi_init()
344 	writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM1);  in exynos5_usbdrd_utmi_init()
349 	reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST);  in exynos5_usbdrd_utmi_init()
350 	reg &= ~PHYTEST_POWERDOWN_HSP;  in exynos5_usbdrd_utmi_init()
351 	writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST);  in exynos5_usbdrd_utmi_init()
357 	u32 reg;  in exynos5_usbdrd_phy_init()  local
373 	reg =	LINKSYSTEM_XHCI_VERSION_CONTROL |  in exynos5_usbdrd_phy_init()
375 	writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_LINKSYSTEM);  in exynos5_usbdrd_phy_init()
377 	reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM0);  in exynos5_usbdrd_phy_init()
379 	reg &= ~PHYPARAM0_REF_USE_PAD;  in exynos5_usbdrd_phy_init()
380 	writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM0);  in exynos5_usbdrd_phy_init()
383 	reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYUTMICLKSEL);  in exynos5_usbdrd_phy_init()
384 	reg |= PHYUTMICLKSEL_UTMI_CLKSEL;  in exynos5_usbdrd_phy_init()
385 	writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYUTMICLKSEL);  in exynos5_usbdrd_phy_init()
391 	reg = inst->phy_cfg->set_refclk(inst);  in exynos5_usbdrd_phy_init()
394 	reg |=	PHYCLKRST_RETENABLEN |  in exynos5_usbdrd_phy_init()
404 	writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST);  in exynos5_usbdrd_phy_init()
408 	reg &= ~PHYCLKRST_PORTRESET;  in exynos5_usbdrd_phy_init()
409 	writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST);  in exynos5_usbdrd_phy_init()
419 	u32 reg;  in exynos5_usbdrd_phy_exit()  local
427 	reg =	PHYUTMI_OTGDISABLE |  in exynos5_usbdrd_phy_exit()
430 	writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYUTMI);  in exynos5_usbdrd_phy_exit()
433 	reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST);  in exynos5_usbdrd_phy_exit()
434 	reg &= ~(PHYCLKRST_REF_SSP_EN |  in exynos5_usbdrd_phy_exit()
437 	writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST);  in exynos5_usbdrd_phy_exit()
440 	reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST);  in exynos5_usbdrd_phy_exit()
441 	reg |=	PHYTEST_POWERDOWN_SSP |  in exynos5_usbdrd_phy_exit()
443 	writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST);  in exynos5_usbdrd_phy_exit()