180 	int reg, err;  in bcm54xx_config_init()  local
182 	reg = phy_read(phydev, MII_BCM54XX_ECR);  in bcm54xx_config_init()
183 	if (reg < 0)  in bcm54xx_config_init()
184 		return reg;  in bcm54xx_config_init()
187 	reg |= MII_BCM54XX_ECR_IM;  in bcm54xx_config_init()
188 	err = phy_write(phydev, MII_BCM54XX_ECR, reg);  in bcm54xx_config_init()
193 	reg = ~(MII_BCM54XX_INT_DUPLEX |  in bcm54xx_config_init()
196 	err = phy_write(phydev, MII_BCM54XX_IMR, reg);  in bcm54xx_config_init()
217 	int err, reg;  in bcm5482_config_init()  local
225 		reg = bcm_phy_read_shadow(phydev, BCM5482_SHD_SSD);  in bcm5482_config_init()
227 				     reg |  in bcm5482_config_init()
234 		reg = BCM5482_SSD_SGMII_SLAVE | MII_BCM54XX_EXP_SEL_SSD;  in bcm5482_config_init()
235 		err = bcm_phy_read_exp(phydev, reg);  in bcm5482_config_init()
238 		err = bcm_phy_write_exp(phydev, reg, err |  in bcm5482_config_init()
247 		reg = BCM5482_SSD_1000BX_CTL | MII_BCM54XX_EXP_SEL_SSD;  in bcm5482_config_init()
248 		err = bcm_phy_read_exp(phydev, reg);  in bcm5482_config_init()
251 		err = bcm_phy_write_exp(phydev, reg,  in bcm5482_config_init()
259 		reg = bcm_phy_read_shadow(phydev, BCM5482_SHD_MODE);  in bcm5482_config_init()
261 				     reg | BCM5482_SHD_MODE_1000BX);  in bcm5482_config_init()
314 		u16 reg;  in bcm5481_config_aneg()  local
326 		reg = 0x7 | (0x7 << 12);  in bcm5481_config_aneg()
327 		phy_write(phydev, 0x18, reg);  in bcm5481_config_aneg()
329 		reg = phy_read(phydev, 0x18);  in bcm5481_config_aneg()
331 		reg |= (1 << 8);  in bcm5481_config_aneg()
333 		reg |= (1 << 15);  in bcm5481_config_aneg()
334 		phy_write(phydev, 0x18, reg);  in bcm5481_config_aneg()
340 static int brcm_phy_setbits(struct phy_device *phydev, int reg, int set)  in brcm_phy_setbits()  argument
344 	val = phy_read(phydev, reg);  in brcm_phy_setbits()
348 	return phy_write(phydev, reg, val | set);  in brcm_phy_setbits()
353 	int reg, err, err2, brcmtest;  in brcm_fet_config_init()  local
360 	reg = phy_read(phydev, MII_BRCM_FET_INTREG);  in brcm_fet_config_init()
361 	if (reg < 0)  in brcm_fet_config_init()
362 		return reg;  in brcm_fet_config_init()
365 	reg = MII_BRCM_FET_IR_DUPLEX_EN |  in brcm_fet_config_init()
371 	err = phy_write(phydev, MII_BRCM_FET_INTREG, reg);  in brcm_fet_config_init()
380 	reg = brcmtest | MII_BRCM_FET_BT_SRE;  in brcm_fet_config_init()
382 	err = phy_write(phydev, MII_BRCM_FET_BRCMTEST, reg);  in brcm_fet_config_init()
387 	reg = phy_read(phydev, MII_BRCM_FET_SHDW_AUXMODE4);  in brcm_fet_config_init()
388 	if (reg < 0) {  in brcm_fet_config_init()
389 		err = reg;  in brcm_fet_config_init()
393 	reg &= ~MII_BRCM_FET_SHDW_AM4_LED_MASK;  in brcm_fet_config_init()
394 	reg |= MII_BRCM_FET_SHDW_AM4_LED_MODE1;  in brcm_fet_config_init()
396 	err = phy_write(phydev, MII_BRCM_FET_SHDW_AUXMODE4, reg);  in brcm_fet_config_init()
423 	int reg;  in brcm_fet_ack_interrupt()  local
426 	reg = phy_read(phydev, MII_BRCM_FET_INTREG);  in brcm_fet_ack_interrupt()
427 	if (reg < 0)  in brcm_fet_ack_interrupt()
428 		return reg;  in brcm_fet_ack_interrupt()
435 	int reg, err;  in brcm_fet_config_intr()  local
437 	reg = phy_read(phydev, MII_BRCM_FET_INTREG);  in brcm_fet_config_intr()
438 	if (reg < 0)  in brcm_fet_config_intr()
439 		return reg;  in brcm_fet_config_intr()
442 		reg &= ~MII_BRCM_FET_IR_MASK;  in brcm_fet_config_intr()
444 		reg |= MII_BRCM_FET_IR_MASK;  in brcm_fet_config_intr()
446 	err = phy_write(phydev, MII_BRCM_FET_INTREG, reg);  in brcm_fet_config_intr()