64 	u8 reg, u8 data)  in m88rs2000_writereg()  argument
67 	u8 buf[] = { reg, data };  in m88rs2000_writereg()
79 			"ret == %i)\n", __func__, reg, data, ret);  in m88rs2000_writereg()
84 static u8 m88rs2000_readreg(struct m88rs2000_state *state, u8 reg)  in m88rs2000_readreg()  argument
87 	u8 b0[] = { reg };  in m88rs2000_readreg()
108 				__func__, reg, ret);  in m88rs2000_readreg()
117 	u8 reg;  in m88rs2000_get_mclk()  local
119 	reg = m88rs2000_readreg(state, 0x86);  in m88rs2000_get_mclk()
120 	if (!reg || reg == 0xff)  in m88rs2000_get_mclk()
123 	reg /= 2;  in m88rs2000_get_mclk()
124 	reg += 1;  in m88rs2000_get_mclk()
126 	mclk = (u32)(reg * RS2000_FE_CRYSTAL_KHZ + 28 / 2) / 28;  in m88rs2000_get_mclk()
136 	u8 reg;  in m88rs2000_set_carrieroffset()  local
150 	reg = m88rs2000_readreg(state, 0x9d);  in m88rs2000_set_carrieroffset()
151 	reg &= 0xf;  in m88rs2000_set_carrieroffset()
152 	reg |= (u8)(tmp & 0xf) << 4;  in m88rs2000_set_carrieroffset()
154 	ret |= m88rs2000_writereg(state, 0x9d, reg);  in m88rs2000_set_carrieroffset()
211 	u8 reg;  in m88rs2000_send_diseqc_msg()  local
214 	reg = m88rs2000_readreg(state, 0xb2);  in m88rs2000_send_diseqc_msg()
215 	reg &= 0x3f;  in m88rs2000_send_diseqc_msg()
216 	m88rs2000_writereg(state, 0xb2, reg);  in m88rs2000_send_diseqc_msg()
220 	reg = m88rs2000_readreg(state, 0xb1);  in m88rs2000_send_diseqc_msg()
221 	reg &= 0x87;  in m88rs2000_send_diseqc_msg()
222 	reg |= ((m->msg_len - 1) << 3) | 0x07;  in m88rs2000_send_diseqc_msg()
223 	reg &= 0x7f;  in m88rs2000_send_diseqc_msg()
224 	m88rs2000_writereg(state, 0xb1, reg);  in m88rs2000_send_diseqc_msg()
232 	reg = m88rs2000_readreg(state, 0xb1);  in m88rs2000_send_diseqc_msg()
233 	if ((reg & 0x40) > 0x0) {  in m88rs2000_send_diseqc_msg()
234 		reg &= 0x7f;  in m88rs2000_send_diseqc_msg()
235 		reg |= 0x40;  in m88rs2000_send_diseqc_msg()
236 		m88rs2000_writereg(state, 0xb1, reg);  in m88rs2000_send_diseqc_msg()
239 	reg = m88rs2000_readreg(state, 0xb2);  in m88rs2000_send_diseqc_msg()
240 	reg &= 0x3f;  in m88rs2000_send_diseqc_msg()
241 	reg |= 0x80;  in m88rs2000_send_diseqc_msg()
242 	m88rs2000_writereg(state, 0xb2, reg);  in m88rs2000_send_diseqc_msg()
297 	u8 reg;  member
395 			ret = m88rs2000_writereg(state, tab[i].reg,  in m88rs2000_tab_set()
399 			if (tab[i].reg > 0)  in m88rs2000_tab_set()
400 				mdelay(tab[i].reg);  in m88rs2000_tab_set()
403 			if (tab[i].reg == 0xaa && tab[i].val == 0xff)  in m88rs2000_tab_set()
471 	u8 reg = m88rs2000_readreg(state, 0x8c);  in m88rs2000_read_status()  local
475 	if ((reg & 0xee) == 0xee) {  in m88rs2000_read_status()
547 	u8 fec_set, reg;  in m88rs2000_set_fec()  local
571 	reg = m88rs2000_readreg(state, 0x70);  in m88rs2000_set_fec()
572 	reg &= 0x7;  in m88rs2000_set_fec()
573 	ret = m88rs2000_writereg(state, 0x70, reg | fec_set);  in m88rs2000_set_fec()
582 	u8 reg;  in m88rs2000_get_fec()  local
584 	reg = m88rs2000_readreg(state, 0x76);  in m88rs2000_get_fec()
587 	reg &= 0xf0;  in m88rs2000_get_fec()
588 	reg >>= 5;  in m88rs2000_get_fec()
590 	switch (reg) {  in m88rs2000_get_fec()
616 	u8 reg;  in m88rs2000_set_frontend()  local
685 		reg = m88rs2000_readreg(state, 0x8c);  in m88rs2000_set_frontend()
686 		if ((reg & 0xee) == 0xee) {  in m88rs2000_set_frontend()
692 			reg = m88rs2000_readreg(state, 0x70);  in m88rs2000_set_frontend()
693 			reg ^= 0x4;  in m88rs2000_set_frontend()
694 			m88rs2000_writereg(state, 0x70, reg);  in m88rs2000_set_frontend()
703 		reg = m88rs2000_readreg(state, 0x65);  in m88rs2000_set_frontend()