Lines Matching refs:reg
51 } reg; variable
67 reg.reset_counter1 = 0; in loongson3_reg_setup()
68 reg.reset_counter2 = 0; in loongson3_reg_setup()
78 reg.reset_counter1 = 0x8000000000000000ULL - ctr[0].count; in loongson3_reg_setup()
88 reg.reset_counter2 = 0x8000000000000000ULL - ctr[1].count; in loongson3_reg_setup()
96 reg.control1 = control1; in loongson3_reg_setup()
97 reg.control2 = control2; in loongson3_reg_setup()
98 reg.ctr1_enable = ctr[0].enabled; in loongson3_reg_setup()
99 reg.ctr2_enable = ctr[1].enabled; in loongson3_reg_setup()
107 perfcount1 = reg.reset_counter1; in loongson3_cpu_setup()
108 perfcount2 = reg.reset_counter2; in loongson3_cpu_setup()
116 reg.control1 |= (LOONGSON3_PERFCTRL_W|LOONGSON3_PERFCTRL_M); in loongson3_cpu_start()
117 reg.control2 |= (LOONGSON3_PERFCTRL_W|LOONGSON3_PERFCTRL_M); in loongson3_cpu_start()
119 if (reg.ctr1_enable) in loongson3_cpu_start()
120 write_c0_perflo1(reg.control1); in loongson3_cpu_start()
121 if (reg.ctr2_enable) in loongson3_cpu_start()
122 write_c0_perflo2(reg.control2); in loongson3_cpu_start()
130 memset(®, 0, sizeof(reg)); in loongson3_cpu_stop()
150 if (reg.ctr1_enable) in loongson3_perfcount_handler()
152 counter1 = reg.reset_counter1; in loongson3_perfcount_handler()
155 if (reg.ctr2_enable) in loongson3_perfcount_handler()
157 counter2 = reg.reset_counter2; in loongson3_perfcount_handler()
177 write_c0_perflo1(reg.control1); in loongson3_cpu_callback()
178 write_c0_perflo2(reg.control2); in loongson3_cpu_callback()