Lines Matching refs:reg
91 u32 reg; in mei_me_mecsr_read() local
93 reg = mei_me_reg_read(to_me_hw(dev), ME_CSR_HA); in mei_me_mecsr_read()
94 trace_mei_reg_read(dev->dev, "ME_CSR_HA", ME_CSR_HA, reg); in mei_me_mecsr_read()
96 return reg; in mei_me_mecsr_read()
108 u32 reg; in mei_hcsr_read() local
110 reg = mei_me_reg_read(to_me_hw(dev), H_CSR); in mei_hcsr_read()
111 trace_mei_reg_read(dev->dev, "H_CSR", H_CSR, reg); in mei_hcsr_read()
113 return reg; in mei_hcsr_read()
122 static inline void mei_hcsr_write(struct mei_device *dev, u32 reg) in mei_hcsr_write() argument
124 trace_mei_reg_write(dev->dev, "H_CSR", H_CSR, reg); in mei_hcsr_write()
125 mei_me_reg_write(to_me_hw(dev), H_CSR, reg); in mei_hcsr_write()
135 static inline void mei_hcsr_set(struct mei_device *dev, u32 reg) in mei_hcsr_set() argument
137 reg &= ~H_CSR_IS_MASK; in mei_hcsr_set()
138 mei_hcsr_write(dev, reg); in mei_hcsr_set()
150 u32 reg; in mei_me_d0i3c_read() local
152 reg = mei_me_reg_read(to_me_hw(dev), H_D0I3C); in mei_me_d0i3c_read()
153 trace_mei_reg_read(dev->dev, "H_D0I3C", H_D0I3C, reg); in mei_me_d0i3c_read()
155 return reg; in mei_me_d0i3c_read()
164 static inline void mei_me_d0i3c_write(struct mei_device *dev, u32 reg) in mei_me_d0i3c_write() argument
166 trace_mei_reg_write(dev->dev, "H_D0I3C", H_D0I3C, reg); in mei_me_d0i3c_write()
167 mei_me_reg_write(to_me_hw(dev), H_D0I3C, reg); in mei_me_d0i3c_write()
210 u32 hcsr, reg; in mei_me_hw_config() local
216 reg = 0; in mei_me_hw_config()
217 pci_read_config_dword(pdev, PCI_CFG_HFS_1, ®); in mei_me_hw_config()
219 ((reg & PCI_CFG_HFS_1_D0I3_MSK) == PCI_CFG_HFS_1_D0I3_MSK); in mei_me_hw_config()
223 reg = mei_me_d0i3c_read(dev); in mei_me_hw_config()
224 if (reg & H_D0I3C_I3) in mei_me_hw_config()
484 u32 reg = 0; in mei_me_write_message() local
486 memcpy(®, &buf[length - rem], rem); in mei_me_write_message()
487 mei_me_hcbww_write(dev, reg); in mei_me_write_message()
544 u32 reg = mei_me_mecbrw_read(dev); in mei_me_read_slots() local
546 memcpy(reg_buf, ®, buffer_length); in mei_me_read_slots()
562 u32 reg; in mei_me_pg_set() local
564 reg = mei_me_reg_read(hw, H_HPG_CSR); in mei_me_pg_set()
565 trace_mei_reg_read(dev->dev, "H_HPG_CSR", H_HPG_CSR, reg); in mei_me_pg_set()
567 reg |= H_HPG_CSR_PGI; in mei_me_pg_set()
569 trace_mei_reg_write(dev->dev, "H_HPG_CSR", H_HPG_CSR, reg); in mei_me_pg_set()
570 mei_me_reg_write(hw, H_HPG_CSR, reg); in mei_me_pg_set()
581 u32 reg; in mei_me_pg_unset() local
583 reg = mei_me_reg_read(hw, H_HPG_CSR); in mei_me_pg_unset()
584 trace_mei_reg_read(dev->dev, "H_HPG_CSR", H_HPG_CSR, reg); in mei_me_pg_unset()
586 WARN(!(reg & H_HPG_CSR_PGI), "PGI is not set\n"); in mei_me_pg_unset()
588 reg |= H_HPG_CSR_PGIHEXR; in mei_me_pg_unset()
590 trace_mei_reg_write(dev->dev, "H_HPG_CSR", H_HPG_CSR, reg); in mei_me_pg_unset()
591 mei_me_reg_write(hw, H_HPG_CSR, reg); in mei_me_pg_unset()
707 u32 reg = mei_me_mecsr_read(dev); in mei_me_pg_is_enabled() local
712 if ((reg & ME_PGIC_HRA) == 0) in mei_me_pg_is_enabled()
723 !!(reg & ME_PGIC_HRA), in mei_me_pg_is_enabled()
742 u32 reg = mei_me_d0i3c_read(dev); in mei_me_d0i3_set() local
744 reg |= H_D0I3C_I3; in mei_me_d0i3_set()
746 reg |= H_D0I3C_IR; in mei_me_d0i3_set()
748 reg &= ~H_D0I3C_IR; in mei_me_d0i3_set()
749 mei_me_d0i3c_write(dev, reg); in mei_me_d0i3_set()
751 reg = mei_me_d0i3c_read(dev); in mei_me_d0i3_set()
752 return reg; in mei_me_d0i3_set()
764 u32 reg = mei_me_d0i3c_read(dev); in mei_me_d0i3_unset() local
766 reg &= ~H_D0I3C_I3; in mei_me_d0i3_unset()
767 reg |= H_D0I3C_IR; in mei_me_d0i3_unset()
768 mei_me_d0i3c_write(dev, reg); in mei_me_d0i3_unset()
770 reg = mei_me_d0i3c_read(dev); in mei_me_d0i3_unset()
771 return reg; in mei_me_d0i3_unset()
787 u32 reg; in mei_me_d0i3_enter_sync() local
789 reg = mei_me_d0i3c_read(dev); in mei_me_d0i3_enter_sync()
790 if (reg & H_D0I3C_I3) { in mei_me_d0i3_enter_sync()
818 reg = mei_me_d0i3_set(dev, true); in mei_me_d0i3_enter_sync()
819 if (!(reg & H_D0I3C_CIP)) { in mei_me_d0i3_enter_sync()
831 reg = mei_me_d0i3c_read(dev); in mei_me_d0i3_enter_sync()
832 if (!(reg & H_D0I3C_I3)) { in mei_me_d0i3_enter_sync()
860 u32 reg; in mei_me_d0i3_enter() local
862 reg = mei_me_d0i3c_read(dev); in mei_me_d0i3_enter()
863 if (reg & H_D0I3C_I3) { in mei_me_d0i3_enter()
889 u32 reg; in mei_me_d0i3_exit_sync() local
893 reg = mei_me_d0i3c_read(dev); in mei_me_d0i3_exit_sync()
894 if (!(reg & H_D0I3C_I3)) { in mei_me_d0i3_exit_sync()
901 reg = mei_me_d0i3_unset(dev); in mei_me_d0i3_exit_sync()
902 if (!(reg & H_D0I3C_CIP)) { in mei_me_d0i3_exit_sync()
914 reg = mei_me_d0i3c_read(dev); in mei_me_d0i3_exit_sync()
915 if (reg & H_D0I3C_I3) { in mei_me_d0i3_exit_sync()
1248 u32 reg; in mei_me_fw_type_nm() local
1250 pci_read_config_dword(pdev, PCI_CFG_HFS_2, ®); in mei_me_fw_type_nm()
1252 return (reg & 0x600) == 0x200; in mei_me_fw_type_nm()
1260 u32 reg; in mei_me_fw_type_sps() local
1262 pci_read_config_dword(pdev, PCI_CFG_HFS_1, ®); in mei_me_fw_type_sps()
1264 return (reg & 0xf0000) == 0xf0000; in mei_me_fw_type_sps()