Lines Matching refs:reg
127 u32 reg; in berlin2_avpll_vco_is_enabled() local
129 reg = readl_relaxed(vco->base + VCO_CTRL0); in berlin2_avpll_vco_is_enabled()
131 reg >>= 4; in berlin2_avpll_vco_is_enabled()
133 return !!(reg & VCO_POWERUP); in berlin2_avpll_vco_is_enabled()
139 u32 reg; in berlin2_avpll_vco_enable() local
141 reg = readl_relaxed(vco->base + VCO_CTRL0); in berlin2_avpll_vco_enable()
143 reg |= VCO_POWERUP << 4; in berlin2_avpll_vco_enable()
145 reg |= VCO_POWERUP; in berlin2_avpll_vco_enable()
146 writel_relaxed(reg, vco->base + VCO_CTRL0); in berlin2_avpll_vco_enable()
154 u32 reg; in berlin2_avpll_vco_disable() local
156 reg = readl_relaxed(vco->base + VCO_CTRL0); in berlin2_avpll_vco_disable()
158 reg &= ~(VCO_POWERUP << 4); in berlin2_avpll_vco_disable()
160 reg &= ~VCO_POWERUP; in berlin2_avpll_vco_disable()
161 writel_relaxed(reg, vco->base + VCO_CTRL0); in berlin2_avpll_vco_disable()
170 u32 reg, refdiv, fbdiv; in berlin2_avpll_vco_recalc_rate() local
174 reg = readl_relaxed(vco->base + VCO_CTRL1); in berlin2_avpll_vco_recalc_rate()
175 refdiv = (reg & VCO_REFDIV_MASK) >> VCO_REFDIV_SHIFT; in berlin2_avpll_vco_recalc_rate()
177 fbdiv = (reg & VCO_FBDIV_MASK) >> VCO_FBDIV_SHIFT; in berlin2_avpll_vco_recalc_rate()
226 u32 reg; in berlin2_avpll_channel_is_enabled() local
231 reg = readl_relaxed(ch->base + VCO_CTRL10); in berlin2_avpll_channel_is_enabled()
232 reg &= VCO_POWERUP_CH1 << ch->index; in berlin2_avpll_channel_is_enabled()
234 return !!reg; in berlin2_avpll_channel_is_enabled()
240 u32 reg; in berlin2_avpll_channel_enable() local
242 reg = readl_relaxed(ch->base + VCO_CTRL10); in berlin2_avpll_channel_enable()
243 reg |= VCO_POWERUP_CH1 << ch->index; in berlin2_avpll_channel_enable()
244 writel_relaxed(reg, ch->base + VCO_CTRL10); in berlin2_avpll_channel_enable()
252 u32 reg; in berlin2_avpll_channel_disable() local
254 reg = readl_relaxed(ch->base + VCO_CTRL10); in berlin2_avpll_channel_disable()
255 reg &= ~(VCO_POWERUP_CH1 << ch->index); in berlin2_avpll_channel_disable()
256 writel_relaxed(reg, ch->base + VCO_CTRL10); in berlin2_avpll_channel_disable()
266 u32 reg, div_av2, div_av3, divider = 1; in berlin2_avpll_channel_recalc_rate() local
269 reg = readl_relaxed(ch->base + VCO_CTRL30); in berlin2_avpll_channel_recalc_rate()
270 if ((reg & (VCO_DPLL_CH1_ENABLE << ch->index)) == 0) in berlin2_avpll_channel_recalc_rate()
278 reg = readl_relaxed(ch->base + VCO_SYNC1n(ch->index)); in berlin2_avpll_channel_recalc_rate()
281 reg >>= 4; in berlin2_avpll_channel_recalc_rate()
282 divider = reg & VCO_SYNC1_MASK; in berlin2_avpll_channel_recalc_rate()
284 reg = readl_relaxed(ch->base + VCO_SYNC2n(ch->index)); in berlin2_avpll_channel_recalc_rate()
285 freq *= reg & VCO_SYNC2_MASK; in berlin2_avpll_channel_recalc_rate()
295 reg = readl_relaxed(ch->base + VCO_CTRL11) >> 7; in berlin2_avpll_channel_recalc_rate()
296 reg = (reg >> (ch->index * 3)); in berlin2_avpll_channel_recalc_rate()
297 if (reg & BIT(2)) in berlin2_avpll_channel_recalc_rate()
298 divider *= div_hdmi[reg & 0x3]; in berlin2_avpll_channel_recalc_rate()
305 reg = readl_relaxed(ch->base + VCO_CTRL11); in berlin2_avpll_channel_recalc_rate()
306 reg >>= 28; in berlin2_avpll_channel_recalc_rate()
308 reg = readl_relaxed(ch->base + VCO_CTRL12); in berlin2_avpll_channel_recalc_rate()
309 reg >>= (ch->index-1) * 3; in berlin2_avpll_channel_recalc_rate()
311 if (reg & BIT(2)) in berlin2_avpll_channel_recalc_rate()
312 divider *= div_av1[reg & 0x3]; in berlin2_avpll_channel_recalc_rate()
319 reg = readl_relaxed(ch->base + VCO_CTRL12); in berlin2_avpll_channel_recalc_rate()
320 reg >>= 18 + (ch->index * 7); in berlin2_avpll_channel_recalc_rate()
322 reg = readl_relaxed(ch->base + VCO_CTRL13); in berlin2_avpll_channel_recalc_rate()
323 reg >>= (ch->index - 2) * 7; in berlin2_avpll_channel_recalc_rate()
325 reg = readl_relaxed(ch->base + VCO_CTRL14); in berlin2_avpll_channel_recalc_rate()
327 div_av2 = reg & 0x7f; in berlin2_avpll_channel_recalc_rate()
337 reg = readl_relaxed(ch->base + VCO_CTRL14); in berlin2_avpll_channel_recalc_rate()
338 reg >>= 7 + (ch->index * 4); in berlin2_avpll_channel_recalc_rate()
340 reg = readl_relaxed(ch->base + VCO_CTRL15); in berlin2_avpll_channel_recalc_rate()
342 div_av3 = reg & 0xf; in berlin2_avpll_channel_recalc_rate()