34 	unsigned int reg;  in exynos_mipi_dsi_func_reset()  local
36 	reg = readl(dsim->reg_base + EXYNOS_DSIM_SWRST);  in exynos_mipi_dsi_func_reset()
38 	reg |= DSIM_FUNCRST;  in exynos_mipi_dsi_func_reset()
40 	writel(reg, dsim->reg_base + EXYNOS_DSIM_SWRST);  in exynos_mipi_dsi_func_reset()
45 	unsigned int reg;  in exynos_mipi_dsi_sw_reset()  local
47 	reg = readl(dsim->reg_base + EXYNOS_DSIM_SWRST);  in exynos_mipi_dsi_sw_reset()
49 	reg |= DSIM_SWRST;  in exynos_mipi_dsi_sw_reset()
51 	writel(reg, dsim->reg_base + EXYNOS_DSIM_SWRST);  in exynos_mipi_dsi_sw_reset()
56 	unsigned int reg;  in exynos_mipi_dsi_sw_reset_release()  local
58 	reg = readl(dsim->reg_base + EXYNOS_DSIM_INTSRC);  in exynos_mipi_dsi_sw_reset_release()
60 	reg |= INTSRC_SW_RST_RELEASE;  in exynos_mipi_dsi_sw_reset_release()
62 	writel(reg, dsim->reg_base + EXYNOS_DSIM_INTSRC);  in exynos_mipi_dsi_sw_reset_release()
73 	unsigned int reg;  in exynos_mipi_dsi_read_interrupt_mask()  local
75 	reg = readl(dsim->reg_base + EXYNOS_DSIM_INTMSK);  in exynos_mipi_dsi_read_interrupt_mask()
77 	return reg;  in exynos_mipi_dsi_read_interrupt_mask()
83 	unsigned int reg = 0;  in exynos_mipi_dsi_set_interrupt_mask()  local
86 		reg |= mode;  in exynos_mipi_dsi_set_interrupt_mask()
88 		reg &= ~mode;  in exynos_mipi_dsi_set_interrupt_mask()
90 	writel(reg, dsim->reg_base + EXYNOS_DSIM_INTMSK);  in exynos_mipi_dsi_set_interrupt_mask()
96 	unsigned int reg;  in exynos_mipi_dsi_init_fifo_pointer()  local
98 	reg = readl(dsim->reg_base + EXYNOS_DSIM_FIFOCTRL);  in exynos_mipi_dsi_init_fifo_pointer()
100 	writel(reg & ~(cfg), dsim->reg_base + EXYNOS_DSIM_FIFOCTRL);  in exynos_mipi_dsi_init_fifo_pointer()
102 	reg |= cfg;  in exynos_mipi_dsi_init_fifo_pointer()
104 	writel(reg, dsim->reg_base + EXYNOS_DSIM_FIFOCTRL);  in exynos_mipi_dsi_init_fifo_pointer()
119 	unsigned int reg;  in exynos_mipi_dsi_set_main_stand_by()  local
121 	reg = readl(dsim->reg_base + EXYNOS_DSIM_MDRESOL);  in exynos_mipi_dsi_set_main_stand_by()
123 	reg &= ~DSIM_MAIN_STAND_BY;  in exynos_mipi_dsi_set_main_stand_by()
126 		reg |= DSIM_MAIN_STAND_BY;  in exynos_mipi_dsi_set_main_stand_by()
128 	writel(reg, dsim->reg_base + EXYNOS_DSIM_MDRESOL);  in exynos_mipi_dsi_set_main_stand_by()
134 	unsigned int reg;  in exynos_mipi_dsi_set_main_disp_resol()  local
137 	reg = (readl(dsim->reg_base + EXYNOS_DSIM_MDRESOL)) &  in exynos_mipi_dsi_set_main_disp_resol()
139 	writel(reg, dsim->reg_base + EXYNOS_DSIM_MDRESOL);  in exynos_mipi_dsi_set_main_disp_resol()
141 	reg &= ~((0x7ff << 16) | (0x7ff << 0));  in exynos_mipi_dsi_set_main_disp_resol()
142 	reg |= DSIM_MAIN_VRESOL(height_resol) | DSIM_MAIN_HRESOL(width_resol);  in exynos_mipi_dsi_set_main_disp_resol()
144 	reg |= DSIM_MAIN_STAND_BY;  in exynos_mipi_dsi_set_main_disp_resol()
145 	writel(reg, dsim->reg_base + EXYNOS_DSIM_MDRESOL);  in exynos_mipi_dsi_set_main_disp_resol()
151 	unsigned int reg;  in exynos_mipi_dsi_set_main_disp_vporch()  local
153 	reg = (readl(dsim->reg_base + EXYNOS_DSIM_MVPORCH)) &  in exynos_mipi_dsi_set_main_disp_vporch()
157 	reg |= (DSIM_CMD_ALLOW_SHIFT(cmd_allow & 0xf) |  in exynos_mipi_dsi_set_main_disp_vporch()
161 	writel(reg, dsim->reg_base + EXYNOS_DSIM_MVPORCH);  in exynos_mipi_dsi_set_main_disp_vporch()
167 	unsigned int reg;  in exynos_mipi_dsi_set_main_disp_hporch()  local
169 	reg = (readl(dsim->reg_base + EXYNOS_DSIM_MHPORCH)) &  in exynos_mipi_dsi_set_main_disp_hporch()
172 	reg |= DSIM_MAIN_HFP_SHIFT(front) | DSIM_MAIN_HBP_SHIFT(back);  in exynos_mipi_dsi_set_main_disp_hporch()
174 	writel(reg, dsim->reg_base + EXYNOS_DSIM_MHPORCH);  in exynos_mipi_dsi_set_main_disp_hporch()
180 	unsigned int reg;  in exynos_mipi_dsi_set_main_disp_sync_area()  local
182 	reg = (readl(dsim->reg_base + EXYNOS_DSIM_MSYNC)) &  in exynos_mipi_dsi_set_main_disp_sync_area()
185 	reg |= (DSIM_MAIN_VSA_SHIFT(vert & 0x3ff) |  in exynos_mipi_dsi_set_main_disp_sync_area()
188 	writel(reg, dsim->reg_base + EXYNOS_DSIM_MSYNC);  in exynos_mipi_dsi_set_main_disp_sync_area()
194 	unsigned int reg;  in exynos_mipi_dsi_set_sub_disp_resol()  local
196 	reg = (readl(dsim->reg_base + EXYNOS_DSIM_SDRESOL)) &  in exynos_mipi_dsi_set_sub_disp_resol()
199 	writel(reg, dsim->reg_base + EXYNOS_DSIM_SDRESOL);  in exynos_mipi_dsi_set_sub_disp_resol()
201 	reg &= ~(DSIM_SUB_VRESOL_MASK) | ~(DSIM_SUB_HRESOL_MASK);  in exynos_mipi_dsi_set_sub_disp_resol()
202 	reg |= (DSIM_SUB_VRESOL_SHIFT(vert & 0x7ff) |  in exynos_mipi_dsi_set_sub_disp_resol()
204 	writel(reg, dsim->reg_base + EXYNOS_DSIM_SDRESOL);  in exynos_mipi_dsi_set_sub_disp_resol()
206 	reg |= DSIM_SUB_STANDY_SHIFT(1);  in exynos_mipi_dsi_set_sub_disp_resol()
207 	writel(reg, dsim->reg_base + EXYNOS_DSIM_SDRESOL);  in exynos_mipi_dsi_set_sub_disp_resol()
232 	u32 reg = (readl(dsim->reg_base + EXYNOS_DSIM_CONFIG)) &  in exynos_mipi_dsi_display_config()  local
237 		reg |= (1 << 25);  in exynos_mipi_dsi_display_config()
239 		reg &= ~(1 << 25);  in exynos_mipi_dsi_display_config()
246 	reg |= ((u8) (dsim_config->e_burst_mode) & 0x3) << 26 |  in exynos_mipi_dsi_display_config()
250 	writel(reg, dsim->reg_base + EXYNOS_DSIM_CONFIG);  in exynos_mipi_dsi_display_config()
256 	unsigned int reg;  in exynos_mipi_dsi_enable_lane()  local
258 	reg = readl(dsim->reg_base + EXYNOS_DSIM_CONFIG);  in exynos_mipi_dsi_enable_lane()
261 		reg |= DSIM_LANE_ENx(lane);  in exynos_mipi_dsi_enable_lane()
263 		reg &= ~DSIM_LANE_ENx(lane);  in exynos_mipi_dsi_enable_lane()
265 	writel(reg, dsim->reg_base + EXYNOS_DSIM_CONFIG);  in exynos_mipi_dsi_enable_lane()
283 	unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_PHYACCHR);  in exynos_mipi_dsi_enable_afc()  local
286 		reg |= (1 << 14);  in exynos_mipi_dsi_enable_afc()
287 		reg &= ~(0x7 << 5);  in exynos_mipi_dsi_enable_afc()
288 		reg |= (afc_code & 0x7) << 5;  in exynos_mipi_dsi_enable_afc()
290 		reg &= ~(1 << 14);  in exynos_mipi_dsi_enable_afc()
292 	writel(reg, dsim->reg_base + EXYNOS_DSIM_PHYACCHR);  in exynos_mipi_dsi_enable_afc()
298 	unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_CLKCTRL)) &  in exynos_mipi_dsi_enable_pll_bypass()  local
301 	reg |= DSIM_PLL_BYPASS_SHIFT(enable);  in exynos_mipi_dsi_enable_pll_bypass()
303 	writel(reg, dsim->reg_base + EXYNOS_DSIM_CLKCTRL);  in exynos_mipi_dsi_enable_pll_bypass()
309 	unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_PLLCTRL);  in exynos_mipi_dsi_set_pll_pms()  local
311 	reg |= ((p & 0x3f) << 13) | ((m & 0x1ff) << 4) | ((s & 0x7) << 1);  in exynos_mipi_dsi_set_pll_pms()
313 	writel(reg, dsim->reg_base + EXYNOS_DSIM_PLLCTRL);  in exynos_mipi_dsi_set_pll_pms()
319 	unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_PLLCTRL)) &  in exynos_mipi_dsi_pll_freq_band()  local
322 	reg |= DSIM_FREQ_BAND_SHIFT(freq_band & 0x1f);  in exynos_mipi_dsi_pll_freq_band()
324 	writel(reg, dsim->reg_base + EXYNOS_DSIM_PLLCTRL);  in exynos_mipi_dsi_pll_freq_band()
331 	unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_PLLCTRL)) &  in exynos_mipi_dsi_pll_freq()  local
334 	reg |= (pre_divider & 0x3f) << 13 | (main_divider & 0x1ff) << 4 |  in exynos_mipi_dsi_pll_freq()
337 	writel(reg, dsim->reg_base + EXYNOS_DSIM_PLLCTRL);  in exynos_mipi_dsi_pll_freq()
348 	unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_PLLCTRL)) &  in exynos_mipi_dsi_enable_pll()  local
351 	reg |= DSIM_PLL_EN_SHIFT(enable & 0x1);  in exynos_mipi_dsi_enable_pll()
353 	writel(reg, dsim->reg_base + EXYNOS_DSIM_PLLCTRL);  in exynos_mipi_dsi_enable_pll()
359 	unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_CLKCTRL)) &  in exynos_mipi_dsi_set_byte_clock_src()  local
362 	reg |= (DSIM_BYTE_CLK_SRC_SHIFT(src));  in exynos_mipi_dsi_set_byte_clock_src()
364 	writel(reg, dsim->reg_base + EXYNOS_DSIM_CLKCTRL);  in exynos_mipi_dsi_set_byte_clock_src()
370 	unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_CLKCTRL)) &  in exynos_mipi_dsi_enable_byte_clock()  local
373 	reg |= DSIM_BYTE_CLKEN_SHIFT(enable);  in exynos_mipi_dsi_enable_byte_clock()
375 	writel(reg, dsim->reg_base + EXYNOS_DSIM_CLKCTRL);  in exynos_mipi_dsi_enable_byte_clock()
381 	unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_CLKCTRL)) &  in exynos_mipi_dsi_set_esc_clk_prs()  local
384 	reg |= DSIM_ESC_CLKEN_SHIFT(enable);  in exynos_mipi_dsi_set_esc_clk_prs()
386 		reg |= prs_val;  in exynos_mipi_dsi_set_esc_clk_prs()
388 	writel(reg, dsim->reg_base + EXYNOS_DSIM_CLKCTRL);  in exynos_mipi_dsi_set_esc_clk_prs()
394 	unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_CLKCTRL);  in exynos_mipi_dsi_enable_esc_clk_on_lane()  local
397 		reg |= DSIM_LANE_ESC_CLKEN(lane_sel);  in exynos_mipi_dsi_enable_esc_clk_on_lane()
400 		reg &= ~DSIM_LANE_ESC_CLKEN(lane_sel);  in exynos_mipi_dsi_enable_esc_clk_on_lane()
402 	writel(reg, dsim->reg_base + EXYNOS_DSIM_CLKCTRL);  in exynos_mipi_dsi_enable_esc_clk_on_lane()
408 	unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_ESCMODE)) &  in exynos_mipi_dsi_force_dphy_stop_state()  local
411 	reg |= (DSIM_FORCE_STOP_STATE_SHIFT(enable & 0x1));  in exynos_mipi_dsi_force_dphy_stop_state()
413 	writel(reg, dsim->reg_base + EXYNOS_DSIM_ESCMODE);  in exynos_mipi_dsi_force_dphy_stop_state()
418 	unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_STATUS);  in exynos_mipi_dsi_is_lane_state()  local
426 	if ((reg & DSIM_STOP_STATE_DAT(0xf)) &&  in exynos_mipi_dsi_is_lane_state()
427 			((reg & DSIM_STOP_STATE_CLK) ||  in exynos_mipi_dsi_is_lane_state()
428 			 (reg & DSIM_TX_READY_HS_CLK)))  in exynos_mipi_dsi_is_lane_state()
437 	unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_ESCMODE)) &  in exynos_mipi_dsi_set_stop_state_counter()  local
440 	reg |= (DSIM_STOP_STATE_CNT_SHIFT(cnt_val & 0x7ff));  in exynos_mipi_dsi_set_stop_state_counter()
442 	writel(reg, dsim->reg_base + EXYNOS_DSIM_ESCMODE);  in exynos_mipi_dsi_set_stop_state_counter()
448 	unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_TIMEOUT)) &  in exynos_mipi_dsi_set_bta_timeout()  local
451 	reg |= (DSIM_BTA_TOUT_SHIFT(timeout));  in exynos_mipi_dsi_set_bta_timeout()
453 	writel(reg, dsim->reg_base + EXYNOS_DSIM_TIMEOUT);  in exynos_mipi_dsi_set_bta_timeout()
459 	unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_TIMEOUT)) &  in exynos_mipi_dsi_set_lpdr_timeout()  local
462 	reg |= (DSIM_LPDR_TOUT_SHIFT(timeout));  in exynos_mipi_dsi_set_lpdr_timeout()
464 	writel(reg, dsim->reg_base + EXYNOS_DSIM_TIMEOUT);  in exynos_mipi_dsi_set_lpdr_timeout()
470 	unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_ESCMODE);  in exynos_mipi_dsi_set_cpu_transfer_mode()  local
472 	reg &= ~DSIM_CMD_LPDT_LP;  in exynos_mipi_dsi_set_cpu_transfer_mode()
475 		reg |= DSIM_CMD_LPDT_LP;  in exynos_mipi_dsi_set_cpu_transfer_mode()
477 	writel(reg, dsim->reg_base + EXYNOS_DSIM_ESCMODE);  in exynos_mipi_dsi_set_cpu_transfer_mode()
483 	unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_ESCMODE);  in exynos_mipi_dsi_set_lcdc_transfer_mode()  local
485 	reg &= ~DSIM_TX_LPDT_LP;  in exynos_mipi_dsi_set_lcdc_transfer_mode()
488 		reg |= DSIM_TX_LPDT_LP;  in exynos_mipi_dsi_set_lcdc_transfer_mode()
490 	writel(reg, dsim->reg_base + EXYNOS_DSIM_ESCMODE);  in exynos_mipi_dsi_set_lcdc_transfer_mode()
496 	unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_CLKCTRL)) &  in exynos_mipi_dsi_enable_hs_clock()  local
499 	reg |= DSIM_TX_REQUEST_HSCLK_SHIFT(enable);  in exynos_mipi_dsi_enable_hs_clock()
501 	writel(reg, dsim->reg_base + EXYNOS_DSIM_CLKCTRL);  in exynos_mipi_dsi_enable_hs_clock()
507 	unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_PHYACCHR1);  in exynos_mipi_dsi_dp_dn_swap()  local
509 	reg &= ~(0x3 << 0);  in exynos_mipi_dsi_dp_dn_swap()
510 	reg |= (swap_en & 0x3) << 0;  in exynos_mipi_dsi_dp_dn_swap()
512 	writel(reg, dsim->reg_base + EXYNOS_DSIM_PHYACCHR1);  in exynos_mipi_dsi_dp_dn_swap()
518 	unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_PLLCTRL)) &  in exynos_mipi_dsi_hs_zero_ctrl()  local
521 	reg |= ((hs_zero & 0xf) << 28);  in exynos_mipi_dsi_hs_zero_ctrl()
523 	writel(reg, dsim->reg_base + EXYNOS_DSIM_PLLCTRL);  in exynos_mipi_dsi_hs_zero_ctrl()
528 	unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_PLLCTRL)) &  in exynos_mipi_dsi_prep_ctrl()  local
531 	reg |= ((prep & 0x7) << 20);  in exynos_mipi_dsi_prep_ctrl()
533 	writel(reg, dsim->reg_base + EXYNOS_DSIM_PLLCTRL);  in exynos_mipi_dsi_prep_ctrl()
544 	unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_INTSRC);  in exynos_mipi_dsi_clear_interrupt()  local
546 	reg |= src;  in exynos_mipi_dsi_clear_interrupt()
548 	writel(reg, dsim->reg_base + EXYNOS_DSIM_INTSRC);  in exynos_mipi_dsi_clear_interrupt()
554 	unsigned int reg = 0;  in exynos_mipi_dsi_set_interrupt()  local
557 		reg |= src;  in exynos_mipi_dsi_set_interrupt()
559 		reg &= ~src;  in exynos_mipi_dsi_set_interrupt()
561 	writel(reg, dsim->reg_base + EXYNOS_DSIM_INTSRC);  in exynos_mipi_dsi_set_interrupt()
566 	unsigned int reg;  in exynos_mipi_dsi_is_pll_stable()  local
568 	reg = readl(dsim->reg_base + EXYNOS_DSIM_STATUS);  in exynos_mipi_dsi_is_pll_stable()
570 	return reg & (1 << 31) ? 1 : 0;  in exynos_mipi_dsi_is_pll_stable()
581 	unsigned int reg = (data1 << 16) | (data0 << 8) | ((di & 0x3f) << 0);  in exynos_mipi_dsi_wr_tx_header()  local
583 	writel(reg, dsim->reg_base + EXYNOS_DSIM_PKTHDR);  in exynos_mipi_dsi_wr_tx_header()
589 	unsigned int reg = (data0 << 8) | (di << 0);  in exynos_mipi_dsi_rd_tx_header()  local
591 	writel(reg, dsim->reg_base + EXYNOS_DSIM_PKTHDR);  in exynos_mipi_dsi_rd_tx_header()
601 	unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_INTSRC);  in _exynos_mipi_dsi_get_frame_done_status()  local
603 	return (reg & INTSRC_FRAME_DONE) ? 1 : 0;  in _exynos_mipi_dsi_get_frame_done_status()
608 	unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_INTSRC);  in _exynos_mipi_dsi_clear_frame_done()  local
610 	writel(reg | INTSRC_FRAME_DONE, dsim->reg_base +  in _exynos_mipi_dsi_clear_frame_done()