Lines Matching refs:reg
59 u32 reg; in rt2500pci_bbp_write() local
67 if (WAIT_FOR_BBP(rt2x00dev, ®)) { in rt2500pci_bbp_write()
68 reg = 0; in rt2500pci_bbp_write()
69 rt2x00_set_field32(®, BBPCSR_VALUE, value); in rt2500pci_bbp_write()
70 rt2x00_set_field32(®, BBPCSR_REGNUM, word); in rt2500pci_bbp_write()
71 rt2x00_set_field32(®, BBPCSR_BUSY, 1); in rt2500pci_bbp_write()
72 rt2x00_set_field32(®, BBPCSR_WRITE_CONTROL, 1); in rt2500pci_bbp_write()
74 rt2x00mmio_register_write(rt2x00dev, BBPCSR, reg); in rt2500pci_bbp_write()
83 u32 reg; in rt2500pci_bbp_read() local
95 if (WAIT_FOR_BBP(rt2x00dev, ®)) { in rt2500pci_bbp_read()
96 reg = 0; in rt2500pci_bbp_read()
97 rt2x00_set_field32(®, BBPCSR_REGNUM, word); in rt2500pci_bbp_read()
98 rt2x00_set_field32(®, BBPCSR_BUSY, 1); in rt2500pci_bbp_read()
99 rt2x00_set_field32(®, BBPCSR_WRITE_CONTROL, 0); in rt2500pci_bbp_read()
101 rt2x00mmio_register_write(rt2x00dev, BBPCSR, reg); in rt2500pci_bbp_read()
103 WAIT_FOR_BBP(rt2x00dev, ®); in rt2500pci_bbp_read()
106 *value = rt2x00_get_field32(reg, BBPCSR_VALUE); in rt2500pci_bbp_read()
114 u32 reg; in rt2500pci_rf_write() local
122 if (WAIT_FOR_RF(rt2x00dev, ®)) { in rt2500pci_rf_write()
123 reg = 0; in rt2500pci_rf_write()
124 rt2x00_set_field32(®, RFCSR_VALUE, value); in rt2500pci_rf_write()
125 rt2x00_set_field32(®, RFCSR_NUMBER_OF_BITS, 20); in rt2500pci_rf_write()
126 rt2x00_set_field32(®, RFCSR_IF_SELECT, 0); in rt2500pci_rf_write()
127 rt2x00_set_field32(®, RFCSR_BUSY, 1); in rt2500pci_rf_write()
129 rt2x00mmio_register_write(rt2x00dev, RFCSR, reg); in rt2500pci_rf_write()
139 u32 reg; in rt2500pci_eepromregister_read() local
141 rt2x00mmio_register_read(rt2x00dev, CSR21, ®); in rt2500pci_eepromregister_read()
143 eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN); in rt2500pci_eepromregister_read()
144 eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT); in rt2500pci_eepromregister_read()
146 !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK); in rt2500pci_eepromregister_read()
148 !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT); in rt2500pci_eepromregister_read()
154 u32 reg = 0; in rt2500pci_eepromregister_write() local
156 rt2x00_set_field32(®, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in); in rt2500pci_eepromregister_write()
157 rt2x00_set_field32(®, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out); in rt2500pci_eepromregister_write()
158 rt2x00_set_field32(®, CSR21_EEPROM_DATA_CLOCK, in rt2500pci_eepromregister_write()
160 rt2x00_set_field32(®, CSR21_EEPROM_CHIP_SELECT, in rt2500pci_eepromregister_write()
163 rt2x00mmio_register_write(rt2x00dev, CSR21, reg); in rt2500pci_eepromregister_write()
203 u32 reg; in rt2500pci_rfkill_poll() local
205 rt2x00mmio_register_read(rt2x00dev, GPIOCSR, ®); in rt2500pci_rfkill_poll()
206 return rt2x00_get_field32(reg, GPIOCSR_VAL0); in rt2500pci_rfkill_poll()
216 u32 reg; in rt2500pci_brightness_set() local
218 rt2x00mmio_register_read(led->rt2x00dev, LEDCSR, ®); in rt2500pci_brightness_set()
221 rt2x00_set_field32(®, LEDCSR_LINK, enabled); in rt2500pci_brightness_set()
223 rt2x00_set_field32(®, LEDCSR_ACTIVITY, enabled); in rt2500pci_brightness_set()
225 rt2x00mmio_register_write(led->rt2x00dev, LEDCSR, reg); in rt2500pci_brightness_set()
234 u32 reg; in rt2500pci_blink_set() local
236 rt2x00mmio_register_read(led->rt2x00dev, LEDCSR, ®); in rt2500pci_blink_set()
237 rt2x00_set_field32(®, LEDCSR_ON_PERIOD, *delay_on); in rt2500pci_blink_set()
238 rt2x00_set_field32(®, LEDCSR_OFF_PERIOD, *delay_off); in rt2500pci_blink_set()
239 rt2x00mmio_register_write(led->rt2x00dev, LEDCSR, reg); in rt2500pci_blink_set()
262 u32 reg; in rt2500pci_config_filter() local
270 rt2x00mmio_register_read(rt2x00dev, RXCSR0, ®); in rt2500pci_config_filter()
271 rt2x00_set_field32(®, RXCSR0_DROP_CRC, in rt2500pci_config_filter()
273 rt2x00_set_field32(®, RXCSR0_DROP_PHYSICAL, in rt2500pci_config_filter()
275 rt2x00_set_field32(®, RXCSR0_DROP_CONTROL, in rt2500pci_config_filter()
277 rt2x00_set_field32(®, RXCSR0_DROP_NOT_TO_ME, 1); in rt2500pci_config_filter()
278 rt2x00_set_field32(®, RXCSR0_DROP_TODS, in rt2500pci_config_filter()
280 rt2x00_set_field32(®, RXCSR0_DROP_VERSION_ERROR, 1); in rt2500pci_config_filter()
281 rt2x00_set_field32(®, RXCSR0_DROP_MCAST, in rt2500pci_config_filter()
283 rt2x00_set_field32(®, RXCSR0_DROP_BCAST, 0); in rt2500pci_config_filter()
284 rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg); in rt2500pci_config_filter()
294 u32 reg; in rt2500pci_config_intf() local
301 rt2x00mmio_register_read(rt2x00dev, BCNCSR1, ®); in rt2500pci_config_intf()
302 rt2x00_set_field32(®, BCNCSR1_PRELOAD, bcn_preload); in rt2500pci_config_intf()
303 rt2x00_set_field32(®, BCNCSR1_BEACON_CWMIN, queue->cw_min); in rt2500pci_config_intf()
304 rt2x00mmio_register_write(rt2x00dev, BCNCSR1, reg); in rt2500pci_config_intf()
309 rt2x00mmio_register_read(rt2x00dev, CSR14, ®); in rt2500pci_config_intf()
310 rt2x00_set_field32(®, CSR14_TSF_SYNC, conf->sync); in rt2500pci_config_intf()
311 rt2x00mmio_register_write(rt2x00dev, CSR14, reg); in rt2500pci_config_intf()
328 u32 reg; in rt2500pci_config_erp() local
336 rt2x00mmio_register_read(rt2x00dev, TXCSR1, ®); in rt2500pci_config_erp()
337 rt2x00_set_field32(®, TXCSR1_ACK_TIMEOUT, 0x162); in rt2500pci_config_erp()
338 rt2x00_set_field32(®, TXCSR1_ACK_CONSUME_TIME, 0xa2); in rt2500pci_config_erp()
339 rt2x00_set_field32(®, TXCSR1_TSF_OFFSET, IEEE80211_HEADER); in rt2500pci_config_erp()
340 rt2x00_set_field32(®, TXCSR1_AUTORESPONDER, 1); in rt2500pci_config_erp()
341 rt2x00mmio_register_write(rt2x00dev, TXCSR1, reg); in rt2500pci_config_erp()
343 rt2x00mmio_register_read(rt2x00dev, ARCSR2, ®); in rt2500pci_config_erp()
344 rt2x00_set_field32(®, ARCSR2_SIGNAL, 0x00); in rt2500pci_config_erp()
345 rt2x00_set_field32(®, ARCSR2_SERVICE, 0x04); in rt2500pci_config_erp()
346 rt2x00_set_field32(®, ARCSR2_LENGTH, in rt2500pci_config_erp()
348 rt2x00mmio_register_write(rt2x00dev, ARCSR2, reg); in rt2500pci_config_erp()
350 rt2x00mmio_register_read(rt2x00dev, ARCSR3, ®); in rt2500pci_config_erp()
351 rt2x00_set_field32(®, ARCSR3_SIGNAL, 0x01 | preamble_mask); in rt2500pci_config_erp()
352 rt2x00_set_field32(®, ARCSR3_SERVICE, 0x04); in rt2500pci_config_erp()
353 rt2x00_set_field32(®, ARCSR2_LENGTH, in rt2500pci_config_erp()
355 rt2x00mmio_register_write(rt2x00dev, ARCSR3, reg); in rt2500pci_config_erp()
357 rt2x00mmio_register_read(rt2x00dev, ARCSR4, ®); in rt2500pci_config_erp()
358 rt2x00_set_field32(®, ARCSR4_SIGNAL, 0x02 | preamble_mask); in rt2500pci_config_erp()
359 rt2x00_set_field32(®, ARCSR4_SERVICE, 0x04); in rt2500pci_config_erp()
360 rt2x00_set_field32(®, ARCSR2_LENGTH, in rt2500pci_config_erp()
362 rt2x00mmio_register_write(rt2x00dev, ARCSR4, reg); in rt2500pci_config_erp()
364 rt2x00mmio_register_read(rt2x00dev, ARCSR5, ®); in rt2500pci_config_erp()
365 rt2x00_set_field32(®, ARCSR5_SIGNAL, 0x03 | preamble_mask); in rt2500pci_config_erp()
366 rt2x00_set_field32(®, ARCSR5_SERVICE, 0x84); in rt2500pci_config_erp()
367 rt2x00_set_field32(®, ARCSR2_LENGTH, in rt2500pci_config_erp()
369 rt2x00mmio_register_write(rt2x00dev, ARCSR5, reg); in rt2500pci_config_erp()
376 rt2x00mmio_register_read(rt2x00dev, CSR11, ®); in rt2500pci_config_erp()
377 rt2x00_set_field32(®, CSR11_SLOT_TIME, erp->slot_time); in rt2500pci_config_erp()
378 rt2x00mmio_register_write(rt2x00dev, CSR11, reg); in rt2500pci_config_erp()
380 rt2x00mmio_register_read(rt2x00dev, CSR18, ®); in rt2500pci_config_erp()
381 rt2x00_set_field32(®, CSR18_SIFS, erp->sifs); in rt2500pci_config_erp()
382 rt2x00_set_field32(®, CSR18_PIFS, erp->pifs); in rt2500pci_config_erp()
383 rt2x00mmio_register_write(rt2x00dev, CSR18, reg); in rt2500pci_config_erp()
385 rt2x00mmio_register_read(rt2x00dev, CSR19, ®); in rt2500pci_config_erp()
386 rt2x00_set_field32(®, CSR19_DIFS, erp->difs); in rt2500pci_config_erp()
387 rt2x00_set_field32(®, CSR19_EIFS, erp->eifs); in rt2500pci_config_erp()
388 rt2x00mmio_register_write(rt2x00dev, CSR19, reg); in rt2500pci_config_erp()
392 rt2x00mmio_register_read(rt2x00dev, CSR12, ®); in rt2500pci_config_erp()
393 rt2x00_set_field32(®, CSR12_BEACON_INTERVAL, in rt2500pci_config_erp()
395 rt2x00_set_field32(®, CSR12_CFP_MAX_DURATION, in rt2500pci_config_erp()
397 rt2x00mmio_register_write(rt2x00dev, CSR12, reg); in rt2500pci_config_erp()
405 u32 reg; in rt2500pci_config_ant() local
416 rt2x00mmio_register_read(rt2x00dev, BBPCSR1, ®); in rt2500pci_config_ant()
426 rt2x00_set_field32(®, BBPCSR1_CCK, 0); in rt2500pci_config_ant()
427 rt2x00_set_field32(®, BBPCSR1_OFDM, 0); in rt2500pci_config_ant()
432 rt2x00_set_field32(®, BBPCSR1_CCK, 2); in rt2500pci_config_ant()
433 rt2x00_set_field32(®, BBPCSR1_OFDM, 2); in rt2500pci_config_ant()
455 rt2x00_set_field32(®, BBPCSR1_CCK_FLIP, 1); in rt2500pci_config_ant()
456 rt2x00_set_field32(®, BBPCSR1_OFDM_FLIP, 1); in rt2500pci_config_ant()
464 rt2x00_set_field32(®, BBPCSR1_CCK_FLIP, 0); in rt2500pci_config_ant()
465 rt2x00_set_field32(®, BBPCSR1_OFDM_FLIP, 0); in rt2500pci_config_ant()
468 rt2x00mmio_register_write(rt2x00dev, BBPCSR1, reg); in rt2500pci_config_ant()
555 u32 reg; in rt2500pci_config_retry_limit() local
557 rt2x00mmio_register_read(rt2x00dev, CSR11, ®); in rt2500pci_config_retry_limit()
558 rt2x00_set_field32(®, CSR11_LONG_RETRY, in rt2500pci_config_retry_limit()
560 rt2x00_set_field32(®, CSR11_SHORT_RETRY, in rt2500pci_config_retry_limit()
562 rt2x00mmio_register_write(rt2x00dev, CSR11, reg); in rt2500pci_config_retry_limit()
571 u32 reg; in rt2500pci_config_ps() local
574 rt2x00mmio_register_read(rt2x00dev, CSR20, ®); in rt2500pci_config_ps()
575 rt2x00_set_field32(®, CSR20_DELAY_AFTER_TBCN, in rt2500pci_config_ps()
577 rt2x00_set_field32(®, CSR20_TBCN_BEFORE_WAKEUP, in rt2500pci_config_ps()
581 rt2x00_set_field32(®, CSR20_AUTOWAKE, 0); in rt2500pci_config_ps()
582 rt2x00mmio_register_write(rt2x00dev, CSR20, reg); in rt2500pci_config_ps()
584 rt2x00_set_field32(®, CSR20_AUTOWAKE, 1); in rt2500pci_config_ps()
585 rt2x00mmio_register_write(rt2x00dev, CSR20, reg); in rt2500pci_config_ps()
587 rt2x00mmio_register_read(rt2x00dev, CSR20, ®); in rt2500pci_config_ps()
588 rt2x00_set_field32(®, CSR20_AUTOWAKE, 0); in rt2500pci_config_ps()
589 rt2x00mmio_register_write(rt2x00dev, CSR20, reg); in rt2500pci_config_ps()
618 u32 reg; in rt2500pci_link_stats() local
623 rt2x00mmio_register_read(rt2x00dev, CNT0, ®); in rt2500pci_link_stats()
624 qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR); in rt2500pci_link_stats()
629 rt2x00mmio_register_read(rt2x00dev, CNT3, ®); in rt2500pci_link_stats()
630 qual->false_cca = rt2x00_get_field32(reg, CNT3_FALSE_CCA); in rt2500pci_link_stats()
725 u32 reg; in rt2500pci_start_queue() local
729 rt2x00mmio_register_read(rt2x00dev, RXCSR0, ®); in rt2500pci_start_queue()
730 rt2x00_set_field32(®, RXCSR0_DISABLE_RX, 0); in rt2500pci_start_queue()
731 rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg); in rt2500pci_start_queue()
734 rt2x00mmio_register_read(rt2x00dev, CSR14, ®); in rt2500pci_start_queue()
735 rt2x00_set_field32(®, CSR14_TSF_COUNT, 1); in rt2500pci_start_queue()
736 rt2x00_set_field32(®, CSR14_TBCN, 1); in rt2500pci_start_queue()
737 rt2x00_set_field32(®, CSR14_BEACON_GEN, 1); in rt2500pci_start_queue()
738 rt2x00mmio_register_write(rt2x00dev, CSR14, reg); in rt2500pci_start_queue()
748 u32 reg; in rt2500pci_kick_queue() local
752 rt2x00mmio_register_read(rt2x00dev, TXCSR0, ®); in rt2500pci_kick_queue()
753 rt2x00_set_field32(®, TXCSR0_KICK_PRIO, 1); in rt2500pci_kick_queue()
754 rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg); in rt2500pci_kick_queue()
757 rt2x00mmio_register_read(rt2x00dev, TXCSR0, ®); in rt2500pci_kick_queue()
758 rt2x00_set_field32(®, TXCSR0_KICK_TX, 1); in rt2500pci_kick_queue()
759 rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg); in rt2500pci_kick_queue()
762 rt2x00mmio_register_read(rt2x00dev, TXCSR0, ®); in rt2500pci_kick_queue()
763 rt2x00_set_field32(®, TXCSR0_KICK_ATIM, 1); in rt2500pci_kick_queue()
764 rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg); in rt2500pci_kick_queue()
774 u32 reg; in rt2500pci_stop_queue() local
780 rt2x00mmio_register_read(rt2x00dev, TXCSR0, ®); in rt2500pci_stop_queue()
781 rt2x00_set_field32(®, TXCSR0_ABORT, 1); in rt2500pci_stop_queue()
782 rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg); in rt2500pci_stop_queue()
785 rt2x00mmio_register_read(rt2x00dev, RXCSR0, ®); in rt2500pci_stop_queue()
786 rt2x00_set_field32(®, RXCSR0_DISABLE_RX, 1); in rt2500pci_stop_queue()
787 rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg); in rt2500pci_stop_queue()
790 rt2x00mmio_register_read(rt2x00dev, CSR14, ®); in rt2500pci_stop_queue()
791 rt2x00_set_field32(®, CSR14_TSF_COUNT, 0); in rt2500pci_stop_queue()
792 rt2x00_set_field32(®, CSR14_TBCN, 0); in rt2500pci_stop_queue()
793 rt2x00_set_field32(®, CSR14_BEACON_GEN, 0); in rt2500pci_stop_queue()
794 rt2x00mmio_register_write(rt2x00dev, CSR14, reg); in rt2500pci_stop_queue()
851 u32 reg; in rt2500pci_init_queues() local
856 rt2x00mmio_register_read(rt2x00dev, TXCSR2, ®); in rt2500pci_init_queues()
857 rt2x00_set_field32(®, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size); in rt2500pci_init_queues()
858 rt2x00_set_field32(®, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit); in rt2500pci_init_queues()
859 rt2x00_set_field32(®, TXCSR2_NUM_ATIM, rt2x00dev->atim->limit); in rt2500pci_init_queues()
860 rt2x00_set_field32(®, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit); in rt2500pci_init_queues()
861 rt2x00mmio_register_write(rt2x00dev, TXCSR2, reg); in rt2500pci_init_queues()
864 rt2x00mmio_register_read(rt2x00dev, TXCSR3, ®); in rt2500pci_init_queues()
865 rt2x00_set_field32(®, TXCSR3_TX_RING_REGISTER, in rt2500pci_init_queues()
867 rt2x00mmio_register_write(rt2x00dev, TXCSR3, reg); in rt2500pci_init_queues()
870 rt2x00mmio_register_read(rt2x00dev, TXCSR5, ®); in rt2500pci_init_queues()
871 rt2x00_set_field32(®, TXCSR5_PRIO_RING_REGISTER, in rt2500pci_init_queues()
873 rt2x00mmio_register_write(rt2x00dev, TXCSR5, reg); in rt2500pci_init_queues()
876 rt2x00mmio_register_read(rt2x00dev, TXCSR4, ®); in rt2500pci_init_queues()
877 rt2x00_set_field32(®, TXCSR4_ATIM_RING_REGISTER, in rt2500pci_init_queues()
879 rt2x00mmio_register_write(rt2x00dev, TXCSR4, reg); in rt2500pci_init_queues()
882 rt2x00mmio_register_read(rt2x00dev, TXCSR6, ®); in rt2500pci_init_queues()
883 rt2x00_set_field32(®, TXCSR6_BEACON_RING_REGISTER, in rt2500pci_init_queues()
885 rt2x00mmio_register_write(rt2x00dev, TXCSR6, reg); in rt2500pci_init_queues()
887 rt2x00mmio_register_read(rt2x00dev, RXCSR1, ®); in rt2500pci_init_queues()
888 rt2x00_set_field32(®, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size); in rt2500pci_init_queues()
889 rt2x00_set_field32(®, RXCSR1_NUM_RXD, rt2x00dev->rx->limit); in rt2500pci_init_queues()
890 rt2x00mmio_register_write(rt2x00dev, RXCSR1, reg); in rt2500pci_init_queues()
893 rt2x00mmio_register_read(rt2x00dev, RXCSR2, ®); in rt2500pci_init_queues()
894 rt2x00_set_field32(®, RXCSR2_RX_RING_REGISTER, in rt2500pci_init_queues()
896 rt2x00mmio_register_write(rt2x00dev, RXCSR2, reg); in rt2500pci_init_queues()
903 u32 reg; in rt2500pci_init_registers() local
910 rt2x00mmio_register_read(rt2x00dev, TIMECSR, ®); in rt2500pci_init_registers()
911 rt2x00_set_field32(®, TIMECSR_US_COUNT, 33); in rt2500pci_init_registers()
912 rt2x00_set_field32(®, TIMECSR_US_64_COUNT, 63); in rt2500pci_init_registers()
913 rt2x00_set_field32(®, TIMECSR_BEACON_EXPECT, 0); in rt2500pci_init_registers()
914 rt2x00mmio_register_write(rt2x00dev, TIMECSR, reg); in rt2500pci_init_registers()
916 rt2x00mmio_register_read(rt2x00dev, CSR9, ®); in rt2500pci_init_registers()
917 rt2x00_set_field32(®, CSR9_MAX_FRAME_UNIT, in rt2500pci_init_registers()
919 rt2x00mmio_register_write(rt2x00dev, CSR9, reg); in rt2500pci_init_registers()
924 rt2x00mmio_register_read(rt2x00dev, CSR11, ®); in rt2500pci_init_registers()
925 rt2x00_set_field32(®, CSR11_CW_SELECT, 0); in rt2500pci_init_registers()
926 rt2x00mmio_register_write(rt2x00dev, CSR11, reg); in rt2500pci_init_registers()
928 rt2x00mmio_register_read(rt2x00dev, CSR14, ®); in rt2500pci_init_registers()
929 rt2x00_set_field32(®, CSR14_TSF_COUNT, 0); in rt2500pci_init_registers()
930 rt2x00_set_field32(®, CSR14_TSF_SYNC, 0); in rt2500pci_init_registers()
931 rt2x00_set_field32(®, CSR14_TBCN, 0); in rt2500pci_init_registers()
932 rt2x00_set_field32(®, CSR14_TCFP, 0); in rt2500pci_init_registers()
933 rt2x00_set_field32(®, CSR14_TATIMW, 0); in rt2500pci_init_registers()
934 rt2x00_set_field32(®, CSR14_BEACON_GEN, 0); in rt2500pci_init_registers()
935 rt2x00_set_field32(®, CSR14_CFP_COUNT_PRELOAD, 0); in rt2500pci_init_registers()
936 rt2x00_set_field32(®, CSR14_TBCM_PRELOAD, 0); in rt2500pci_init_registers()
937 rt2x00mmio_register_write(rt2x00dev, CSR14, reg); in rt2500pci_init_registers()
941 rt2x00mmio_register_read(rt2x00dev, TXCSR8, ®); in rt2500pci_init_registers()
942 rt2x00_set_field32(®, TXCSR8_BBP_ID0, 10); in rt2500pci_init_registers()
943 rt2x00_set_field32(®, TXCSR8_BBP_ID0_VALID, 1); in rt2500pci_init_registers()
944 rt2x00_set_field32(®, TXCSR8_BBP_ID1, 11); in rt2500pci_init_registers()
945 rt2x00_set_field32(®, TXCSR8_BBP_ID1_VALID, 1); in rt2500pci_init_registers()
946 rt2x00_set_field32(®, TXCSR8_BBP_ID2, 13); in rt2500pci_init_registers()
947 rt2x00_set_field32(®, TXCSR8_BBP_ID2_VALID, 1); in rt2500pci_init_registers()
948 rt2x00_set_field32(®, TXCSR8_BBP_ID3, 12); in rt2500pci_init_registers()
949 rt2x00_set_field32(®, TXCSR8_BBP_ID3_VALID, 1); in rt2500pci_init_registers()
950 rt2x00mmio_register_write(rt2x00dev, TXCSR8, reg); in rt2500pci_init_registers()
952 rt2x00mmio_register_read(rt2x00dev, ARTCSR0, ®); in rt2500pci_init_registers()
953 rt2x00_set_field32(®, ARTCSR0_ACK_CTS_1MBS, 112); in rt2500pci_init_registers()
954 rt2x00_set_field32(®, ARTCSR0_ACK_CTS_2MBS, 56); in rt2500pci_init_registers()
955 rt2x00_set_field32(®, ARTCSR0_ACK_CTS_5_5MBS, 20); in rt2500pci_init_registers()
956 rt2x00_set_field32(®, ARTCSR0_ACK_CTS_11MBS, 10); in rt2500pci_init_registers()
957 rt2x00mmio_register_write(rt2x00dev, ARTCSR0, reg); in rt2500pci_init_registers()
959 rt2x00mmio_register_read(rt2x00dev, ARTCSR1, ®); in rt2500pci_init_registers()
960 rt2x00_set_field32(®, ARTCSR1_ACK_CTS_6MBS, 45); in rt2500pci_init_registers()
961 rt2x00_set_field32(®, ARTCSR1_ACK_CTS_9MBS, 37); in rt2500pci_init_registers()
962 rt2x00_set_field32(®, ARTCSR1_ACK_CTS_12MBS, 33); in rt2500pci_init_registers()
963 rt2x00_set_field32(®, ARTCSR1_ACK_CTS_18MBS, 29); in rt2500pci_init_registers()
964 rt2x00mmio_register_write(rt2x00dev, ARTCSR1, reg); in rt2500pci_init_registers()
966 rt2x00mmio_register_read(rt2x00dev, ARTCSR2, ®); in rt2500pci_init_registers()
967 rt2x00_set_field32(®, ARTCSR2_ACK_CTS_24MBS, 29); in rt2500pci_init_registers()
968 rt2x00_set_field32(®, ARTCSR2_ACK_CTS_36MBS, 25); in rt2500pci_init_registers()
969 rt2x00_set_field32(®, ARTCSR2_ACK_CTS_48MBS, 25); in rt2500pci_init_registers()
970 rt2x00_set_field32(®, ARTCSR2_ACK_CTS_54MBS, 25); in rt2500pci_init_registers()
971 rt2x00mmio_register_write(rt2x00dev, ARTCSR2, reg); in rt2500pci_init_registers()
973 rt2x00mmio_register_read(rt2x00dev, RXCSR3, ®); in rt2500pci_init_registers()
974 rt2x00_set_field32(®, RXCSR3_BBP_ID0, 47); /* CCK Signal */ in rt2500pci_init_registers()
975 rt2x00_set_field32(®, RXCSR3_BBP_ID0_VALID, 1); in rt2500pci_init_registers()
976 rt2x00_set_field32(®, RXCSR3_BBP_ID1, 51); /* Rssi */ in rt2500pci_init_registers()
977 rt2x00_set_field32(®, RXCSR3_BBP_ID1_VALID, 1); in rt2500pci_init_registers()
978 rt2x00_set_field32(®, RXCSR3_BBP_ID2, 42); /* OFDM Rate */ in rt2500pci_init_registers()
979 rt2x00_set_field32(®, RXCSR3_BBP_ID2_VALID, 1); in rt2500pci_init_registers()
980 rt2x00_set_field32(®, RXCSR3_BBP_ID3, 51); /* RSSI */ in rt2500pci_init_registers()
981 rt2x00_set_field32(®, RXCSR3_BBP_ID3_VALID, 1); in rt2500pci_init_registers()
982 rt2x00mmio_register_write(rt2x00dev, RXCSR3, reg); in rt2500pci_init_registers()
984 rt2x00mmio_register_read(rt2x00dev, PCICSR, ®); in rt2500pci_init_registers()
985 rt2x00_set_field32(®, PCICSR_BIG_ENDIAN, 0); in rt2500pci_init_registers()
986 rt2x00_set_field32(®, PCICSR_RX_TRESHOLD, 0); in rt2500pci_init_registers()
987 rt2x00_set_field32(®, PCICSR_TX_TRESHOLD, 3); in rt2500pci_init_registers()
988 rt2x00_set_field32(®, PCICSR_BURST_LENTH, 1); in rt2500pci_init_registers()
989 rt2x00_set_field32(®, PCICSR_ENABLE_CLK, 1); in rt2500pci_init_registers()
990 rt2x00_set_field32(®, PCICSR_READ_MULTIPLE, 1); in rt2500pci_init_registers()
991 rt2x00_set_field32(®, PCICSR_WRITE_INVALID, 1); in rt2500pci_init_registers()
992 rt2x00mmio_register_write(rt2x00dev, PCICSR, reg); in rt2500pci_init_registers()
1005 rt2x00mmio_register_read(rt2x00dev, MACCSR2, ®); in rt2500pci_init_registers()
1006 rt2x00_set_field32(®, MACCSR2_DELAY, 64); in rt2500pci_init_registers()
1007 rt2x00mmio_register_write(rt2x00dev, MACCSR2, reg); in rt2500pci_init_registers()
1009 rt2x00mmio_register_read(rt2x00dev, RALINKCSR, ®); in rt2500pci_init_registers()
1010 rt2x00_set_field32(®, RALINKCSR_AR_BBP_DATA0, 17); in rt2500pci_init_registers()
1011 rt2x00_set_field32(®, RALINKCSR_AR_BBP_ID0, 26); in rt2500pci_init_registers()
1012 rt2x00_set_field32(®, RALINKCSR_AR_BBP_VALID0, 1); in rt2500pci_init_registers()
1013 rt2x00_set_field32(®, RALINKCSR_AR_BBP_DATA1, 0); in rt2500pci_init_registers()
1014 rt2x00_set_field32(®, RALINKCSR_AR_BBP_ID1, 26); in rt2500pci_init_registers()
1015 rt2x00_set_field32(®, RALINKCSR_AR_BBP_VALID1, 1); in rt2500pci_init_registers()
1016 rt2x00mmio_register_write(rt2x00dev, RALINKCSR, reg); in rt2500pci_init_registers()
1022 rt2x00mmio_register_read(rt2x00dev, CSR1, ®); in rt2500pci_init_registers()
1023 rt2x00_set_field32(®, CSR1_SOFT_RESET, 1); in rt2500pci_init_registers()
1024 rt2x00_set_field32(®, CSR1_BBP_RESET, 0); in rt2500pci_init_registers()
1025 rt2x00_set_field32(®, CSR1_HOST_READY, 0); in rt2500pci_init_registers()
1026 rt2x00mmio_register_write(rt2x00dev, CSR1, reg); in rt2500pci_init_registers()
1028 rt2x00mmio_register_read(rt2x00dev, CSR1, ®); in rt2500pci_init_registers()
1029 rt2x00_set_field32(®, CSR1_SOFT_RESET, 0); in rt2500pci_init_registers()
1030 rt2x00_set_field32(®, CSR1_HOST_READY, 1); in rt2500pci_init_registers()
1031 rt2x00mmio_register_write(rt2x00dev, CSR1, reg); in rt2500pci_init_registers()
1038 rt2x00mmio_register_read(rt2x00dev, CNT0, ®); in rt2500pci_init_registers()
1039 rt2x00mmio_register_read(rt2x00dev, CNT4, ®); in rt2500pci_init_registers()
1121 u32 reg; in rt2500pci_toggle_irq() local
1129 rt2x00mmio_register_read(rt2x00dev, CSR7, ®); in rt2500pci_toggle_irq()
1130 rt2x00mmio_register_write(rt2x00dev, CSR7, reg); in rt2500pci_toggle_irq()
1139 rt2x00mmio_register_read(rt2x00dev, CSR8, ®); in rt2500pci_toggle_irq()
1140 rt2x00_set_field32(®, CSR8_TBCN_EXPIRE, mask); in rt2500pci_toggle_irq()
1141 rt2x00_set_field32(®, CSR8_TXDONE_TXRING, mask); in rt2500pci_toggle_irq()
1142 rt2x00_set_field32(®, CSR8_TXDONE_ATIMRING, mask); in rt2500pci_toggle_irq()
1143 rt2x00_set_field32(®, CSR8_TXDONE_PRIORING, mask); in rt2500pci_toggle_irq()
1144 rt2x00_set_field32(®, CSR8_RXDONE, mask); in rt2500pci_toggle_irq()
1145 rt2x00mmio_register_write(rt2x00dev, CSR8, reg); in rt2500pci_toggle_irq()
1183 u32 reg, reg2; in rt2500pci_set_state() local
1191 rt2x00mmio_register_read(rt2x00dev, PWRCSR1, ®); in rt2500pci_set_state()
1192 rt2x00_set_field32(®, PWRCSR1_SET_STATE, 1); in rt2500pci_set_state()
1193 rt2x00_set_field32(®, PWRCSR1_BBP_DESIRE_STATE, state); in rt2500pci_set_state()
1194 rt2x00_set_field32(®, PWRCSR1_RF_DESIRE_STATE, state); in rt2500pci_set_state()
1195 rt2x00_set_field32(®, PWRCSR1_PUT_TO_SLEEP, put_to_sleep); in rt2500pci_set_state()
1196 rt2x00mmio_register_write(rt2x00dev, PWRCSR1, reg); in rt2500pci_set_state()
1209 rt2x00mmio_register_write(rt2x00dev, PWRCSR1, reg); in rt2500pci_set_state()
1327 u32 reg; in rt2500pci_write_beacon() local
1333 rt2x00mmio_register_read(rt2x00dev, CSR14, ®); in rt2500pci_write_beacon()
1334 rt2x00_set_field32(®, CSR14_BEACON_GEN, 0); in rt2500pci_write_beacon()
1335 rt2x00mmio_register_write(rt2x00dev, CSR14, reg); in rt2500pci_write_beacon()
1355 rt2x00_set_field32(®, CSR14_BEACON_GEN, 1); in rt2500pci_write_beacon()
1356 rt2x00mmio_register_write(rt2x00dev, CSR14, reg); in rt2500pci_write_beacon()
1441 u32 reg; in rt2500pci_enable_interrupt() local
1449 rt2x00mmio_register_read(rt2x00dev, CSR8, ®); in rt2500pci_enable_interrupt()
1450 rt2x00_set_field32(®, irq_field, 0); in rt2500pci_enable_interrupt()
1451 rt2x00mmio_register_write(rt2x00dev, CSR8, reg); in rt2500pci_enable_interrupt()
1459 u32 reg; in rt2500pci_txstatus_tasklet() local
1474 rt2x00mmio_register_read(rt2x00dev, CSR8, ®); in rt2500pci_txstatus_tasklet()
1475 rt2x00_set_field32(®, CSR8_TXDONE_TXRING, 0); in rt2500pci_txstatus_tasklet()
1476 rt2x00_set_field32(®, CSR8_TXDONE_ATIMRING, 0); in rt2500pci_txstatus_tasklet()
1477 rt2x00_set_field32(®, CSR8_TXDONE_PRIORING, 0); in rt2500pci_txstatus_tasklet()
1478 rt2x00mmio_register_write(rt2x00dev, CSR8, reg); in rt2500pci_txstatus_tasklet()
1504 u32 reg, mask; in rt2500pci_interrupt() local
1510 rt2x00mmio_register_read(rt2x00dev, CSR7, ®); in rt2500pci_interrupt()
1511 rt2x00mmio_register_write(rt2x00dev, CSR7, reg); in rt2500pci_interrupt()
1513 if (!reg) in rt2500pci_interrupt()
1519 mask = reg; in rt2500pci_interrupt()
1524 if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE)) in rt2500pci_interrupt()
1527 if (rt2x00_get_field32(reg, CSR7_RXDONE)) in rt2500pci_interrupt()
1530 if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING) || in rt2500pci_interrupt()
1531 rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING) || in rt2500pci_interrupt()
1532 rt2x00_get_field32(reg, CSR7_TXDONE_TXRING)) { in rt2500pci_interrupt()
1548 rt2x00mmio_register_read(rt2x00dev, CSR8, ®); in rt2500pci_interrupt()
1549 reg |= mask; in rt2500pci_interrupt()
1550 rt2x00mmio_register_write(rt2x00dev, CSR8, reg); in rt2500pci_interrupt()
1563 u32 reg; in rt2500pci_validate_eeprom() local
1567 rt2x00mmio_register_read(rt2x00dev, CSR21, ®); in rt2500pci_validate_eeprom()
1572 eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ? in rt2500pci_validate_eeprom()
1630 u32 reg; in rt2500pci_init_eeprom() local
1643 rt2x00mmio_register_read(rt2x00dev, CSR0, ®); in rt2500pci_init_eeprom()
1645 rt2x00_get_field32(reg, CSR0_REVISION)); in rt2500pci_init_eeprom()
1942 u32 reg; in rt2500pci_probe_hw() local
1959 rt2x00mmio_register_read(rt2x00dev, GPIOCSR, ®); in rt2500pci_probe_hw()
1960 rt2x00_set_field32(®, GPIOCSR_DIR0, 1); in rt2500pci_probe_hw()
1961 rt2x00mmio_register_write(rt2x00dev, GPIOCSR, reg); in rt2500pci_probe_hw()
1993 u32 reg; in rt2500pci_get_tsf() local
1995 rt2x00mmio_register_read(rt2x00dev, CSR17, ®); in rt2500pci_get_tsf()
1996 tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32; in rt2500pci_get_tsf()
1997 rt2x00mmio_register_read(rt2x00dev, CSR16, ®); in rt2500pci_get_tsf()
1998 tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER); in rt2500pci_get_tsf()
2006 u32 reg; in rt2500pci_tx_last_beacon() local
2008 rt2x00mmio_register_read(rt2x00dev, CSR15, ®); in rt2500pci_tx_last_beacon()
2009 return rt2x00_get_field32(reg, CSR15_BEACON_SENT); in rt2500pci_tx_last_beacon()