57 	void __iomem *reg;  member
83 	return !!(readl(corediv->reg) & enable_mask);  in clk_corediv_is_enabled()
92 	u32 reg;  in clk_corediv_enable()  local
96 	reg = readl(corediv->reg);  in clk_corediv_enable()
97 	reg |= (BIT(desc->fieldbit) << soc_desc->enable_bit_offset);  in clk_corediv_enable()
98 	writel(reg, corediv->reg);  in clk_corediv_enable()
111 	u32 reg;  in clk_corediv_disable()  local
115 	reg = readl(corediv->reg);  in clk_corediv_disable()
116 	reg &= ~(BIT(desc->fieldbit) << soc_desc->enable_bit_offset);  in clk_corediv_disable()
117 	writel(reg, corediv->reg);  in clk_corediv_disable()
128 	u32 reg, div;  in clk_corediv_recalc_rate()  local
130 	reg = readl(corediv->reg + soc_desc->ratio_offset);  in clk_corediv_recalc_rate()
131 	div = (reg >> desc->offset) & desc->mask;  in clk_corediv_recalc_rate()
157 	u32 reg, div;  in clk_corediv_set_rate()  local
164 	reg = readl(corediv->reg + soc_desc->ratio_offset);  in clk_corediv_set_rate()
165 	reg &= ~(desc->mask << desc->offset);  in clk_corediv_set_rate()
166 	reg |= (div & desc->mask) << desc->offset;  in clk_corediv_set_rate()
167 	writel(reg, corediv->reg + soc_desc->ratio_offset);  in clk_corediv_set_rate()
170 	reg = readl(corediv->reg) | BIT(desc->fieldbit);  in clk_corediv_set_rate()
171 	writel(reg, corediv->reg);  in clk_corediv_set_rate()
174 	reg = readl(corediv->reg) | soc_desc->ratio_reload;  in clk_corediv_set_rate()
175 	writel(reg, corediv->reg);  in clk_corediv_set_rate()
182 	reg &= ~(CORE_CLK_DIV_RATIO_MASK | soc_desc->ratio_reload);  in clk_corediv_set_rate()
183 	writel(reg, corediv->reg);  in clk_corediv_set_rate()
279 		corediv[i].reg = base;  in mvebu_corediv_clk_init()