Lines Matching refs:reg
88 u32 reg; in rt2800_bbp_write() local
96 if (WAIT_FOR_BBP(rt2x00dev, ®)) { in rt2800_bbp_write()
97 reg = 0; in rt2800_bbp_write()
98 rt2x00_set_field32(®, BBP_CSR_CFG_VALUE, value); in rt2800_bbp_write()
99 rt2x00_set_field32(®, BBP_CSR_CFG_REGNUM, word); in rt2800_bbp_write()
100 rt2x00_set_field32(®, BBP_CSR_CFG_BUSY, 1); in rt2800_bbp_write()
101 rt2x00_set_field32(®, BBP_CSR_CFG_READ_CONTROL, 0); in rt2800_bbp_write()
102 rt2x00_set_field32(®, BBP_CSR_CFG_BBP_RW_MODE, 1); in rt2800_bbp_write()
104 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg); in rt2800_bbp_write()
113 u32 reg; in rt2800_bbp_read() local
125 if (WAIT_FOR_BBP(rt2x00dev, ®)) { in rt2800_bbp_read()
126 reg = 0; in rt2800_bbp_read()
127 rt2x00_set_field32(®, BBP_CSR_CFG_REGNUM, word); in rt2800_bbp_read()
128 rt2x00_set_field32(®, BBP_CSR_CFG_BUSY, 1); in rt2800_bbp_read()
129 rt2x00_set_field32(®, BBP_CSR_CFG_READ_CONTROL, 1); in rt2800_bbp_read()
130 rt2x00_set_field32(®, BBP_CSR_CFG_BBP_RW_MODE, 1); in rt2800_bbp_read()
132 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg); in rt2800_bbp_read()
134 WAIT_FOR_BBP(rt2x00dev, ®); in rt2800_bbp_read()
137 *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE); in rt2800_bbp_read()
145 u32 reg; in rt2800_rfcsr_write() local
153 if (WAIT_FOR_RFCSR(rt2x00dev, ®)) { in rt2800_rfcsr_write()
154 reg = 0; in rt2800_rfcsr_write()
155 rt2x00_set_field32(®, RF_CSR_CFG_DATA, value); in rt2800_rfcsr_write()
156 rt2x00_set_field32(®, RF_CSR_CFG_REGNUM, word); in rt2800_rfcsr_write()
157 rt2x00_set_field32(®, RF_CSR_CFG_WRITE, 1); in rt2800_rfcsr_write()
158 rt2x00_set_field32(®, RF_CSR_CFG_BUSY, 1); in rt2800_rfcsr_write()
160 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg); in rt2800_rfcsr_write()
169 u32 reg; in rt2800_rfcsr_read() local
181 if (WAIT_FOR_RFCSR(rt2x00dev, ®)) { in rt2800_rfcsr_read()
182 reg = 0; in rt2800_rfcsr_read()
183 rt2x00_set_field32(®, RF_CSR_CFG_REGNUM, word); in rt2800_rfcsr_read()
184 rt2x00_set_field32(®, RF_CSR_CFG_WRITE, 0); in rt2800_rfcsr_read()
185 rt2x00_set_field32(®, RF_CSR_CFG_BUSY, 1); in rt2800_rfcsr_read()
187 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg); in rt2800_rfcsr_read()
189 WAIT_FOR_RFCSR(rt2x00dev, ®); in rt2800_rfcsr_read()
192 *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA); in rt2800_rfcsr_read()
200 u32 reg; in rt2800_rf_write() local
208 if (WAIT_FOR_RF(rt2x00dev, ®)) { in rt2800_rf_write()
209 reg = 0; in rt2800_rf_write()
210 rt2x00_set_field32(®, RF_CSR_CFG0_REG_VALUE_BW, value); in rt2800_rf_write()
211 rt2x00_set_field32(®, RF_CSR_CFG0_STANDBYMODE, 0); in rt2800_rf_write()
212 rt2x00_set_field32(®, RF_CSR_CFG0_SEL, 0); in rt2800_rf_write()
213 rt2x00_set_field32(®, RF_CSR_CFG0_BUSY, 1); in rt2800_rf_write()
215 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg); in rt2800_rf_write()
372 u32 reg; in rt2800_enable_wlan_rt3290() local
375 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, ®); in rt2800_enable_wlan_rt3290()
376 if (rt2x00_get_field32(reg, WLAN_EN)) in rt2800_enable_wlan_rt3290()
379 rt2x00_set_field32(®, WLAN_GPIO_OUT_OE_BIT_ALL, 0xff); in rt2800_enable_wlan_rt3290()
380 rt2x00_set_field32(®, FRC_WL_ANT_SET, 1); in rt2800_enable_wlan_rt3290()
381 rt2x00_set_field32(®, WLAN_CLK_EN, 0); in rt2800_enable_wlan_rt3290()
382 rt2x00_set_field32(®, WLAN_EN, 1); in rt2800_enable_wlan_rt3290()
383 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg); in rt2800_enable_wlan_rt3290()
393 rt2800_register_read(rt2x00dev, CMB_CTRL, ®); in rt2800_enable_wlan_rt3290()
394 if (rt2x00_get_field32(reg, PLL_LD) && in rt2800_enable_wlan_rt3290()
395 rt2x00_get_field32(reg, XTAL_RDY)) in rt2800_enable_wlan_rt3290()
416 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, ®); in rt2800_enable_wlan_rt3290()
417 rt2x00_set_field32(®, PCIE_APP0_CLK_REQ, 0); in rt2800_enable_wlan_rt3290()
418 rt2x00_set_field32(®, WLAN_CLK_EN, 1); in rt2800_enable_wlan_rt3290()
419 rt2x00_set_field32(®, WLAN_RESET, 1); in rt2800_enable_wlan_rt3290()
420 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg); in rt2800_enable_wlan_rt3290()
422 rt2x00_set_field32(®, WLAN_RESET, 0); in rt2800_enable_wlan_rt3290()
423 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg); in rt2800_enable_wlan_rt3290()
435 u32 reg; in rt2800_mcu_request() local
449 if (WAIT_FOR_MCU(rt2x00dev, ®)) { in rt2800_mcu_request()
450 rt2x00_set_field32(®, H2M_MAILBOX_CSR_OWNER, 1); in rt2800_mcu_request()
451 rt2x00_set_field32(®, H2M_MAILBOX_CSR_CMD_TOKEN, token); in rt2800_mcu_request()
452 rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG0, arg0); in rt2800_mcu_request()
453 rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG1, arg1); in rt2800_mcu_request()
454 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg); in rt2800_mcu_request()
456 reg = 0; in rt2800_mcu_request()
457 rt2x00_set_field32(®, HOST_CMD_CSR_HOST_COMMAND, command); in rt2800_mcu_request()
458 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg); in rt2800_mcu_request()
468 u32 reg; in rt2800_wait_csr_ready() local
471 rt2800_register_read(rt2x00dev, MAC_CSR0, ®); in rt2800_wait_csr_ready()
472 if (reg && reg != ~0) in rt2800_wait_csr_ready()
485 u32 reg; in rt2800_wait_wpdma_ready() local
492 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, ®); in rt2800_wait_wpdma_ready()
493 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) && in rt2800_wait_wpdma_ready()
494 !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY)) in rt2800_wait_wpdma_ready()
500 rt2x00_err(rt2x00dev, "WPDMA TX/RX busy [0x%08x]\n", reg); in rt2800_wait_wpdma_ready()
507 u32 reg; in rt2800_disable_wpdma() local
509 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, ®); in rt2800_disable_wpdma()
510 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0); in rt2800_disable_wpdma()
511 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_DMA_BUSY, 0); in rt2800_disable_wpdma()
512 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0); in rt2800_disable_wpdma()
513 rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_DMA_BUSY, 0); in rt2800_disable_wpdma()
514 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1); in rt2800_disable_wpdma()
515 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); in rt2800_disable_wpdma()
632 u32 reg; in rt2800_load_firmware() local
658 rt2800_register_read(rt2x00dev, AUX_CTRL, ®); in rt2800_load_firmware()
659 rt2x00_set_field32(®, AUX_CTRL_FORCE_PCIE_CLK, 1); in rt2800_load_firmware()
660 rt2x00_set_field32(®, AUX_CTRL_WAKE_PCIE_EN, 1); in rt2800_load_firmware()
661 rt2800_register_write(rt2x00dev, AUX_CTRL, reg); in rt2800_load_firmware()
677 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, ®); in rt2800_load_firmware()
678 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY)) in rt2800_load_firmware()
955 u64 off, reg = 0; in rt2800_update_beacons_setup() local
966 reg |= off << (8 * bcn_num); in rt2800_update_beacons_setup()
972 rt2800_register_write(rt2x00dev, BCN_OFFSET0, (u32) reg); in rt2800_update_beacons_setup()
973 rt2800_register_write(rt2x00dev, BCN_OFFSET1, (u32) (reg >> 32)); in rt2800_update_beacons_setup()
990 u32 orig_reg, reg; in rt2800_write_beacon() local
997 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, ®); in rt2800_write_beacon()
998 orig_reg = reg; in rt2800_write_beacon()
999 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0); in rt2800_write_beacon()
1000 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); in rt2800_write_beacon()
1081 u32 orig_reg, reg; in rt2800_clear_beacon() local
1088 reg = orig_reg; in rt2800_clear_beacon()
1089 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0); in rt2800_clear_beacon()
1090 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); in rt2800_clear_beacon()
1157 u32 reg; in rt2800_rfkill_poll() local
1160 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, ®); in rt2800_rfkill_poll()
1161 return rt2x00_get_field32(reg, WLAN_GPIO_IN_BIT0); in rt2800_rfkill_poll()
1163 rt2800_register_read(rt2x00dev, GPIO_CTRL, ®); in rt2800_rfkill_poll()
1164 return rt2x00_get_field32(reg, GPIO_CTRL_VAL2); in rt2800_rfkill_poll()
1184 u32 reg; in rt2800_brightness_set() local
1188 rt2800_register_read(led->rt2x00dev, LED_CFG, ®); in rt2800_brightness_set()
1191 rt2x00_set_field32(®, LED_CFG_LED_POLAR, polarity); in rt2800_brightness_set()
1195 rt2x00_set_field32(®, LED_CFG_G_LED_MODE, in rt2800_brightness_set()
1198 rt2x00_set_field32(®, LED_CFG_Y_LED_MODE, in rt2800_brightness_set()
1201 rt2x00_set_field32(®, LED_CFG_R_LED_MODE, in rt2800_brightness_set()
1205 rt2800_register_write(led->rt2x00dev, LED_CFG, reg); in rt2800_brightness_set()
1271 u32 reg; in rt2800_config_wcid_attr_bssidx() local
1277 rt2800_register_read(rt2x00dev, offset, ®); in rt2800_config_wcid_attr_bssidx()
1278 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_BSS_IDX, (bssidx & 0x7)); in rt2800_config_wcid_attr_bssidx()
1279 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT, in rt2800_config_wcid_attr_bssidx()
1281 rt2800_register_write(rt2x00dev, offset, reg); in rt2800_config_wcid_attr_bssidx()
1290 u32 reg; in rt2800_config_wcid_attr_cipher() local
1295 rt2800_register_read(rt2x00dev, offset, ®); in rt2800_config_wcid_attr_cipher()
1296 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_KEYTAB, in rt2800_config_wcid_attr_cipher()
1303 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER, in rt2800_config_wcid_attr_cipher()
1305 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER_EXT, in rt2800_config_wcid_attr_cipher()
1307 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher); in rt2800_config_wcid_attr_cipher()
1308 rt2800_register_write(rt2x00dev, offset, reg); in rt2800_config_wcid_attr_cipher()
1311 rt2800_register_read(rt2x00dev, offset, ®); in rt2800_config_wcid_attr_cipher()
1312 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_KEYTAB, 0); in rt2800_config_wcid_attr_cipher()
1313 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER, 0); in rt2800_config_wcid_attr_cipher()
1314 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 0); in rt2800_config_wcid_attr_cipher()
1315 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0); in rt2800_config_wcid_attr_cipher()
1316 rt2800_register_write(rt2x00dev, offset, reg); in rt2800_config_wcid_attr_cipher()
1338 u32 reg; in rt2800_config_shared_key() local
1367 rt2800_register_read(rt2x00dev, offset, ®); in rt2800_config_shared_key()
1368 rt2x00_set_field32(®, field, in rt2800_config_shared_key()
1370 rt2800_register_write(rt2x00dev, offset, reg); in rt2800_config_shared_key()
1480 u32 reg; in rt2800_config_filter() local
1488 rt2800_register_read(rt2x00dev, RX_FILTER_CFG, ®); in rt2800_config_filter()
1489 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CRC_ERROR, in rt2800_config_filter()
1491 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_PHY_ERROR, in rt2800_config_filter()
1493 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_NOT_TO_ME, 1); in rt2800_config_filter()
1494 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0); in rt2800_config_filter()
1495 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_VER_ERROR, 1); in rt2800_config_filter()
1496 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_MULTICAST, in rt2800_config_filter()
1498 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BROADCAST, 0); in rt2800_config_filter()
1499 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_DUPLICATE, 1); in rt2800_config_filter()
1500 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CF_END_ACK, in rt2800_config_filter()
1502 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CF_END, in rt2800_config_filter()
1504 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_ACK, in rt2800_config_filter()
1506 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CTS, in rt2800_config_filter()
1508 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_RTS, in rt2800_config_filter()
1510 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_PSPOLL, in rt2800_config_filter()
1512 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BA, 0); in rt2800_config_filter()
1513 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BAR, in rt2800_config_filter()
1515 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CNTL, in rt2800_config_filter()
1517 rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg); in rt2800_config_filter()
1524 u32 reg; in rt2800_config_intf() local
1531 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, ®); in rt2800_config_intf()
1532 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_SYNC, conf->sync); in rt2800_config_intf()
1533 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); in rt2800_config_intf()
1539 rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, ®); in rt2800_config_intf()
1540 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_CWMIN, 0); in rt2800_config_intf()
1541 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_AIFSN, 1); in rt2800_config_intf()
1542 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_EXP_WIN, 32); in rt2800_config_intf()
1543 rt2x00_set_field32(®, TBTT_SYNC_CFG_TBTT_ADJUST, 0); in rt2800_config_intf()
1544 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg); in rt2800_config_intf()
1546 rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, ®); in rt2800_config_intf()
1547 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_CWMIN, 4); in rt2800_config_intf()
1548 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_AIFSN, 2); in rt2800_config_intf()
1549 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_EXP_WIN, 32); in rt2800_config_intf()
1550 rt2x00_set_field32(®, TBTT_SYNC_CFG_TBTT_ADJUST, 16); in rt2800_config_intf()
1551 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg); in rt2800_config_intf()
1567 reg = le32_to_cpu(conf->mac[1]); in rt2800_config_intf()
1568 rt2x00_set_field32(®, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff); in rt2800_config_intf()
1569 conf->mac[1] = cpu_to_le32(reg); in rt2800_config_intf()
1578 reg = le32_to_cpu(conf->bssid[1]); in rt2800_config_intf()
1579 rt2x00_set_field32(®, MAC_BSSID_DW1_BSS_ID_MASK, 3); in rt2800_config_intf()
1580 rt2x00_set_field32(®, MAC_BSSID_DW1_BSS_BCN_NUM, 0); in rt2800_config_intf()
1581 conf->bssid[1] = cpu_to_le32(reg); in rt2800_config_intf()
1598 u32 reg; in rt2800_config_ht_opmode() local
1665 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, ®); in rt2800_config_ht_opmode()
1666 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_RATE, mm20_rate); in rt2800_config_ht_opmode()
1667 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode); in rt2800_config_ht_opmode()
1668 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg); in rt2800_config_ht_opmode()
1670 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, ®); in rt2800_config_ht_opmode()
1671 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_RATE, mm40_rate); in rt2800_config_ht_opmode()
1672 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode); in rt2800_config_ht_opmode()
1673 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg); in rt2800_config_ht_opmode()
1675 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, ®); in rt2800_config_ht_opmode()
1676 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_RATE, gf20_rate); in rt2800_config_ht_opmode()
1677 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode); in rt2800_config_ht_opmode()
1678 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg); in rt2800_config_ht_opmode()
1680 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, ®); in rt2800_config_ht_opmode()
1681 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_RATE, gf40_rate); in rt2800_config_ht_opmode()
1682 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode); in rt2800_config_ht_opmode()
1683 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg); in rt2800_config_ht_opmode()
1689 u32 reg; in rt2800_config_erp() local
1692 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, ®); in rt2800_config_erp()
1693 rt2x00_set_field32(®, AUTO_RSP_CFG_BAC_ACK_POLICY, in rt2800_config_erp()
1695 rt2x00_set_field32(®, AUTO_RSP_CFG_AR_PREAMBLE, in rt2800_config_erp()
1697 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg); in rt2800_config_erp()
1701 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, ®); in rt2800_config_erp()
1702 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_CTRL, in rt2800_config_erp()
1704 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg); in rt2800_config_erp()
1714 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, ®); in rt2800_config_erp()
1715 rt2x00_set_field32(®, BKOFF_SLOT_CFG_SLOT_TIME, in rt2800_config_erp()
1717 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg); in rt2800_config_erp()
1719 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, ®); in rt2800_config_erp()
1720 rt2x00_set_field32(®, XIFS_TIME_CFG_EIFS, erp->eifs); in rt2800_config_erp()
1721 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg); in rt2800_config_erp()
1725 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, ®); in rt2800_config_erp()
1726 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_INTERVAL, in rt2800_config_erp()
1728 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); in rt2800_config_erp()
1738 u32 reg; in rt2800_config_3572bt_ant() local
1742 rt2800_register_read(rt2x00dev, GPIO_SWITCH, ®); in rt2800_config_3572bt_ant()
1744 rt2x00_set_field32(®, GPIO_SWITCH_0, 1); in rt2800_config_3572bt_ant()
1745 rt2x00_set_field32(®, GPIO_SWITCH_1, 1); in rt2800_config_3572bt_ant()
1747 rt2x00_set_field32(®, GPIO_SWITCH_0, 0); in rt2800_config_3572bt_ant()
1748 rt2x00_set_field32(®, GPIO_SWITCH_1, 0); in rt2800_config_3572bt_ant()
1750 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg); in rt2800_config_3572bt_ant()
1752 rt2800_register_read(rt2x00dev, LED_CFG, ®); in rt2800_config_3572bt_ant()
1753 led_g_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 3 : 0; in rt2800_config_3572bt_ant()
1754 led_r_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 0 : 3; in rt2800_config_3572bt_ant()
1755 if (led_g_mode != rt2x00_get_field32(reg, LED_CFG_G_LED_MODE) || in rt2800_config_3572bt_ant()
1756 led_r_mode != rt2x00_get_field32(reg, LED_CFG_R_LED_MODE)) { in rt2800_config_3572bt_ant()
1760 rt2x00_set_field32(®, LED_CFG_G_LED_MODE, led_g_mode); in rt2800_config_3572bt_ant()
1761 rt2x00_set_field32(®, LED_CFG_R_LED_MODE, led_r_mode); in rt2800_config_3572bt_ant()
1762 rt2800_register_write(rt2x00dev, LED_CFG, reg); in rt2800_config_3572bt_ant()
1773 u32 reg; in rt2800_set_ant_diversity() local
1778 rt2800_register_read(rt2x00dev, E2PROM_CSR, ®); in rt2800_set_ant_diversity()
1779 rt2x00_set_field32(®, E2PROM_CSR_DATA_CLOCK, eesk_pin); in rt2800_set_ant_diversity()
1780 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg); in rt2800_set_ant_diversity()
1785 rt2800_register_read(rt2x00dev, GPIO_CTRL, ®); in rt2800_set_ant_diversity()
1786 rt2x00_set_field32(®, GPIO_CTRL_DIR3, 0); in rt2800_set_ant_diversity()
1787 rt2x00_set_field32(®, GPIO_CTRL_VAL3, gpio_bit3); in rt2800_set_ant_diversity()
1788 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg); in rt2800_set_ant_diversity()
2091 u32 reg; in rt2800_config_channel_rf3052() local
2241 rt2800_register_read(rt2x00dev, GPIO_CTRL, ®); in rt2800_config_channel_rf3052()
2242 rt2x00_set_field32(®, GPIO_CTRL_DIR7, 0); in rt2800_config_channel_rf3052()
2244 rt2x00_set_field32(®, GPIO_CTRL_VAL7, 1); in rt2800_config_channel_rf3052()
2246 rt2x00_set_field32(®, GPIO_CTRL_VAL7, 0); in rt2800_config_channel_rf3052()
2247 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg); in rt2800_config_channel_rf3052()
2738 u32 reg; in rt2800_config_channel_rf55xx() local
2745 rt2800_register_read(rt2x00dev, LDO_CFG0, ®); in rt2800_config_channel_rf55xx()
2746 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, in rt2800_config_channel_rf55xx()
2748 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); in rt2800_config_channel_rf55xx()
3011 u8 chain, reg; in rt2800_bbp_write_with_rx_chain() local
3014 rt2800_bbp_read(rt2x00dev, 27, ®); in rt2800_bbp_write_with_rx_chain()
3015 rt2x00_set_field8(®, BBP27_RX_CHAIN_SEL, chain); in rt2800_bbp_write_with_rx_chain()
3016 rt2800_bbp_write(rt2x00dev, 27, reg); in rt2800_bbp_write_with_rx_chain()
3130 u32 reg; in rt2800_config_channel() local
3264 rt2800_register_read(rt2x00dev, TX_BAND_CFG, ®); in rt2800_config_channel()
3265 rt2x00_set_field32(®, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf)); in rt2800_config_channel()
3266 rt2x00_set_field32(®, TX_BAND_CFG_A, rf->channel > 14); in rt2800_config_channel()
3267 rt2x00_set_field32(®, TX_BAND_CFG_BG, rf->channel <= 14); in rt2800_config_channel()
3268 rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg); in rt2800_config_channel()
3330 reg = 0x1c + (2 * rt2x00dev->lna_gain); in rt2800_config_channel()
3332 reg = 0x22 + ((rt2x00dev->lna_gain * 5) / 3); in rt2800_config_channel()
3334 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg); in rt2800_config_channel()
3338 rt2800_register_read(rt2x00dev, GPIO_CTRL, ®); in rt2800_config_channel()
3344 rt2x00_set_field32(®, GPIO_CTRL_DIR8, 0); in rt2800_config_channel()
3346 rt2x00_set_field32(®, GPIO_CTRL_VAL8, 1); in rt2800_config_channel()
3348 rt2x00_set_field32(®, GPIO_CTRL_VAL8, 0); in rt2800_config_channel()
3356 rt2x00_set_field32(®, GPIO_CTRL_DIR4, 0); in rt2800_config_channel()
3357 rt2x00_set_field32(®, GPIO_CTRL_DIR7, 0); in rt2800_config_channel()
3359 rt2x00_set_field32(®, GPIO_CTRL_VAL4, 1); in rt2800_config_channel()
3360 rt2x00_set_field32(®, GPIO_CTRL_VAL7, 1); in rt2800_config_channel()
3363 rt2x00_set_field32(®, GPIO_CTRL_DIR4, 0); in rt2800_config_channel()
3364 rt2x00_set_field32(®, GPIO_CTRL_VAL4, 1); in rt2800_config_channel()
3367 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg); in rt2800_config_channel()
3371 reg = 0x1c + 2 * rt2x00dev->lna_gain; in rt2800_config_channel()
3373 reg = 0x22 + ((rt2x00dev->lna_gain * 5) / 3); in rt2800_config_channel()
3375 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg); in rt2800_config_channel()
3385 reg = (rf->channel <= 14 ? 0x1c : 0x24) + 2 * rt2x00dev->lna_gain; in rt2800_config_channel()
3386 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg); in rt2800_config_channel()
3416 rt2800_register_read(rt2x00dev, CH_IDLE_STA, ®); in rt2800_config_channel()
3417 rt2800_register_read(rt2x00dev, CH_BUSY_STA, ®); in rt2800_config_channel()
3418 rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, ®); in rt2800_config_channel()
4081 u32 reg, offset; in rt2800_config_txpower_rt28xx() local
4149 rt2800_register_read(rt2x00dev, offset, ®); in rt2800_config_txpower_rt28xx()
4165 rt2x00_set_field32(®, TX_PWR_CFG_RATE0, txpower); in rt2800_config_txpower_rt28xx()
4176 rt2x00_set_field32(®, TX_PWR_CFG_RATE1, txpower); in rt2800_config_txpower_rt28xx()
4187 rt2x00_set_field32(®, TX_PWR_CFG_RATE2, txpower); in rt2800_config_txpower_rt28xx()
4198 rt2x00_set_field32(®, TX_PWR_CFG_RATE3, txpower); in rt2800_config_txpower_rt28xx()
4214 rt2x00_set_field32(®, TX_PWR_CFG_RATE4, txpower); in rt2800_config_txpower_rt28xx()
4225 rt2x00_set_field32(®, TX_PWR_CFG_RATE5, txpower); in rt2800_config_txpower_rt28xx()
4236 rt2x00_set_field32(®, TX_PWR_CFG_RATE6, txpower); in rt2800_config_txpower_rt28xx()
4247 rt2x00_set_field32(®, TX_PWR_CFG_RATE7, txpower); in rt2800_config_txpower_rt28xx()
4249 rt2800_register_write(rt2x00dev, offset, reg); in rt2800_config_txpower_rt28xx()
4356 u32 reg; in rt2800_config_retry_limit() local
4358 rt2800_register_read(rt2x00dev, TX_RTY_CFG, ®); in rt2800_config_retry_limit()
4359 rt2x00_set_field32(®, TX_RTY_CFG_SHORT_RTY_LIMIT, in rt2800_config_retry_limit()
4361 rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_LIMIT, in rt2800_config_retry_limit()
4363 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg); in rt2800_config_retry_limit()
4372 u32 reg; in rt2800_config_ps() local
4377 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, ®); in rt2800_config_ps()
4378 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5); in rt2800_config_ps()
4379 rt2x00_set_field32(®, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, in rt2800_config_ps()
4381 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTOWAKE, 1); in rt2800_config_ps()
4382 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg); in rt2800_config_ps()
4386 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, ®); in rt2800_config_ps()
4387 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0); in rt2800_config_ps()
4388 rt2x00_set_field32(®, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0); in rt2800_config_ps()
4389 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTOWAKE, 0); in rt2800_config_ps()
4390 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg); in rt2800_config_ps()
4424 u32 reg; in rt2800_link_stats() local
4429 rt2800_register_read(rt2x00dev, RX_STA_CNT0, ®); in rt2800_link_stats()
4430 qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR); in rt2800_link_stats()
4540 u32 reg; in rt2800_init_registers() local
4556 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, ®); in rt2800_init_registers()
4557 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_INTERVAL, 1600); in rt2800_init_registers()
4558 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_TICKING, 0); in rt2800_init_registers()
4559 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_SYNC, 0); in rt2800_init_registers()
4560 rt2x00_set_field32(®, BCN_TIME_CFG_TBTT_ENABLE, 0); in rt2800_init_registers()
4561 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0); in rt2800_init_registers()
4562 rt2x00_set_field32(®, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0); in rt2800_init_registers()
4563 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); in rt2800_init_registers()
4567 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, ®); in rt2800_init_registers()
4568 rt2x00_set_field32(®, BKOFF_SLOT_CFG_SLOT_TIME, 9); in rt2800_init_registers()
4569 rt2x00_set_field32(®, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2); in rt2800_init_registers()
4570 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg); in rt2800_init_registers()
4573 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, ®); in rt2800_init_registers()
4574 if (rt2x00_get_field32(reg, WLAN_EN) == 1) { in rt2800_init_registers()
4575 rt2x00_set_field32(®, PCIE_APP0_CLK_REQ, 1); in rt2800_init_registers()
4576 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg); in rt2800_init_registers()
4579 rt2800_register_read(rt2x00dev, CMB_CTRL, ®); in rt2800_init_registers()
4580 if (!(rt2x00_get_field32(reg, LDO0_EN) == 1)) { in rt2800_init_registers()
4581 rt2x00_set_field32(®, LDO0_EN, 1); in rt2800_init_registers()
4582 rt2x00_set_field32(®, LDO_BGSEL, 3); in rt2800_init_registers()
4583 rt2800_register_write(rt2x00dev, CMB_CTRL, reg); in rt2800_init_registers()
4586 rt2800_register_read(rt2x00dev, OSC_CTRL, ®); in rt2800_init_registers()
4587 rt2x00_set_field32(®, OSC_ROSC_EN, 1); in rt2800_init_registers()
4588 rt2x00_set_field32(®, OSC_CAL_REQ, 1); in rt2800_init_registers()
4589 rt2x00_set_field32(®, OSC_REF_CYCLE, 0x27); in rt2800_init_registers()
4590 rt2800_register_write(rt2x00dev, OSC_CTRL, reg); in rt2800_init_registers()
4592 rt2800_register_read(rt2x00dev, COEX_CFG0, ®); in rt2800_init_registers()
4593 rt2x00_set_field32(®, COEX_CFG_ANT, 0x5e); in rt2800_init_registers()
4594 rt2800_register_write(rt2x00dev, COEX_CFG0, reg); in rt2800_init_registers()
4596 rt2800_register_read(rt2x00dev, COEX_CFG2, ®); in rt2800_init_registers()
4597 rt2x00_set_field32(®, BT_COEX_CFG1, 0x00); in rt2800_init_registers()
4598 rt2x00_set_field32(®, BT_COEX_CFG0, 0x17); in rt2800_init_registers()
4599 rt2x00_set_field32(®, WL_COEX_CFG1, 0x93); in rt2800_init_registers()
4600 rt2x00_set_field32(®, WL_COEX_CFG0, 0x7f); in rt2800_init_registers()
4601 rt2800_register_write(rt2x00dev, COEX_CFG2, reg); in rt2800_init_registers()
4603 rt2800_register_read(rt2x00dev, PLL_CTRL, ®); in rt2800_init_registers()
4604 rt2x00_set_field32(®, PLL_CONTROL, 1); in rt2800_init_registers()
4605 rt2800_register_write(rt2x00dev, PLL_CTRL, reg); in rt2800_init_registers()
4684 rt2800_register_read(rt2x00dev, TX_LINK_CFG, ®); in rt2800_init_registers()
4685 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32); in rt2800_init_registers()
4686 rt2x00_set_field32(®, TX_LINK_CFG_MFB_ENABLE, 0); in rt2800_init_registers()
4687 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0); in rt2800_init_registers()
4688 rt2x00_set_field32(®, TX_LINK_CFG_TX_MRQ_EN, 0); in rt2800_init_registers()
4689 rt2x00_set_field32(®, TX_LINK_CFG_TX_RDG_EN, 0); in rt2800_init_registers()
4690 rt2x00_set_field32(®, TX_LINK_CFG_TX_CF_ACK_EN, 1); in rt2800_init_registers()
4691 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFB, 0); in rt2800_init_registers()
4692 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFS, 0); in rt2800_init_registers()
4693 rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg); in rt2800_init_registers()
4695 rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, ®); in rt2800_init_registers()
4696 rt2x00_set_field32(®, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9); in rt2800_init_registers()
4697 rt2x00_set_field32(®, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32); in rt2800_init_registers()
4698 rt2x00_set_field32(®, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10); in rt2800_init_registers()
4699 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg); in rt2800_init_registers()
4701 rt2800_register_read(rt2x00dev, MAX_LEN_CFG, ®); in rt2800_init_registers()
4702 rt2x00_set_field32(®, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE); in rt2800_init_registers()
4706 rt2x00_set_field32(®, MAX_LEN_CFG_MAX_PSDU, 2); in rt2800_init_registers()
4708 rt2x00_set_field32(®, MAX_LEN_CFG_MAX_PSDU, 1); in rt2800_init_registers()
4709 rt2x00_set_field32(®, MAX_LEN_CFG_MIN_PSDU, 0); in rt2800_init_registers()
4710 rt2x00_set_field32(®, MAX_LEN_CFG_MIN_MPDU, 0); in rt2800_init_registers()
4711 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg); in rt2800_init_registers()
4713 rt2800_register_read(rt2x00dev, LED_CFG, ®); in rt2800_init_registers()
4714 rt2x00_set_field32(®, LED_CFG_ON_PERIOD, 70); in rt2800_init_registers()
4715 rt2x00_set_field32(®, LED_CFG_OFF_PERIOD, 30); in rt2800_init_registers()
4716 rt2x00_set_field32(®, LED_CFG_SLOW_BLINK_PERIOD, 3); in rt2800_init_registers()
4717 rt2x00_set_field32(®, LED_CFG_R_LED_MODE, 3); in rt2800_init_registers()
4718 rt2x00_set_field32(®, LED_CFG_G_LED_MODE, 3); in rt2800_init_registers()
4719 rt2x00_set_field32(®, LED_CFG_Y_LED_MODE, 3); in rt2800_init_registers()
4720 rt2x00_set_field32(®, LED_CFG_LED_POLAR, 1); in rt2800_init_registers()
4721 rt2800_register_write(rt2x00dev, LED_CFG, reg); in rt2800_init_registers()
4725 rt2800_register_read(rt2x00dev, TX_RTY_CFG, ®); in rt2800_init_registers()
4726 rt2x00_set_field32(®, TX_RTY_CFG_SHORT_RTY_LIMIT, 15); in rt2800_init_registers()
4727 rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_LIMIT, 31); in rt2800_init_registers()
4728 rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_THRE, 2000); in rt2800_init_registers()
4729 rt2x00_set_field32(®, TX_RTY_CFG_NON_AGG_RTY_MODE, 0); in rt2800_init_registers()
4730 rt2x00_set_field32(®, TX_RTY_CFG_AGG_RTY_MODE, 0); in rt2800_init_registers()
4731 rt2x00_set_field32(®, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1); in rt2800_init_registers()
4732 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg); in rt2800_init_registers()
4734 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, ®); in rt2800_init_registers()
4735 rt2x00_set_field32(®, AUTO_RSP_CFG_AUTORESPONDER, 1); in rt2800_init_registers()
4736 rt2x00_set_field32(®, AUTO_RSP_CFG_BAC_ACK_POLICY, 1); in rt2800_init_registers()
4737 rt2x00_set_field32(®, AUTO_RSP_CFG_CTS_40_MMODE, 0); in rt2800_init_registers()
4738 rt2x00_set_field32(®, AUTO_RSP_CFG_CTS_40_MREF, 0); in rt2800_init_registers()
4739 rt2x00_set_field32(®, AUTO_RSP_CFG_AR_PREAMBLE, 1); in rt2800_init_registers()
4740 rt2x00_set_field32(®, AUTO_RSP_CFG_DUAL_CTS_EN, 0); in rt2800_init_registers()
4741 rt2x00_set_field32(®, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0); in rt2800_init_registers()
4742 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg); in rt2800_init_registers()
4744 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, ®); in rt2800_init_registers()
4745 rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_RATE, 3); in rt2800_init_registers()
4746 rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_CTRL, 0); in rt2800_init_registers()
4747 rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1); in rt2800_init_registers()
4748 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1); in rt2800_init_registers()
4749 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1); in rt2800_init_registers()
4750 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1); in rt2800_init_registers()
4751 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0); in rt2800_init_registers()
4752 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1); in rt2800_init_registers()
4753 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0); in rt2800_init_registers()
4754 rt2x00_set_field32(®, CCK_PROT_CFG_RTS_TH_EN, 1); in rt2800_init_registers()
4755 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg); in rt2800_init_registers()
4757 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, ®); in rt2800_init_registers()
4758 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_RATE, 3); in rt2800_init_registers()
4759 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_CTRL, 0); in rt2800_init_registers()
4760 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1); in rt2800_init_registers()
4761 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1); in rt2800_init_registers()
4762 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1); in rt2800_init_registers()
4763 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1); in rt2800_init_registers()
4764 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0); in rt2800_init_registers()
4765 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1); in rt2800_init_registers()
4766 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0); in rt2800_init_registers()
4767 rt2x00_set_field32(®, OFDM_PROT_CFG_RTS_TH_EN, 1); in rt2800_init_registers()
4768 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg); in rt2800_init_registers()
4770 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, ®); in rt2800_init_registers()
4771 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_RATE, 0x4004); in rt2800_init_registers()
4772 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_CTRL, 0); in rt2800_init_registers()
4773 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1); in rt2800_init_registers()
4774 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1); in rt2800_init_registers()
4775 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1); in rt2800_init_registers()
4776 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1); in rt2800_init_registers()
4777 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0); in rt2800_init_registers()
4778 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1); in rt2800_init_registers()
4779 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0); in rt2800_init_registers()
4780 rt2x00_set_field32(®, MM20_PROT_CFG_RTS_TH_EN, 0); in rt2800_init_registers()
4781 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg); in rt2800_init_registers()
4783 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, ®); in rt2800_init_registers()
4784 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_RATE, 0x4084); in rt2800_init_registers()
4785 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_CTRL, 0); in rt2800_init_registers()
4786 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1); in rt2800_init_registers()
4787 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1); in rt2800_init_registers()
4788 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1); in rt2800_init_registers()
4789 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1); in rt2800_init_registers()
4790 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1); in rt2800_init_registers()
4791 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1); in rt2800_init_registers()
4792 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1); in rt2800_init_registers()
4793 rt2x00_set_field32(®, MM40_PROT_CFG_RTS_TH_EN, 0); in rt2800_init_registers()
4794 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg); in rt2800_init_registers()
4796 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, ®); in rt2800_init_registers()
4797 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_RATE, 0x4004); in rt2800_init_registers()
4798 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_CTRL, 0); in rt2800_init_registers()
4799 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1); in rt2800_init_registers()
4800 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1); in rt2800_init_registers()
4801 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1); in rt2800_init_registers()
4802 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1); in rt2800_init_registers()
4803 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0); in rt2800_init_registers()
4804 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1); in rt2800_init_registers()
4805 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0); in rt2800_init_registers()
4806 rt2x00_set_field32(®, GF20_PROT_CFG_RTS_TH_EN, 0); in rt2800_init_registers()
4807 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg); in rt2800_init_registers()
4809 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, ®); in rt2800_init_registers()
4810 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_RATE, 0x4084); in rt2800_init_registers()
4811 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_CTRL, 0); in rt2800_init_registers()
4812 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1); in rt2800_init_registers()
4813 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1); in rt2800_init_registers()
4814 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1); in rt2800_init_registers()
4815 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1); in rt2800_init_registers()
4816 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1); in rt2800_init_registers()
4817 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1); in rt2800_init_registers()
4818 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1); in rt2800_init_registers()
4819 rt2x00_set_field32(®, GF40_PROT_CFG_RTS_TH_EN, 0); in rt2800_init_registers()
4820 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg); in rt2800_init_registers()
4825 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, ®); in rt2800_init_registers()
4826 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0); in rt2800_init_registers()
4827 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_DMA_BUSY, 0); in rt2800_init_registers()
4828 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0); in rt2800_init_registers()
4829 rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_DMA_BUSY, 0); in rt2800_init_registers()
4830 rt2x00_set_field32(®, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3); in rt2800_init_registers()
4831 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0); in rt2800_init_registers()
4832 rt2x00_set_field32(®, WPDMA_GLO_CFG_BIG_ENDIAN, 0); in rt2800_init_registers()
4833 rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0); in rt2800_init_registers()
4834 rt2x00_set_field32(®, WPDMA_GLO_CFG_HDR_SEG_LEN, 0); in rt2800_init_registers()
4835 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); in rt2800_init_registers()
4842 rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG, ®); in rt2800_init_registers()
4843 rt2x00_set_field32(®, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1); in rt2800_init_registers()
4844 rt2x00_set_field32(®, TXOP_CTRL_CFG_AC_TRUN_EN, 1); in rt2800_init_registers()
4845 rt2x00_set_field32(®, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1); in rt2800_init_registers()
4846 rt2x00_set_field32(®, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1); in rt2800_init_registers()
4847 rt2x00_set_field32(®, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1); in rt2800_init_registers()
4848 rt2x00_set_field32(®, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1); in rt2800_init_registers()
4849 rt2x00_set_field32(®, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0); in rt2800_init_registers()
4850 rt2x00_set_field32(®, TXOP_CTRL_CFG_EXT_CCA_EN, 0); in rt2800_init_registers()
4851 rt2x00_set_field32(®, TXOP_CTRL_CFG_EXT_CCA_DLY, 88); in rt2800_init_registers()
4852 rt2x00_set_field32(®, TXOP_CTRL_CFG_EXT_CWMIN, 0); in rt2800_init_registers()
4853 rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg); in rt2800_init_registers()
4855 reg = rt2x00_rt(rt2x00dev, RT5592) ? 0x00000082 : 0x00000002; in rt2800_init_registers()
4856 rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, reg); in rt2800_init_registers()
4858 rt2800_register_read(rt2x00dev, TX_RTS_CFG, ®); in rt2800_init_registers()
4859 rt2x00_set_field32(®, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32); in rt2800_init_registers()
4860 rt2x00_set_field32(®, TX_RTS_CFG_RTS_THRES, in rt2800_init_registers()
4862 rt2x00_set_field32(®, TX_RTS_CFG_RTS_FBK_EN, 0); in rt2800_init_registers()
4863 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg); in rt2800_init_registers()
4874 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, ®); in rt2800_init_registers()
4875 rt2x00_set_field32(®, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16); in rt2800_init_registers()
4876 rt2x00_set_field32(®, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16); in rt2800_init_registers()
4877 rt2x00_set_field32(®, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4); in rt2800_init_registers()
4878 rt2x00_set_field32(®, XIFS_TIME_CFG_EIFS, 314); in rt2800_init_registers()
4879 rt2x00_set_field32(®, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1); in rt2800_init_registers()
4880 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg); in rt2800_init_registers()
4904 rt2800_register_read(rt2x00dev, US_CYC_CNT, ®); in rt2800_init_registers()
4905 rt2x00_set_field32(®, US_CYC_CNT_CLOCK_CYCLE, 30); in rt2800_init_registers()
4906 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg); in rt2800_init_registers()
4908 rt2800_register_read(rt2x00dev, US_CYC_CNT, ®); in rt2800_init_registers()
4909 rt2x00_set_field32(®, US_CYC_CNT_CLOCK_CYCLE, 125); in rt2800_init_registers()
4910 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg); in rt2800_init_registers()
4913 rt2800_register_read(rt2x00dev, HT_FBK_CFG0, ®); in rt2800_init_registers()
4914 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS0FBK, 0); in rt2800_init_registers()
4915 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS1FBK, 0); in rt2800_init_registers()
4916 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS2FBK, 1); in rt2800_init_registers()
4917 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS3FBK, 2); in rt2800_init_registers()
4918 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS4FBK, 3); in rt2800_init_registers()
4919 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS5FBK, 4); in rt2800_init_registers()
4920 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS6FBK, 5); in rt2800_init_registers()
4921 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS7FBK, 6); in rt2800_init_registers()
4922 rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg); in rt2800_init_registers()
4924 rt2800_register_read(rt2x00dev, HT_FBK_CFG1, ®); in rt2800_init_registers()
4925 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS8FBK, 8); in rt2800_init_registers()
4926 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS9FBK, 8); in rt2800_init_registers()
4927 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS10FBK, 9); in rt2800_init_registers()
4928 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS11FBK, 10); in rt2800_init_registers()
4929 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS12FBK, 11); in rt2800_init_registers()
4930 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS13FBK, 12); in rt2800_init_registers()
4931 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS14FBK, 13); in rt2800_init_registers()
4932 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS15FBK, 14); in rt2800_init_registers()
4933 rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg); in rt2800_init_registers()
4935 rt2800_register_read(rt2x00dev, LG_FBK_CFG0, ®); in rt2800_init_registers()
4936 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS0FBK, 8); in rt2800_init_registers()
4937 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS1FBK, 8); in rt2800_init_registers()
4938 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS2FBK, 9); in rt2800_init_registers()
4939 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS3FBK, 10); in rt2800_init_registers()
4940 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS4FBK, 11); in rt2800_init_registers()
4941 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS5FBK, 12); in rt2800_init_registers()
4942 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS6FBK, 13); in rt2800_init_registers()
4943 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS7FBK, 14); in rt2800_init_registers()
4944 rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg); in rt2800_init_registers()
4946 rt2800_register_read(rt2x00dev, LG_FBK_CFG1, ®); in rt2800_init_registers()
4947 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS0FBK, 0); in rt2800_init_registers()
4948 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS1FBK, 0); in rt2800_init_registers()
4949 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS2FBK, 1); in rt2800_init_registers()
4950 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS3FBK, 2); in rt2800_init_registers()
4951 rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg); in rt2800_init_registers()
4956 rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE, ®); in rt2800_init_registers()
4957 rt2x00_set_field32(®, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0); in rt2800_init_registers()
4958 rt2x00_set_field32(®, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0); in rt2800_init_registers()
4959 rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg); in rt2800_init_registers()
4966 rt2800_register_read(rt2x00dev, RX_STA_CNT0, ®); in rt2800_init_registers()
4967 rt2800_register_read(rt2x00dev, RX_STA_CNT1, ®); in rt2800_init_registers()
4968 rt2800_register_read(rt2x00dev, RX_STA_CNT2, ®); in rt2800_init_registers()
4969 rt2800_register_read(rt2x00dev, TX_STA_CNT0, ®); in rt2800_init_registers()
4970 rt2800_register_read(rt2x00dev, TX_STA_CNT1, ®); in rt2800_init_registers()
4971 rt2800_register_read(rt2x00dev, TX_STA_CNT2, ®); in rt2800_init_registers()
4976 rt2800_register_read(rt2x00dev, INT_TIMER_CFG, ®); in rt2800_init_registers()
4977 rt2x00_set_field32(®, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4); in rt2800_init_registers()
4978 rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg); in rt2800_init_registers()
4983 rt2800_register_read(rt2x00dev, CH_TIME_CFG, ®); in rt2800_init_registers()
4984 rt2x00_set_field32(®, CH_TIME_CFG_EIFS_BUSY, 1); in rt2800_init_registers()
4985 rt2x00_set_field32(®, CH_TIME_CFG_NAV_BUSY, 1); in rt2800_init_registers()
4986 rt2x00_set_field32(®, CH_TIME_CFG_RX_BUSY, 1); in rt2800_init_registers()
4987 rt2x00_set_field32(®, CH_TIME_CFG_TX_BUSY, 1); in rt2800_init_registers()
4988 rt2x00_set_field32(®, CH_TIME_CFG_TMR_EN, 1); in rt2800_init_registers()
4989 rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg); in rt2800_init_registers()
4997 u32 reg; in rt2800_wait_bbp_rf_ready() local
5000 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, ®); in rt2800_wait_bbp_rf_ready()
5001 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY)) in rt2800_wait_bbp_rf_ready()
5533 u32 reg; in rt2800_init_bbp_53xx() local
5535 rt2800_register_read(rt2x00dev, GPIO_CTRL, ®); in rt2800_init_bbp_53xx()
5536 rt2x00_set_field32(®, GPIO_CTRL_DIR3, 0); in rt2800_init_bbp_53xx()
5537 rt2x00_set_field32(®, GPIO_CTRL_DIR6, 0); in rt2800_init_bbp_53xx()
5538 rt2x00_set_field32(®, GPIO_CTRL_VAL3, 0); in rt2800_init_bbp_53xx()
5539 rt2x00_set_field32(®, GPIO_CTRL_VAL6, 0); in rt2800_init_bbp_53xx()
5541 rt2x00_set_field32(®, GPIO_CTRL_VAL3, 1); in rt2800_init_bbp_53xx()
5543 rt2x00_set_field32(®, GPIO_CTRL_VAL6, 1); in rt2800_init_bbp_53xx()
5544 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg); in rt2800_init_bbp_53xx()
5697 u32 reg; in rt2800_led_open_drain_enable() local
5699 rt2800_register_read(rt2x00dev, OPT_14_CSR, ®); in rt2800_led_open_drain_enable()
5700 rt2x00_set_field32(®, OPT_14_CSR_BIT0, 1); in rt2800_led_open_drain_enable()
5701 rt2800_register_write(rt2x00dev, OPT_14_CSR, reg); in rt2800_led_open_drain_enable()
5937 u8 reg; in rt2800_normal_mode_setup_5xxx() local
5941 rt2800_bbp_read(rt2x00dev, 138, ®); in rt2800_normal_mode_setup_5xxx()
5944 rt2x00_set_field8(®, BBP138_RX_ADC1, 0); in rt2800_normal_mode_setup_5xxx()
5946 rt2x00_set_field8(®, BBP138_TX_DAC1, 1); in rt2800_normal_mode_setup_5xxx()
5947 rt2800_bbp_write(rt2x00dev, 138, reg); in rt2800_normal_mode_setup_5xxx()
5949 rt2800_rfcsr_read(rt2x00dev, 38, ®); in rt2800_normal_mode_setup_5xxx()
5950 rt2x00_set_field8(®, RFCSR38_RX_LO1_EN, 0); in rt2800_normal_mode_setup_5xxx()
5951 rt2800_rfcsr_write(rt2x00dev, 38, reg); in rt2800_normal_mode_setup_5xxx()
5953 rt2800_rfcsr_read(rt2x00dev, 39, ®); in rt2800_normal_mode_setup_5xxx()
5954 rt2x00_set_field8(®, RFCSR39_RX_LO2_EN, 0); in rt2800_normal_mode_setup_5xxx()
5955 rt2800_rfcsr_write(rt2x00dev, 39, reg); in rt2800_normal_mode_setup_5xxx()
5959 rt2800_rfcsr_read(rt2x00dev, 30, ®); in rt2800_normal_mode_setup_5xxx()
5960 rt2x00_set_field8(®, RFCSR30_RX_VCM, 2); in rt2800_normal_mode_setup_5xxx()
5961 rt2800_rfcsr_write(rt2x00dev, 30, reg); in rt2800_normal_mode_setup_5xxx()
6006 u32 reg; in rt2800_init_rfcsr_30xx() local
6032 rt2800_register_read(rt2x00dev, LDO_CFG0, ®); in rt2800_init_rfcsr_30xx()
6033 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); in rt2800_init_rfcsr_30xx()
6034 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3); in rt2800_init_rfcsr_30xx()
6035 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); in rt2800_init_rfcsr_30xx()
6044 rt2800_register_read(rt2x00dev, LDO_CFG0, ®); in rt2800_init_rfcsr_30xx()
6045 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); in rt2800_init_rfcsr_30xx()
6051 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3); in rt2800_init_rfcsr_30xx()
6053 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 0); in rt2800_init_rfcsr_30xx()
6055 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); in rt2800_init_rfcsr_30xx()
6057 rt2800_register_read(rt2x00dev, GPIO_SWITCH, ®); in rt2800_init_rfcsr_30xx()
6058 rt2x00_set_field32(®, GPIO_SWITCH_5, 0); in rt2800_init_rfcsr_30xx()
6059 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg); in rt2800_init_rfcsr_30xx()
6209 u32 reg; in rt2800_init_rfcsr_3390() local
6246 rt2800_register_read(rt2x00dev, GPIO_SWITCH, ®); in rt2800_init_rfcsr_3390()
6247 rt2x00_set_field32(®, GPIO_SWITCH_5, 0); in rt2800_init_rfcsr_3390()
6248 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg); in rt2800_init_rfcsr_3390()
6262 u32 reg; in rt2800_init_rfcsr_3572() local
6302 rt2800_register_read(rt2x00dev, LDO_CFG0, ®); in rt2800_init_rfcsr_3572()
6303 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3); in rt2800_init_rfcsr_3572()
6304 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); in rt2800_init_rfcsr_3572()
6305 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); in rt2800_init_rfcsr_3572()
6307 rt2800_register_read(rt2x00dev, LDO_CFG0, ®); in rt2800_init_rfcsr_3572()
6308 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 0); in rt2800_init_rfcsr_3572()
6309 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); in rt2800_init_rfcsr_3572()
6310 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); in rt2800_init_rfcsr_3572()
6367 u32 reg; in rt2800_init_rfcsr_3593() local
6371 rt2800_register_read(rt2x00dev, GPIO_SWITCH, ®); in rt2800_init_rfcsr_3593()
6372 rt2x00_set_field32(®, GPIO_SWITCH_4, 0); in rt2800_init_rfcsr_3593()
6373 rt2x00_set_field32(®, GPIO_SWITCH_7, 0); in rt2800_init_rfcsr_3593()
6374 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg); in rt2800_init_rfcsr_3593()
6422 rt2800_register_read(rt2x00dev, LDO_CFG0, ®); in rt2800_init_rfcsr_3593()
6423 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3); in rt2800_init_rfcsr_3593()
6424 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); in rt2800_init_rfcsr_3593()
6425 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); in rt2800_init_rfcsr_3593()
6427 rt2800_register_read(rt2x00dev, LDO_CFG0, ®); in rt2800_init_rfcsr_3593()
6428 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 0); in rt2800_init_rfcsr_3593()
6429 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); in rt2800_init_rfcsr_3593()
6698 u32 reg; in rt2800_enable_radio() local
6748 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, ®); in rt2800_enable_radio()
6749 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_TX, 1); in rt2800_enable_radio()
6750 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 0); in rt2800_enable_radio()
6751 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg); in rt2800_enable_radio()
6755 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, ®); in rt2800_enable_radio()
6756 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1); in rt2800_enable_radio()
6757 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1); in rt2800_enable_radio()
6758 rt2x00_set_field32(®, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2); in rt2800_enable_radio()
6759 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1); in rt2800_enable_radio()
6760 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); in rt2800_enable_radio()
6762 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, ®); in rt2800_enable_radio()
6763 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_TX, 1); in rt2800_enable_radio()
6764 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 1); in rt2800_enable_radio()
6765 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg); in rt2800_enable_radio()
6788 u32 reg; in rt2800_disable_radio() local
6795 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, ®); in rt2800_disable_radio()
6796 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_TX, 0); in rt2800_disable_radio()
6797 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 0); in rt2800_disable_radio()
6798 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg); in rt2800_disable_radio()
6804 u32 reg; in rt2800_efuse_detect() local
6812 rt2800_register_read(rt2x00dev, efuse_ctrl_reg, ®); in rt2800_efuse_detect()
6813 return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT); in rt2800_efuse_detect()
6819 u32 reg; in rt2800_efuse_read() local
6841 rt2800_register_read_lock(rt2x00dev, efuse_ctrl_reg, ®); in rt2800_efuse_read()
6842 rt2x00_set_field32(®, EFUSE_CTRL_ADDRESS_IN, i); in rt2800_efuse_read()
6843 rt2x00_set_field32(®, EFUSE_CTRL_MODE, 0); in rt2800_efuse_read()
6844 rt2x00_set_field32(®, EFUSE_CTRL_KICK, 1); in rt2800_efuse_read()
6845 rt2800_register_write_lock(rt2x00dev, efuse_ctrl_reg, reg); in rt2800_efuse_read()
6848 rt2800_regbusy_read(rt2x00dev, efuse_ctrl_reg, EFUSE_CTRL_KICK, ®); in rt2800_efuse_read()
6850 rt2800_register_read_lock(rt2x00dev, efuse_data3_reg, ®); in rt2800_efuse_read()
6852 *(u32 *)&rt2x00dev->eeprom[i] = cpu_to_le32(reg); in rt2800_efuse_read()
6853 rt2800_register_read_lock(rt2x00dev, efuse_data2_reg, ®); in rt2800_efuse_read()
6854 *(u32 *)&rt2x00dev->eeprom[i + 2] = cpu_to_le32(reg); in rt2800_efuse_read()
6855 rt2800_register_read_lock(rt2x00dev, efuse_data1_reg, ®); in rt2800_efuse_read()
6856 *(u32 *)&rt2x00dev->eeprom[i + 4] = cpu_to_le32(reg); in rt2800_efuse_read()
6857 rt2800_register_read_lock(rt2x00dev, efuse_data0_reg, ®); in rt2800_efuse_read()
6858 *(u32 *)&rt2x00dev->eeprom[i + 6] = cpu_to_le32(reg); in rt2800_efuse_read()
7467 u32 reg; in rt2800_probe_hw_mode() local
7555 rt2800_register_read(rt2x00dev, MAC_DEBUG_INDEX, ®); in rt2800_probe_hw_mode()
7556 if (rt2x00_get_field32(reg, MAC_DEBUG_INDEX_XTAL)) { in rt2800_probe_hw_mode()
7683 u32 reg; in rt2800_probe_rt() local
7688 rt2800_register_read(rt2x00dev, MAC_CSR0_3290, ®); in rt2800_probe_rt()
7690 rt2800_register_read(rt2x00dev, MAC_CSR0, ®); in rt2800_probe_rt()
7692 rt = rt2x00_get_field32(reg, MAC_CSR0_CHIPSET); in rt2800_probe_rt()
7693 rev = rt2x00_get_field32(reg, MAC_CSR0_REVISION); in rt2800_probe_rt()
7725 u32 reg; in rt2800_probe_hw() local
7746 rt2800_register_read(rt2x00dev, GPIO_CTRL, ®); in rt2800_probe_hw()
7747 rt2x00_set_field32(®, GPIO_CTRL_DIR2, 1); in rt2800_probe_hw()
7748 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg); in rt2800_probe_hw()
7818 u32 reg; in rt2800_set_rts_threshold() local
7821 rt2800_register_read(rt2x00dev, TX_RTS_CFG, ®); in rt2800_set_rts_threshold()
7822 rt2x00_set_field32(®, TX_RTS_CFG_RTS_THRES, value); in rt2800_set_rts_threshold()
7823 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg); in rt2800_set_rts_threshold()
7825 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, ®); in rt2800_set_rts_threshold()
7826 rt2x00_set_field32(®, CCK_PROT_CFG_RTS_TH_EN, enabled); in rt2800_set_rts_threshold()
7827 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg); in rt2800_set_rts_threshold()
7829 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, ®); in rt2800_set_rts_threshold()
7830 rt2x00_set_field32(®, OFDM_PROT_CFG_RTS_TH_EN, enabled); in rt2800_set_rts_threshold()
7831 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg); in rt2800_set_rts_threshold()
7833 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, ®); in rt2800_set_rts_threshold()
7834 rt2x00_set_field32(®, MM20_PROT_CFG_RTS_TH_EN, enabled); in rt2800_set_rts_threshold()
7835 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg); in rt2800_set_rts_threshold()
7837 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, ®); in rt2800_set_rts_threshold()
7838 rt2x00_set_field32(®, MM40_PROT_CFG_RTS_TH_EN, enabled); in rt2800_set_rts_threshold()
7839 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg); in rt2800_set_rts_threshold()
7841 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, ®); in rt2800_set_rts_threshold()
7842 rt2x00_set_field32(®, GF20_PROT_CFG_RTS_TH_EN, enabled); in rt2800_set_rts_threshold()
7843 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg); in rt2800_set_rts_threshold()
7845 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, ®); in rt2800_set_rts_threshold()
7846 rt2x00_set_field32(®, GF40_PROT_CFG_RTS_TH_EN, enabled); in rt2800_set_rts_threshold()
7847 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg); in rt2800_set_rts_threshold()
7861 u32 reg; in rt2800_conf_tx() local
7888 rt2800_register_read(rt2x00dev, offset, ®); in rt2800_conf_tx()
7889 rt2x00_set_field32(®, field, queue->txop); in rt2800_conf_tx()
7890 rt2800_register_write(rt2x00dev, offset, reg); in rt2800_conf_tx()
7896 rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, ®); in rt2800_conf_tx()
7897 rt2x00_set_field32(®, field, queue->aifs); in rt2800_conf_tx()
7898 rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg); in rt2800_conf_tx()
7900 rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, ®); in rt2800_conf_tx()
7901 rt2x00_set_field32(®, field, queue->cw_min); in rt2800_conf_tx()
7902 rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg); in rt2800_conf_tx()
7904 rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, ®); in rt2800_conf_tx()
7905 rt2x00_set_field32(®, field, queue->cw_max); in rt2800_conf_tx()
7906 rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg); in rt2800_conf_tx()
7911 rt2800_register_read(rt2x00dev, offset, ®); in rt2800_conf_tx()
7912 rt2x00_set_field32(®, EDCA_AC0_CFG_TX_OP, queue->txop); in rt2800_conf_tx()
7913 rt2x00_set_field32(®, EDCA_AC0_CFG_AIFSN, queue->aifs); in rt2800_conf_tx()
7914 rt2x00_set_field32(®, EDCA_AC0_CFG_CWMIN, queue->cw_min); in rt2800_conf_tx()
7915 rt2x00_set_field32(®, EDCA_AC0_CFG_CWMAX, queue->cw_max); in rt2800_conf_tx()
7916 rt2800_register_write(rt2x00dev, offset, reg); in rt2800_conf_tx()
7926 u32 reg; in rt2800_get_tsf() local
7928 rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, ®); in rt2800_get_tsf()
7929 tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32; in rt2800_get_tsf()
7930 rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, ®); in rt2800_get_tsf()
7931 tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD); in rt2800_get_tsf()