121 		offset = s->reg + CORE_P_MIB_OFFSET(port);  in bcm_sf2_sw_get_ethtool_stats()
147 	u32 reg;  in bcm_sf2_imp_vlan_setup()  local
157 		reg = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(i));  in bcm_sf2_imp_vlan_setup()
158 		reg |= (1 << cpu_port);  in bcm_sf2_imp_vlan_setup()
159 		core_writel(priv, reg, CORE_PORT_VLAN_CTL_PORT(i));  in bcm_sf2_imp_vlan_setup()
166 	u32 reg, val;  in bcm_sf2_imp_setup()  local
169 	reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);  in bcm_sf2_imp_setup()
170 	reg &= ~P_TXQ_PSM_VDD(port);  in bcm_sf2_imp_setup()
171 	core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);  in bcm_sf2_imp_setup()
174 	reg = core_readl(priv, CORE_IMP_CTL);  in bcm_sf2_imp_setup()
175 	reg |= (RX_BCST_EN | RX_MCST_EN | RX_UCST_EN);  in bcm_sf2_imp_setup()
176 	reg &= ~(RX_DIS | TX_DIS);  in bcm_sf2_imp_setup()
177 	core_writel(priv, reg, CORE_IMP_CTL);  in bcm_sf2_imp_setup()
183 	reg = core_readl(priv, CORE_SWITCH_CTRL);  in bcm_sf2_imp_setup()
184 	reg |= MII_DUMB_FWDG_EN;  in bcm_sf2_imp_setup()
185 	core_writel(priv, reg, CORE_SWITCH_CTRL);  in bcm_sf2_imp_setup()
204 	reg = core_readl(priv, CORE_BRCM_HDR_CTRL);  in bcm_sf2_imp_setup()
205 	reg |= val;  in bcm_sf2_imp_setup()
206 	core_writel(priv, reg, CORE_BRCM_HDR_CTRL);  in bcm_sf2_imp_setup()
211 	reg = core_readl(priv, CORE_BRCM_HDR_RX_DIS);  in bcm_sf2_imp_setup()
212 	reg &= ~(1 << port);  in bcm_sf2_imp_setup()
213 	core_writel(priv, reg, CORE_BRCM_HDR_RX_DIS);  in bcm_sf2_imp_setup()
218 	reg = core_readl(priv, CORE_BRCM_HDR_TX_DIS);  in bcm_sf2_imp_setup()
219 	reg &= ~(1 << port);  in bcm_sf2_imp_setup()
220 	core_writel(priv, reg, CORE_BRCM_HDR_TX_DIS);  in bcm_sf2_imp_setup()
223 	reg = core_readl(priv, CORE_STS_OVERRIDE_IMP);  in bcm_sf2_imp_setup()
224 	reg |= (MII_SW_OR | LINK_STS);  in bcm_sf2_imp_setup()
225 	core_writel(priv, reg, CORE_STS_OVERRIDE_IMP);  in bcm_sf2_imp_setup()
231 	u32 reg;  in bcm_sf2_eee_enable_set()  local
233 	reg = core_readl(priv, CORE_EEE_EN_CTRL);  in bcm_sf2_eee_enable_set()
235 		reg |= 1 << port;  in bcm_sf2_eee_enable_set()
237 		reg &= ~(1 << port);  in bcm_sf2_eee_enable_set()
238 	core_writel(priv, reg, CORE_EEE_EN_CTRL);  in bcm_sf2_eee_enable_set()
244 	u32 reg;  in bcm_sf2_gphy_enable_set()  local
246 	reg = reg_readl(priv, REG_SPHY_CNTRL);  in bcm_sf2_gphy_enable_set()
248 		reg |= PHY_RESET;  in bcm_sf2_gphy_enable_set()
249 		reg &= ~(EXT_PWR_DOWN | IDDQ_BIAS | CK25_DIS);  in bcm_sf2_gphy_enable_set()
250 		reg_writel(priv, reg, REG_SPHY_CNTRL);  in bcm_sf2_gphy_enable_set()
252 		reg = reg_readl(priv, REG_SPHY_CNTRL);  in bcm_sf2_gphy_enable_set()
253 		reg &= ~PHY_RESET;  in bcm_sf2_gphy_enable_set()
255 		reg |= EXT_PWR_DOWN | IDDQ_BIAS | PHY_RESET;  in bcm_sf2_gphy_enable_set()
256 		reg_writel(priv, reg, REG_SPHY_CNTRL);  in bcm_sf2_gphy_enable_set()
258 		reg |= CK25_DIS;  in bcm_sf2_gphy_enable_set()
260 	reg_writel(priv, reg, REG_SPHY_CNTRL);  in bcm_sf2_gphy_enable_set()
264 		reg = reg_readl(priv, REG_LED_CNTRL(0));  in bcm_sf2_gphy_enable_set()
265 		reg |= SPDLNK_SRC_SEL;  in bcm_sf2_gphy_enable_set()
266 		reg_writel(priv, reg, REG_LED_CNTRL(0));  in bcm_sf2_gphy_enable_set()
319 	u32 reg;  in bcm_sf2_port_setup()  local
322 	reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);  in bcm_sf2_port_setup()
323 	reg &= ~P_TXQ_PSM_VDD(port);  in bcm_sf2_port_setup()
324 	core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);  in bcm_sf2_port_setup()
355 	reg = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(port));  in bcm_sf2_port_setup()
356 	reg &= ~PORT_VLAN_CTRL_MASK;  in bcm_sf2_port_setup()
357 	reg |= (1 << port);  in bcm_sf2_port_setup()
358 	reg |= priv->port_sts[port].vlan_ctl_mask;  in bcm_sf2_port_setup()
359 	core_writel(priv, reg, CORE_PORT_VLAN_CTL_PORT(port));  in bcm_sf2_port_setup()
374 	u32 off, reg;  in bcm_sf2_port_disable()  local
390 	reg = core_readl(priv, off);  in bcm_sf2_port_disable()
391 	reg |= RX_DIS | TX_DIS;  in bcm_sf2_port_disable()
392 	core_writel(priv, reg, off);  in bcm_sf2_port_disable()
395 	reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);  in bcm_sf2_port_disable()
396 	reg |= P_TXQ_PSM_VDD(port);  in bcm_sf2_port_disable()
397 	core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);  in bcm_sf2_port_disable()
425 	u32 reg;  in bcm_sf2_sw_get_eee()  local
427 	reg = core_readl(priv, CORE_EEE_LPI_INDICATE);  in bcm_sf2_sw_get_eee()
429 	e->eee_active = !!(reg & (1 << port));  in bcm_sf2_sw_get_eee()
461 	u32 reg;  in bcm_sf2_sw_fast_age_port()  local
465 	reg = core_readl(priv, CORE_FAST_AGE_CTRL);  in bcm_sf2_sw_fast_age_port()
466 	reg |= EN_AGE_PORT | EN_AGE_DYNAMIC | FAST_AGE_STR_DONE;  in bcm_sf2_sw_fast_age_port()
467 	core_writel(priv, reg, CORE_FAST_AGE_CTRL);  in bcm_sf2_sw_fast_age_port()
470 		reg = core_readl(priv, CORE_FAST_AGE_CTRL);  in bcm_sf2_sw_fast_age_port()
471 		if (!(reg & FAST_AGE_STR_DONE))  in bcm_sf2_sw_fast_age_port()
490 	u32 reg, p_ctl;  in bcm_sf2_sw_br_join()  local
501 		reg = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(i));  in bcm_sf2_sw_br_join()
502 		reg |= 1 << port;  in bcm_sf2_sw_br_join()
503 		core_writel(priv, reg, CORE_PORT_VLAN_CTL_PORT(i));  in bcm_sf2_sw_br_join()
504 		priv->port_sts[i].vlan_ctl_mask = reg;  in bcm_sf2_sw_br_join()
523 	u32 reg, p_ctl;  in bcm_sf2_sw_br_leave()  local
532 		reg = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(i));  in bcm_sf2_sw_br_leave()
533 		reg &= ~(1 << port);  in bcm_sf2_sw_br_leave()
534 		core_writel(priv, reg, CORE_PORT_VLAN_CTL_PORT(i));  in bcm_sf2_sw_br_leave()
535 		priv->port_sts[port].vlan_ctl_mask = reg;  in bcm_sf2_sw_br_leave()
554 	u32 reg;  in bcm_sf2_sw_br_set_stp_state()  local
556 	reg = core_readl(priv, CORE_G_PCTL_PORT(port));  in bcm_sf2_sw_br_set_stp_state()
557 	cur_hw_state = reg & (G_MISTP_STATE_MASK << G_MISTP_STATE_SHIFT);  in bcm_sf2_sw_br_set_stp_state()
595 	reg = core_readl(priv, CORE_G_PCTL_PORT(port));  in bcm_sf2_sw_br_set_stp_state()
596 	reg &= ~(G_MISTP_STATE_MASK << G_MISTP_STATE_SHIFT);  in bcm_sf2_sw_br_set_stp_state()
597 	reg |= hw_state;  in bcm_sf2_sw_br_set_stp_state()
598 	core_writel(priv, reg, CORE_G_PCTL_PORT(port));  in bcm_sf2_sw_br_set_stp_state()
607 	u32 reg;  in bcm_sf2_arl_op_wait()  local
610 		reg = core_readl(priv, CORE_ARLA_RWCTL);  in bcm_sf2_arl_op_wait()
611 		if (!(reg & ARL_STRTDN))  in bcm_sf2_arl_op_wait()
751 	u32 reg;  in bcm_sf2_arl_search_wait()  local
754 		reg = core_readl(priv, CORE_ARLA_SRCH_CTL);  in bcm_sf2_arl_search_wait()
755 		if (!(reg & ARLA_SRCH_STDN))  in bcm_sf2_arl_search_wait()
758 		if (reg & ARLA_SRCH_VLID)  in bcm_sf2_arl_search_wait()
863 	u32 reg;  in bcm_sf2_sw_rst()  local
865 	reg = core_readl(priv, CORE_WATCHDOG_CTRL);  in bcm_sf2_sw_rst()
866 	reg |= SOFTWARE_RESET | EN_CHIP_RST | EN_SW_RESET;  in bcm_sf2_sw_rst()
867 	core_writel(priv, reg, CORE_WATCHDOG_CTRL);  in bcm_sf2_sw_rst()
870 		reg = core_readl(priv, CORE_WATCHDOG_CTRL);  in bcm_sf2_sw_rst()
871 		if (!(reg & SOFTWARE_RESET))  in bcm_sf2_sw_rst()
937 	u32 reg, rev;  in bcm_sf2_sw_setup()  local
987 	reg = core_readl(priv, CORE_GMNCFGCFG);  in bcm_sf2_sw_setup()
988 	reg |= RST_MIB_CNT;  in bcm_sf2_sw_setup()
989 	core_writel(priv, reg, CORE_GMNCFGCFG);  in bcm_sf2_sw_setup()
990 	reg &= ~RST_MIB_CNT;  in bcm_sf2_sw_setup()
991 	core_writel(priv, reg, CORE_GMNCFGCFG);  in bcm_sf2_sw_setup()
1079 	u32 reg;  in bcm_sf2_sw_indir_rw()  local
1081 	reg = reg_readl(priv, REG_SWITCH_CNTRL);  in bcm_sf2_sw_indir_rw()
1082 	reg |= MDIO_MASTER_SEL;  in bcm_sf2_sw_indir_rw()
1083 	reg_writel(priv, reg, REG_SWITCH_CNTRL);  in bcm_sf2_sw_indir_rw()
1086 	reg = 0x70;  in bcm_sf2_sw_indir_rw()
1087 	reg <<= 2;  in bcm_sf2_sw_indir_rw()
1088 	core_writel(priv, addr, reg);  in bcm_sf2_sw_indir_rw()
1091 	reg = 0x80 << 8 | regnum << 1;  in bcm_sf2_sw_indir_rw()
1092 	reg <<= 2;  in bcm_sf2_sw_indir_rw()
1095 		ret = core_readl(priv, reg);  in bcm_sf2_sw_indir_rw()
1097 		core_writel(priv, val, reg);  in bcm_sf2_sw_indir_rw()
1099 	reg = reg_readl(priv, REG_SWITCH_CNTRL);  in bcm_sf2_sw_indir_rw()
1100 	reg &= ~MDIO_MASTER_SEL;  in bcm_sf2_sw_indir_rw()
1101 	reg_writel(priv, reg, REG_SWITCH_CNTRL);  in bcm_sf2_sw_indir_rw()
1142 	u32 reg;  in bcm_sf2_sw_adjust_link()  local
1168 		reg = reg_readl(priv, REG_RGMII_CNTRL_P(port));  in bcm_sf2_sw_adjust_link()
1169 		reg &= ~RGMII_MODE_EN;  in bcm_sf2_sw_adjust_link()
1170 		reg_writel(priv, reg, REG_RGMII_CNTRL_P(port));  in bcm_sf2_sw_adjust_link()
1177 	reg = reg_readl(priv, REG_RGMII_CNTRL_P(port));  in bcm_sf2_sw_adjust_link()
1178 	reg &= ~ID_MODE_DIS;  in bcm_sf2_sw_adjust_link()
1179 	reg &= ~(PORT_MODE_MASK << PORT_MODE_SHIFT);  in bcm_sf2_sw_adjust_link()
1180 	reg &= ~(RX_PAUSE_EN | TX_PAUSE_EN);  in bcm_sf2_sw_adjust_link()
1182 	reg |= port_mode | RGMII_MODE_EN;  in bcm_sf2_sw_adjust_link()
1184 		reg |= ID_MODE_DIS;  in bcm_sf2_sw_adjust_link()
1188 			reg |= TX_PAUSE_EN;  in bcm_sf2_sw_adjust_link()
1189 		reg |= RX_PAUSE_EN;  in bcm_sf2_sw_adjust_link()
1192 	reg_writel(priv, reg, REG_RGMII_CNTRL_P(port));  in bcm_sf2_sw_adjust_link()
1198 	reg = SW_OVERRIDE;  in bcm_sf2_sw_adjust_link()
1201 		reg |= SPDSTS_1000 << SPEED_SHIFT;  in bcm_sf2_sw_adjust_link()
1204 		reg |= SPDSTS_100 << SPEED_SHIFT;  in bcm_sf2_sw_adjust_link()
1209 		reg |= LINK_STS;  in bcm_sf2_sw_adjust_link()
1211 		reg |= DUPLX_MODE;  in bcm_sf2_sw_adjust_link()
1213 	core_writel(priv, reg, CORE_STS_OVERRIDE_GMIIP_PORT(port));  in bcm_sf2_sw_adjust_link()
1221 	u32 reg;  in bcm_sf2_sw_fixed_link_update()  local
1251 	reg = core_readl(priv, CORE_STS_OVERRIDE_GMIIP_PORT(port));  in bcm_sf2_sw_fixed_link_update()
1252 	reg |= SW_OVERRIDE;  in bcm_sf2_sw_fixed_link_update()
1254 		reg |= LINK_STS;  in bcm_sf2_sw_fixed_link_update()
1256 		reg &= ~LINK_STS;  in bcm_sf2_sw_fixed_link_update()
1257 	core_writel(priv, reg, CORE_STS_OVERRIDE_GMIIP_PORT(port));  in bcm_sf2_sw_fixed_link_update()