Lines Matching refs:reg
327 u32 reg; in rt2800mmio_enable_interrupt() local
334 rt2x00mmio_register_read(rt2x00dev, INT_MASK_CSR, ®); in rt2800mmio_enable_interrupt()
335 rt2x00_set_field32(®, irq_field, 1); in rt2800mmio_enable_interrupt()
336 rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg); in rt2800mmio_enable_interrupt()
367 u32 reg; in rt2800mmio_tbtt_tasklet() local
379 rt2x00mmio_register_read(rt2x00dev, BCN_TIME_CFG, ®); in rt2800mmio_tbtt_tasklet()
380 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_INTERVAL, in rt2800mmio_tbtt_tasklet()
382 rt2x00mmio_register_write(rt2x00dev, BCN_TIME_CFG, reg); in rt2800mmio_tbtt_tasklet()
384 rt2x00mmio_register_read(rt2x00dev, BCN_TIME_CFG, ®); in rt2800mmio_tbtt_tasklet()
385 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_INTERVAL, in rt2800mmio_tbtt_tasklet()
387 rt2x00mmio_register_write(rt2x00dev, BCN_TIME_CFG, reg); in rt2800mmio_tbtt_tasklet()
460 u32 reg, mask; in rt2800mmio_interrupt() local
463 rt2x00mmio_register_read(rt2x00dev, INT_SOURCE_CSR, ®); in rt2800mmio_interrupt()
464 rt2x00mmio_register_write(rt2x00dev, INT_SOURCE_CSR, reg); in rt2800mmio_interrupt()
466 if (!reg) in rt2800mmio_interrupt()
477 mask = ~reg; in rt2800mmio_interrupt()
479 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TX_FIFO_STATUS)) { in rt2800mmio_interrupt()
487 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_PRE_TBTT)) in rt2800mmio_interrupt()
490 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TBTT)) in rt2800mmio_interrupt()
493 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RX_DONE)) in rt2800mmio_interrupt()
496 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_AUTO_WAKEUP)) in rt2800mmio_interrupt()
504 rt2x00mmio_register_read(rt2x00dev, INT_MASK_CSR, ®); in rt2800mmio_interrupt()
505 reg &= mask; in rt2800mmio_interrupt()
506 rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg); in rt2800mmio_interrupt()
516 u32 reg; in rt2800mmio_toggle_irq() local
524 rt2x00mmio_register_read(rt2x00dev, INT_SOURCE_CSR, ®); in rt2800mmio_toggle_irq()
525 rt2x00mmio_register_write(rt2x00dev, INT_SOURCE_CSR, reg); in rt2800mmio_toggle_irq()
529 reg = 0; in rt2800mmio_toggle_irq()
531 rt2x00_set_field32(®, INT_MASK_CSR_RX_DONE, 1); in rt2800mmio_toggle_irq()
532 rt2x00_set_field32(®, INT_MASK_CSR_TBTT, 1); in rt2800mmio_toggle_irq()
533 rt2x00_set_field32(®, INT_MASK_CSR_PRE_TBTT, 1); in rt2800mmio_toggle_irq()
534 rt2x00_set_field32(®, INT_MASK_CSR_TX_FIFO_STATUS, 1); in rt2800mmio_toggle_irq()
535 rt2x00_set_field32(®, INT_MASK_CSR_AUTO_WAKEUP, 1); in rt2800mmio_toggle_irq()
537 rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg); in rt2800mmio_toggle_irq()
559 u32 reg; in rt2800mmio_start_queue() local
563 rt2x00mmio_register_read(rt2x00dev, MAC_SYS_CTRL, ®); in rt2800mmio_start_queue()
564 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 1); in rt2800mmio_start_queue()
565 rt2x00mmio_register_write(rt2x00dev, MAC_SYS_CTRL, reg); in rt2800mmio_start_queue()
568 rt2x00mmio_register_read(rt2x00dev, BCN_TIME_CFG, ®); in rt2800mmio_start_queue()
569 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_TICKING, 1); in rt2800mmio_start_queue()
570 rt2x00_set_field32(®, BCN_TIME_CFG_TBTT_ENABLE, 1); in rt2800mmio_start_queue()
571 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 1); in rt2800mmio_start_queue()
572 rt2x00mmio_register_write(rt2x00dev, BCN_TIME_CFG, reg); in rt2800mmio_start_queue()
574 rt2x00mmio_register_read(rt2x00dev, INT_TIMER_EN, ®); in rt2800mmio_start_queue()
575 rt2x00_set_field32(®, INT_TIMER_EN_PRE_TBTT_TIMER, 1); in rt2800mmio_start_queue()
576 rt2x00mmio_register_write(rt2x00dev, INT_TIMER_EN, reg); in rt2800mmio_start_queue()
612 u32 reg; in rt2800mmio_stop_queue() local
616 rt2x00mmio_register_read(rt2x00dev, MAC_SYS_CTRL, ®); in rt2800mmio_stop_queue()
617 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 0); in rt2800mmio_stop_queue()
618 rt2x00mmio_register_write(rt2x00dev, MAC_SYS_CTRL, reg); in rt2800mmio_stop_queue()
621 rt2x00mmio_register_read(rt2x00dev, BCN_TIME_CFG, ®); in rt2800mmio_stop_queue()
622 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_TICKING, 0); in rt2800mmio_stop_queue()
623 rt2x00_set_field32(®, BCN_TIME_CFG_TBTT_ENABLE, 0); in rt2800mmio_stop_queue()
624 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0); in rt2800mmio_stop_queue()
625 rt2x00mmio_register_write(rt2x00dev, BCN_TIME_CFG, reg); in rt2800mmio_stop_queue()
627 rt2x00mmio_register_read(rt2x00dev, INT_TIMER_EN, ®); in rt2800mmio_stop_queue()
628 rt2x00_set_field32(®, INT_TIMER_EN_PRE_TBTT_TIMER, 0); in rt2800mmio_stop_queue()
629 rt2x00mmio_register_write(rt2x00dev, INT_TIMER_EN, reg); in rt2800mmio_stop_queue()
808 u32 reg; in rt2800mmio_init_registers() local
813 rt2x00mmio_register_read(rt2x00dev, WPDMA_RST_IDX, ®); in rt2800mmio_init_registers()
814 rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX0, 1); in rt2800mmio_init_registers()
815 rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX1, 1); in rt2800mmio_init_registers()
816 rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX2, 1); in rt2800mmio_init_registers()
817 rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX3, 1); in rt2800mmio_init_registers()
818 rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX4, 1); in rt2800mmio_init_registers()
819 rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX5, 1); in rt2800mmio_init_registers()
820 rt2x00_set_field32(®, WPDMA_RST_IDX_DRX_IDX0, 1); in rt2800mmio_init_registers()
821 rt2x00mmio_register_write(rt2x00dev, WPDMA_RST_IDX, reg); in rt2800mmio_init_registers()
834 rt2x00mmio_register_read(rt2x00dev, AUX_CTRL, ®); in rt2800mmio_init_registers()
835 rt2x00_set_field32(®, AUX_CTRL_FORCE_PCIE_CLK, 1); in rt2800mmio_init_registers()
836 rt2x00_set_field32(®, AUX_CTRL_WAKE_PCIE_EN, 1); in rt2800mmio_init_registers()
837 rt2x00mmio_register_write(rt2x00dev, AUX_CTRL, reg); in rt2800mmio_init_registers()
842 reg = 0; in rt2800mmio_init_registers()
843 rt2x00_set_field32(®, MAC_SYS_CTRL_RESET_CSR, 1); in rt2800mmio_init_registers()
844 rt2x00_set_field32(®, MAC_SYS_CTRL_RESET_BBP, 1); in rt2800mmio_init_registers()
845 rt2x00mmio_register_write(rt2x00dev, MAC_SYS_CTRL, reg); in rt2800mmio_init_registers()