Lines Matching refs:reg
29 u32 reg; in exynos_dp_enable_video_mute() local
32 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1); in exynos_dp_enable_video_mute()
33 reg |= HDCP_VIDEO_MUTE; in exynos_dp_enable_video_mute()
34 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1); in exynos_dp_enable_video_mute()
36 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1); in exynos_dp_enable_video_mute()
37 reg &= ~HDCP_VIDEO_MUTE; in exynos_dp_enable_video_mute()
38 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1); in exynos_dp_enable_video_mute()
44 u32 reg; in exynos_dp_stop_video() local
46 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1); in exynos_dp_stop_video()
47 reg &= ~VIDEO_EN; in exynos_dp_stop_video()
48 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1); in exynos_dp_stop_video()
53 u32 reg; in exynos_dp_lane_swap() local
56 reg = LANE3_MAP_LOGIC_LANE_0 | LANE2_MAP_LOGIC_LANE_1 | in exynos_dp_lane_swap()
59 reg = LANE3_MAP_LOGIC_LANE_3 | LANE2_MAP_LOGIC_LANE_2 | in exynos_dp_lane_swap()
62 writel(reg, dp->reg_base + EXYNOS_DP_LANE_MAP); in exynos_dp_lane_swap()
67 u32 reg; in exynos_dp_init_analog_param() local
69 reg = TX_TERMINAL_CTRL_50_OHM; in exynos_dp_init_analog_param()
70 writel(reg, dp->reg_base + EXYNOS_DP_ANALOG_CTL_1); in exynos_dp_init_analog_param()
72 reg = SEL_24M | TX_DVDD_BIT_1_0625V; in exynos_dp_init_analog_param()
73 writel(reg, dp->reg_base + EXYNOS_DP_ANALOG_CTL_2); in exynos_dp_init_analog_param()
75 reg = DRIVE_DVDD_BIT_1_0625V | VCO_BIT_600_MICRO; in exynos_dp_init_analog_param()
76 writel(reg, dp->reg_base + EXYNOS_DP_ANALOG_CTL_3); in exynos_dp_init_analog_param()
78 reg = PD_RING_OSC | AUX_TERMINAL_CTRL_50_OHM | in exynos_dp_init_analog_param()
80 writel(reg, dp->reg_base + EXYNOS_DP_PLL_FILTER_CTL_1); in exynos_dp_init_analog_param()
82 reg = CH3_AMP_400_MV | CH2_AMP_400_MV | in exynos_dp_init_analog_param()
84 writel(reg, dp->reg_base + EXYNOS_DP_TX_AMP_TUNING_CTL); in exynos_dp_init_analog_param()
109 u32 reg; in exynos_dp_reset() local
114 reg = MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N | in exynos_dp_reset()
117 writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_1); in exynos_dp_reset()
119 reg = SSC_FUNC_EN_N | AUX_FUNC_EN_N | in exynos_dp_reset()
122 writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2); in exynos_dp_reset()
159 u32 reg; in exynos_dp_config_interrupt() local
162 reg = COMMON_INT_MASK_1; in exynos_dp_config_interrupt()
163 writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_1); in exynos_dp_config_interrupt()
165 reg = COMMON_INT_MASK_2; in exynos_dp_config_interrupt()
166 writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_2); in exynos_dp_config_interrupt()
168 reg = COMMON_INT_MASK_3; in exynos_dp_config_interrupt()
169 writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_3); in exynos_dp_config_interrupt()
171 reg = COMMON_INT_MASK_4; in exynos_dp_config_interrupt()
172 writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_4); in exynos_dp_config_interrupt()
174 reg = INT_STA_MASK; in exynos_dp_config_interrupt()
175 writel(reg, dp->reg_base + EXYNOS_DP_INT_STA_MASK); in exynos_dp_config_interrupt()
180 u32 reg; in exynos_dp_get_pll_lock_status() local
182 reg = readl(dp->reg_base + EXYNOS_DP_DEBUG_CTL); in exynos_dp_get_pll_lock_status()
183 if (reg & PLL_LOCK) in exynos_dp_get_pll_lock_status()
191 u32 reg; in exynos_dp_set_pll_power_down() local
194 reg = readl(dp->reg_base + EXYNOS_DP_PLL_CTL); in exynos_dp_set_pll_power_down()
195 reg |= DP_PLL_PD; in exynos_dp_set_pll_power_down()
196 writel(reg, dp->reg_base + EXYNOS_DP_PLL_CTL); in exynos_dp_set_pll_power_down()
198 reg = readl(dp->reg_base + EXYNOS_DP_PLL_CTL); in exynos_dp_set_pll_power_down()
199 reg &= ~DP_PLL_PD; in exynos_dp_set_pll_power_down()
200 writel(reg, dp->reg_base + EXYNOS_DP_PLL_CTL); in exynos_dp_set_pll_power_down()
208 u32 reg; in exynos_dp_set_analog_power_down() local
213 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD); in exynos_dp_set_analog_power_down()
214 reg |= AUX_PD; in exynos_dp_set_analog_power_down()
215 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD); in exynos_dp_set_analog_power_down()
217 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD); in exynos_dp_set_analog_power_down()
218 reg &= ~AUX_PD; in exynos_dp_set_analog_power_down()
219 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD); in exynos_dp_set_analog_power_down()
224 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD); in exynos_dp_set_analog_power_down()
225 reg |= CH0_PD; in exynos_dp_set_analog_power_down()
226 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD); in exynos_dp_set_analog_power_down()
228 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD); in exynos_dp_set_analog_power_down()
229 reg &= ~CH0_PD; in exynos_dp_set_analog_power_down()
230 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD); in exynos_dp_set_analog_power_down()
235 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD); in exynos_dp_set_analog_power_down()
236 reg |= CH1_PD; in exynos_dp_set_analog_power_down()
237 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD); in exynos_dp_set_analog_power_down()
239 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD); in exynos_dp_set_analog_power_down()
240 reg &= ~CH1_PD; in exynos_dp_set_analog_power_down()
241 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD); in exynos_dp_set_analog_power_down()
246 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD); in exynos_dp_set_analog_power_down()
247 reg |= CH2_PD; in exynos_dp_set_analog_power_down()
248 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD); in exynos_dp_set_analog_power_down()
250 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD); in exynos_dp_set_analog_power_down()
251 reg &= ~CH2_PD; in exynos_dp_set_analog_power_down()
252 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD); in exynos_dp_set_analog_power_down()
257 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD); in exynos_dp_set_analog_power_down()
258 reg |= CH3_PD; in exynos_dp_set_analog_power_down()
259 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD); in exynos_dp_set_analog_power_down()
261 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD); in exynos_dp_set_analog_power_down()
262 reg &= ~CH3_PD; in exynos_dp_set_analog_power_down()
263 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD); in exynos_dp_set_analog_power_down()
268 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD); in exynos_dp_set_analog_power_down()
269 reg |= DP_PHY_PD; in exynos_dp_set_analog_power_down()
270 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD); in exynos_dp_set_analog_power_down()
272 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD); in exynos_dp_set_analog_power_down()
273 reg &= ~DP_PHY_PD; in exynos_dp_set_analog_power_down()
274 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD); in exynos_dp_set_analog_power_down()
279 reg = DP_PHY_PD | AUX_PD | CH3_PD | CH2_PD | in exynos_dp_set_analog_power_down()
281 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD); in exynos_dp_set_analog_power_down()
293 u32 reg; in exynos_dp_init_analog_func() local
298 reg = PLL_LOCK_CHG; in exynos_dp_init_analog_func()
299 writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_1); in exynos_dp_init_analog_func()
301 reg = readl(dp->reg_base + EXYNOS_DP_DEBUG_CTL); in exynos_dp_init_analog_func()
302 reg &= ~(F_PLL_LOCK | PLL_LOCK_CTRL); in exynos_dp_init_analog_func()
303 writel(reg, dp->reg_base + EXYNOS_DP_DEBUG_CTL); in exynos_dp_init_analog_func()
320 reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_2); in exynos_dp_init_analog_func()
321 reg &= ~(SERDES_FIFO_FUNC_EN_N | LS_CLK_DOMAIN_FUNC_EN_N in exynos_dp_init_analog_func()
323 writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2); in exynos_dp_init_analog_func()
328 u32 reg; in exynos_dp_clear_hotplug_interrupts() local
333 reg = HOTPLUG_CHG | HPD_LOST | PLUG; in exynos_dp_clear_hotplug_interrupts()
334 writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_4); in exynos_dp_clear_hotplug_interrupts()
336 reg = INT_HPD; in exynos_dp_clear_hotplug_interrupts()
337 writel(reg, dp->reg_base + EXYNOS_DP_INT_STA); in exynos_dp_clear_hotplug_interrupts()
342 u32 reg; in exynos_dp_init_hpd() local
349 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3); in exynos_dp_init_hpd()
350 reg &= ~(F_HPD | HPD_CTRL); in exynos_dp_init_hpd()
351 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_3); in exynos_dp_init_hpd()
356 u32 reg; in exynos_dp_get_irq_type() local
359 reg = gpio_get_value(dp->hpd_gpio); in exynos_dp_get_irq_type()
360 if (reg) in exynos_dp_get_irq_type()
366 reg = readl(dp->reg_base + EXYNOS_DP_COMMON_INT_STA_4); in exynos_dp_get_irq_type()
368 if (reg & PLUG) in exynos_dp_get_irq_type()
371 if (reg & HPD_LOST) in exynos_dp_get_irq_type()
374 if (reg & HOTPLUG_CHG) in exynos_dp_get_irq_type()
383 u32 reg; in exynos_dp_reset_aux() local
386 reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_2); in exynos_dp_reset_aux()
387 reg |= AUX_FUNC_EN_N; in exynos_dp_reset_aux()
388 writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2); in exynos_dp_reset_aux()
393 u32 reg; in exynos_dp_init_aux() local
396 reg = RPLY_RECEIV | AUX_ERR; in exynos_dp_init_aux()
397 writel(reg, dp->reg_base + EXYNOS_DP_INT_STA); in exynos_dp_init_aux()
402 reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | AUX_HW_RETRY_COUNT_SEL(0)| in exynos_dp_init_aux()
404 writel(reg, dp->reg_base + EXYNOS_DP_AUX_HW_RETRY_CTL); in exynos_dp_init_aux()
407 reg = DEFER_CTRL_EN | DEFER_COUNT(1); in exynos_dp_init_aux()
408 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_DEFER_CTL); in exynos_dp_init_aux()
411 reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_2); in exynos_dp_init_aux()
412 reg &= ~AUX_FUNC_EN_N; in exynos_dp_init_aux()
413 writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2); in exynos_dp_init_aux()
418 u32 reg; in exynos_dp_get_plug_in_status() local
424 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3); in exynos_dp_get_plug_in_status()
425 if (reg & HPD_STATUS) in exynos_dp_get_plug_in_status()
434 u32 reg; in exynos_dp_enable_sw_function() local
436 reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_1); in exynos_dp_enable_sw_function()
437 reg &= ~SW_FUNC_EN_N; in exynos_dp_enable_sw_function()
438 writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_1); in exynos_dp_enable_sw_function()
443 int reg; in exynos_dp_start_aux_transaction() local
448 reg = readl(dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2); in exynos_dp_start_aux_transaction()
449 reg |= AUX_EN; in exynos_dp_start_aux_transaction()
450 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2); in exynos_dp_start_aux_transaction()
453 reg = readl(dp->reg_base + EXYNOS_DP_INT_STA); in exynos_dp_start_aux_transaction()
454 while (!(reg & RPLY_RECEIV)) { in exynos_dp_start_aux_transaction()
460 reg = readl(dp->reg_base + EXYNOS_DP_INT_STA); in exynos_dp_start_aux_transaction()
468 reg = readl(dp->reg_base + EXYNOS_DP_INT_STA); in exynos_dp_start_aux_transaction()
469 if (reg & AUX_ERR) { in exynos_dp_start_aux_transaction()
475 reg = readl(dp->reg_base + EXYNOS_DP_AUX_CH_STA); in exynos_dp_start_aux_transaction()
476 if ((reg & AUX_STATUS_MASK) != 0) { in exynos_dp_start_aux_transaction()
478 reg & AUX_STATUS_MASK); in exynos_dp_start_aux_transaction()
489 u32 reg; in exynos_dp_write_byte_to_dpcd() local
495 reg = BUF_CLR; in exynos_dp_write_byte_to_dpcd()
496 writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL); in exynos_dp_write_byte_to_dpcd()
499 reg = AUX_ADDR_7_0(reg_addr); in exynos_dp_write_byte_to_dpcd()
500 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0); in exynos_dp_write_byte_to_dpcd()
501 reg = AUX_ADDR_15_8(reg_addr); in exynos_dp_write_byte_to_dpcd()
502 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8); in exynos_dp_write_byte_to_dpcd()
503 reg = AUX_ADDR_19_16(reg_addr); in exynos_dp_write_byte_to_dpcd()
504 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16); in exynos_dp_write_byte_to_dpcd()
507 reg = (unsigned int)data; in exynos_dp_write_byte_to_dpcd()
508 writel(reg, dp->reg_base + EXYNOS_DP_BUF_DATA_0); in exynos_dp_write_byte_to_dpcd()
515 reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE; in exynos_dp_write_byte_to_dpcd()
516 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1); in exynos_dp_write_byte_to_dpcd()
534 u32 reg; in exynos_dp_read_byte_from_dpcd() local
540 reg = BUF_CLR; in exynos_dp_read_byte_from_dpcd()
541 writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL); in exynos_dp_read_byte_from_dpcd()
544 reg = AUX_ADDR_7_0(reg_addr); in exynos_dp_read_byte_from_dpcd()
545 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0); in exynos_dp_read_byte_from_dpcd()
546 reg = AUX_ADDR_15_8(reg_addr); in exynos_dp_read_byte_from_dpcd()
547 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8); in exynos_dp_read_byte_from_dpcd()
548 reg = AUX_ADDR_19_16(reg_addr); in exynos_dp_read_byte_from_dpcd()
549 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16); in exynos_dp_read_byte_from_dpcd()
556 reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ; in exynos_dp_read_byte_from_dpcd()
557 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1); in exynos_dp_read_byte_from_dpcd()
569 reg = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0); in exynos_dp_read_byte_from_dpcd()
570 *data = (unsigned char)(reg & 0xff); in exynos_dp_read_byte_from_dpcd()
580 u32 reg; in exynos_dp_write_bytes_to_dpcd() local
588 reg = BUF_CLR; in exynos_dp_write_bytes_to_dpcd()
589 writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL); in exynos_dp_write_bytes_to_dpcd()
601 reg = AUX_ADDR_7_0(reg_addr + start_offset); in exynos_dp_write_bytes_to_dpcd()
602 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0); in exynos_dp_write_bytes_to_dpcd()
603 reg = AUX_ADDR_15_8(reg_addr + start_offset); in exynos_dp_write_bytes_to_dpcd()
604 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8); in exynos_dp_write_bytes_to_dpcd()
605 reg = AUX_ADDR_19_16(reg_addr + start_offset); in exynos_dp_write_bytes_to_dpcd()
606 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16); in exynos_dp_write_bytes_to_dpcd()
610 reg = data[start_offset + cur_data_idx]; in exynos_dp_write_bytes_to_dpcd()
611 writel(reg, dp->reg_base + EXYNOS_DP_BUF_DATA_0 in exynos_dp_write_bytes_to_dpcd()
620 reg = AUX_LENGTH(cur_data_count) | in exynos_dp_write_bytes_to_dpcd()
622 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1); in exynos_dp_write_bytes_to_dpcd()
644 u32 reg; in exynos_dp_read_bytes_from_dpcd() local
652 reg = BUF_CLR; in exynos_dp_read_bytes_from_dpcd()
653 writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL); in exynos_dp_read_bytes_from_dpcd()
666 reg = AUX_ADDR_7_0(reg_addr + start_offset); in exynos_dp_read_bytes_from_dpcd()
667 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0); in exynos_dp_read_bytes_from_dpcd()
668 reg = AUX_ADDR_15_8(reg_addr + start_offset); in exynos_dp_read_bytes_from_dpcd()
669 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8); in exynos_dp_read_bytes_from_dpcd()
670 reg = AUX_ADDR_19_16(reg_addr + start_offset); in exynos_dp_read_bytes_from_dpcd()
671 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16); in exynos_dp_read_bytes_from_dpcd()
678 reg = AUX_LENGTH(cur_data_count) | in exynos_dp_read_bytes_from_dpcd()
680 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1); in exynos_dp_read_bytes_from_dpcd()
693 reg = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0 in exynos_dp_read_bytes_from_dpcd()
696 (unsigned char)reg; in exynos_dp_read_bytes_from_dpcd()
709 u32 reg; in exynos_dp_select_i2c_device() local
713 reg = device_addr; in exynos_dp_select_i2c_device()
714 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0); in exynos_dp_select_i2c_device()
726 reg = AUX_TX_COMM_I2C_TRANSACTION | AUX_TX_COMM_MOT | in exynos_dp_select_i2c_device()
728 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1); in exynos_dp_select_i2c_device()
743 u32 reg; in exynos_dp_read_byte_from_i2c() local
749 reg = BUF_CLR; in exynos_dp_read_byte_from_i2c()
750 writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL); in exynos_dp_read_byte_from_i2c()
762 reg = AUX_TX_COMM_I2C_TRANSACTION | in exynos_dp_read_byte_from_i2c()
764 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1); in exynos_dp_read_byte_from_i2c()
788 u32 reg; in exynos_dp_read_bytes_from_i2c() local
797 reg = BUF_CLR; in exynos_dp_read_bytes_from_i2c()
798 writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL); in exynos_dp_read_bytes_from_i2c()
801 reg = readl(dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2); in exynos_dp_read_bytes_from_i2c()
802 reg &= ~ADDR_ONLY; in exynos_dp_read_bytes_from_i2c()
803 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2); in exynos_dp_read_bytes_from_i2c()
821 reg = AUX_LENGTH(16) | in exynos_dp_read_bytes_from_i2c()
824 writel(reg, dp->reg_base + in exynos_dp_read_bytes_from_i2c()
837 reg = readl(dp->reg_base + EXYNOS_DP_AUX_RX_COMM); in exynos_dp_read_bytes_from_i2c()
838 if (reg == AUX_RX_COMM_AUX_DEFER || in exynos_dp_read_bytes_from_i2c()
839 reg == AUX_RX_COMM_I2C_DEFER) { in exynos_dp_read_bytes_from_i2c()
840 dev_err(dp->dev, "Defer: %d\n\n", reg); in exynos_dp_read_bytes_from_i2c()
846 reg = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0 in exynos_dp_read_bytes_from_i2c()
848 edid[i + cur_data_idx] = (unsigned char)reg; in exynos_dp_read_bytes_from_i2c()
857 u32 reg; in exynos_dp_set_link_bandwidth() local
859 reg = bwtype; in exynos_dp_set_link_bandwidth()
861 writel(reg, dp->reg_base + EXYNOS_DP_LINK_BW_SET); in exynos_dp_set_link_bandwidth()
866 u32 reg; in exynos_dp_get_link_bandwidth() local
868 reg = readl(dp->reg_base + EXYNOS_DP_LINK_BW_SET); in exynos_dp_get_link_bandwidth()
869 *bwtype = reg; in exynos_dp_get_link_bandwidth()
874 u32 reg; in exynos_dp_set_lane_count() local
876 reg = count; in exynos_dp_set_lane_count()
877 writel(reg, dp->reg_base + EXYNOS_DP_LANE_COUNT_SET); in exynos_dp_set_lane_count()
882 u32 reg; in exynos_dp_get_lane_count() local
884 reg = readl(dp->reg_base + EXYNOS_DP_LANE_COUNT_SET); in exynos_dp_get_lane_count()
885 *count = reg; in exynos_dp_get_lane_count()
890 u32 reg; in exynos_dp_enable_enhanced_mode() local
893 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4); in exynos_dp_enable_enhanced_mode()
894 reg |= ENHANCED; in exynos_dp_enable_enhanced_mode()
895 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4); in exynos_dp_enable_enhanced_mode()
897 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4); in exynos_dp_enable_enhanced_mode()
898 reg &= ~ENHANCED; in exynos_dp_enable_enhanced_mode()
899 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4); in exynos_dp_enable_enhanced_mode()
906 u32 reg; in exynos_dp_set_training_pattern() local
910 reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_PRBS7; in exynos_dp_set_training_pattern()
911 writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET); in exynos_dp_set_training_pattern()
914 reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_D10_2; in exynos_dp_set_training_pattern()
915 writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET); in exynos_dp_set_training_pattern()
918 reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN1; in exynos_dp_set_training_pattern()
919 writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET); in exynos_dp_set_training_pattern()
922 reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN2; in exynos_dp_set_training_pattern()
923 writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET); in exynos_dp_set_training_pattern()
926 reg = SCRAMBLING_ENABLE | in exynos_dp_set_training_pattern()
929 writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET); in exynos_dp_set_training_pattern()
938 u32 reg; in exynos_dp_set_lane0_pre_emphasis() local
940 reg = readl(dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL); in exynos_dp_set_lane0_pre_emphasis()
941 reg &= ~PRE_EMPHASIS_SET_MASK; in exynos_dp_set_lane0_pre_emphasis()
942 reg |= level << PRE_EMPHASIS_SET_SHIFT; in exynos_dp_set_lane0_pre_emphasis()
943 writel(reg, dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL); in exynos_dp_set_lane0_pre_emphasis()
948 u32 reg; in exynos_dp_set_lane1_pre_emphasis() local
950 reg = readl(dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL); in exynos_dp_set_lane1_pre_emphasis()
951 reg &= ~PRE_EMPHASIS_SET_MASK; in exynos_dp_set_lane1_pre_emphasis()
952 reg |= level << PRE_EMPHASIS_SET_SHIFT; in exynos_dp_set_lane1_pre_emphasis()
953 writel(reg, dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL); in exynos_dp_set_lane1_pre_emphasis()
958 u32 reg; in exynos_dp_set_lane2_pre_emphasis() local
960 reg = readl(dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL); in exynos_dp_set_lane2_pre_emphasis()
961 reg &= ~PRE_EMPHASIS_SET_MASK; in exynos_dp_set_lane2_pre_emphasis()
962 reg |= level << PRE_EMPHASIS_SET_SHIFT; in exynos_dp_set_lane2_pre_emphasis()
963 writel(reg, dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL); in exynos_dp_set_lane2_pre_emphasis()
968 u32 reg; in exynos_dp_set_lane3_pre_emphasis() local
970 reg = readl(dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL); in exynos_dp_set_lane3_pre_emphasis()
971 reg &= ~PRE_EMPHASIS_SET_MASK; in exynos_dp_set_lane3_pre_emphasis()
972 reg |= level << PRE_EMPHASIS_SET_SHIFT; in exynos_dp_set_lane3_pre_emphasis()
973 writel(reg, dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL); in exynos_dp_set_lane3_pre_emphasis()
979 u32 reg; in exynos_dp_set_lane0_link_training() local
981 reg = training_lane; in exynos_dp_set_lane0_link_training()
982 writel(reg, dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL); in exynos_dp_set_lane0_link_training()
988 u32 reg; in exynos_dp_set_lane1_link_training() local
990 reg = training_lane; in exynos_dp_set_lane1_link_training()
991 writel(reg, dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL); in exynos_dp_set_lane1_link_training()
997 u32 reg; in exynos_dp_set_lane2_link_training() local
999 reg = training_lane; in exynos_dp_set_lane2_link_training()
1000 writel(reg, dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL); in exynos_dp_set_lane2_link_training()
1006 u32 reg; in exynos_dp_set_lane3_link_training() local
1008 reg = training_lane; in exynos_dp_set_lane3_link_training()
1009 writel(reg, dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL); in exynos_dp_set_lane3_link_training()
1014 u32 reg; in exynos_dp_get_lane0_link_training() local
1016 reg = readl(dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL); in exynos_dp_get_lane0_link_training()
1017 return reg; in exynos_dp_get_lane0_link_training()
1022 u32 reg; in exynos_dp_get_lane1_link_training() local
1024 reg = readl(dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL); in exynos_dp_get_lane1_link_training()
1025 return reg; in exynos_dp_get_lane1_link_training()
1030 u32 reg; in exynos_dp_get_lane2_link_training() local
1032 reg = readl(dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL); in exynos_dp_get_lane2_link_training()
1033 return reg; in exynos_dp_get_lane2_link_training()
1038 u32 reg; in exynos_dp_get_lane3_link_training() local
1040 reg = readl(dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL); in exynos_dp_get_lane3_link_training()
1041 return reg; in exynos_dp_get_lane3_link_training()
1046 u32 reg; in exynos_dp_reset_macro() local
1048 reg = readl(dp->reg_base + EXYNOS_DP_PHY_TEST); in exynos_dp_reset_macro()
1049 reg |= MACRO_RST; in exynos_dp_reset_macro()
1050 writel(reg, dp->reg_base + EXYNOS_DP_PHY_TEST); in exynos_dp_reset_macro()
1055 reg &= ~MACRO_RST; in exynos_dp_reset_macro()
1056 writel(reg, dp->reg_base + EXYNOS_DP_PHY_TEST); in exynos_dp_reset_macro()
1061 u32 reg; in exynos_dp_init_video() local
1063 reg = VSYNC_DET | VID_FORMAT_CHG | VID_CLK_CHG; in exynos_dp_init_video()
1064 writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_1); in exynos_dp_init_video()
1066 reg = 0x0; in exynos_dp_init_video()
1067 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_1); in exynos_dp_init_video()
1069 reg = CHA_CRI(4) | CHA_CTRL; in exynos_dp_init_video()
1070 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_2); in exynos_dp_init_video()
1072 reg = 0x0; in exynos_dp_init_video()
1073 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_3); in exynos_dp_init_video()
1075 reg = VID_HRES_TH(2) | VID_VRES_TH(0); in exynos_dp_init_video()
1076 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_8); in exynos_dp_init_video()
1081 u32 reg; in exynos_dp_set_video_color_format() local
1084 reg = (dp->video_info->dynamic_range << IN_D_RANGE_SHIFT) | in exynos_dp_set_video_color_format()
1087 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_2); in exynos_dp_set_video_color_format()
1090 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_3); in exynos_dp_set_video_color_format()
1091 reg &= ~IN_YC_COEFFI_MASK; in exynos_dp_set_video_color_format()
1093 reg |= IN_YC_COEFFI_ITU709; in exynos_dp_set_video_color_format()
1095 reg |= IN_YC_COEFFI_ITU601; in exynos_dp_set_video_color_format()
1096 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_3); in exynos_dp_set_video_color_format()
1101 u32 reg; in exynos_dp_is_slave_video_stream_clock_on() local
1103 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_1); in exynos_dp_is_slave_video_stream_clock_on()
1104 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_1); in exynos_dp_is_slave_video_stream_clock_on()
1106 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_1); in exynos_dp_is_slave_video_stream_clock_on()
1108 if (!(reg & DET_STA)) { in exynos_dp_is_slave_video_stream_clock_on()
1113 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_2); in exynos_dp_is_slave_video_stream_clock_on()
1114 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_2); in exynos_dp_is_slave_video_stream_clock_on()
1116 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_2); in exynos_dp_is_slave_video_stream_clock_on()
1119 if (reg & CHA_STA) { in exynos_dp_is_slave_video_stream_clock_on()
1132 u32 reg; in exynos_dp_set_video_cr_mn() local
1135 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4); in exynos_dp_set_video_cr_mn()
1136 reg |= FIX_M_VID; in exynos_dp_set_video_cr_mn()
1137 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4); in exynos_dp_set_video_cr_mn()
1138 reg = m_value & 0xff; in exynos_dp_set_video_cr_mn()
1139 writel(reg, dp->reg_base + EXYNOS_DP_M_VID_0); in exynos_dp_set_video_cr_mn()
1140 reg = (m_value >> 8) & 0xff; in exynos_dp_set_video_cr_mn()
1141 writel(reg, dp->reg_base + EXYNOS_DP_M_VID_1); in exynos_dp_set_video_cr_mn()
1142 reg = (m_value >> 16) & 0xff; in exynos_dp_set_video_cr_mn()
1143 writel(reg, dp->reg_base + EXYNOS_DP_M_VID_2); in exynos_dp_set_video_cr_mn()
1145 reg = n_value & 0xff; in exynos_dp_set_video_cr_mn()
1146 writel(reg, dp->reg_base + EXYNOS_DP_N_VID_0); in exynos_dp_set_video_cr_mn()
1147 reg = (n_value >> 8) & 0xff; in exynos_dp_set_video_cr_mn()
1148 writel(reg, dp->reg_base + EXYNOS_DP_N_VID_1); in exynos_dp_set_video_cr_mn()
1149 reg = (n_value >> 16) & 0xff; in exynos_dp_set_video_cr_mn()
1150 writel(reg, dp->reg_base + EXYNOS_DP_N_VID_2); in exynos_dp_set_video_cr_mn()
1152 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4); in exynos_dp_set_video_cr_mn()
1153 reg &= ~FIX_M_VID; in exynos_dp_set_video_cr_mn()
1154 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4); in exynos_dp_set_video_cr_mn()
1164 u32 reg; in exynos_dp_set_video_timing_mode() local
1167 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10); in exynos_dp_set_video_timing_mode()
1168 reg &= ~FORMAT_SEL; in exynos_dp_set_video_timing_mode()
1169 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10); in exynos_dp_set_video_timing_mode()
1171 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10); in exynos_dp_set_video_timing_mode()
1172 reg |= FORMAT_SEL; in exynos_dp_set_video_timing_mode()
1173 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10); in exynos_dp_set_video_timing_mode()
1179 u32 reg; in exynos_dp_enable_video_master() local
1182 reg = readl(dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL); in exynos_dp_enable_video_master()
1183 reg &= ~VIDEO_MODE_MASK; in exynos_dp_enable_video_master()
1184 reg |= VIDEO_MASTER_MODE_EN | VIDEO_MODE_MASTER_MODE; in exynos_dp_enable_video_master()
1185 writel(reg, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL); in exynos_dp_enable_video_master()
1187 reg = readl(dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL); in exynos_dp_enable_video_master()
1188 reg &= ~VIDEO_MODE_MASK; in exynos_dp_enable_video_master()
1189 reg |= VIDEO_MODE_SLAVE_MODE; in exynos_dp_enable_video_master()
1190 writel(reg, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL); in exynos_dp_enable_video_master()
1196 u32 reg; in exynos_dp_start_video() local
1198 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1); in exynos_dp_start_video()
1199 reg |= VIDEO_EN; in exynos_dp_start_video()
1200 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1); in exynos_dp_start_video()
1205 u32 reg; in exynos_dp_is_video_stream_on() local
1207 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3); in exynos_dp_is_video_stream_on()
1208 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_3); in exynos_dp_is_video_stream_on()
1210 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3); in exynos_dp_is_video_stream_on()
1211 if (!(reg & STRM_VALID)) { in exynos_dp_is_video_stream_on()
1221 u32 reg; in exynos_dp_config_video_slave_mode() local
1223 reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_1); in exynos_dp_config_video_slave_mode()
1224 reg &= ~(MASTER_VID_FUNC_EN_N|SLAVE_VID_FUNC_EN_N); in exynos_dp_config_video_slave_mode()
1225 reg |= MASTER_VID_FUNC_EN_N; in exynos_dp_config_video_slave_mode()
1226 writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_1); in exynos_dp_config_video_slave_mode()
1228 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10); in exynos_dp_config_video_slave_mode()
1229 reg &= ~INTERACE_SCAN_CFG; in exynos_dp_config_video_slave_mode()
1230 reg |= (dp->video_info->interlaced << 2); in exynos_dp_config_video_slave_mode()
1231 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10); in exynos_dp_config_video_slave_mode()
1233 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10); in exynos_dp_config_video_slave_mode()
1234 reg &= ~VSYNC_POLARITY_CFG; in exynos_dp_config_video_slave_mode()
1235 reg |= (dp->video_info->v_sync_polarity << 1); in exynos_dp_config_video_slave_mode()
1236 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10); in exynos_dp_config_video_slave_mode()
1238 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10); in exynos_dp_config_video_slave_mode()
1239 reg &= ~HSYNC_POLARITY_CFG; in exynos_dp_config_video_slave_mode()
1240 reg |= (dp->video_info->h_sync_polarity << 0); in exynos_dp_config_video_slave_mode()
1241 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10); in exynos_dp_config_video_slave_mode()
1243 reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE; in exynos_dp_config_video_slave_mode()
1244 writel(reg, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL); in exynos_dp_config_video_slave_mode()
1249 u32 reg; in exynos_dp_enable_scrambling() local
1251 reg = readl(dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET); in exynos_dp_enable_scrambling()
1252 reg &= ~SCRAMBLING_DISABLE; in exynos_dp_enable_scrambling()
1253 writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET); in exynos_dp_enable_scrambling()
1258 u32 reg; in exynos_dp_disable_scrambling() local
1260 reg = readl(dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET); in exynos_dp_disable_scrambling()
1261 reg |= SCRAMBLING_DISABLE; in exynos_dp_disable_scrambling()
1262 writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET); in exynos_dp_disable_scrambling()