79 	u32 reg;  in emma2rh_sw_irq_enable()  local
81 	reg = emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN);  in emma2rh_sw_irq_enable()
82 	reg |= 1 << irq;  in emma2rh_sw_irq_enable()
83 	emma2rh_out32(EMMA2RH_BHIF_SW_INT_EN, reg);  in emma2rh_sw_irq_enable()
89 	u32 reg;  in emma2rh_sw_irq_disable()  local
91 	reg = emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN);  in emma2rh_sw_irq_disable()
92 	reg &= ~(1 << irq);  in emma2rh_sw_irq_disable()
93 	emma2rh_out32(EMMA2RH_BHIF_SW_INT_EN, reg);  in emma2rh_sw_irq_disable()
115 	u32 reg;  in emma2rh_gpio_irq_enable()  local
117 	reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK);  in emma2rh_gpio_irq_enable()
118 	reg |= 1 << irq;  in emma2rh_gpio_irq_enable()
119 	emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg);  in emma2rh_gpio_irq_enable()
125 	u32 reg;  in emma2rh_gpio_irq_disable()  local
127 	reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK);  in emma2rh_gpio_irq_disable()
128 	reg &= ~(1 << irq);  in emma2rh_gpio_irq_disable()
129 	emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg);  in emma2rh_gpio_irq_disable()
142 	u32 reg;  in emma2rh_gpio_irq_mask_ack()  local
146 	reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK);  in emma2rh_gpio_irq_mask_ack()
147 	reg &= ~(1 << irq);  in emma2rh_gpio_irq_mask_ack()
148 	emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg);  in emma2rh_gpio_irq_mask_ack()
251 	u32 reg;  in arch_init_irq()  local
268 	reg = emma2rh_in32(EMMA2RH_GPIO_DIR);  in arch_init_irq()
269 	emma2rh_out32(EMMA2RH_GPIO_DIR, reg & ~GPIO_PCI);  in arch_init_irq()
271 	reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK);  in arch_init_irq()
272 	emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg & ~GPIO_PCI);  in arch_init_irq()
274 	reg = emma2rh_in32(EMMA2RH_GPIO_INT_MODE);  in arch_init_irq()
275 	emma2rh_out32(EMMA2RH_GPIO_INT_MODE, reg | GPIO_PCI);  in arch_init_irq()
276 	reg = emma2rh_in32(EMMA2RH_GPIO_INT_CND_A);  in arch_init_irq()
277 	emma2rh_out32(EMMA2RH_GPIO_INT_CND_A, reg & (~GPIO_PCI));  in arch_init_irq()