Searched refs:oclass (Results 1 - 200 of 206) sorted by relevance

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/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/device/
H A D	nv40.c	55 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; nv40_identify() 56 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; nv40_identify() 57 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; nv40_identify() 58 device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass; nv40_identify() 59 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; nv40_identify() 60 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; nv40_identify() 61 device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; nv40_identify() 62 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; nv40_identify() 63 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; nv40_identify() 64 device->oclass[NVDEV_SUBDEV_FB ] = nv40_fb_oclass; nv40_identify() 65 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; nv40_identify() 66 device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; nv40_identify() 67 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; nv40_identify() 68 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; nv40_identify() 69 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; nv40_identify() 70 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; nv40_identify() 71 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; nv40_identify() 72 device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass; nv40_identify() 73 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; nv40_identify() 74 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; nv40_identify() 78 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; nv40_identify() 79 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; nv40_identify() 80 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; nv40_identify() 81 device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass; nv40_identify() 82 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; nv40_identify() 83 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; nv40_identify() 84 device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; nv40_identify() 85 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; nv40_identify() 86 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; nv40_identify() 87 device->oclass[NVDEV_SUBDEV_FB ] = nv41_fb_oclass; nv40_identify() 88 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; nv40_identify() 89 device->oclass[NVDEV_SUBDEV_MMU ] = &nv41_mmu_oclass; nv40_identify() 90 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; nv40_identify() 91 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; nv40_identify() 92 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; nv40_identify() 93 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; nv40_identify() 94 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; nv40_identify() 95 device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass; nv40_identify() 96 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; nv40_identify() 97 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; nv40_identify() 101 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; nv40_identify() 102 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; nv40_identify() 103 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; nv40_identify() 104 device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass; nv40_identify() 105 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; nv40_identify() 106 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; nv40_identify() 107 device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; nv40_identify() 108 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; nv40_identify() 109 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; nv40_identify() 110 device->oclass[NVDEV_SUBDEV_FB ] = nv41_fb_oclass; nv40_identify() 111 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; nv40_identify() 112 device->oclass[NVDEV_SUBDEV_MMU ] = &nv41_mmu_oclass; nv40_identify() 113 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; nv40_identify() 114 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; nv40_identify() 115 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; nv40_identify() 116 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; nv40_identify() 117 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; nv40_identify() 118 device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass; nv40_identify() 119 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; nv40_identify() 120 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; nv40_identify() 124 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; nv40_identify() 125 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; nv40_identify() 126 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; nv40_identify() 127 device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass; nv40_identify() 128 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; nv40_identify() 129 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; nv40_identify() 130 device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; nv40_identify() 131 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; nv40_identify() 132 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; nv40_identify() 133 device->oclass[NVDEV_SUBDEV_FB ] = nv41_fb_oclass; nv40_identify() 134 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; nv40_identify() 135 device->oclass[NVDEV_SUBDEV_MMU ] = &nv41_mmu_oclass; nv40_identify() 136 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; nv40_identify() 137 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; nv40_identify() 138 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; nv40_identify() 139 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; nv40_identify() 140 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; nv40_identify() 141 device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass; nv40_identify() 142 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; nv40_identify() 143 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; nv40_identify() 147 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; nv40_identify() 148 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; nv40_identify() 149 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; nv40_identify() 150 device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass; nv40_identify() 151 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; nv40_identify() 152 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; nv40_identify() 153 device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; nv40_identify() 154 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; nv40_identify() 155 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; nv40_identify() 156 device->oclass[NVDEV_SUBDEV_FB ] = nv40_fb_oclass; nv40_identify() 157 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; nv40_identify() 158 device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; nv40_identify() 159 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; nv40_identify() 160 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; nv40_identify() 161 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; nv40_identify() 162 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; nv40_identify() 163 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; nv40_identify() 164 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; nv40_identify() 165 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; nv40_identify() 166 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; nv40_identify() 170 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; nv40_identify() 171 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; nv40_identify() 172 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; nv40_identify() 173 device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass; nv40_identify() 174 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; nv40_identify() 175 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; nv40_identify() 176 device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; nv40_identify() 177 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; nv40_identify() 178 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; nv40_identify() 179 device->oclass[NVDEV_SUBDEV_FB ] = nv47_fb_oclass; nv40_identify() 180 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; nv40_identify() 181 device->oclass[NVDEV_SUBDEV_MMU ] = &nv41_mmu_oclass; nv40_identify() 182 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; nv40_identify() 183 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; nv40_identify() 184 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; nv40_identify() 185 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; nv40_identify() 186 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; nv40_identify() 187 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; nv40_identify() 188 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; nv40_identify() 189 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; nv40_identify() 193 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; nv40_identify() 194 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; nv40_identify() 195 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; nv40_identify() 196 device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass; nv40_identify() 197 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; nv40_identify() 198 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; nv40_identify() 199 device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; nv40_identify() 200 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; nv40_identify() 201 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; nv40_identify() 202 device->oclass[NVDEV_SUBDEV_FB ] = nv49_fb_oclass; nv40_identify() 203 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; nv40_identify() 204 device->oclass[NVDEV_SUBDEV_MMU ] = &nv41_mmu_oclass; nv40_identify() 205 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; nv40_identify() 206 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; nv40_identify() 207 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; nv40_identify() 208 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; nv40_identify() 209 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; nv40_identify() 210 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; nv40_identify() 211 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; nv40_identify() 212 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; nv40_identify() 216 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; nv40_identify() 217 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; nv40_identify() 218 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; nv40_identify() 219 device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass; nv40_identify() 220 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; nv40_identify() 221 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; nv40_identify() 222 device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; nv40_identify() 223 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; nv40_identify() 224 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; nv40_identify() 225 device->oclass[NVDEV_SUBDEV_FB ] = nv49_fb_oclass; nv40_identify() 226 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; nv40_identify() 227 device->oclass[NVDEV_SUBDEV_MMU ] = &nv41_mmu_oclass; nv40_identify() 228 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; nv40_identify() 229 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; nv40_identify() 230 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; nv40_identify() 231 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; nv40_identify() 232 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; nv40_identify() 233 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; nv40_identify() 234 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; nv40_identify() 235 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; nv40_identify() 239 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; nv40_identify() 240 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; nv40_identify() 241 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; nv40_identify() 242 device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass; nv40_identify() 243 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; nv40_identify() 244 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; nv40_identify() 245 device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass; nv40_identify() 246 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; nv40_identify() 247 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; nv40_identify() 248 device->oclass[NVDEV_SUBDEV_FB ] = nv44_fb_oclass; nv40_identify() 249 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; nv40_identify() 250 device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass; nv40_identify() 251 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; nv40_identify() 252 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; nv40_identify() 253 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; nv40_identify() 254 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; nv40_identify() 255 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; nv40_identify() 256 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; nv40_identify() 257 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; nv40_identify() 258 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; nv40_identify() 262 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; nv40_identify() 263 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; nv40_identify() 264 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; nv40_identify() 265 device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass; nv40_identify() 266 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; nv40_identify() 267 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; nv40_identify() 268 device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass; nv40_identify() 269 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; nv40_identify() 270 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; nv40_identify() 271 device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass; nv40_identify() 272 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; nv40_identify() 273 device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass; nv40_identify() 274 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; nv40_identify() 275 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; nv40_identify() 276 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; nv40_identify() 277 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; nv40_identify() 278 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; nv40_identify() 279 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; nv40_identify() 280 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; nv40_identify() 281 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; nv40_identify() 285 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; nv40_identify() 286 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; nv40_identify() 287 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; nv40_identify() 288 device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass; nv40_identify() 289 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; nv40_identify() 290 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; nv40_identify() 291 device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass; nv40_identify() 292 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; nv40_identify() 293 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; nv40_identify() 294 device->oclass[NVDEV_SUBDEV_FB ] = nv44_fb_oclass; nv40_identify() 295 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; nv40_identify() 296 device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass; nv40_identify() 297 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; nv40_identify() 298 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; nv40_identify() 299 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; nv40_identify() 300 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; nv40_identify() 301 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; nv40_identify() 302 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; nv40_identify() 303 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; nv40_identify() 304 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; nv40_identify() 308 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; nv40_identify() 309 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; nv40_identify() 310 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; nv40_identify() 311 device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass; nv40_identify() 312 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; nv40_identify() 313 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; nv40_identify() 314 device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass; nv40_identify() 315 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; nv40_identify() 316 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; nv40_identify() 317 device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass; nv40_identify() 318 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; nv40_identify() 319 device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass; nv40_identify() 320 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; nv40_identify() 321 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; nv40_identify() 322 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; nv40_identify() 323 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; nv40_identify() 324 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; nv40_identify() 325 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; nv40_identify() 326 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; nv40_identify() 327 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; nv40_identify() 331 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; nv40_identify() 332 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; nv40_identify() 333 device->oclass[NVDEV_SUBDEV_I2C ] = nv4e_i2c_oclass; nv40_identify() 334 device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass; nv40_identify() 335 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; nv40_identify() 336 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; nv40_identify() 337 device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass; nv40_identify() 338 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; nv40_identify() 339 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; nv40_identify() 340 device->oclass[NVDEV_SUBDEV_FB ] = nv4e_fb_oclass; nv40_identify() 341 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; nv40_identify() 342 device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass; nv40_identify() 343 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; nv40_identify() 344 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; nv40_identify() 345 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; nv40_identify() 346 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; nv40_identify() 347 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; nv40_identify() 348 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; nv40_identify() 349 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; nv40_identify() 350 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; nv40_identify() 354 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; nv40_identify() 355 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; nv40_identify() 356 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; nv40_identify() 357 device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass; nv40_identify() 358 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; nv40_identify() 359 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; nv40_identify() 360 device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass; nv40_identify() 361 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; nv40_identify() 362 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; nv40_identify() 363 device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass; nv40_identify() 364 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; nv40_identify() 365 device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass; nv40_identify() 366 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; nv40_identify() 367 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; nv40_identify() 368 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; nv40_identify() 369 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; nv40_identify() 370 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; nv40_identify() 371 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; nv40_identify() 372 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; nv40_identify() 373 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; nv40_identify() 377 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; nv40_identify() 378 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; nv40_identify() 379 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; nv40_identify() 380 device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass; nv40_identify() 381 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; nv40_identify() 382 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; nv40_identify() 383 device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass; nv40_identify() 384 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; nv40_identify() 385 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; nv40_identify() 386 device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass; nv40_identify() 387 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; nv40_identify() 388 device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass; nv40_identify() 389 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; nv40_identify() 390 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; nv40_identify() 391 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; nv40_identify() 392 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; nv40_identify() 393 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; nv40_identify() 394 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; nv40_identify() 395 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; nv40_identify() 396 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; nv40_identify() 400 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; nv40_identify() 401 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; nv40_identify() 402 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; nv40_identify() 403 device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass; nv40_identify() 404 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; nv40_identify() 405 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; nv40_identify() 406 device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass; nv40_identify() 407 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; nv40_identify() 408 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; nv40_identify() 409 device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass; nv40_identify() 410 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; nv40_identify() 411 device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass; nv40_identify() 412 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; nv40_identify() 413 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; nv40_identify() 414 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; nv40_identify() 415 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; nv40_identify() 416 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; nv40_identify() 417 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; nv40_identify() 418 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; nv40_identify() 419 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; nv40_identify()
H A D	gk104.c	64 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; gk104_identify() 65 device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass; gk104_identify() 66 device->oclass[NVDEV_SUBDEV_I2C ] = gk104_i2c_oclass; gk104_identify() 67 device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; gk104_identify() 68 device->oclass[NVDEV_SUBDEV_CLK ] = &gk104_clk_oclass; gk104_identify() 69 device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass; gk104_identify() 70 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; gk104_identify() 71 device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; gk104_identify() 72 device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass; gk104_identify() 73 device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; gk104_identify() 74 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; gk104_identify() 75 device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass; gk104_identify() 76 device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; gk104_identify() 77 device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass; gk104_identify() 78 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; gk104_identify() 79 device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; gk104_identify() 80 device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; gk104_identify() 81 device->oclass[NVDEV_SUBDEV_PMU ] = gk104_pmu_oclass; gk104_identify() 82 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; gk104_identify() 83 device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; gk104_identify() 84 device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass; gk104_identify() 85 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; gk104_identify() 86 device->oclass[NVDEV_ENGINE_GR ] = gk104_gr_oclass; gk104_identify() 87 device->oclass[NVDEV_ENGINE_DISP ] = gk104_disp_oclass; gk104_identify() 88 device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass; gk104_identify() 89 device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass; gk104_identify() 90 device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass; gk104_identify() 91 device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass; gk104_identify() 92 device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass; gk104_identify() 93 device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; gk104_identify() 94 device->oclass[NVDEV_ENGINE_PM ] = &gk104_pm_oclass; gk104_identify() 98 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; gk104_identify() 99 device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass; gk104_identify() 100 device->oclass[NVDEV_SUBDEV_I2C ] = gk104_i2c_oclass; gk104_identify() 101 device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; gk104_identify() 102 device->oclass[NVDEV_SUBDEV_CLK ] = &gk104_clk_oclass; gk104_identify() 103 device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass; gk104_identify() 104 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; gk104_identify() 105 device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; gk104_identify() 106 device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass; gk104_identify() 107 device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; gk104_identify() 108 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; gk104_identify() 109 device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass; gk104_identify() 110 device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; gk104_identify() 111 device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass; gk104_identify() 112 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; gk104_identify() 113 device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; gk104_identify() 114 device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; gk104_identify() 115 device->oclass[NVDEV_SUBDEV_PMU ] = gf110_pmu_oclass; gk104_identify() 116 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; gk104_identify() 117 device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; gk104_identify() 118 device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass; gk104_identify() 119 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; gk104_identify() 120 device->oclass[NVDEV_ENGINE_GR ] = gk104_gr_oclass; gk104_identify() 121 device->oclass[NVDEV_ENGINE_DISP ] = gk104_disp_oclass; gk104_identify() 122 device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass; gk104_identify() 123 device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass; gk104_identify() 124 device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass; gk104_identify() 125 device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass; gk104_identify() 126 device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass; gk104_identify() 127 device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; gk104_identify() 128 device->oclass[NVDEV_ENGINE_PM ] = &gk104_pm_oclass; gk104_identify() 132 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; gk104_identify() 133 device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass; gk104_identify() 134 device->oclass[NVDEV_SUBDEV_I2C ] = gk104_i2c_oclass; gk104_identify() 135 device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; gk104_identify() 136 device->oclass[NVDEV_SUBDEV_CLK ] = &gk104_clk_oclass; gk104_identify() 137 device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass; gk104_identify() 138 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; gk104_identify() 139 device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; gk104_identify() 140 device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass; gk104_identify() 141 device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; gk104_identify() 142 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; gk104_identify() 143 device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass; gk104_identify() 144 device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; gk104_identify() 145 device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass; gk104_identify() 146 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; gk104_identify() 147 device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; gk104_identify() 148 device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; gk104_identify() 149 device->oclass[NVDEV_SUBDEV_PMU ] = gk104_pmu_oclass; gk104_identify() 150 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; gk104_identify() 151 device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; gk104_identify() 152 device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass; gk104_identify() 153 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; gk104_identify() 154 device->oclass[NVDEV_ENGINE_GR ] = gk104_gr_oclass; gk104_identify() 155 device->oclass[NVDEV_ENGINE_DISP ] = gk104_disp_oclass; gk104_identify() 156 device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass; gk104_identify() 157 device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass; gk104_identify() 158 device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass; gk104_identify() 159 device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass; gk104_identify() 160 device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass; gk104_identify() 161 device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; gk104_identify() 162 device->oclass[NVDEV_ENGINE_PM ] = &gk104_pm_oclass; gk104_identify() 166 device->oclass[NVDEV_SUBDEV_CLK ] = &gk20a_clk_oclass; gk104_identify() 167 device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass; gk104_identify() 168 device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; gk104_identify() 169 device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; gk104_identify() 170 device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass; gk104_identify() 171 device->oclass[NVDEV_SUBDEV_FB ] = gk20a_fb_oclass; gk104_identify() 172 device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; gk104_identify() 173 device->oclass[NVDEV_SUBDEV_IBUS ] = &gk20a_ibus_oclass; gk104_identify() 174 device->oclass[NVDEV_SUBDEV_INSTMEM] = gk20a_instmem_oclass; gk104_identify() 175 device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; gk104_identify() 176 device->oclass[NVDEV_SUBDEV_BAR ] = &gk20a_bar_oclass; gk104_identify() 177 device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; gk104_identify() 178 device->oclass[NVDEV_ENGINE_FIFO ] = gk20a_fifo_oclass; gk104_identify() 179 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; gk104_identify() 180 device->oclass[NVDEV_ENGINE_GR ] = gk20a_gr_oclass; gk104_identify() 181 device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass; gk104_identify() 182 device->oclass[NVDEV_ENGINE_PM ] = &gk104_pm_oclass; gk104_identify() 183 device->oclass[NVDEV_SUBDEV_VOLT ] = &gk20a_volt_oclass; gk104_identify() 184 device->oclass[NVDEV_SUBDEV_PMU ] = gk20a_pmu_oclass; gk104_identify() 188 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; gk104_identify() 189 device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass; gk104_identify() 190 device->oclass[NVDEV_SUBDEV_I2C ] = gk104_i2c_oclass; gk104_identify() 191 device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; gk104_identify() 192 device->oclass[NVDEV_SUBDEV_CLK ] = &gk104_clk_oclass; gk104_identify() 193 device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass; gk104_identify() 194 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; gk104_identify() 195 device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; gk104_identify() 196 device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass; gk104_identify() 197 device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; gk104_identify() 198 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; gk104_identify() 199 device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass; gk104_identify() 200 device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; gk104_identify() 201 device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass; gk104_identify() 202 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; gk104_identify() 203 device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; gk104_identify() 204 device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; gk104_identify() 205 device->oclass[NVDEV_SUBDEV_PMU ] = gk110_pmu_oclass; gk104_identify() 206 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; gk104_identify() 207 device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; gk104_identify() 208 device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass; gk104_identify() 209 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; gk104_identify() 210 device->oclass[NVDEV_ENGINE_GR ] = gk110_gr_oclass; gk104_identify() 211 device->oclass[NVDEV_ENGINE_DISP ] = gk110_disp_oclass; gk104_identify() 212 device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass; gk104_identify() 213 device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass; gk104_identify() 214 device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass; gk104_identify() 215 device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass; gk104_identify() 216 device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass; gk104_identify() 217 device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; gk104_identify() 218 device->oclass[NVDEV_ENGINE_PM ] = &gk110_pm_oclass; gk104_identify() 222 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; gk104_identify() 223 device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass; gk104_identify() 224 device->oclass[NVDEV_SUBDEV_I2C ] = gf110_i2c_oclass; gk104_identify() 225 device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; gk104_identify() 226 device->oclass[NVDEV_SUBDEV_CLK ] = &gk104_clk_oclass; gk104_identify() 227 device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass; gk104_identify() 228 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; gk104_identify() 229 device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; gk104_identify() 230 device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass; gk104_identify() 231 device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; gk104_identify() 232 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; gk104_identify() 233 device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass; gk104_identify() 234 device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; gk104_identify() 235 device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass; gk104_identify() 236 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; gk104_identify() 237 device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; gk104_identify() 238 device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; gk104_identify() 239 device->oclass[NVDEV_SUBDEV_PMU ] = gk110_pmu_oclass; gk104_identify() 240 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; gk104_identify() 241 device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; gk104_identify() 242 device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass; gk104_identify() 243 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; gk104_identify() 244 device->oclass[NVDEV_ENGINE_GR ] = gk110b_gr_oclass; gk104_identify() 245 device->oclass[NVDEV_ENGINE_DISP ] = gk110_disp_oclass; gk104_identify() 246 device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass; gk104_identify() 247 device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass; gk104_identify() 248 device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass; gk104_identify() 249 device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass; gk104_identify() 250 device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass; gk104_identify() 251 device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; gk104_identify() 252 device->oclass[NVDEV_ENGINE_PM ] = &gk110_pm_oclass; gk104_identify() 256 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; gk104_identify() 257 device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass; gk104_identify() 258 device->oclass[NVDEV_SUBDEV_I2C ] = gk104_i2c_oclass; gk104_identify() 259 device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; gk104_identify() 260 device->oclass[NVDEV_SUBDEV_CLK ] = &gk104_clk_oclass; gk104_identify() 261 device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass; gk104_identify() 262 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; gk104_identify() 263 device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; gk104_identify() 264 device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass; gk104_identify() 265 device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; gk104_identify() 266 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; gk104_identify() 267 device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass; gk104_identify() 268 device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; gk104_identify() 269 device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass; gk104_identify() 270 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; gk104_identify() 271 device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; gk104_identify() 272 device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; gk104_identify() 273 device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass; gk104_identify() 274 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; gk104_identify() 275 device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; gk104_identify() 276 device->oclass[NVDEV_ENGINE_FIFO ] = gk208_fifo_oclass; gk104_identify() 277 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; gk104_identify() 278 device->oclass[NVDEV_ENGINE_GR ] = gk208_gr_oclass; gk104_identify() 279 device->oclass[NVDEV_ENGINE_DISP ] = gk110_disp_oclass; gk104_identify() 280 device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass; gk104_identify() 281 device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass; gk104_identify() 282 device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass; gk104_identify() 283 device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass; gk104_identify() 284 device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass; gk104_identify() 285 device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; gk104_identify() 289 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; gk104_identify() 290 device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass; gk104_identify() 291 device->oclass[NVDEV_SUBDEV_I2C ] = gk104_i2c_oclass; gk104_identify() 292 device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; gk104_identify() 293 device->oclass[NVDEV_SUBDEV_CLK ] = &gk104_clk_oclass; gk104_identify() 294 device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass; gk104_identify() 295 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; gk104_identify() 296 device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; gk104_identify() 297 device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass; gk104_identify() 298 device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; gk104_identify() 299 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; gk104_identify() 300 device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass; gk104_identify() 301 device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; gk104_identify() 302 device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass; gk104_identify() 303 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; gk104_identify() 304 device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; gk104_identify() 305 device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; gk104_identify() 306 device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass; gk104_identify() 307 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; gk104_identify() 308 device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; gk104_identify() 309 device->oclass[NVDEV_ENGINE_FIFO ] = gk208_fifo_oclass; gk104_identify() 310 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; gk104_identify() 311 device->oclass[NVDEV_ENGINE_GR ] = gk208_gr_oclass; gk104_identify() 312 device->oclass[NVDEV_ENGINE_DISP ] = gk110_disp_oclass; gk104_identify() 313 device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass; gk104_identify() 314 device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass; gk104_identify() 315 device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass; gk104_identify() 316 device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass; gk104_identify() 317 device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass; gk104_identify() 318 device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; gk104_identify()
H A D	gf100.c	64 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; gf100_identify() 65 device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass; gf100_identify() 66 device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass; gf100_identify() 67 device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; gf100_identify() 68 device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass; gf100_identify() 69 device->oclass[NVDEV_SUBDEV_THERM ] = &gt215_therm_oclass; gf100_identify() 70 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; gf100_identify() 71 device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; gf100_identify() 72 device->oclass[NVDEV_SUBDEV_MC ] = gf100_mc_oclass; gf100_identify() 73 device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; gf100_identify() 74 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; gf100_identify() 75 device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass; gf100_identify() 76 device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; gf100_identify() 77 device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass; gf100_identify() 78 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; gf100_identify() 79 device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; gf100_identify() 80 device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; gf100_identify() 81 device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass; gf100_identify() 82 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; gf100_identify() 83 device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass; gf100_identify() 84 device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; gf100_identify() 85 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; gf100_identify() 86 device->oclass[NVDEV_ENGINE_GR ] = gf100_gr_oclass; gf100_identify() 87 device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass; gf100_identify() 88 device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass; gf100_identify() 89 device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; gf100_identify() 90 device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass; gf100_identify() 91 device->oclass[NVDEV_ENGINE_CE1 ] = &gf100_ce1_oclass; gf100_identify() 92 device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass; gf100_identify() 93 device->oclass[NVDEV_ENGINE_PM ] = &gf100_pm_oclass; gf100_identify() 97 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; gf100_identify() 98 device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass; gf100_identify() 99 device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass; gf100_identify() 100 device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; gf100_identify() 101 device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass; gf100_identify() 102 device->oclass[NVDEV_SUBDEV_THERM ] = &gt215_therm_oclass; gf100_identify() 103 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; gf100_identify() 104 device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; gf100_identify() 105 device->oclass[NVDEV_SUBDEV_MC ] = gf100_mc_oclass; gf100_identify() 106 device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; gf100_identify() 107 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; gf100_identify() 108 device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass; gf100_identify() 109 device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; gf100_identify() 110 device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass; gf100_identify() 111 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; gf100_identify() 112 device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; gf100_identify() 113 device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; gf100_identify() 114 device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass; gf100_identify() 115 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; gf100_identify() 116 device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass; gf100_identify() 117 device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; gf100_identify() 118 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; gf100_identify() 119 device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass; gf100_identify() 120 device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass; gf100_identify() 121 device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass; gf100_identify() 122 device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; gf100_identify() 123 device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass; gf100_identify() 124 device->oclass[NVDEV_ENGINE_CE1 ] = &gf100_ce1_oclass; gf100_identify() 125 device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass; gf100_identify() 126 device->oclass[NVDEV_ENGINE_PM ] = &gf100_pm_oclass; gf100_identify() 130 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; gf100_identify() 131 device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass; gf100_identify() 132 device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass; gf100_identify() 133 device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; gf100_identify() 134 device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass; gf100_identify() 135 device->oclass[NVDEV_SUBDEV_THERM ] = &gt215_therm_oclass; gf100_identify() 136 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; gf100_identify() 137 device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; gf100_identify() 138 device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass; gf100_identify() 139 device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; gf100_identify() 140 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; gf100_identify() 141 device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass; gf100_identify() 142 device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; gf100_identify() 143 device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass; gf100_identify() 144 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; gf100_identify() 145 device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; gf100_identify() 146 device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; gf100_identify() 147 device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass; gf100_identify() 148 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; gf100_identify() 149 device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass; gf100_identify() 150 device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; gf100_identify() 151 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; gf100_identify() 152 device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass; gf100_identify() 153 device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass; gf100_identify() 154 device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass; gf100_identify() 155 device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; gf100_identify() 156 device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass; gf100_identify() 157 device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass; gf100_identify() 158 device->oclass[NVDEV_ENGINE_PM ] = &gf100_pm_oclass; gf100_identify() 162 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; gf100_identify() 163 device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass; gf100_identify() 164 device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass; gf100_identify() 165 device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; gf100_identify() 166 device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass; gf100_identify() 167 device->oclass[NVDEV_SUBDEV_THERM ] = &gt215_therm_oclass; gf100_identify() 168 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; gf100_identify() 169 device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; gf100_identify() 170 device->oclass[NVDEV_SUBDEV_MC ] = gf100_mc_oclass; gf100_identify() 171 device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; gf100_identify() 172 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; gf100_identify() 173 device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass; gf100_identify() 174 device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; gf100_identify() 175 device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass; gf100_identify() 176 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; gf100_identify() 177 device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; gf100_identify() 178 device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; gf100_identify() 179 device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass; gf100_identify() 180 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; gf100_identify() 181 device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass; gf100_identify() 182 device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; gf100_identify() 183 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; gf100_identify() 184 device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass; gf100_identify() 185 device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass; gf100_identify() 186 device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass; gf100_identify() 187 device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; gf100_identify() 188 device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass; gf100_identify() 189 device->oclass[NVDEV_ENGINE_CE1 ] = &gf100_ce1_oclass; gf100_identify() 190 device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass; gf100_identify() 191 device->oclass[NVDEV_ENGINE_PM ] = &gf100_pm_oclass; gf100_identify() 195 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; gf100_identify() 196 device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass; gf100_identify() 197 device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass; gf100_identify() 198 device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; gf100_identify() 199 device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass; gf100_identify() 200 device->oclass[NVDEV_SUBDEV_THERM ] = &gt215_therm_oclass; gf100_identify() 201 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; gf100_identify() 202 device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; gf100_identify() 203 device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass; gf100_identify() 204 device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; gf100_identify() 205 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; gf100_identify() 206 device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass; gf100_identify() 207 device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; gf100_identify() 208 device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass; gf100_identify() 209 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; gf100_identify() 210 device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; gf100_identify() 211 device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; gf100_identify() 212 device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass; gf100_identify() 213 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; gf100_identify() 214 device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass; gf100_identify() 215 device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; gf100_identify() 216 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; gf100_identify() 217 device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass; gf100_identify() 218 device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass; gf100_identify() 219 device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass; gf100_identify() 220 device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; gf100_identify() 221 device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass; gf100_identify() 222 device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass; gf100_identify() 223 device->oclass[NVDEV_ENGINE_PM ] = &gf100_pm_oclass; gf100_identify() 227 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; gf100_identify() 228 device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass; gf100_identify() 229 device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass; gf100_identify() 230 device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; gf100_identify() 231 device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass; gf100_identify() 232 device->oclass[NVDEV_SUBDEV_THERM ] = &gt215_therm_oclass; gf100_identify() 233 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; gf100_identify() 234 device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; gf100_identify() 235 device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass; gf100_identify() 236 device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; gf100_identify() 237 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; gf100_identify() 238 device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass; gf100_identify() 239 device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; gf100_identify() 240 device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass; gf100_identify() 241 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; gf100_identify() 242 device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; gf100_identify() 243 device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; gf100_identify() 244 device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass; gf100_identify() 245 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; gf100_identify() 246 device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass; gf100_identify() 247 device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; gf100_identify() 248 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; gf100_identify() 249 device->oclass[NVDEV_ENGINE_GR ] = gf108_gr_oclass; gf100_identify() 250 device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass; gf100_identify() 251 device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass; gf100_identify() 252 device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; gf100_identify() 253 device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass; gf100_identify() 254 device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass; gf100_identify() 255 device->oclass[NVDEV_ENGINE_PM ] = &gf100_pm_oclass; gf100_identify() 259 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; gf100_identify() 260 device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass; gf100_identify() 261 device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass; gf100_identify() 262 device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; gf100_identify() 263 device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass; gf100_identify() 264 device->oclass[NVDEV_SUBDEV_THERM ] = &gt215_therm_oclass; gf100_identify() 265 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; gf100_identify() 266 device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; gf100_identify() 267 device->oclass[NVDEV_SUBDEV_MC ] = gf100_mc_oclass; gf100_identify() 268 device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; gf100_identify() 269 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; gf100_identify() 270 device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass; gf100_identify() 271 device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; gf100_identify() 272 device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass; gf100_identify() 273 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; gf100_identify() 274 device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; gf100_identify() 275 device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; gf100_identify() 276 device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass; gf100_identify() 277 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; gf100_identify() 278 device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass; gf100_identify() 279 device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; gf100_identify() 280 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; gf100_identify() 281 device->oclass[NVDEV_ENGINE_GR ] = gf110_gr_oclass; gf100_identify() 282 device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass; gf100_identify() 283 device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass; gf100_identify() 284 device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; gf100_identify() 285 device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass; gf100_identify() 286 device->oclass[NVDEV_ENGINE_CE1 ] = &gf100_ce1_oclass; gf100_identify() 287 device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass; gf100_identify() 288 device->oclass[NVDEV_ENGINE_PM ] = &gf100_pm_oclass; gf100_identify() 292 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; gf100_identify() 293 device->oclass[NVDEV_SUBDEV_GPIO ] = gf110_gpio_oclass; gf100_identify() 294 device->oclass[NVDEV_SUBDEV_I2C ] = gf110_i2c_oclass; gf100_identify() 295 device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; gf100_identify() 296 device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass; gf100_identify() 297 device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass; gf100_identify() 298 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; gf100_identify() 299 device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; gf100_identify() 300 device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass; gf100_identify() 301 device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; gf100_identify() 302 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; gf100_identify() 303 device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass; gf100_identify() 304 device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; gf100_identify() 305 device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass; gf100_identify() 306 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; gf100_identify() 307 device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; gf100_identify() 308 device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; gf100_identify() 309 device->oclass[NVDEV_SUBDEV_PMU ] = gf110_pmu_oclass; gf100_identify() 310 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; gf100_identify() 311 device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; gf100_identify() 312 device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; gf100_identify() 313 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; gf100_identify() 314 device->oclass[NVDEV_ENGINE_GR ] = gf119_gr_oclass; gf100_identify() 315 device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass; gf100_identify() 316 device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass; gf100_identify() 317 device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; gf100_identify() 318 device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass; gf100_identify() 319 device->oclass[NVDEV_ENGINE_DISP ] = gf110_disp_oclass; gf100_identify() 320 device->oclass[NVDEV_ENGINE_PM ] = &gf100_pm_oclass; gf100_identify() 324 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; gf100_identify() 325 device->oclass[NVDEV_SUBDEV_GPIO ] = gf110_gpio_oclass; gf100_identify() 326 device->oclass[NVDEV_SUBDEV_I2C ] = gf117_i2c_oclass; gf100_identify() 327 device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; gf100_identify() 328 device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass; gf100_identify() 329 device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass; gf100_identify() 330 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; gf100_identify() 331 device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; gf100_identify() 332 device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass; gf100_identify() 333 device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; gf100_identify() 334 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; gf100_identify() 335 device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass; gf100_identify() 336 device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; gf100_identify() 337 device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass; gf100_identify() 338 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; gf100_identify() 339 device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; gf100_identify() 340 device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; gf100_identify() 341 device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; gf100_identify() 342 device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; gf100_identify() 343 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; gf100_identify() 344 device->oclass[NVDEV_ENGINE_GR ] = gf117_gr_oclass; gf100_identify() 345 device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass; gf100_identify() 346 device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass; gf100_identify() 347 device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; gf100_identify() 348 device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass; gf100_identify() 349 device->oclass[NVDEV_ENGINE_DISP ] = gf110_disp_oclass; gf100_identify() 350 device->oclass[NVDEV_ENGINE_PM ] = &gf100_pm_oclass; gf100_identify()
H A D	nv50.c	66 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; nv50_identify() 67 device->oclass[NVDEV_SUBDEV_GPIO ] = nv50_gpio_oclass; nv50_identify() 68 device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass; nv50_identify() 69 device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass; nv50_identify() 70 device->oclass[NVDEV_SUBDEV_CLK ] = nv50_clk_oclass; nv50_identify() 71 device->oclass[NVDEV_SUBDEV_THERM ] = &nv50_therm_oclass; nv50_identify() 72 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; nv50_identify() 73 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv50_devinit_oclass; nv50_identify() 74 device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass; nv50_identify() 75 device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass; nv50_identify() 76 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; nv50_identify() 77 device->oclass[NVDEV_SUBDEV_FB ] = nv50_fb_oclass; nv50_identify() 78 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; nv50_identify() 79 device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; nv50_identify() 80 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; nv50_identify() 81 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; nv50_identify() 82 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; nv50_identify() 83 device->oclass[NVDEV_ENGINE_FIFO ] = nv50_fifo_oclass; nv50_identify() 84 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; nv50_identify() 85 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; nv50_identify() 86 device->oclass[NVDEV_ENGINE_MPEG ] = &nv50_mpeg_oclass; nv50_identify() 87 device->oclass[NVDEV_ENGINE_DISP ] = nv50_disp_oclass; nv50_identify() 88 device->oclass[NVDEV_ENGINE_PM ] = nv50_pm_oclass; nv50_identify() 92 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; nv50_identify() 93 device->oclass[NVDEV_SUBDEV_GPIO ] = nv50_gpio_oclass; nv50_identify() 94 device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass; nv50_identify() 95 device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass; nv50_identify() 96 device->oclass[NVDEV_SUBDEV_CLK ] = g84_clk_oclass; nv50_identify() 97 device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass; nv50_identify() 98 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; nv50_identify() 99 device->oclass[NVDEV_SUBDEV_DEVINIT] = g84_devinit_oclass; nv50_identify() 100 device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass; nv50_identify() 101 device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass; nv50_identify() 102 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; nv50_identify() 103 device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass; nv50_identify() 104 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; nv50_identify() 105 device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; nv50_identify() 106 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; nv50_identify() 107 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; nv50_identify() 108 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; nv50_identify() 109 device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; nv50_identify() 110 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; nv50_identify() 111 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; nv50_identify() 112 device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass; nv50_identify() 113 device->oclass[NVDEV_ENGINE_VP ] = &g84_vp_oclass; nv50_identify() 114 device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass; nv50_identify() 115 device->oclass[NVDEV_ENGINE_BSP ] = &g84_bsp_oclass; nv50_identify() 116 device->oclass[NVDEV_ENGINE_DISP ] = g84_disp_oclass; nv50_identify() 117 device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; nv50_identify() 121 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; nv50_identify() 122 device->oclass[NVDEV_SUBDEV_GPIO ] = nv50_gpio_oclass; nv50_identify() 123 device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass; nv50_identify() 124 device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass; nv50_identify() 125 device->oclass[NVDEV_SUBDEV_CLK ] = g84_clk_oclass; nv50_identify() 126 device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass; nv50_identify() 127 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; nv50_identify() 128 device->oclass[NVDEV_SUBDEV_DEVINIT] = g84_devinit_oclass; nv50_identify() 129 device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass; nv50_identify() 130 device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass; nv50_identify() 131 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; nv50_identify() 132 device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass; nv50_identify() 133 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; nv50_identify() 134 device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; nv50_identify() 135 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; nv50_identify() 136 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; nv50_identify() 137 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; nv50_identify() 138 device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; nv50_identify() 139 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; nv50_identify() 140 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; nv50_identify() 141 device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass; nv50_identify() 142 device->oclass[NVDEV_ENGINE_VP ] = &g84_vp_oclass; nv50_identify() 143 device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass; nv50_identify() 144 device->oclass[NVDEV_ENGINE_BSP ] = &g84_bsp_oclass; nv50_identify() 145 device->oclass[NVDEV_ENGINE_DISP ] = g84_disp_oclass; nv50_identify() 146 device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; nv50_identify() 150 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; nv50_identify() 151 device->oclass[NVDEV_SUBDEV_GPIO ] = nv50_gpio_oclass; nv50_identify() 152 device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass; nv50_identify() 153 device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass; nv50_identify() 154 device->oclass[NVDEV_SUBDEV_CLK ] = g84_clk_oclass; nv50_identify() 155 device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass; nv50_identify() 156 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; nv50_identify() 157 device->oclass[NVDEV_SUBDEV_DEVINIT] = g84_devinit_oclass; nv50_identify() 158 device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass; nv50_identify() 159 device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass; nv50_identify() 160 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; nv50_identify() 161 device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass; nv50_identify() 162 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; nv50_identify() 163 device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; nv50_identify() 164 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; nv50_identify() 165 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; nv50_identify() 166 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; nv50_identify() 167 device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; nv50_identify() 168 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; nv50_identify() 169 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; nv50_identify() 170 device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass; nv50_identify() 171 device->oclass[NVDEV_ENGINE_VP ] = &g84_vp_oclass; nv50_identify() 172 device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass; nv50_identify() 173 device->oclass[NVDEV_ENGINE_BSP ] = &g84_bsp_oclass; nv50_identify() 174 device->oclass[NVDEV_ENGINE_DISP ] = g84_disp_oclass; nv50_identify() 175 device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; nv50_identify() 179 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; nv50_identify() 180 device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass; nv50_identify() 181 device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass; nv50_identify() 182 device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass; nv50_identify() 183 device->oclass[NVDEV_SUBDEV_CLK ] = g84_clk_oclass; nv50_identify() 184 device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass; nv50_identify() 185 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; nv50_identify() 186 device->oclass[NVDEV_SUBDEV_DEVINIT] = g84_devinit_oclass; nv50_identify() 187 device->oclass[NVDEV_SUBDEV_MC ] = g94_mc_oclass; nv50_identify() 188 device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass; nv50_identify() 189 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; nv50_identify() 190 device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass; nv50_identify() 191 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; nv50_identify() 192 device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; nv50_identify() 193 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; nv50_identify() 194 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; nv50_identify() 195 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; nv50_identify() 196 device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; nv50_identify() 197 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; nv50_identify() 198 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; nv50_identify() 199 device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass; nv50_identify() 200 device->oclass[NVDEV_ENGINE_VP ] = &g84_vp_oclass; nv50_identify() 201 device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass; nv50_identify() 202 device->oclass[NVDEV_ENGINE_BSP ] = &g84_bsp_oclass; nv50_identify() 203 device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass; nv50_identify() 204 device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; nv50_identify() 208 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; nv50_identify() 209 device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass; nv50_identify() 210 device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass; nv50_identify() 211 device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass; nv50_identify() 212 device->oclass[NVDEV_SUBDEV_CLK ] = g84_clk_oclass; nv50_identify() 213 device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass; nv50_identify() 214 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; nv50_identify() 215 device->oclass[NVDEV_SUBDEV_DEVINIT] = g84_devinit_oclass; nv50_identify() 216 device->oclass[NVDEV_SUBDEV_MC ] = g94_mc_oclass; nv50_identify() 217 device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass; nv50_identify() 218 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; nv50_identify() 219 device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass; nv50_identify() 220 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; nv50_identify() 221 device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; nv50_identify() 222 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; nv50_identify() 223 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; nv50_identify() 224 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; nv50_identify() 225 device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; nv50_identify() 226 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; nv50_identify() 227 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; nv50_identify() 228 device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass; nv50_identify() 229 device->oclass[NVDEV_ENGINE_VP ] = &g84_vp_oclass; nv50_identify() 230 device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass; nv50_identify() 231 device->oclass[NVDEV_ENGINE_BSP ] = &g84_bsp_oclass; nv50_identify() 232 device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass; nv50_identify() 233 device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; nv50_identify() 237 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; nv50_identify() 238 device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass; nv50_identify() 239 device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass; nv50_identify() 240 device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass; nv50_identify() 241 device->oclass[NVDEV_SUBDEV_CLK ] = g84_clk_oclass; nv50_identify() 242 device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass; nv50_identify() 243 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; nv50_identify() 244 device->oclass[NVDEV_SUBDEV_DEVINIT] = g98_devinit_oclass; nv50_identify() 245 device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass; nv50_identify() 246 device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass; nv50_identify() 247 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; nv50_identify() 248 device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass; nv50_identify() 249 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; nv50_identify() 250 device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; nv50_identify() 251 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; nv50_identify() 252 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; nv50_identify() 253 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; nv50_identify() 254 device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; nv50_identify() 255 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; nv50_identify() 256 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; nv50_identify() 257 device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass; nv50_identify() 258 device->oclass[NVDEV_ENGINE_SEC ] = &g98_sec_oclass; nv50_identify() 259 device->oclass[NVDEV_ENGINE_MSVLD ] = &g98_msvld_oclass; nv50_identify() 260 device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass; nv50_identify() 261 device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass; nv50_identify() 262 device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; nv50_identify() 266 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; nv50_identify() 267 device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass; nv50_identify() 268 device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass; nv50_identify() 269 device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass; nv50_identify() 270 device->oclass[NVDEV_SUBDEV_CLK ] = g84_clk_oclass; nv50_identify() 271 device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass; nv50_identify() 272 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; nv50_identify() 273 device->oclass[NVDEV_SUBDEV_DEVINIT] = g84_devinit_oclass; nv50_identify() 274 device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass; nv50_identify() 275 device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass; nv50_identify() 276 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; nv50_identify() 277 device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass; nv50_identify() 278 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; nv50_identify() 279 device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; nv50_identify() 280 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; nv50_identify() 281 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; nv50_identify() 282 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; nv50_identify() 283 device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; nv50_identify() 284 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; nv50_identify() 285 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; nv50_identify() 286 device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass; nv50_identify() 287 device->oclass[NVDEV_ENGINE_VP ] = &g84_vp_oclass; nv50_identify() 288 device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass; nv50_identify() 289 device->oclass[NVDEV_ENGINE_BSP ] = &g84_bsp_oclass; nv50_identify() 290 device->oclass[NVDEV_ENGINE_DISP ] = gt200_disp_oclass; nv50_identify() 291 device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; nv50_identify() 295 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; nv50_identify() 296 device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass; nv50_identify() 297 device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass; nv50_identify() 298 device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass; nv50_identify() 299 device->oclass[NVDEV_SUBDEV_CLK ] = mcp77_clk_oclass; nv50_identify() 300 device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass; nv50_identify() 301 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; nv50_identify() 302 device->oclass[NVDEV_SUBDEV_DEVINIT] = g98_devinit_oclass; nv50_identify() 303 device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass; nv50_identify() 304 device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass; nv50_identify() 305 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; nv50_identify() 306 device->oclass[NVDEV_SUBDEV_FB ] = mcp77_fb_oclass; nv50_identify() 307 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; nv50_identify() 308 device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; nv50_identify() 309 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; nv50_identify() 310 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; nv50_identify() 311 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; nv50_identify() 312 device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; nv50_identify() 313 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; nv50_identify() 314 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; nv50_identify() 315 device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass; nv50_identify() 316 device->oclass[NVDEV_ENGINE_SEC ] = &g98_sec_oclass; nv50_identify() 317 device->oclass[NVDEV_ENGINE_MSVLD ] = &g98_msvld_oclass; nv50_identify() 318 device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass; nv50_identify() 319 device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass; nv50_identify() 320 device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; nv50_identify() 324 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; nv50_identify() 325 device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass; nv50_identify() 326 device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass; nv50_identify() 327 device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass; nv50_identify() 328 device->oclass[NVDEV_SUBDEV_CLK ] = mcp77_clk_oclass; nv50_identify() 329 device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass; nv50_identify() 330 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; nv50_identify() 331 device->oclass[NVDEV_SUBDEV_DEVINIT] = g98_devinit_oclass; nv50_identify() 332 device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass; nv50_identify() 333 device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass; nv50_identify() 334 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; nv50_identify() 335 device->oclass[NVDEV_SUBDEV_FB ] = mcp77_fb_oclass; nv50_identify() 336 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; nv50_identify() 337 device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; nv50_identify() 338 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; nv50_identify() 339 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; nv50_identify() 340 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; nv50_identify() 341 device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; nv50_identify() 342 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; nv50_identify() 343 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; nv50_identify() 344 device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass; nv50_identify() 345 device->oclass[NVDEV_ENGINE_SEC ] = &g98_sec_oclass; nv50_identify() 346 device->oclass[NVDEV_ENGINE_MSVLD ] = &g98_msvld_oclass; nv50_identify() 347 device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass; nv50_identify() 348 device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass; nv50_identify() 349 device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; nv50_identify() 353 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; nv50_identify() 354 device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass; nv50_identify() 355 device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass; nv50_identify() 356 device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass; nv50_identify() 357 device->oclass[NVDEV_SUBDEV_CLK ] = &gt215_clk_oclass; nv50_identify() 358 device->oclass[NVDEV_SUBDEV_THERM ] = &gt215_therm_oclass; nv50_identify() 359 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; nv50_identify() 360 device->oclass[NVDEV_SUBDEV_DEVINIT] = gt215_devinit_oclass; nv50_identify() 361 device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass; nv50_identify() 362 device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass; nv50_identify() 363 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; nv50_identify() 364 device->oclass[NVDEV_SUBDEV_FB ] = gt215_fb_oclass; nv50_identify() 365 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; nv50_identify() 366 device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; nv50_identify() 367 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; nv50_identify() 368 device->oclass[NVDEV_SUBDEV_PMU ] = gt215_pmu_oclass; nv50_identify() 369 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; nv50_identify() 370 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; nv50_identify() 371 device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; nv50_identify() 372 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; nv50_identify() 373 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; nv50_identify() 374 device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass; nv50_identify() 375 device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass; nv50_identify() 376 device->oclass[NVDEV_ENGINE_MSVLD ] = &g98_msvld_oclass; nv50_identify() 377 device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass; nv50_identify() 378 device->oclass[NVDEV_ENGINE_CE0 ] = &gt215_ce_oclass; nv50_identify() 379 device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass; nv50_identify() 380 device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass; nv50_identify() 384 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; nv50_identify() 385 device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass; nv50_identify() 386 device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass; nv50_identify() 387 device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass; nv50_identify() 388 device->oclass[NVDEV_SUBDEV_CLK ] = &gt215_clk_oclass; nv50_identify() 389 device->oclass[NVDEV_SUBDEV_THERM ] = &gt215_therm_oclass; nv50_identify() 390 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; nv50_identify() 391 device->oclass[NVDEV_SUBDEV_DEVINIT] = gt215_devinit_oclass; nv50_identify() 392 device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass; nv50_identify() 393 device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass; nv50_identify() 394 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; nv50_identify() 395 device->oclass[NVDEV_SUBDEV_FB ] = gt215_fb_oclass; nv50_identify() 396 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; nv50_identify() 397 device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; nv50_identify() 398 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; nv50_identify() 399 device->oclass[NVDEV_SUBDEV_PMU ] = gt215_pmu_oclass; nv50_identify() 400 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; nv50_identify() 401 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; nv50_identify() 402 device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; nv50_identify() 403 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; nv50_identify() 404 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; nv50_identify() 405 device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass; nv50_identify() 406 device->oclass[NVDEV_ENGINE_MSVLD ] = &g98_msvld_oclass; nv50_identify() 407 device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass; nv50_identify() 408 device->oclass[NVDEV_ENGINE_CE0 ] = &gt215_ce_oclass; nv50_identify() 409 device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass; nv50_identify() 410 device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass; nv50_identify() 414 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; nv50_identify() 415 device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass; nv50_identify() 416 device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass; nv50_identify() 417 device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass; nv50_identify() 418 device->oclass[NVDEV_SUBDEV_CLK ] = &gt215_clk_oclass; nv50_identify() 419 device->oclass[NVDEV_SUBDEV_THERM ] = &gt215_therm_oclass; nv50_identify() 420 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; nv50_identify() 421 device->oclass[NVDEV_SUBDEV_DEVINIT] = gt215_devinit_oclass; nv50_identify() 422 device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass; nv50_identify() 423 device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass; nv50_identify() 424 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; nv50_identify() 425 device->oclass[NVDEV_SUBDEV_FB ] = gt215_fb_oclass; nv50_identify() 426 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; nv50_identify() 427 device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; nv50_identify() 428 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; nv50_identify() 429 device->oclass[NVDEV_SUBDEV_PMU ] = gt215_pmu_oclass; nv50_identify() 430 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; nv50_identify() 431 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; nv50_identify() 432 device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; nv50_identify() 433 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; nv50_identify() 434 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; nv50_identify() 435 device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass; nv50_identify() 436 device->oclass[NVDEV_ENGINE_MSVLD ] = &g98_msvld_oclass; nv50_identify() 437 device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass; nv50_identify() 438 device->oclass[NVDEV_ENGINE_CE0 ] = &gt215_ce_oclass; nv50_identify() 439 device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass; nv50_identify() 440 device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass; nv50_identify() 444 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; nv50_identify() 445 device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass; nv50_identify() 446 device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass; nv50_identify() 447 device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass; nv50_identify() 448 device->oclass[NVDEV_SUBDEV_CLK ] = &gt215_clk_oclass; nv50_identify() 449 device->oclass[NVDEV_SUBDEV_THERM ] = &gt215_therm_oclass; nv50_identify() 450 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; nv50_identify() 451 device->oclass[NVDEV_SUBDEV_DEVINIT] = mcp89_devinit_oclass; nv50_identify() 452 device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass; nv50_identify() 453 device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass; nv50_identify() 454 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; nv50_identify() 455 device->oclass[NVDEV_SUBDEV_FB ] = mcp89_fb_oclass; nv50_identify() 456 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; nv50_identify() 457 device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; nv50_identify() 458 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; nv50_identify() 459 device->oclass[NVDEV_SUBDEV_PMU ] = gt215_pmu_oclass; nv50_identify() 460 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; nv50_identify() 461 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; nv50_identify() 462 device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; nv50_identify() 463 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; nv50_identify() 464 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; nv50_identify() 465 device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass; nv50_identify() 466 device->oclass[NVDEV_ENGINE_MSVLD ] = &g98_msvld_oclass; nv50_identify() 467 device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass; nv50_identify() 468 device->oclass[NVDEV_ENGINE_CE0 ] = &gt215_ce_oclass; nv50_identify() 469 device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass; nv50_identify() 470 device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass; nv50_identify()
H A D	nv30.c	51 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; nv30_identify() 52 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; nv30_identify() 53 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; nv30_identify() 54 device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass; nv30_identify() 55 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass; nv30_identify() 56 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; nv30_identify() 57 device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; nv30_identify() 58 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; nv30_identify() 59 device->oclass[NVDEV_SUBDEV_FB ] = nv30_fb_oclass; nv30_identify() 60 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; nv30_identify() 61 device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; nv30_identify() 62 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; nv30_identify() 63 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; nv30_identify() 64 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; nv30_identify() 65 device->oclass[NVDEV_ENGINE_GR ] = &nv30_gr_oclass; nv30_identify() 66 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; nv30_identify() 70 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; nv30_identify() 71 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; nv30_identify() 72 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; nv30_identify() 73 device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass; nv30_identify() 74 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass; nv30_identify() 75 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; nv30_identify() 76 device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; nv30_identify() 77 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; nv30_identify() 78 device->oclass[NVDEV_SUBDEV_FB ] = nv35_fb_oclass; nv30_identify() 79 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; nv30_identify() 80 device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; nv30_identify() 81 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; nv30_identify() 82 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; nv30_identify() 83 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; nv30_identify() 84 device->oclass[NVDEV_ENGINE_GR ] = &nv35_gr_oclass; nv30_identify() 85 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; nv30_identify() 89 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; nv30_identify() 90 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; nv30_identify() 91 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; nv30_identify() 92 device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass; nv30_identify() 93 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass; nv30_identify() 94 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; nv30_identify() 95 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; nv30_identify() 96 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; nv30_identify() 97 device->oclass[NVDEV_SUBDEV_FB ] = nv30_fb_oclass; nv30_identify() 98 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; nv30_identify() 99 device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; nv30_identify() 100 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; nv30_identify() 101 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; nv30_identify() 102 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; nv30_identify() 103 device->oclass[NVDEV_ENGINE_GR ] = &nv30_gr_oclass; nv30_identify() 104 device->oclass[NVDEV_ENGINE_MPEG ] = &nv31_mpeg_oclass; nv30_identify() 105 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; nv30_identify() 109 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; nv30_identify() 110 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; nv30_identify() 111 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; nv30_identify() 112 device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass; nv30_identify() 113 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass; nv30_identify() 114 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; nv30_identify() 115 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; nv30_identify() 116 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; nv30_identify() 117 device->oclass[NVDEV_SUBDEV_FB ] = nv36_fb_oclass; nv30_identify() 118 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; nv30_identify() 119 device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; nv30_identify() 120 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; nv30_identify() 121 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; nv30_identify() 122 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; nv30_identify() 123 device->oclass[NVDEV_ENGINE_GR ] = &nv35_gr_oclass; nv30_identify() 124 device->oclass[NVDEV_ENGINE_MPEG ] = &nv31_mpeg_oclass; nv30_identify() 125 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; nv30_identify() 129 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; nv30_identify() 130 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; nv30_identify() 131 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; nv30_identify() 132 device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass; nv30_identify() 133 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass; nv30_identify() 134 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; nv30_identify() 135 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; nv30_identify() 136 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; nv30_identify() 137 device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; nv30_identify() 138 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; nv30_identify() 139 device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; nv30_identify() 140 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; nv30_identify() 141 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; nv30_identify() 142 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; nv30_identify() 143 device->oclass[NVDEV_ENGINE_GR ] = &nv34_gr_oclass; nv30_identify() 144 device->oclass[NVDEV_ENGINE_MPEG ] = &nv31_mpeg_oclass; nv30_identify() 145 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; nv30_identify()
H A D	nv10.c	50 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; nv10_identify() 51 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; nv10_identify() 52 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; nv10_identify() 53 device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass; nv10_identify() 54 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass; nv10_identify() 55 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; nv10_identify() 56 device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; nv10_identify() 57 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; nv10_identify() 58 device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; nv10_identify() 59 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; nv10_identify() 60 device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; nv10_identify() 61 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; nv10_identify() 62 device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; nv10_identify() 63 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; nv10_identify() 67 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; nv10_identify() 68 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; nv10_identify() 69 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; nv10_identify() 70 device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass; nv10_identify() 71 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass; nv10_identify() 72 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; nv10_identify() 73 device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; nv10_identify() 74 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; nv10_identify() 75 device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; nv10_identify() 76 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; nv10_identify() 77 device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; nv10_identify() 78 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; nv10_identify() 79 device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; nv10_identify() 80 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; nv10_identify() 81 device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; nv10_identify() 82 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; nv10_identify() 86 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; nv10_identify() 87 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; nv10_identify() 88 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; nv10_identify() 89 device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass; nv10_identify() 90 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass; nv10_identify() 91 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; nv10_identify() 92 device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; nv10_identify() 93 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; nv10_identify() 94 device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; nv10_identify() 95 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; nv10_identify() 96 device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; nv10_identify() 97 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; nv10_identify() 98 device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; nv10_identify() 99 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; nv10_identify() 100 device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; nv10_identify() 101 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; nv10_identify() 105 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; nv10_identify() 106 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; nv10_identify() 107 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; nv10_identify() 108 device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass; nv10_identify() 109 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; nv10_identify() 110 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; nv10_identify() 111 device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; nv10_identify() 112 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; nv10_identify() 113 device->oclass[NVDEV_SUBDEV_FB ] = nv1a_fb_oclass; nv10_identify() 114 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; nv10_identify() 115 device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; nv10_identify() 116 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; nv10_identify() 117 device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; nv10_identify() 118 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; nv10_identify() 119 device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; nv10_identify() 120 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; nv10_identify() 124 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; nv10_identify() 125 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; nv10_identify() 126 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; nv10_identify() 127 device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass; nv10_identify() 128 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass; nv10_identify() 129 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; nv10_identify() 130 device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; nv10_identify() 131 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; nv10_identify() 132 device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; nv10_identify() 133 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; nv10_identify() 134 device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; nv10_identify() 135 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; nv10_identify() 136 device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; nv10_identify() 137 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; nv10_identify() 138 device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; nv10_identify() 139 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; nv10_identify() 143 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; nv10_identify() 144 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; nv10_identify() 145 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; nv10_identify() 146 device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass; nv10_identify() 147 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass; nv10_identify() 148 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; nv10_identify() 149 device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; nv10_identify() 150 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; nv10_identify() 151 device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; nv10_identify() 152 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; nv10_identify() 153 device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; nv10_identify() 154 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; nv10_identify() 155 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; nv10_identify() 156 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; nv10_identify() 157 device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; nv10_identify() 158 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; nv10_identify() 162 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; nv10_identify() 163 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; nv10_identify() 164 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; nv10_identify() 165 device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass; nv10_identify() 166 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; nv10_identify() 167 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; nv10_identify() 168 device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; nv10_identify() 169 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; nv10_identify() 170 device->oclass[NVDEV_SUBDEV_FB ] = nv1a_fb_oclass; nv10_identify() 171 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; nv10_identify() 172 device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; nv10_identify() 173 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; nv10_identify() 174 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; nv10_identify() 175 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; nv10_identify() 176 device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; nv10_identify() 177 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; nv10_identify() 181 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; nv10_identify() 182 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; nv10_identify() 183 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; nv10_identify() 184 device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass; nv10_identify() 185 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass; nv10_identify() 186 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; nv10_identify() 187 device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; nv10_identify() 188 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; nv10_identify() 189 device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; nv10_identify() 190 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; nv10_identify() 191 device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; nv10_identify() 192 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; nv10_identify() 193 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; nv10_identify() 194 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; nv10_identify() 195 device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; nv10_identify() 196 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; nv10_identify()
H A D	nv20.c	51 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; nv20_identify() 52 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; nv20_identify() 53 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; nv20_identify() 54 device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass; nv20_identify() 55 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass; nv20_identify() 56 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; nv20_identify() 57 device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; nv20_identify() 58 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; nv20_identify() 59 device->oclass[NVDEV_SUBDEV_FB ] = nv20_fb_oclass; nv20_identify() 60 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; nv20_identify() 61 device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; nv20_identify() 62 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; nv20_identify() 63 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; nv20_identify() 64 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; nv20_identify() 65 device->oclass[NVDEV_ENGINE_GR ] = &nv20_gr_oclass; nv20_identify() 66 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; nv20_identify() 70 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; nv20_identify() 71 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; nv20_identify() 72 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; nv20_identify() 73 device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass; nv20_identify() 74 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass; nv20_identify() 75 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; nv20_identify() 76 device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; nv20_identify() 77 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; nv20_identify() 78 device->oclass[NVDEV_SUBDEV_FB ] = nv25_fb_oclass; nv20_identify() 79 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; nv20_identify() 80 device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; nv20_identify() 81 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; nv20_identify() 82 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; nv20_identify() 83 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; nv20_identify() 84 device->oclass[NVDEV_ENGINE_GR ] = &nv25_gr_oclass; nv20_identify() 85 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; nv20_identify() 89 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; nv20_identify() 90 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; nv20_identify() 91 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; nv20_identify() 92 device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass; nv20_identify() 93 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass; nv20_identify() 94 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; nv20_identify() 95 device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; nv20_identify() 96 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; nv20_identify() 97 device->oclass[NVDEV_SUBDEV_FB ] = nv25_fb_oclass; nv20_identify() 98 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; nv20_identify() 99 device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; nv20_identify() 100 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; nv20_identify() 101 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; nv20_identify() 102 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; nv20_identify() 103 device->oclass[NVDEV_ENGINE_GR ] = &nv25_gr_oclass; nv20_identify() 104 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; nv20_identify() 108 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; nv20_identify() 109 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; nv20_identify() 110 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; nv20_identify() 111 device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass; nv20_identify() 112 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass; nv20_identify() 113 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; nv20_identify() 114 device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; nv20_identify() 115 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; nv20_identify() 116 device->oclass[NVDEV_SUBDEV_FB ] = nv25_fb_oclass; nv20_identify() 117 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; nv20_identify() 118 device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; nv20_identify() 119 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; nv20_identify() 120 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; nv20_identify() 121 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; nv20_identify() 122 device->oclass[NVDEV_ENGINE_GR ] = &nv2a_gr_oclass; nv20_identify() 123 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; nv20_identify()
H A D	gm100.c	64 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; gm100_identify() 65 device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass; gm100_identify() 66 device->oclass[NVDEV_SUBDEV_I2C ] = gf110_i2c_oclass; gm100_identify() 67 device->oclass[NVDEV_SUBDEV_FUSE ] = &gm107_fuse_oclass; gm100_identify() 68 device->oclass[NVDEV_SUBDEV_CLK ] = &gk104_clk_oclass; gm100_identify() 69 device->oclass[NVDEV_SUBDEV_THERM ] = &gm107_therm_oclass; gm100_identify() 70 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; gm100_identify() 71 device->oclass[NVDEV_SUBDEV_DEVINIT] = gm107_devinit_oclass; gm100_identify() 72 device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass; gm100_identify() 73 device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; gm100_identify() 74 device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass; gm100_identify() 75 device->oclass[NVDEV_SUBDEV_FB ] = gm107_fb_oclass; gm100_identify() 76 device->oclass[NVDEV_SUBDEV_LTC ] = gm107_ltc_oclass; gm100_identify() 77 device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass; gm100_identify() 78 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; gm100_identify() 79 device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; gm100_identify() 80 device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; gm100_identify() 81 device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass; gm100_identify() 84 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; gm100_identify() 86 device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; gm100_identify() 87 device->oclass[NVDEV_ENGINE_FIFO ] = gk208_fifo_oclass; gm100_identify() 88 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; gm100_identify() 89 device->oclass[NVDEV_ENGINE_GR ] = gm107_gr_oclass; gm100_identify() 90 device->oclass[NVDEV_ENGINE_DISP ] = gm107_disp_oclass; gm100_identify() 91 device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass; gm100_identify() 93 device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass; gm100_identify() 95 device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass; gm100_identify() 97 device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass; gm100_identify() 98 device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass; gm100_identify() 99 device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; gm100_identify() 104 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; gm100_identify() 105 device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass; gm100_identify() 106 device->oclass[NVDEV_SUBDEV_I2C ] = gm204_i2c_oclass; gm100_identify() 107 device->oclass[NVDEV_SUBDEV_FUSE ] = &gm107_fuse_oclass; gm100_identify() 110 device->oclass[NVDEV_SUBDEV_CLK ] = &gk104_clk_oclass; gm100_identify() 112 device->oclass[NVDEV_SUBDEV_THERM ] = &gm107_therm_oclass; gm100_identify() 114 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; gm100_identify() 115 device->oclass[NVDEV_SUBDEV_DEVINIT] = gm204_devinit_oclass; gm100_identify() 116 device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass; gm100_identify() 117 device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; gm100_identify() 118 device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass; gm100_identify() 119 device->oclass[NVDEV_SUBDEV_FB ] = gm107_fb_oclass; gm100_identify() 120 device->oclass[NVDEV_SUBDEV_LTC ] = gm107_ltc_oclass; gm100_identify() 121 device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass; gm100_identify() 122 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; gm100_identify() 123 device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; gm100_identify() 124 device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; gm100_identify() 125 device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass; gm100_identify() 127 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; gm100_identify() 129 device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; gm100_identify() 130 device->oclass[NVDEV_ENGINE_FIFO ] = gm204_fifo_oclass; gm100_identify() 131 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; gm100_identify() 132 device->oclass[NVDEV_ENGINE_GR ] = gm204_gr_oclass; gm100_identify() 133 device->oclass[NVDEV_ENGINE_DISP ] = gm204_disp_oclass; gm100_identify() 134 device->oclass[NVDEV_ENGINE_CE0 ] = &gm204_ce0_oclass; gm100_identify() 135 device->oclass[NVDEV_ENGINE_CE1 ] = &gm204_ce1_oclass; gm100_identify() 136 device->oclass[NVDEV_ENGINE_CE2 ] = &gm204_ce2_oclass; gm100_identify() 138 device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass; gm100_identify() 139 device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass; gm100_identify() 140 device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; gm100_identify() 145 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; gm100_identify() 146 device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass; gm100_identify() 147 device->oclass[NVDEV_SUBDEV_I2C ] = gm204_i2c_oclass; gm100_identify() 148 device->oclass[NVDEV_SUBDEV_FUSE ] = &gm107_fuse_oclass; gm100_identify() 151 device->oclass[NVDEV_SUBDEV_CLK ] = &gk104_clk_oclass; gm100_identify() 153 device->oclass[NVDEV_SUBDEV_THERM ] = &gm107_therm_oclass; gm100_identify() 155 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; gm100_identify() 156 device->oclass[NVDEV_SUBDEV_DEVINIT] = gm204_devinit_oclass; gm100_identify() 157 device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass; gm100_identify() 158 device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; gm100_identify() 159 device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass; gm100_identify() 160 device->oclass[NVDEV_SUBDEV_FB ] = gm107_fb_oclass; gm100_identify() 161 device->oclass[NVDEV_SUBDEV_LTC ] = gm107_ltc_oclass; gm100_identify() 162 device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass; gm100_identify() 163 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; gm100_identify() 164 device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; gm100_identify() 165 device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; gm100_identify() 166 device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass; gm100_identify() 168 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; gm100_identify() 170 device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; gm100_identify() 171 device->oclass[NVDEV_ENGINE_FIFO ] = gm204_fifo_oclass; gm100_identify() 172 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; gm100_identify() 173 device->oclass[NVDEV_ENGINE_GR ] = gm206_gr_oclass; gm100_identify() 174 device->oclass[NVDEV_ENGINE_DISP ] = gm204_disp_oclass; gm100_identify() 175 device->oclass[NVDEV_ENGINE_CE0 ] = &gm204_ce0_oclass; gm100_identify() 176 device->oclass[NVDEV_ENGINE_CE1 ] = &gm204_ce1_oclass; gm100_identify() 177 device->oclass[NVDEV_ENGINE_CE2 ] = &gm204_ce2_oclass; gm100_identify() 179 device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass; gm100_identify() 180 device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass; gm100_identify() 181 device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; gm100_identify()
H A D	nv04.c	49 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; nv04_identify() 50 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; nv04_identify() 51 device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass; nv04_identify() 52 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv04_devinit_oclass; nv04_identify() 53 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; nv04_identify() 54 device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; nv04_identify() 55 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; nv04_identify() 56 device->oclass[NVDEV_SUBDEV_FB ] = nv04_fb_oclass; nv04_identify() 57 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; nv04_identify() 58 device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; nv04_identify() 59 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; nv04_identify() 60 device->oclass[NVDEV_ENGINE_FIFO ] = nv04_fifo_oclass; nv04_identify() 61 device->oclass[NVDEV_ENGINE_SW ] = nv04_sw_oclass; nv04_identify() 62 device->oclass[NVDEV_ENGINE_GR ] = &nv04_gr_oclass; nv04_identify() 63 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; nv04_identify() 67 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; nv04_identify() 68 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; nv04_identify() 69 device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass; nv04_identify() 70 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv05_devinit_oclass; nv04_identify() 71 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; nv04_identify() 72 device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; nv04_identify() 73 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; nv04_identify() 74 device->oclass[NVDEV_SUBDEV_FB ] = nv04_fb_oclass; nv04_identify() 75 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; nv04_identify() 76 device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; nv04_identify() 77 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; nv04_identify() 78 device->oclass[NVDEV_ENGINE_FIFO ] = nv04_fifo_oclass; nv04_identify() 79 device->oclass[NVDEV_ENGINE_SW ] = nv04_sw_oclass; nv04_identify() 80 device->oclass[NVDEV_ENGINE_GR ] = &nv04_gr_oclass; nv04_identify() 81 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; nv04_identify()
H A D	base.c	283 struct nvkm_oclass *oclass, void *data, u32 size, 308 oclass = &nvkm_devobj_oclass_super; 318 ret = nvkm_parent_create(parent, nv_object(device), oclass, 0, 444 device->oclass[NVDEV_SUBDEV_VBIOS] = &nvkm_bios_oclass; 458 if (!(oclass = device->oclass[i]) || (disable & (1ULL << i))) 466 ret = nvkm_object_ctor(nv_object(device), NULL, oclass, 282 nvkm_devobj_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nvkm_devobj_ctor() argument
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/core/
H A D	parent.c	35 struct nvkm_oclass *oclass; nvkm_parent_sclass() local 40 if ((sclass->oclass->handle & 0xffff) == handle) { nvkm_parent_sclass() 42 *poclass = sclass->oclass; nvkm_parent_sclass() 59 oclass = engine->sclass; nvkm_parent_sclass() 60 while (oclass->ofuncs) { nvkm_parent_sclass() 61 if ((oclass->handle & 0xffff) == handle) { nvkm_parent_sclass() 63 *poclass = oclass; nvkm_parent_sclass() 66 oclass++; nvkm_parent_sclass() 81 struct nvkm_oclass *oclass; nvkm_parent_lclass() local 88 lclass[nr] = sclass->oclass->handle & 0xffff; nvkm_parent_lclass() 95 if (engine && (oclass = engine->sclass)) { nvkm_parent_lclass() 96 while (oclass->ofuncs) { nvkm_parent_lclass() 98 lclass[nr] = oclass->handle & 0xffff; nvkm_parent_lclass() 99 oclass++; nvkm_parent_lclass() 111 struct nvkm_oclass *oclass, u32 pclass, nvkm_parent_create_() 119 ret = nvkm_object_create_(parent, engine, oclass, pclass | nvkm_parent_create_() 133 nclass->oclass = sclass; nvkm_parent_create_() 110 nvkm_parent_create_(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, u32 pclass, struct nvkm_oclass *sclass, u64 engcls, int size, void **pobject) nvkm_parent_create_() argument
H A D	namedb.c	42 nvkm_namedb_lookup_class(struct nvkm_namedb *namedb, u16 oclass) nvkm_namedb_lookup_class() argument 47 if (nv_mclass(handle->object) == oclass) nvkm_namedb_lookup_class() 125 nvkm_namedb_get_class(struct nvkm_namedb *namedb, u16 oclass) nvkm_namedb_get_class() argument 129 handle = nvkm_namedb_lookup_class(namedb, oclass); nvkm_namedb_get_class() 166 struct nvkm_oclass *oclass, u32 pclass, nvkm_namedb_create_() 173 ret = nvkm_parent_create_(parent, engine, oclass, pclass | nvkm_namedb_create_() 187 struct nvkm_oclass *oclass, void *data, u32 size, _nvkm_namedb_ctor() 193 ret = nvkm_namedb_create(parent, engine, oclass, 0, NULL, 0, &object); _nvkm_namedb_ctor() 165 nvkm_namedb_create_(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, u32 pclass, struct nvkm_oclass *sclass, u64 engcls, int length, void **pobject) nvkm_namedb_create_() argument 186 _nvkm_namedb_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) _nvkm_namedb_ctor() argument
H A D	object.c	34 struct nvkm_oclass *oclass, u32 pclass, nvkm_object_create_() 45 object->oclass = oclass; nvkm_object_create_() 46 object->oclass->handle |= pclass; nvkm_object_create_() 61 struct nvkm_oclass *oclass, void *data, u32 size, _nvkm_object_ctor() 66 return nvkm_object_create(parent, engine, oclass, 0, pobject); _nvkm_object_ctor() 104 struct nvkm_oclass *oclass, void *data, u32 size, nvkm_object_ctor() 107 struct nvkm_ofuncs *ofuncs = oclass->ofuncs; nvkm_object_ctor() 111 ret = ofuncs->ctor(parent, engine, oclass, data, size, &object); nvkm_object_ctor() 116 oclass->handle, ret); nvkm_object_ctor() 33 nvkm_object_create_(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, u32 pclass, int size, void **pobject) nvkm_object_create_() argument 60 _nvkm_object_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) _nvkm_object_ctor() argument 103 nvkm_object_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nvkm_object_ctor() argument
H A D	subdev.c	97 struct nvkm_oclass *oclass, u32 pclass, nvkm_subdev_create_() 104 ret = nvkm_object_create_(parent, engine, oclass, pclass | nvkm_subdev_create_() 110 __mutex_init(&subdev->mutex, subname, &oclass->lock_class_key); nvkm_subdev_create_() 96 nvkm_subdev_create_(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, u32 pclass, const char *subname, const char *sysname, int size, void **pobject) nvkm_subdev_create_() argument
H A D	ioctl.c	68 if (size == args->v0.count * sizeof(args->v0.oclass[0])) { nvkm_ioctl_sclass() 69 ret = nvkm_parent_lclass(object, args->v0.oclass, nvkm_ioctl_sclass() 94 struct nvkm_oclass *oclass; nvkm_ioctl_new() local 101 _oclass = args->v0.oclass; nvkm_ioctl_new() 119 ret = nvkm_parent_sclass(&parent->object, _oclass, &engine, &oclass); nvkm_ioctl_new() 149 ret = nvkm_object_ctor(engctx, engine, oclass, data, size, &object); nvkm_ioctl_new() 205 struct nvkm_ofuncs *ofuncs = object->oclass->ofuncs; nvkm_ioctl_mthd() 227 struct nvkm_ofuncs *ofuncs = object->oclass->ofuncs; nvkm_ioctl_rd() 269 struct nvkm_ofuncs *ofuncs = object->oclass->ofuncs; nvkm_ioctl_wr() 312 struct nvkm_ofuncs *ofuncs = object->oclass->ofuncs; nvkm_ioctl_map() 351 struct nvkm_ofuncs *ofuncs = object->oclass->ofuncs; nvkm_ioctl_ntfy_new()
H A D	engine.c	39 struct nvkm_oclass *oclass, bool enable, nvkm_engine_create_() 46 ret = nvkm_subdev_create_(parent, engobj, oclass, NV_ENGINE_CLASS, nvkm_engine_create_() 38 nvkm_engine_create_(struct nvkm_object *parent, struct nvkm_object *engobj, struct nvkm_oclass *oclass, bool enable, const char *iname, const char *fname, int length, void **pobject) nvkm_engine_create_() argument
H A D	engctx.c	49 struct nvkm_oclass *oclass, struct nvkm_object *pargpu, nvkm_engctx_create_() 71 ret = nvkm_gpuobj_create_(parent, engobj, oclass, nvkm_engctx_create_() 75 ret = nvkm_object_create_(parent, engobj, oclass, nvkm_engctx_create_() 184 struct nvkm_oclass *oclass, void *data, u32 size, _nvkm_engctx_ctor() 190 ret = nvkm_engctx_create(parent, engine, oclass, NULL, 256, 256, _nvkm_engctx_ctor() 48 nvkm_engctx_create_(struct nvkm_object *parent, struct nvkm_object *engobj, struct nvkm_oclass *oclass, struct nvkm_object *pargpu, u32 size, u32 align, u32 flags, int length, void **pobject) nvkm_engctx_create_() argument 183 _nvkm_engctx_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) _nvkm_engctx_ctor() argument
H A D	gpuobj.c	52 struct nvkm_oclass *oclass, u32 pclass, nvkm_gpuobj_create_() 100 ret = nvkm_object_create_(parent, engine, oclass, pclass | nvkm_gpuobj_create_() 144 struct nvkm_oclass *oclass, void *data, u32 size, _nvkm_gpuobj_ctor() 151 ret = nvkm_gpuobj_create(parent, engine, oclass, 0, args->pargpu, _nvkm_gpuobj_ctor() 51 nvkm_gpuobj_create_(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, u32 pclass, struct nvkm_object *pargpu, u32 size, u32 align, u32 flags, int length, void **pobject) nvkm_gpuobj_create_() argument 143 _nvkm_gpuobj_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) _nvkm_gpuobj_ctor() argument
H A D	handle.c	190 nvkm_handle_get_class(struct nvkm_object *engctx, u16 oclass) nvkm_handle_get_class() argument 194 return nvkm_namedb_get_class(namedb, oclass); nvkm_handle_get_class()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvif/
H A D	object.c	54 nvif_object_sclass(struct nvif_object *object, u32 *oclass, int count) nvif_object_sclass() argument 60 u32 size = count * sizeof(args->sclass.oclass[0]); nvif_object_sclass() 70 memcpy(args->sclass.oclass, oclass, size); nvif_object_sclass() 73 memcpy(oclass, args->sclass.oclass, size); nvif_object_sclass() 219 u32 handle, u32 oclass, void *data, u32 size, nvif_object_init() 230 object->oclass = oclass; nvif_object_init() 252 ctor->new.oclass = oclass; nvif_object_init() 271 nvif_object_new(struct nvif_object *parent, u32 handle, u32 oclass, nvif_object_new() argument 277 oclass, data, size, object); nvif_object_new() 218 nvif_object_init(struct nvif_object *parent, void (*dtor)(struct nvif_object *), u32 handle, u32 oclass, void *data, u32 size, struct nvif_object *object) nvif_object_init() argument
H A D	device.c	35 u32 handle, u32 oclass, void *data, u32 size, nvif_device_init() 38 int ret = nvif_object_init(parent, (void *)dtor, handle, oclass, nvif_device_init() 57 nvif_device_new(struct nvif_object *parent, u32 handle, u32 oclass, nvif_device_new() argument 63 oclass, data, size, device); nvif_device_new() 34 nvif_device_init(struct nvif_object *parent, void (*dtor)(struct nvif_device *), u32 handle, u32 oclass, void *data, u32 size, struct nvif_device *device) nvif_device_init() argument
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/gr/
H A D	nv2a.c	12 struct nvkm_oclass *oclass, void *data, u32 size, nv2a_gr_context_ctor() 18 ret = nvkm_gr_context_create(parent, engine, oclass, NULL, 0x36b0, nv2a_gr_context_ctor() 92 struct nvkm_oclass *oclass, void *data, u32 size, nv2a_gr_ctor() 98 ret = nvkm_gr_create(parent, engine, oclass, true, &priv); nv2a_gr_ctor() 11 nv2a_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv2a_gr_context_ctor() argument 91 nv2a_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv2a_gr_ctor() argument
H A D	ctxgf117.c	222 struct gf100_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass; gf117_grctx_generate_main() local 227 gf100_gr_mmio(priv, oclass->hub); gf117_grctx_generate_main() 228 gf100_gr_mmio(priv, oclass->gpc); gf117_grctx_generate_main() 229 gf100_gr_mmio(priv, oclass->zcull); gf117_grctx_generate_main() 230 gf100_gr_mmio(priv, oclass->tpc); gf117_grctx_generate_main() 231 gf100_gr_mmio(priv, oclass->ppc); gf117_grctx_generate_main() 235 oclass->bundle(info); gf117_grctx_generate_main() 236 oclass->pagepool(info); gf117_grctx_generate_main() 237 oclass->attrib(info); gf117_grctx_generate_main() 238 oclass->unkn(priv); gf117_grctx_generate_main() 249 gf100_gr_icmd(priv, oclass->icmd); gf117_grctx_generate_main() 251 gf100_gr_mthd(priv, oclass->mthd); gf117_grctx_generate_main()
H A D	nv25.c	36 struct nvkm_oclass *oclass, void *data, u32 size, nv25_gr_context_ctor() 42 ret = nvkm_gr_context_create(parent, engine, oclass, NULL, 0x3724, nv25_gr_context_ctor() 125 struct nvkm_oclass *oclass, void *data, u32 size, nv25_gr_ctor() 131 ret = nvkm_gr_create(parent, engine, oclass, true, &priv); nv25_gr_ctor() 35 nv25_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv25_gr_context_ctor() argument 124 nv25_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv25_gr_ctor() argument
H A D	nv34.c	38 struct nvkm_oclass *oclass, void *data, u32 size, nv34_gr_context_ctor() 44 ret = nvkm_gr_context_create(parent, engine, oclass, NULL, 0x46dc, nv34_gr_context_ctor() 126 struct nvkm_oclass *oclass, void *data, u32 size, nv34_gr_ctor() 132 ret = nvkm_gr_create(parent, engine, oclass, true, &priv); nv34_gr_ctor() 37 nv34_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv34_gr_context_ctor() argument 125 nv34_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv34_gr_ctor() argument
H A D	nv35.c	38 struct nvkm_oclass *oclass, void *data, u32 size, nv35_gr_context_ctor() 44 ret = nvkm_gr_context_create(parent, engine, oclass, NULL, 0x577c, nv35_gr_context_ctor() 126 struct nvkm_oclass *oclass, void *data, u32 size, nv35_gr_ctor() 132 ret = nvkm_gr_create(parent, engine, oclass, true, &priv); nv35_gr_ctor() 37 nv35_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv35_gr_context_ctor() argument 125 nv35_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv35_gr_ctor() argument
H A D	gk104.c	198 struct gf100_gr_oclass *oclass = (void *)object->oclass; gk104_gr_init() local 223 gf100_gr_mmio(priv, oclass->mmio); gk104_gr_init() 315 struct nvkm_oclass *oclass, void *data, u32 size, gk104_gr_ctor() 321 return gf100_gr_ctor(parent, engine, oclass, data, size, pobject); gk104_gr_ctor() 314 gk104_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) gk104_gr_ctor() argument
H A D	gf100.c	276 struct nvkm_oclass *oclass, void *args, u32 size, gf100_gr_context_ctor() 287 ret = nvkm_gr_context_create(parent, engine, oclass, NULL, gf100_gr_context_ctor() 1261 struct gf100_gr_oclass *oclass = (void *)nv_object(priv)->oclass; gf100_gr_init_ctxctl() local 1354 if (!oclass->fecs.ucode) { gf100_gr_init_ctxctl() 1361 for (i = 0; i < oclass->fecs.ucode->data.size / 4; i++) gf100_gr_init_ctxctl() 1362 nv_wr32(priv, 0x4091c4, oclass->fecs.ucode->data.data[i]); gf100_gr_init_ctxctl() 1365 for (i = 0; i < oclass->fecs.ucode->code.size / 4; i++) { gf100_gr_init_ctxctl() 1368 nv_wr32(priv, 0x409184, oclass->fecs.ucode->code.data[i]); gf100_gr_init_ctxctl() 1373 for (i = 0; i < oclass->gpccs.ucode->data.size / 4; i++) gf100_gr_init_ctxctl() 1374 nv_wr32(priv, 0x41a1c4, oclass->gpccs.ucode->data.data[i]); gf100_gr_init_ctxctl() 1377 for (i = 0; i < oclass->gpccs.ucode->code.size / 4; i++) { gf100_gr_init_ctxctl() 1380 nv_wr32(priv, 0x41a184, oclass->gpccs.ucode->code.data[i]); gf100_gr_init_ctxctl() 1414 struct gf100_gr_oclass *oclass = (void *)object->oclass; gf100_gr_init() local 1435 gf100_gr_mmio(priv, oclass->mmio); gf100_gr_init() 1579 struct gf100_gr_oclass *oclass = (void *)bclass; gf100_gr_ctor() local 1586 oclass->fecs.ucode == NULL); gf100_gr_ctor() 1587 enable = use_ext_fw || oclass->fecs.ucode != NULL; gf100_gr_ctor() 1629 priv->ppc_nr[i] = oclass->ppc_nr; gf100_gr_ctor() 1673 nv_engine(priv)->cclass = *oclass->cclass; gf100_gr_ctor() 1674 nv_engine(priv)->sclass = oclass->sclass; gf100_gr_ctor() 275 gf100_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *args, u32 size, struct nvkm_object **pobject) gf100_gr_context_ctor() argument
H A D	nv30.c	40 struct nvkm_oclass *oclass, void *data, u32 size, nv30_gr_context_ctor() 46 ret = nvkm_gr_context_create(parent, engine, oclass, NULL, 0x5f48, nv30_gr_context_ctor() 128 struct nvkm_oclass *oclass, void *data, u32 size, nv30_gr_ctor() 134 ret = nvkm_gr_create(parent, engine, oclass, true, &priv); nv30_gr_ctor() 39 nv30_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv30_gr_context_ctor() argument 127 nv30_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv30_gr_ctor() argument
H A D	ctxgf100.c	1234 struct gf100_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass; gf100_grctx_generate_main() local 1238 gf100_gr_mmio(priv, oclass->hub); gf100_grctx_generate_main() 1239 gf100_gr_mmio(priv, oclass->gpc); gf100_grctx_generate_main() 1240 gf100_gr_mmio(priv, oclass->zcull); gf100_grctx_generate_main() 1241 gf100_gr_mmio(priv, oclass->tpc); gf100_grctx_generate_main() 1242 gf100_gr_mmio(priv, oclass->ppc); gf100_grctx_generate_main() 1246 oclass->bundle(info); gf100_grctx_generate_main() 1247 oclass->pagepool(info); gf100_grctx_generate_main() 1248 oclass->attrib(info); gf100_grctx_generate_main() 1249 oclass->unkn(priv); gf100_grctx_generate_main() 1257 gf100_gr_icmd(priv, oclass->icmd); gf100_grctx_generate_main() 1259 gf100_gr_mthd(priv, oclass->mthd); gf100_grctx_generate_main() 1266 struct gf100_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass; gf100_grctx_generate() local 1337 oclass->main(priv, &info); gf100_grctx_generate()
H A D	nv40.c	56 struct nvkm_oclass *oclass, void *data, u32 size, nv40_gr_object_ctor() 62 ret = nvkm_gpuobj_create(parent, engine, oclass, 0, parent, nv40_gr_object_ctor() 137 struct nvkm_oclass *oclass, void *data, u32 size, nv40_gr_context_ctor() 144 ret = nvkm_gr_context_create(parent, engine, oclass, NULL, priv->size, nv40_gr_context_ctor() 341 struct nvkm_oclass *oclass, void *data, u32 size, nv40_gr_ctor() 347 ret = nvkm_gr_create(parent, engine, oclass, true, &priv); nv40_gr_ctor() 55 nv40_gr_object_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv40_gr_object_ctor() argument 136 nv40_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv40_gr_context_ctor() argument 340 nv40_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv40_gr_ctor() argument
H A D	nv20.c	41 struct nvkm_oclass *oclass, void *data, u32 size, nv20_gr_context_ctor() 47 ret = nvkm_gr_context_create(parent, engine, oclass, NULL, 0x37f0, nv20_gr_context_ctor() 238 struct nvkm_oclass *oclass, void *data, u32 size, nv20_gr_ctor() 244 ret = nvkm_gr_create(parent, engine, oclass, true, &priv); nv20_gr_ctor() 40 nv20_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv20_gr_context_ctor() argument 237 nv20_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv20_gr_ctor() argument
H A D	ctxgk104.c	954 struct gf100_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass; gk104_grctx_generate_main() local 959 gf100_gr_mmio(priv, oclass->hub); gk104_grctx_generate_main() 960 gf100_gr_mmio(priv, oclass->gpc); gk104_grctx_generate_main() 961 gf100_gr_mmio(priv, oclass->zcull); gk104_grctx_generate_main() 962 gf100_gr_mmio(priv, oclass->tpc); gk104_grctx_generate_main() 963 gf100_gr_mmio(priv, oclass->ppc); gk104_grctx_generate_main() 967 oclass->bundle(info); gk104_grctx_generate_main() 968 oclass->pagepool(info); gk104_grctx_generate_main() 969 oclass->attrib(info); gk104_grctx_generate_main() 970 oclass->unkn(priv); gk104_grctx_generate_main() 984 gf100_gr_icmd(priv, oclass->icmd); gk104_grctx_generate_main() 986 gf100_gr_mthd(priv, oclass->mthd); gk104_grctx_generate_main()
H A D	ctxgm107.c	957 struct gf100_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass; gm107_grctx_generate_main() local 960 gf100_gr_mmio(priv, oclass->hub); gm107_grctx_generate_main() 961 gf100_gr_mmio(priv, oclass->gpc); gm107_grctx_generate_main() 962 gf100_gr_mmio(priv, oclass->zcull); gm107_grctx_generate_main() 963 gf100_gr_mmio(priv, oclass->tpc); gm107_grctx_generate_main() 964 gf100_gr_mmio(priv, oclass->ppc); gm107_grctx_generate_main() 968 oclass->bundle(info); gm107_grctx_generate_main() 969 oclass->pagepool(info); gm107_grctx_generate_main() 970 oclass->attrib(info); gm107_grctx_generate_main() 971 oclass->unkn(priv); gm107_grctx_generate_main() 987 gf100_gr_icmd(priv, oclass->icmd); gm107_grctx_generate_main() 989 gf100_gr_mthd(priv, oclass->mthd); gm107_grctx_generate_main()
H A D	ctxgm204.c	980 struct gf100_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass; gm204_grctx_generate_main() local 984 gf100_gr_mmio(priv, oclass->hub); gm204_grctx_generate_main() 985 gf100_gr_mmio(priv, oclass->gpc); gm204_grctx_generate_main() 986 gf100_gr_mmio(priv, oclass->zcull); gm204_grctx_generate_main() 987 gf100_gr_mmio(priv, oclass->tpc); gm204_grctx_generate_main() 988 gf100_gr_mmio(priv, oclass->ppc); gm204_grctx_generate_main() 992 oclass->bundle(info); gm204_grctx_generate_main() 993 oclass->pagepool(info); gm204_grctx_generate_main() 994 oclass->attrib(info); gm204_grctx_generate_main() 995 oclass->unkn(priv); gm204_grctx_generate_main() 1015 gf100_gr_icmd(priv, oclass->icmd); gm204_grctx_generate_main() 1017 gf100_gr_mthd(priv, oclass->mthd); gm204_grctx_generate_main()
H A D	nv50.c	56 struct nvkm_oclass *oclass, void *data, u32 size, nv50_gr_object_ctor() 62 ret = nvkm_gpuobj_create(parent, engine, oclass, 0, parent, nv50_gr_object_ctor() 143 struct nvkm_oclass *oclass, void *data, u32 size, nv50_gr_context_ctor() 150 ret = nvkm_gr_context_create(parent, engine, oclass, NULL, priv->size, nv50_gr_context_ctor() 850 struct nvkm_oclass *oclass, void *data, u32 size, nv50_gr_ctor() 856 ret = nvkm_gr_create(parent, engine, oclass, true, &priv); nv50_gr_ctor() 55 nv50_gr_object_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv50_gr_object_ctor() argument 142 nv50_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv50_gr_context_ctor() argument 849 nv50_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv50_gr_ctor() argument
H A D	gm107.c	325 struct gf100_gr_oclass *oclass = (void *)object->oclass; gm107_gr_init() local 343 gf100_gr_mmio(priv, oclass->mmio); gm107_gr_init()
H A D	gm204.c	254 struct gf100_gr_oclass *oclass = (void *)object->oclass; gm204_gr_init() local 280 gf100_gr_mmio(priv, oclass->mmio); gm204_gr_init()
H A D	nv04.c	952 struct nvkm_oclass *oclass, void *data, u32 size, nv04_gr_object_ctor() 958 ret = nvkm_gpuobj_create(parent, engine, oclass, 0, parent, nv04_gr_object_ctor() 1115 struct nvkm_oclass *oclass, void *data, u32 size, nv04_gr_context_ctor() 1124 ret = nvkm_object_create(parent, engine, oclass, 0, &chan); nv04_gr_context_ctor() 1312 struct nvkm_oclass *oclass, void *data, u32 size, nv04_gr_ctor() 1318 ret = nvkm_gr_create(parent, engine, oclass, true, &priv); nv04_gr_ctor() 951 nv04_gr_object_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv04_gr_object_ctor() argument 1113 nv04_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv04_gr_context_ctor() argument 1311 nv04_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv04_gr_ctor() argument
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/
H A D	pad.c	47 struct nvkm_oclass *oclass, int index, nvkm_i2c_pad_create_() 64 ret = nvkm_object_create_(parent, engine, oclass, 0, size, pobject); nvkm_i2c_pad_create_() 75 struct nvkm_oclass *oclass, void *data, u32 index, _nvkm_i2c_pad_ctor() 80 ret = nvkm_i2c_pad_create(parent, engine, oclass, index, &pad); _nvkm_i2c_pad_ctor() 45 nvkm_i2c_pad_create_(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, int index, int size, void **pobject) nvkm_i2c_pad_create_() argument 74 _nvkm_i2c_pad_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 index, struct nvkm_object **pobject) _nvkm_i2c_pad_ctor() argument
H A D	base.c	110 struct nvkm_oclass *oclass, u8 index, nvkm_i2c_port_create_() 120 ret = nvkm_object_create_(parent, engine, oclass, 0, size, pobject); nvkm_i2c_port_create_() 329 const struct nvkm_i2c_impl *impl = (void *)nv_object(i2c)->oclass; nvkm_i2c_intr_fini() 339 const struct nvkm_i2c_impl *impl = (void *)nv_object(i2c)->oclass; nvkm_i2c_intr_init() 476 struct nvkm_oclass *oclass; nvkm_i2c_create_port() local 483 oclass = impl->pad_s; nvkm_i2c_create_port() 489 oclass = impl->pad_x; nvkm_i2c_create_port() 492 ret = nvkm_object_ctor(nv_object(i2c), NULL, oclass, nvkm_i2c_create_port() 497 oclass = impl->sclass; nvkm_i2c_create_port() 500 if (oclass->handle == type) { nvkm_i2c_create_port() 501 ret = nvkm_object_ctor(parent, NULL, oclass, nvkm_i2c_create_port() 504 } while (ret && (++oclass)->handle); nvkm_i2c_create_port() 511 struct nvkm_oclass *oclass, int length, void **pobject) nvkm_i2c_create_() 522 ret = nvkm_subdev_create(parent, engine, oclass, 0, "I2C", "i2c", &i2c); nvkm_i2c_create_() 591 oclass = nvkm_i2c_extdev_sclass[j]; nvkm_i2c_create_() 593 if (oclass->handle != info.type) nvkm_i2c_create_() 595 ret = nvkm_object_ctor(parent, NULL, oclass, nvkm_i2c_create_() 597 } while (ret && (++oclass)->handle); nvkm_i2c_create_() 610 struct nvkm_oclass *oclass, void *data, u32 size, _nvkm_i2c_ctor() 616 ret = nvkm_i2c_create(parent, engine, oclass, &i2c); _nvkm_i2c_ctor() 109 nvkm_i2c_port_create_(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, u8 index, const struct i2c_algorithm *algo, const struct nvkm_i2c_func *func, int size, void **pobject) nvkm_i2c_port_create_() argument 510 nvkm_i2c_create_(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, int length, void **pobject) nvkm_i2c_create_() argument 609 _nvkm_i2c_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) _nvkm_i2c_ctor() argument
H A D	padg94.c	62 struct nvkm_oclass *oclass, void *data, u32 index, g94_i2c_pad_ctor() 68 ret = nvkm_i2c_pad_create(parent, engine, oclass, index, &pad); g94_i2c_pad_ctor() 61 g94_i2c_pad_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 index, struct nvkm_object **pobject) g94_i2c_pad_ctor() argument
H A D	padgm204.c	62 struct nvkm_oclass *oclass, void *data, u32 index, gm204_i2c_pad_ctor() 68 ret = nvkm_i2c_pad_create(parent, engine, oclass, index, &pad); gm204_i2c_pad_ctor() 61 gm204_i2c_pad_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 index, struct nvkm_object **pobject) gm204_i2c_pad_ctor() argument
H A D	anx9805.c	127 struct nvkm_oclass *oclass, void *data, u32 index, anx9805_aux_chan_ctor() 134 ret = nvkm_i2c_port_create(parent, engine, oclass, index, anx9805_aux_chan_ctor() 141 switch ((oclass->handle & 0xff00) >> 8) { anx9805_aux_chan_ctor() 243 struct nvkm_oclass *oclass, void *data, u32 index, anx9805_ddc_port_ctor() 250 ret = nvkm_i2c_port_create(parent, engine, oclass, index, anx9805_ddc_port_ctor() 256 switch ((oclass->handle & 0xff00) >> 8) { anx9805_ddc_port_ctor() 125 anx9805_aux_chan_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 index, struct nvkm_object **pobject) anx9805_aux_chan_ctor() argument 241 anx9805_ddc_port_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 index, struct nvkm_object **pobject) anx9805_ddc_port_ctor() argument
H A D	gf110.c	52 struct nvkm_oclass *oclass, void *data, u32 index, gf110_i2c_port_ctor() 59 ret = nvkm_i2c_port_create(parent, engine, oclass, index, gf110_i2c_port_ctor() 51 gf110_i2c_port_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 index, struct nvkm_object **pobject) gf110_i2c_port_ctor() argument
H A D	nv04.c	86 struct nvkm_oclass *oclass, void *data, u32 index, nv04_i2c_port_ctor() 93 ret = nvkm_i2c_port_create(parent, engine, oclass, index, nv04_i2c_port_ctor() 85 nv04_i2c_port_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 index, struct nvkm_object **pobject) nv04_i2c_port_ctor() argument
H A D	nv4e.c	79 struct nvkm_oclass *oclass, void *data, u32 index, nv4e_i2c_port_ctor() 86 ret = nvkm_i2c_port_create(parent, engine, oclass, index, nv4e_i2c_port_ctor() 78 nv4e_i2c_port_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 index, struct nvkm_object **pobject) nv4e_i2c_port_ctor() argument
H A D	nv50.c	79 struct nvkm_oclass *oclass, void *data, u32 index, nv50_i2c_port_ctor() 86 ret = nvkm_i2c_port_create(parent, engine, oclass, index, nv50_i2c_port_ctor() 78 nv50_i2c_port_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 index, struct nvkm_object **pobject) nv50_i2c_port_ctor() argument
H A D	g94.c	197 struct nvkm_oclass *oclass, void *data, u32 index, g94_i2c_port_ctor() 204 ret = nvkm_i2c_port_create(parent, engine, oclass, index, g94_i2c_port_ctor() 225 struct nvkm_oclass *oclass, void *data, u32 index, g94_aux_port_ctor() 232 ret = nvkm_i2c_port_create(parent, engine, oclass, index, g94_aux_port_ctor() 196 g94_i2c_port_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 index, struct nvkm_object **pobject) g94_i2c_port_ctor() argument 224 g94_aux_port_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 index, struct nvkm_object **pobject) g94_aux_port_ctor() argument
H A D	gm204.c	165 struct nvkm_oclass *oclass, void *data, u32 index, gm204_aux_port_ctor() 172 ret = nvkm_i2c_port_create(parent, engine, oclass, index, gm204_aux_port_ctor() 163 gm204_aux_port_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 index, struct nvkm_object **pobject) gm204_aux_port_ctor() argument
/linux-4.1.27/drivers/gpu/drm/nouveau/include/nvif/
H A D	device.h	16 while (object && object->oclass != 0x0080 /*XXX: NV_DEVICE_CLASS*/ ) nvif_device() 22 u32 handle, u32 oclass, void *, u32, 25 int nvif_device_new(struct nvif_object *, u32 handle, u32 oclass,
H A D	object.h	11 u32 oclass; member in struct:nvif_object 23 u32 handle, u32 oclass, void *, u32, 26 int nvif_object_new(struct nvif_object *, u32 handle, u32 oclass,
H A D	ioctl.h	41 __u32 oclass[]; member in struct:nvif_ioctl_sclass_v0 54 __u32 oclass; member in struct:nvif_ioctl_new_v0
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/
H A D	base.c	32 const struct nvkm_gpio_impl *impl = (void *)nv_object(gpio)->oclass; nvkm_gpio_drive() 39 const struct nvkm_gpio_impl *impl = (void *)nv_object(gpio)->oclass; nvkm_gpio_sense() 110 const struct nvkm_gpio_impl *impl = (void *)nv_object(gpio)->oclass; nvkm_gpio_intr_fini() 118 const struct nvkm_gpio_impl *impl = (void *)nv_object(gpio)->oclass; nvkm_gpio_intr_init() 140 const struct nvkm_gpio_impl *impl = (void *)nv_object(gpio)->oclass; nvkm_gpio_intr() 164 const struct nvkm_gpio_impl *impl = (void *)object->oclass; _nvkm_gpio_fini() 211 struct nvkm_oclass *oclass, int length, void **pobject) nvkm_gpio_create_() 213 const struct nvkm_gpio_impl *impl = (void *)oclass; nvkm_gpio_create_() 217 ret = nvkm_subdev_create_(parent, engine, oclass, 0, "GPIO", nvkm_gpio_create_() 239 struct nvkm_oclass *oclass, void *data, u32 size, _nvkm_gpio_ctor() 245 ret = nvkm_gpio_create(parent, engine, oclass, &gpio); _nvkm_gpio_ctor() 210 nvkm_gpio_create_(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, int length, void **pobject) nvkm_gpio_create_() argument 238 _nvkm_gpio_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) _nvkm_gpio_ctor() argument
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/mc/
H A D	base.c	50 const struct nvkm_mc_oclass *oclass = (void *)nv_object(pmc)->oclass; nvkm_mc_intr() local 51 const struct nvkm_mc_intr *map = oclass->intr; nvkm_mc_intr() 59 oclass->msi_rearm(pmc); nvkm_mc_intr() 115 const struct nvkm_mc_oclass *oclass = (void *)bclass; nvkm_mc_create_() local 148 if (pmc->use_msi && oclass->msi_rearm) { nvkm_mc_create_() 152 oclass->msi_rearm(pmc); nvkm_mc_create_()
H A D	nv04.c	54 struct nvkm_oclass *oclass, void *data, u32 size, nv04_mc_ctor() 60 ret = nvkm_mc_create(parent, engine, oclass, &priv); nv04_mc_ctor() 53 nv04_mc_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv04_mc_ctor() argument
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/ce/
H A D	gk104.c	81 struct nvkm_oclass *oclass, void *data, u32 size, gk104_ce0_ctor() 87 ret = nvkm_engine_create(parent, engine, oclass, true, gk104_ce0_ctor() 102 struct nvkm_oclass *oclass, void *data, u32 size, gk104_ce1_ctor() 108 ret = nvkm_engine_create(parent, engine, oclass, true, gk104_ce1_ctor() 123 struct nvkm_oclass *oclass, void *data, u32 size, gk104_ce2_ctor() 129 ret = nvkm_engine_create(parent, engine, oclass, true, gk104_ce2_ctor() 80 gk104_ce0_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) gk104_ce0_ctor() argument 101 gk104_ce1_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) gk104_ce1_ctor() argument 122 gk104_ce2_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) gk104_ce2_ctor() argument
H A D	gm204.c	81 struct nvkm_oclass *oclass, void *data, u32 size, gm204_ce0_ctor() 87 ret = nvkm_engine_create(parent, engine, oclass, true, gm204_ce0_ctor() 102 struct nvkm_oclass *oclass, void *data, u32 size, gm204_ce1_ctor() 108 ret = nvkm_engine_create(parent, engine, oclass, true, gm204_ce1_ctor() 123 struct nvkm_oclass *oclass, void *data, u32 size, gm204_ce2_ctor() 129 ret = nvkm_engine_create(parent, engine, oclass, true, gm204_ce2_ctor() 80 gm204_ce0_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) gm204_ce0_ctor() argument 101 gm204_ce1_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) gm204_ce1_ctor() argument 122 gm204_ce2_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) gm204_ce2_ctor() argument
H A D	gf100.c	94 struct nvkm_oclass *oclass, void *data, u32 size, gf100_ce0_ctor() 100 ret = nvkm_falcon_create(parent, engine, oclass, 0x104000, true, gf100_ce0_ctor() 119 struct nvkm_oclass *oclass, void *data, u32 size, gf100_ce1_ctor() 125 ret = nvkm_falcon_create(parent, engine, oclass, 0x105000, true, gf100_ce1_ctor() 93 gf100_ce0_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) gf100_ce0_ctor() argument 118 gf100_ce1_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) gf100_ce1_ctor() argument
H A D	gt215.c	117 struct nvkm_oclass *oclass, void *data, u32 size, gt215_ce_ctor() 124 ret = nvkm_falcon_create(parent, engine, oclass, 0x104000, enable, gt215_ce_ctor() 116 gt215_ce_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) gt215_ce_ctor() argument
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/
H A D	nv50.c	44 struct nvkm_oclass *oclass, void *data, u32 size, nv50_mpeg_object_ctor() 50 ret = nvkm_gpuobj_create(parent, engine, oclass, 0, parent, nv50_mpeg_object_ctor() 86 struct nvkm_oclass *oclass, void *data, u32 size, nv50_mpeg_context_ctor() 93 ret = nvkm_mpeg_context_create(parent, engine, oclass, NULL, 128 * 4, nv50_mpeg_context_ctor() 166 struct nvkm_oclass *oclass, void *data, u32 size, nv50_mpeg_ctor() 172 ret = nvkm_mpeg_create(parent, engine, oclass, &priv); nv50_mpeg_ctor() 42 nv50_mpeg_object_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv50_mpeg_object_ctor() argument 84 nv50_mpeg_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv50_mpeg_context_ctor() argument 165 nv50_mpeg_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv50_mpeg_ctor() argument
H A D	nv44.c	45 struct nvkm_oclass *oclass, void *data, u32 size, nv44_mpeg_context_ctor() 51 ret = nvkm_mpeg_context_create(parent, engine, oclass, NULL, 264 * 4, nv44_mpeg_context_ctor() 157 struct nvkm_oclass *oclass, void *data, u32 size, nv44_mpeg_ctor() 163 ret = nvkm_mpeg_create(parent, engine, oclass, &priv); nv44_mpeg_ctor() 43 nv44_mpeg_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv44_mpeg_context_ctor() argument 156 nv44_mpeg_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv44_mpeg_ctor() argument
H A D	g84.c	67 struct nvkm_oclass *oclass, void *data, u32 size, g84_mpeg_ctor() 73 ret = nvkm_mpeg_create(parent, engine, oclass, &priv); g84_mpeg_ctor() 66 g84_mpeg_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) g84_mpeg_ctor() argument
H A D	nv31.c	40 struct nvkm_oclass *oclass, void *data, u32 size, nv31_mpeg_object_ctor() 46 ret = nvkm_gpuobj_create(parent, engine, oclass, 0, parent, nv31_mpeg_object_ctor() 129 struct nvkm_oclass *oclass, void *data, u32 size, nv31_mpeg_context_ctor() 137 ret = nvkm_object_create(parent, engine, oclass, 0, &chan); nv31_mpeg_context_ctor() 239 struct nvkm_oclass *oclass, void *data, u32 size, nv31_mpeg_ctor() 245 ret = nvkm_mpeg_create(parent, engine, oclass, &priv); nv31_mpeg_ctor() 38 nv31_mpeg_object_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv31_mpeg_object_ctor() argument 127 nv31_mpeg_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv31_mpeg_context_ctor() argument 238 nv31_mpeg_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv31_mpeg_ctor() argument
H A D	nv40.c	106 struct nvkm_oclass *oclass, void *data, u32 size, nv40_mpeg_ctor() 112 ret = nvkm_mpeg_create(parent, engine, oclass, &priv); nv40_mpeg_ctor() 105 nv40_mpeg_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv40_mpeg_ctor() argument
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/sw/
H A D	nv04.c	76 struct nvkm_oclass *oclass, void *data, u32 size, nv04_sw_context_ctor() 82 ret = nvkm_sw_context_create(parent, engine, oclass, &chan); nv04_sw_context_ctor() 113 struct nvkm_oclass *oclass, void *data, u32 size, nv04_sw_ctor() 119 ret = nvkm_sw_create(parent, engine, oclass, &priv); nv04_sw_ctor() 75 nv04_sw_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv04_sw_context_ctor() argument 112 nv04_sw_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv04_sw_ctor() argument
H A D	nv10.c	65 struct nvkm_oclass *oclass, void *data, u32 size, nv10_sw_context_ctor() 71 ret = nvkm_sw_context_create(parent, engine, oclass, &chan); nv10_sw_context_ctor() 96 struct nvkm_oclass *oclass, void *data, u32 size, nv10_sw_ctor() 102 ret = nvkm_sw_create(parent, engine, oclass, &priv); nv10_sw_ctor() 64 nv10_sw_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv10_sw_context_ctor() argument 95 nv10_sw_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv10_sw_ctor() argument
H A D	nv50.c	157 struct nvkm_oclass *oclass, void *data, u32 size, nv50_sw_context_ctor() 161 struct nv50_sw_cclass *pclass = (void *)oclass; nv50_sw_context_ctor() 165 ret = nvkm_sw_context_create(parent, engine, oclass, &chan); nv50_sw_context_ctor() 205 struct nvkm_oclass *oclass, void *data, u32 size, nv50_sw_ctor() 208 struct nv50_sw_oclass *pclass = (void *)oclass; nv50_sw_ctor() 212 ret = nvkm_sw_create(parent, engine, oclass, &priv); nv50_sw_ctor() 156 nv50_sw_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv50_sw_context_ctor() argument 204 nv50_sw_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv50_sw_ctor() argument
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/
H A D	base.c	48 struct nvkm_devinit_impl *impl = (void *)object->oclass; _nvkm_devinit_init() 78 struct nvkm_oclass *oclass, int size, void **pobject) nvkm_devinit_create_() 80 struct nvkm_devinit_impl *impl = (void *)oclass; nvkm_devinit_create_() 85 ret = nvkm_subdev_create_(parent, engine, oclass, 0, "DEVINIT", nvkm_devinit_create_() 77 nvkm_devinit_create_(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, int size, void **pobject) nvkm_devinit_create_() argument
H A D	gf100.c	95 struct nvkm_oclass *oclass, void *data, u32 size, gf100_devinit_ctor() 98 struct nvkm_devinit_impl *impl = (void *)oclass; gf100_devinit_ctor() 103 ret = nvkm_devinit_create(parent, engine, oclass, &priv); gf100_devinit_ctor() 94 gf100_devinit_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) gf100_devinit_ctor() argument
H A D	nv50.c	148 struct nvkm_oclass *oclass, void *data, u32 size, nv50_devinit_ctor() 154 ret = nvkm_devinit_create(parent, engine, oclass, &priv); nv50_devinit_ctor() 147 nv50_devinit_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv50_devinit_ctor() argument
H A D	nv04.c	443 struct nvkm_oclass *oclass, void *data, u32 size, nv04_devinit_ctor() 449 ret = nvkm_devinit_create(parent, engine, oclass, &priv); nv04_devinit_ctor() 442 nv04_devinit_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv04_devinit_ctor() argument
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/fifo/
H A D	gm204.c	36 struct nvkm_oclass *oclass, void *data, u32 size, gm204_fifo_ctor() 39 int ret = gk104_fifo_ctor(parent, engine, oclass, data, size, pobject); gm204_fifo_ctor() 35 gm204_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) gm204_fifo_ctor() argument
H A D	nv10.c	55 struct nvkm_oclass *oclass, void *data, u32 size, nv10_fifo_chan_ctor() 73 ret = nvkm_fifo_channel_create(parent, engine, oclass, 0, 0x800000, nv10_fifo_chan_ctor() 143 struct nvkm_oclass *oclass, void *data, u32 size, nv10_fifo_ctor() 150 ret = nvkm_fifo_create(parent, engine, oclass, 0, 31, &priv); nv10_fifo_ctor() 53 nv10_fifo_chan_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv10_fifo_chan_ctor() argument 142 nv10_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv10_fifo_ctor() argument
H A D	nv17.c	60 struct nvkm_oclass *oclass, void *data, u32 size, nv17_fifo_chan_ctor() 78 ret = nvkm_fifo_channel_create(parent, engine, oclass, 0, 0x800000, nv17_fifo_chan_ctor() 150 struct nvkm_oclass *oclass, void *data, u32 size, nv17_fifo_ctor() 157 ret = nvkm_fifo_create(parent, engine, oclass, 0, 31, &priv); nv17_fifo_ctor() 58 nv17_fifo_chan_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv17_fifo_chan_ctor() argument 149 nv17_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv17_fifo_ctor() argument
H A D	base.c	57 struct nvkm_oclass *oclass, nvkm_fifo_channel_create_() 69 ret = nvkm_namedb_create_(parent, engine, oclass, 0, NULL, nvkm_fifo_channel_create_() 81 switch (chan->pushdma->base.oclass->handle) { nvkm_fifo_channel_create_() 257 struct nvkm_oclass *oclass, nvkm_fifo_create_() 263 ret = nvkm_engine_create_(parent, engine, oclass, true, "PFIFO", nvkm_fifo_create_() 55 nvkm_fifo_channel_create_(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, int bar, u32 addr, u32 size, u32 pushbuf, u64 engmask, int len, void **ptr) nvkm_fifo_channel_create_() argument 256 nvkm_fifo_create_(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, int min, int max, int length, void **pobject) nvkm_fifo_create_() argument
H A D	g84.c	163 struct nvkm_oclass *oclass, void *data, u32 size, g84_fifo_chan_ctor_dma() 182 ret = nvkm_fifo_channel_create(parent, engine, oclass, 0, 0xc00000, g84_fifo_chan_ctor_dma() 236 struct nvkm_oclass *oclass, void *data, u32 size, g84_fifo_chan_ctor_ind() 257 ret = nvkm_fifo_channel_create(parent, engine, oclass, 0, 0xc00000, g84_fifo_chan_ctor_ind() 365 struct nvkm_oclass *oclass, void *data, u32 size, g84_fifo_context_ctor() 371 ret = nvkm_fifo_context_create(parent, engine, oclass, NULL, 0x10000, g84_fifo_context_ctor() 444 struct nvkm_oclass *oclass, void *data, u32 size, g84_fifo_ctor() 450 ret = nvkm_fifo_create(parent, engine, oclass, 1, 127, &priv); g84_fifo_ctor() 162 g84_fifo_chan_ctor_dma(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) g84_fifo_chan_ctor_dma() argument 235 g84_fifo_chan_ctor_ind(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) g84_fifo_chan_ctor_ind() argument 364 g84_fifo_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) g84_fifo_context_ctor() argument 443 g84_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) g84_fifo_ctor() argument
H A D	nv50.c	190 struct nvkm_oclass *oclass, void *data, u32 size, nv50_fifo_chan_ctor_dma() 209 ret = nvkm_fifo_channel_create(parent, engine, oclass, 0, 0xc00000, nv50_fifo_chan_ctor_dma() 251 struct nvkm_oclass *oclass, void *data, u32 size, nv50_fifo_chan_ctor_ind() 272 ret = nvkm_fifo_channel_create(parent, engine, oclass, 0, 0xc00000, nv50_fifo_chan_ctor_ind() 391 struct nvkm_oclass *oclass, void *data, u32 size, nv50_fifo_context_ctor() 397 ret = nvkm_fifo_context_create(parent, engine, oclass, NULL, 0x10000, nv50_fifo_context_ctor() 456 struct nvkm_oclass *oclass, void *data, u32 size, nv50_fifo_ctor() 462 ret = nvkm_fifo_create(parent, engine, oclass, 1, 127, &priv); nv50_fifo_ctor() 189 nv50_fifo_chan_ctor_dma(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv50_fifo_chan_ctor_dma() argument 250 nv50_fifo_chan_ctor_ind(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv50_fifo_chan_ctor_ind() argument 390 nv50_fifo_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv50_fifo_context_ctor() argument 455 nv50_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv50_fifo_ctor() argument
H A D	nv40.c	178 struct nvkm_oclass *oclass, void *data, u32 size, nv40_fifo_chan_ctor() 196 ret = nvkm_fifo_channel_create(parent, engine, oclass, 0, 0xc00000, nv40_fifo_chan_ctor() 269 struct nvkm_oclass *oclass, void *data, u32 size, nv40_fifo_ctor() 276 ret = nvkm_fifo_create(parent, engine, oclass, 0, 31, &priv); nv40_fifo_ctor() 177 nv40_fifo_chan_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv40_fifo_chan_ctor() argument 268 nv40_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv40_fifo_ctor() argument
H A D	nv04.c	112 struct nvkm_oclass *oclass, void *data, u32 size, nv04_fifo_chan_ctor() 130 ret = nvkm_fifo_channel_create(parent, engine, oclass, 0, 0x800000, nv04_fifo_chan_ctor() 268 struct nvkm_oclass *oclass, void *data, u32 size, nv04_fifo_context_ctor() 274 ret = nvkm_fifo_context_create(parent, engine, oclass, NULL, 0x1000, nv04_fifo_context_ctor() 560 struct nvkm_oclass *oclass, void *data, u32 size, nv04_fifo_ctor() 567 ret = nvkm_fifo_create(parent, engine, oclass, 0, 15, &priv); nv04_fifo_ctor() 110 nv04_fifo_chan_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv04_fifo_chan_ctor() argument 266 nv04_fifo_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv04_fifo_context_ctor() argument 559 nv04_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv04_fifo_ctor() argument
H A D	gk104.c	210 struct nvkm_oclass *oclass, void *data, u32 size, gk104_fifo_chan_ctor() 246 ret = nvkm_fifo_channel_create(parent, engine, oclass, 1, gk104_fifo_chan_ctor() 350 struct nvkm_oclass *oclass, void *data, u32 size, gk104_fifo_context_ctor() 356 ret = nvkm_fifo_context_create(parent, engine, oclass, NULL, 0x1000, gk104_fifo_context_ctor() 1079 struct nvkm_oclass *oclass, void *data, u32 size, gk104_fifo_ctor() 1082 struct gk104_fifo_impl *impl = (void *)oclass; gk104_fifo_ctor() 1086 ret = nvkm_fifo_create(parent, engine, oclass, 0, gk104_fifo_ctor() 209 gk104_fifo_chan_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) gk104_fifo_chan_ctor() argument 349 gk104_fifo_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) gk104_fifo_context_ctor() argument 1078 gk104_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) gk104_fifo_ctor() argument
H A D	gf100.c	182 struct nvkm_oclass *oclass, void *data, u32 size, gf100_fifo_chan_ctor() 204 ret = nvkm_fifo_channel_create(parent, engine, oclass, 1, gf100_fifo_chan_ctor() 317 struct nvkm_oclass *oclass, void *data, u32 size, gf100_fifo_context_ctor() 323 ret = nvkm_fifo_context_create(parent, engine, oclass, NULL, 0x1000, gf100_fifo_context_ctor() 857 struct nvkm_oclass *oclass, void *data, u32 size, gf100_fifo_ctor() 863 ret = nvkm_fifo_create(parent, engine, oclass, 0, 127, &priv); gf100_fifo_ctor() 181 gf100_fifo_chan_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) gf100_fifo_chan_ctor() argument 316 gf100_fifo_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) gf100_fifo_context_ctor() argument 856 gf100_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) gf100_fifo_ctor() argument
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/pm/
H A D	gk110.c	28 struct nvkm_oclass *oclass, void *data, u32 size, gk110_pm_ctor() 34 ret = nvkm_pm_create(parent, engine, oclass, &priv); gk110_pm_ctor() 27 gk110_pm_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) gk110_pm_ctor() argument
H A D	gt215.c	57 struct nvkm_oclass *oclass, void *data, u32 size, gt215_pm_ctor() 60 int ret = nv40_pm_ctor(parent, engine, oclass, data, size, object); gt215_pm_ctor() 56 gt215_pm_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **object) gt215_pm_ctor() argument
H A D	nv40.c	99 struct nvkm_oclass *oclass, void *data, u32 size, nv40_pm_ctor() 102 struct nv40_pm_oclass *mclass = (void *)oclass; nv40_pm_ctor() 106 ret = nvkm_pm_create(parent, engine, oclass, &priv); nv40_pm_ctor() 98 nv40_pm_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv40_pm_ctor() argument
H A D	base.c	267 struct nvkm_oclass *oclass, void *data, u32 size, nvkm_perfctr_ctor() 295 ret = nvkm_object_create(parent, engine, oclass, 0, &ctr); nvkm_perfctr_ctor() 343 struct nvkm_oclass *oclass, void *data, u32 size, nvkm_perfctx_ctor() 350 ret = nvkm_engctx_create(parent, engine, oclass, NULL, 0, 0, 0, &ctx); nvkm_perfctx_ctor() 463 struct nvkm_oclass *oclass, int length, void **pobject) nvkm_pm_create_() 468 ret = nvkm_engine_create_(parent, engine, oclass, true, "PPM", nvkm_pm_create_() 266 nvkm_perfctr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nvkm_perfctr_ctor() argument 342 nvkm_perfctx_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nvkm_perfctx_ctor() argument 462 nvkm_pm_create_(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, int length, void **pobject) nvkm_pm_create_() argument
H A D	gk104.c	90 struct nvkm_oclass *oclass, void *data, u32 size, gk104_pm_ctor() 97 ret = nvkm_pm_create(parent, engine, oclass, &priv); gk104_pm_ctor() 89 gk104_pm_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) gk104_pm_ctor() argument
H A D	gf100.c	102 struct nvkm_oclass *oclass, void *data, u32 size, gf100_pm_ctor() 109 ret = nvkm_pm_create(parent, engine, oclass, &priv); gf100_pm_ctor() 101 gf100_pm_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) gf100_pm_ctor() argument
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/bar/
H A D	gk20a.c	26 struct nvkm_oclass *oclass, void *data, u32 size, gk20a_bar_ctor() 32 ret = gf100_bar_ctor(parent, engine, oclass, data, size, pobject); gk20a_bar_ctor() 25 gk20a_bar_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) gk20a_bar_ctor() argument
H A D	base.c	38 struct nvkm_oclass *oclass, void *data, u32 size, nvkm_barobj_ctor() 47 ret = nvkm_object_create(parent, engine, oclass, 0, &barobj); nvkm_barobj_ctor() 119 struct nvkm_oclass *oclass, int length, void **pobject) nvkm_bar_create_() 124 ret = nvkm_subdev_create_(parent, engine, oclass, 0, "BARCTL", nvkm_bar_create_() 37 nvkm_barobj_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nvkm_barobj_ctor() argument 118 nvkm_bar_create_(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, int length, void **pobject) nvkm_bar_create_() argument
H A D	gf100.c	135 struct nvkm_oclass *oclass, void *data, u32 size, gf100_bar_ctor() 143 ret = nvkm_bar_create(parent, engine, oclass, &priv); gf100_bar_ctor() 134 gf100_bar_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) gf100_bar_ctor() argument
H A D	nv50.c	107 struct nvkm_oclass *oclass, void *data, u32 size, nv50_bar_ctor() 117 ret = nvkm_bar_create(parent, engine, oclass, &priv); nv50_bar_ctor() 106 nv50_bar_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv50_bar_ctor() argument
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
H A D	ramgm107.c	32 struct nvkm_oclass *oclass, void *data, u32 size, gm107_ram_ctor() 38 ret = gf100_ram_create(parent, engine, oclass, 0x021c14, &ram); gm107_ram_ctor() 31 gm107_ram_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) gm107_ram_ctor() argument
H A D	ramnv10.c	28 struct nvkm_oclass *oclass, void *data, u32 size, nv10_ram_create() 36 ret = nvkm_ram_create(parent, engine, oclass, &ram); nv10_ram_create() 27 nv10_ram_create(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv10_ram_create() argument
H A D	ramnv4e.c	28 struct nvkm_oclass *oclass, void *data, u32 size, nv4e_ram_create() 35 ret = nvkm_ram_create(parent, engine, oclass, &ram); nv4e_ram_create() 27 nv4e_ram_create(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv4e_ram_create() argument
H A D	nv04.c	56 struct nvkm_oclass *oclass, void *data, u32 size, nv04_fb_ctor() 59 struct nv04_fb_impl *impl = (void *)oclass; nv04_fb_ctor() 63 ret = nvkm_fb_create(parent, engine, oclass, &priv); nv04_fb_ctor() 55 nv04_fb_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv04_fb_ctor() argument
H A D	gk20a.c	44 struct nvkm_oclass *oclass, void *data, u32 size, gk20a_fb_ctor() 50 ret = nvkm_fb_create(parent, engine, oclass, &priv); gk20a_fb_ctor() 43 gk20a_fb_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) gk20a_fb_ctor() argument
H A D	ramnv04.c	29 struct nvkm_oclass *oclass, void *data, u32 size, nv04_ram_create() 37 ret = nvkm_ram_create(parent, engine, oclass, &ram); nv04_ram_create() 28 nv04_ram_create(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv04_ram_create() argument
H A D	ramnv1a.c	30 struct nvkm_oclass *oclass, void *data, u32 size, nv1a_ram_create() 45 ret = nvkm_ram_create(parent, engine, oclass, &ram); nv1a_ram_create() 29 nv1a_ram_create(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv1a_ram_create() argument
H A D	ramnv20.c	28 struct nvkm_oclass *oclass, void *data, u32 size, nv20_ram_create() 36 ret = nvkm_ram_create(parent, engine, oclass, &ram); nv20_ram_create() 27 nv20_ram_create(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv20_ram_create() argument
H A D	ramnv41.c	28 struct nvkm_oclass *oclass, void *data, u32 size, nv41_ram_create() 36 ret = nvkm_ram_create(parent, engine, oclass, &ram); nv41_ram_create() 27 nv41_ram_create(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv41_ram_create() argument
H A D	ramnv44.c	28 struct nvkm_oclass *oclass, void *data, u32 size, nv44_ram_create() 36 ret = nvkm_ram_create(parent, engine, oclass, &ram); nv44_ram_create() 27 nv44_ram_create(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv44_ram_create() argument
H A D	ramnv49.c	28 struct nvkm_oclass *oclass, void *data, u32 size, nv49_ram_create() 36 ret = nvkm_ram_create(parent, engine, oclass, &ram); nv49_ram_create() 27 nv49_ram_create(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv49_ram_create() argument
H A D	base.c	109 struct nvkm_oclass *oclass, int length, void **pobject) nvkm_fb_create_() 111 struct nvkm_fb_impl *impl = (void *)oclass; nvkm_fb_create_() 129 ret = nvkm_subdev_create_(parent, engine, oclass, 0, "PFB", "fb", nvkm_fb_create_() 108 nvkm_fb_create_(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, int length, void **pobject) nvkm_fb_create_() argument
H A D	gf100.c	86 struct nvkm_oclass *oclass, void *data, u32 size, gf100_fb_ctor() 93 ret = nvkm_fb_create(parent, engine, oclass, &priv); gf100_fb_ctor() 85 gf100_fb_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) gf100_fb_ctor() argument
H A D	rammcp77.c	33 struct nvkm_oclass *oclass, void *data, u32 datasize, mcp77_ram_ctor() 42 ret = nvkm_ram_create(parent, engine, oclass, &priv); mcp77_ram_ctor() 32 mcp77_ram_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 datasize, struct nvkm_object **pobject) mcp77_ram_ctor() argument
H A D	nv50.c	243 struct nvkm_oclass *oclass, void *data, u32 size, nv50_fb_ctor() 250 ret = nvkm_fb_create(parent, engine, oclass, &priv); nv50_fb_ctor() 288 struct nv50_fb_impl *impl = (void *)object->oclass; nv50_fb_init() 242 nv50_fb_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv50_fb_ctor() argument
H A D	ramnv50.c	352 struct nvkm_oclass *oclass, int length, void **pobject) nv50_ram_create_() 361 ret = nvkm_ram_create_(parent, engine, oclass, length, pobject); nv50_ram_create_() 402 struct nvkm_oclass *oclass, void *data, u32 datasize, nv50_ram_ctor() 408 ret = nv50_ram_create(parent, engine, oclass, &ram); nv50_ram_ctor() 351 nv50_ram_create_(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, int length, void **pobject) nv50_ram_create_() argument 401 nv50_ram_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 datasize, struct nvkm_object **pobject) nv50_ram_ctor() argument
H A D	ramnv40.c	173 struct nvkm_oclass *oclass, void *data, u32 size, nv40_ram_create() 181 ret = nvkm_ram_create(parent, engine, oclass, &ram); nv40_ram_create() 172 nv40_ram_create(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv40_ram_create() argument
H A D	ramgf100.c	507 struct nvkm_oclass *oclass, u32 maskaddr, int size, gf100_ram_create_() 522 ret = nvkm_ram_create_(parent, engine, oclass, size, pobject); gf100_ram_create_() 626 struct nvkm_oclass *oclass, void *data, u32 size, gf100_ram_ctor() 633 ret = gf100_ram_create(parent, engine, oclass, 0x022554, &ram); gf100_ram_ctor() 506 gf100_ram_create_(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, u32 maskaddr, int size, void **pobject) gf100_ram_create_() argument 625 gf100_ram_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) gf100_ram_ctor() argument
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/
H A D	base.c	42 struct nvkm_oclass *oclass, int length, void **pobject) nvkm_fuse_create_() 47 ret = nvkm_subdev_create_(parent, engine, oclass, 0, "FUSE", nvkm_fuse_create_() 41 nvkm_fuse_create_(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, int length, void **pobject) nvkm_fuse_create_() argument
H A D	gm107.c	40 struct nvkm_oclass *oclass, void *data, u32 size, gm107_fuse_ctor() 46 ret = nvkm_fuse_create(parent, engine, oclass, &priv); gm107_fuse_ctor() 39 gm107_fuse_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) gm107_fuse_ctor() argument
H A D	gf100.c	53 struct nvkm_oclass *oclass, void *data, u32 size, gf100_fuse_ctor() 59 ret = nvkm_fuse_create(parent, engine, oclass, &priv); gf100_fuse_ctor() 52 gf100_fuse_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) gf100_fuse_ctor() argument
H A D	nv50.c	51 struct nvkm_oclass *oclass, void *data, u32 size, nv50_fuse_ctor() 57 ret = nvkm_fuse_create(parent, engine, oclass, &priv); nv50_fuse_ctor() 50 nv50_fuse_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv50_fuse_ctor() argument
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/volt/
H A D	nv40.c	32 struct nvkm_oclass *oclass, void *data, u32 size, nv40_volt_ctor() 38 ret = nvkm_volt_create(parent, engine, oclass, &priv); nv40_volt_ctor() 31 nv40_volt_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv40_volt_ctor() argument
H A D	base.c	167 struct nvkm_oclass *oclass, int length, void **pobject) nvkm_volt_create_() 173 ret = nvkm_subdev_create_(parent, engine, oclass, 0, "VOLT", nvkm_volt_create_() 166 nvkm_volt_create_(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, int length, void **pobject) nvkm_volt_create_() argument
H A D	gk20a.c	150 struct nvkm_oclass *oclass, void *data, u32 size, gk20a_volt_ctor() 158 ret = nvkm_volt_create(parent, engine, oclass, &priv); gk20a_volt_ctor() 149 gk20a_volt_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) gk20a_volt_ctor() argument
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/
H A D	base.c	59 struct nvkm_oclass *oclass, void **pdata, u32 *psize, nvkm_dmaobj_create_() 74 ret = nvkm_object_create_(parent, engine, oclass, 0, length, pobject); nvkm_dmaobj_create_() 148 struct nvkm_oclass *oclass, void *data, u32 size, _nvkm_dmaeng_ctor() 151 const struct nvkm_dmaeng_impl *impl = (void *)oclass; _nvkm_dmaeng_ctor() 155 ret = nvkm_engine_create(parent, engine, oclass, true, "DMAOBJ", _nvkm_dmaeng_ctor() 57 nvkm_dmaobj_create_(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void **pdata, u32 *psize, int length, void **pobject) nvkm_dmaobj_create_() argument 147 _nvkm_dmaeng_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) _nvkm_dmaeng_ctor() argument
H A D	nv04.c	85 struct nvkm_oclass *oclass, void *data, u32 size, nv04_dmaobj_ctor() 93 ret = nvkm_dmaobj_create(parent, engine, oclass, &data, &size, &priv); nv04_dmaobj_ctor() 99 if (nv_object(mmu)->oclass == &nv04_mmu_oclass) nv04_dmaobj_ctor() 84 nv04_dmaobj_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv04_dmaobj_ctor() argument
H A D	gf100.c	74 struct nvkm_oclass *oclass, void *data, u32 size, gf100_dmaobj_ctor() 85 ret = nvkm_dmaobj_create(parent, engine, oclass, &data, &size, &priv); gf100_dmaobj_ctor() 73 gf100_dmaobj_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) gf100_dmaobj_ctor() argument
H A D	gf110.c	79 struct nvkm_oclass *oclass, void *data, u32 size, gf110_dmaobj_ctor() 90 ret = nvkm_dmaobj_create(parent, engine, oclass, &data, &size, &priv); gf110_dmaobj_ctor() 78 gf110_dmaobj_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) gf110_dmaobj_ctor() argument
H A D	nv50.c	86 struct nvkm_oclass *oclass, void *data, u32 size, nv50_dmaobj_ctor() 97 ret = nvkm_dmaobj_create(parent, engine, oclass, &data, &size, &priv); nv50_dmaobj_ctor() 85 nv50_dmaobj_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv50_dmaobj_ctor() argument
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/
H A D	base.c	47 struct nvkm_oclass *oclass, int length, void **pobject) nvkm_instobj_create_() 53 ret = nvkm_object_create_(parent, engine, oclass, NV_MEMOBJ_CLASS, nvkm_instobj_create_() 73 struct nvkm_instmem_impl *impl = (void *)imem->base.object.oclass; nvkm_instmem_alloc() 132 struct nvkm_oclass *oclass, int length, void **pobject) nvkm_instmem_create_() 137 ret = nvkm_subdev_create_(parent, engine, oclass, 0, "INSTMEM", nvkm_instmem_create_() 46 nvkm_instobj_create_(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, int length, void **pobject) nvkm_instobj_create_() argument 131 nvkm_instmem_create_(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, int length, void **pobject) nvkm_instmem_create_() argument
H A D	nv04.c	64 struct nvkm_oclass *oclass, void *data, u32 size, nv04_instobj_ctor() 76 ret = nvkm_instobj_create(parent, engine, oclass, &node); nv04_instobj_ctor() 137 struct nvkm_oclass *oclass, void *data, u32 size, nv04_instmem_ctor() 143 ret = nvkm_instmem_create(parent, engine, oclass, &priv); nv04_instmem_ctor() 63 nv04_instobj_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv04_instobj_ctor() argument 136 nv04_instmem_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv04_instmem_ctor() argument
H A D	nv50.c	92 struct nvkm_oclass *oclass, void *data, u32 size, nv50_instobj_ctor() 103 ret = nvkm_instobj_create(parent, engine, oclass, &node); nv50_instobj_ctor() 144 struct nvkm_oclass *oclass, void *data, u32 size, nv50_instmem_ctor() 150 ret = nvkm_instmem_create(parent, engine, oclass, &priv); nv50_instmem_ctor() 91 nv50_instobj_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv50_instobj_ctor() argument 143 nv50_instmem_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv50_instmem_ctor() argument
H A D	gk20a.c	204 struct nvkm_oclass *oclass, u32 npages, u32 align, gk20a_instobj_ctor_dma() 212 ret = nvkm_instobj_create_(parent, engine, oclass, sizeof(*node), gk20a_instobj_ctor_dma() 246 struct nvkm_oclass *oclass, u32 npages, u32 align, gk20a_instobj_ctor_iommu() 255 ret = nvkm_instobj_create_(parent, engine, oclass, gk20a_instobj_ctor_iommu() 325 struct nvkm_oclass *oclass, void *data, u32 _size, gk20a_instobj_ctor() 342 ret = gk20a_instobj_ctor_iommu(parent, engine, oclass, gk20a_instobj_ctor() 345 ret = gk20a_instobj_ctor_dma(parent, engine, oclass, gk20a_instobj_ctor() 391 struct nvkm_oclass *oclass, void *data, u32 size, gk20a_instmem_ctor() 398 ret = nvkm_instmem_create(parent, engine, oclass, &priv); gk20a_instmem_ctor() 203 gk20a_instobj_ctor_dma(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, u32 npages, u32 align, struct gk20a_instobj_priv **_node) gk20a_instobj_ctor_dma() argument 245 gk20a_instobj_ctor_iommu(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, u32 npages, u32 align, struct gk20a_instobj_priv **_node) gk20a_instobj_ctor_iommu() argument 324 gk20a_instobj_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 _size, struct nvkm_object **pobject) gk20a_instobj_ctor() argument 390 gk20a_instmem_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) gk20a_instmem_ctor() argument
H A D	nv40.c	49 struct nvkm_oclass *oclass, void *data, u32 size, nv40_instmem_ctor() 56 ret = nvkm_instmem_create(parent, engine, oclass, &priv); nv40_instmem_ctor() 48 nv40_instmem_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv40_instmem_ctor() argument
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/bus/
H A D	nv04.c	66 struct nvkm_oclass *oclass, void *data, u32 size, nv04_bus_ctor() 69 struct nv04_bus_impl *impl = (void *)oclass; nv04_bus_ctor() 73 ret = nvkm_bus_create(parent, engine, oclass, &priv); nv04_bus_ctor() 65 nv04_bus_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv04_bus_ctor() argument
/linux-4.1.27/drivers/gpu/drm/nouveau/include/nvkm/core/
H A D	object.h	17 struct nvkm_oclass *oclass; member in struct:nvkm_object 65 #define nv_oclass(o) nv_object(o)->oclass 71 nv_pclass(struct nvkm_object *parent, u32 oclass) nv_pclass() argument 73 while (parent && !nv_iclass(parent, oclass)) nv_pclass()
H A D	parent.h	8 struct nvkm_oclass *oclass; member in struct:nvkm_sclass
H A D	device.h	38 struct nvkm_oclass *oclass[NVDEV_SUBDEV_NR]; member in struct:nvkm_device
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/cipher/
H A D	g84.c	42 struct nvkm_oclass *oclass, void *data, u32 size, g84_cipher_object_ctor() 48 ret = nvkm_gpuobj_create(parent, engine, oclass, 0, parent, g84_cipher_object_ctor() 140 struct nvkm_oclass *oclass, void *data, u32 size, g84_cipher_ctor() 146 ret = nvkm_engine_create(parent, engine, oclass, true, g84_cipher_ctor() 40 g84_cipher_object_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) g84_cipher_object_ctor() argument 139 g84_cipher_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) g84_cipher_ctor() argument
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/disp/
H A D	conn.c	83 struct nvkm_oclass *oclass, nvkm_connector_create_() 103 ret = nvkm_object_create_(parent, engine, oclass, 0, length, pobject); nvkm_connector_create_() 149 struct nvkm_oclass *oclass, void *info, u32 index, _nvkm_connector_ctor() 155 ret = nvkm_connector_create(parent, engine, oclass, info, index, &conn); _nvkm_connector_ctor() 81 nvkm_connector_create_(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, struct nvbios_connE *info, int index, int length, void **pobject) nvkm_connector_create_() argument 147 _nvkm_connector_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *info, u32 index, struct nvkm_object **pobject) _nvkm_connector_ctor() argument
H A D	outp.c	62 struct nvkm_oclass *oclass, nvkm_output_create_() 75 ret = nvkm_object_create_(parent, engine, oclass, 0, length, pobject); nvkm_output_create_() 117 struct nvkm_oclass *oclass, void *dcbE, u32 index, _nvkm_output_ctor() 123 ret = nvkm_output_create(parent, engine, oclass, dcbE, index, &outp); _nvkm_output_ctor() 60 nvkm_output_create_(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, struct dcb_output *dcbE, int index, int length, void **pobject) nvkm_output_create_() argument 115 _nvkm_output_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *dcbE, u32 index, struct nvkm_object **pobject) _nvkm_output_ctor() argument
H A D	piornv50.c	41 struct nvkm_oclass *oclass, void *info, u32 index, nv50_pior_tmds_ctor() 48 ret = nvkm_output_create(parent, engine, oclass, info, index, &outp); nv50_pior_tmds_ctor() 108 struct nvkm_oclass *oclass, void *info, u32 index, nv50_pior_dp_ctor() 115 ret = nvkm_output_dp_create(parent, engine, oclass, info, index, &outp); nv50_pior_dp_ctor() 39 nv50_pior_tmds_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *info, u32 index, struct nvkm_object **pobject) nv50_pior_tmds_ctor() argument 106 nv50_pior_dp_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *info, u32 index, struct nvkm_object **pobject) nv50_pior_dp_ctor() argument
H A D	base.c	187 struct nvkm_oclass *oclass, int heads, const char *intname, nvkm_disp_create_() 190 struct nvkm_disp_impl *impl = (void *)oclass; nvkm_disp_create_() 200 ret = nvkm_engine_create_(parent, engine, oclass, true, intname, nvkm_disp_create_() 217 oclass = nvkm_output_oclass; nvkm_disp_create_() 221 oclass = sclass[0]; nvkm_disp_create_() 227 nvkm_object_ctor(*pobject, NULL, oclass, &dcbE, i, &object); nvkm_disp_create_() 186 nvkm_disp_create_(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, int heads, const char *intname, const char *extname, int length, void **pobject) nvkm_disp_create_() argument
H A D	g94.c	83 struct nvkm_oclass *oclass, void *data, u32 size, g94_disp_ctor() 89 ret = nvkm_disp_create(parent, engine, oclass, 2, "PDISP", g94_disp_ctor() 82 g94_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) g94_disp_ctor() argument
H A D	gk110.c	54 struct nvkm_oclass *oclass, void *data, u32 size, gk110_disp_ctor() 61 ret = nvkm_disp_create(parent, engine, oclass, heads, gk110_disp_ctor() 53 gk110_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) gk110_disp_ctor() argument
H A D	gm107.c	54 struct nvkm_oclass *oclass, void *data, u32 size, gm107_disp_ctor() 61 ret = nvkm_disp_create(parent, engine, oclass, heads, gm107_disp_ctor() 53 gm107_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) gm107_disp_ctor() argument
H A D	gm204.c	55 struct nvkm_oclass *oclass, void *data, u32 size, gm204_disp_ctor() 62 ret = nvkm_disp_create(parent, engine, oclass, heads, gm204_disp_ctor() 54 gm204_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) gm204_disp_ctor() argument
H A D	gt200.c	99 struct nvkm_oclass *oclass, void *data, u32 size, gt200_disp_ctor() 105 ret = nvkm_disp_create(parent, engine, oclass, 2, "PDISP", gt200_disp_ctor() 98 gt200_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) gt200_disp_ctor() argument
H A D	gt215.c	54 struct nvkm_oclass *oclass, void *data, u32 size, gt215_disp_ctor() 60 ret = nvkm_disp_create(parent, engine, oclass, 2, "PDISP", gt215_disp_ctor() 53 gt215_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) gt215_disp_ctor() argument
H A D	outpdp.c	214 struct nvkm_oclass *oclass, nvkm_output_dp_create_() 225 ret = nvkm_output_create_(parent, engine, oclass, info, index, nvkm_output_dp_create_() 289 struct nvkm_oclass *oclass, void *info, u32 index, _nvkm_output_dp_ctor() 295 ret = nvkm_output_dp_create(parent, engine, oclass, info, index, &outp); _nvkm_output_dp_ctor() 212 nvkm_output_dp_create_(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, struct dcb_output *info, int index, int length, void **pobject) nvkm_output_dp_create_() argument 287 _nvkm_output_dp_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *info, u32 index, struct nvkm_object **pobject) _nvkm_output_dp_ctor() argument
H A D	nv50.c	55 struct nvkm_oclass *oclass, int head, nv50_disp_chan_create_() 58 const struct nv50_disp_chan_impl *impl = (void *)oclass->ofuncs; nv50_disp_chan_create_() 68 ret = nvkm_namedb_create_(parent, engine, oclass, 0, NULL, nv50_disp_chan_create_() 208 struct nvkm_oclass *oclass, u32 pushbuf, int head, nv50_disp_dmac_create_() 214 ret = nv50_disp_chan_create_(parent, engine, oclass, head, nv50_disp_dmac_create_() 348 const struct nv50_disp_impl *impl = (void *)disp->oclass; nv50_disp_mthd_chan() 490 struct nvkm_oclass *oclass, void *data, u32 size, nv50_disp_core_ctor() 507 ret = nv50_disp_dmac_create_(parent, engine, oclass, args->v0.pushbuf, nv50_disp_core_ctor() 646 struct nvkm_oclass *oclass, void *data, u32 size, nv50_disp_base_ctor() 666 ret = nv50_disp_dmac_create_(parent, engine, oclass, args->v0.pushbuf, nv50_disp_base_ctor() 736 struct nvkm_oclass *oclass, void *data, u32 size, nv50_disp_ovly_ctor() 756 ret = nv50_disp_dmac_create_(parent, engine, oclass, args->v0.pushbuf, nv50_disp_ovly_ctor() 788 struct nvkm_oclass *oclass, int head, nv50_disp_pioc_create_() 791 return nv50_disp_chan_create_(parent, engine, oclass, head, nv50_disp_pioc_create_() 856 struct nvkm_oclass *oclass, void *data, u32 size, nv50_disp_oimm_ctor() 875 ret = nv50_disp_pioc_create_(parent, engine, oclass, args->v0.head, nv50_disp_oimm_ctor() 904 struct nvkm_oclass *oclass, void *data, u32 size, nv50_disp_curs_ctor() 923 ret = nv50_disp_pioc_create_(parent, engine, oclass, args->v0.head, nv50_disp_curs_ctor() 1107 struct nvkm_oclass *oclass, void *data, u32 size, nv50_disp_main_ctor() 1114 ret = nvkm_parent_create(parent, engine, oclass, 0, nv50_disp_main_ctor() 1247 struct nvkm_oclass *oclass, void *data, u32 size, nv50_disp_data_ctor() 1264 ret = nvkm_engctx_create(parent, engine, oclass, NULL, 0x10000, nv50_disp_data_ctor() 1328 struct nv50_disp_impl *impl = (void *)nv_object(priv)->oclass; nv50_disp_intr_error() 1880 struct nv50_disp_impl *impl = (void *)nv_object(priv)->oclass; nv50_disp_intr_supervisor() 1965 struct nvkm_oclass *oclass, void *data, u32 size, nv50_disp_ctor() 1971 ret = nvkm_disp_create(parent, engine, oclass, 2, "PDISP", nv50_disp_ctor() 53 nv50_disp_chan_create_(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, int head, int length, void **pobject) nv50_disp_chan_create_() argument 206 nv50_disp_dmac_create_(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, u32 pushbuf, int head, int length, void **pobject) nv50_disp_dmac_create_() argument 488 nv50_disp_core_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv50_disp_core_ctor() argument 644 nv50_disp_base_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv50_disp_base_ctor() argument 734 nv50_disp_ovly_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv50_disp_ovly_ctor() argument 786 nv50_disp_pioc_create_(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, int head, int length, void **pobject) nv50_disp_pioc_create_() argument 854 nv50_disp_oimm_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv50_disp_oimm_ctor() argument 902 nv50_disp_curs_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv50_disp_curs_ctor() argument 1105 nv50_disp_main_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv50_disp_main_ctor() argument 1245 nv50_disp_data_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv50_disp_data_ctor() argument 1964 nv50_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv50_disp_ctor() argument
H A D	g84.c	223 struct nvkm_oclass *oclass, void *data, u32 size, g84_disp_ctor() 229 ret = nvkm_disp_create(parent, engine, oclass, 2, "PDISP", g84_disp_ctor() 222 g84_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) g84_disp_ctor() argument
H A D	gk104.c	219 struct nvkm_oclass *oclass, void *data, u32 size, gk104_disp_ctor() 226 ret = nvkm_disp_create(parent, engine, oclass, heads, gk104_disp_ctor() 218 gk104_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) gk104_disp_ctor() argument
H A D	nv04.c	178 struct nvkm_oclass *oclass, void *data, u32 size, nv04_disp_ctor() 184 ret = nvkm_disp_create(parent, engine, oclass, 2, "DISPLAY", nv04_disp_ctor() 177 nv04_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv04_disp_ctor() argument
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/
H A D	xtensa.c	43 struct nvkm_oclass *oclass, void *data, u32 size, _nvkm_xtensa_engctx_ctor() 49 ret = nvkm_engctx_create(parent, engine, oclass, NULL, 0x10000, 0x1000, _nvkm_xtensa_engctx_ctor() 76 struct nvkm_oclass *oclass, u32 addr, bool enable, nvkm_xtensa_create_() 83 ret = nvkm_engine_create_(parent, engine, oclass, enable, iname, nvkm_xtensa_create_() 42 _nvkm_xtensa_engctx_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) _nvkm_xtensa_engctx_ctor() argument 75 nvkm_xtensa_create_(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, u32 addr, bool enable, const char *iname, const char *fname, int length, void **pobject) nvkm_xtensa_create_() argument
H A D	falcon.c	262 struct nvkm_oclass *oclass, u32 addr, bool enable, nvkm_falcon_create_() 269 ret = nvkm_engine_create_(parent, engine, oclass, enable, iname, nvkm_falcon_create_() 261 nvkm_falcon_create_(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, u32 addr, bool enable, const char *iname, const char *fname, int length, void **pobject) nvkm_falcon_create_() argument
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/bsp/
H A D	g84.c	62 struct nvkm_oclass *oclass, void *data, u32 size, g84_bsp_ctor() 68 ret = nvkm_xtensa_create(parent, engine, oclass, 0x103000, true, g84_bsp_ctor() 61 g84_bsp_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) g84_bsp_ctor() argument
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/
H A D	g98.c	80 struct nvkm_oclass *oclass, void *data, u32 size, g98_mspdec_ctor() 86 ret = nvkm_falcon_create(parent, engine, oclass, 0x085000, true, g98_mspdec_ctor() 79 g98_mspdec_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) g98_mspdec_ctor() argument
H A D	gf100.c	79 struct nvkm_oclass *oclass, void *data, u32 size, gf100_mspdec_ctor() 85 ret = nvkm_falcon_create(parent, engine, oclass, 0x085000, true, gf100_mspdec_ctor() 78 gf100_mspdec_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) gf100_mspdec_ctor() argument
H A D	gk104.c	79 struct nvkm_oclass *oclass, void *data, u32 size, gk104_mspdec_ctor() 85 ret = nvkm_falcon_create(parent, engine, oclass, 0x085000, true, gk104_mspdec_ctor() 78 gk104_mspdec_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) gk104_mspdec_ctor() argument
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/msppp/
H A D	g98.c	80 struct nvkm_oclass *oclass, void *data, u32 size, g98_msppp_ctor() 86 ret = nvkm_falcon_create(parent, engine, oclass, 0x086000, true, g98_msppp_ctor() 79 g98_msppp_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) g98_msppp_ctor() argument
H A D	gf100.c	79 struct nvkm_oclass *oclass, void *data, u32 size, gf100_msppp_ctor() 85 ret = nvkm_falcon_create(parent, engine, oclass, 0x086000, true, gf100_msppp_ctor() 78 gf100_msppp_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) gf100_msppp_ctor() argument
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/msvld/
H A D	g98.c	81 struct nvkm_oclass *oclass, void *data, u32 size, g98_msvld_ctor() 87 ret = nvkm_falcon_create(parent, engine, oclass, 0x084000, true, g98_msvld_ctor() 80 g98_msvld_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) g98_msvld_ctor() argument
H A D	gf100.c	79 struct nvkm_oclass *oclass, void *data, u32 size, gf100_msvld_ctor() 85 ret = nvkm_falcon_create(parent, engine, oclass, 0x084000, true, gf100_msvld_ctor() 78 gf100_msvld_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) gf100_msvld_ctor() argument
H A D	gk104.c	79 struct nvkm_oclass *oclass, void *data, u32 size, gk104_msvld_ctor() 85 ret = nvkm_falcon_create(parent, engine, oclass, 0x084000, true, gk104_msvld_ctor() 78 gk104_msvld_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) gk104_msvld_ctor() argument
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/vp/
H A D	g84.c	62 struct nvkm_oclass *oclass, void *data, u32 size, g84_vp_ctor() 68 ret = nvkm_xtensa_create(parent, engine, oclass, 0xf000, true, g84_vp_ctor() 61 g84_vp_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) g84_vp_ctor() argument
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/bios/
H A D	shadow.c	43 struct shadow *mthd = (void *)nv_object(bios)->oclass; shadow_fetch() 133 struct nvkm_oclass *oclass = nv_object(bios)->oclass; shadow_score() local 135 nv_object(bios)->oclass = &mthd->base; shadow_score() 137 nv_object(bios)->oclass = oclass; shadow_score()
H A D	base.c	116 struct nvkm_oclass *oclass, void *data, u32 size, nvkm_bios_ctor() 123 ret = nvkm_subdev_create(parent, engine, oclass, 0, nvkm_bios_ctor() 115 nvkm_bios_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nvkm_bios_ctor() argument
/linux-4.1.27/drivers/gpu/drm/nouveau/
H A D	nouveau_chan.c	193 const u16 *oclass = oclasses; nouveau_channel_ind() local 210 if (oclass[0] >= KEPLER_CHANNEL_GPFIFO_A) { nouveau_channel_ind() 225 ret = nvif_object_new(nvif_object(device), handle, *oclass++, nouveau_channel_ind() 229 if (chan->object->oclass >= KEPLER_CHANNEL_GPFIFO_A) nouveau_channel_ind() 235 } while (*oclass); nouveau_channel_ind() 250 const u16 *oclass = oclasses; nouveau_channel_dma() local 267 ret = nvif_object_new(nvif_object(device), handle, *oclass++, nouveau_channel_dma() 274 } while (ret && *oclass); nouveau_channel_dma() 339 switch (chan->object->oclass & 0x00ff) { nouveau_channel_init()
H A D	nv50_display.c	66 nv50_chan_create(struct nvif_object *disp, const u32 *oclass, u8 head, nv50_chan_create() argument 69 const u32 handle = (oclass[0] << 16) | head; nv50_chan_create() 78 while (oclass[0]) { nv50_chan_create() 80 if (sclass[i] == oclass[0]) { nv50_chan_create() 82 oclass[0], data, size, nv50_chan_create() 89 oclass++; nv50_chan_create() 116 nv50_pioc_create(struct nvif_object *disp, const u32 *oclass, u8 head, nv50_pioc_create() argument 119 return nv50_chan_create(disp, oclass, head, data, size, &pioc->base); nv50_pioc_create() 136 static const u32 oclass[] = { nv50_curs_create() local 145 return nv50_pioc_create(disp, oclass, head, &args, sizeof(args), nv50_curs_create() 163 static const u32 oclass[] = { nv50_oimm_create() local 172 return nv50_pioc_create(disp, oclass, head, &args, sizeof(args), nv50_oimm_create() 209 nv50_dmac_create(struct nvif_object *disp, const u32 *oclass, u8 head, nv50_dmac_create() argument 236 ret = nv50_chan_create(disp, oclass, head, data, size, &dmac->base); nv50_dmac_create() 282 static const u32 oclass[] = { nv50_core_create() local 296 return nv50_dmac_create(disp, oclass, 0, &args, sizeof(args), syncbuf, nv50_core_create() 318 static const u32 oclass[] = { nv50_base_create() local 329 return nv50_dmac_create(disp, oclass, head, &args, sizeof(args), nv50_base_create() 349 static const u32 oclass[] = { nv50_ovly_create() local 359 return nv50_dmac_create(disp, oclass, head, &args, sizeof(args), nv50_ovly_create() 378 #define nv50_vers(c) nv50_chan(c)->user.oclass 566 if (chan && chan->object->oclass < G82_CHANNEL_GPFIFO) { nv50_display_flip_next() 580 if (chan && chan->object->oclass < FERMI_CHANNEL_GPFIFO) { nv50_display_flip_next() 1255 if (disp->disp->oclass < GF110_DISP) { nv50_crtc_lut_load() 2391 if (disp->disp->oclass < G82_DISP) { nv50_fb_ctor() 2396 if (disp->disp->oclass < GF110_DISP) { nv50_fb_ctor() 2511 if (disp->disp->oclass >= GF110_DISP) nv50_display_create()
H A D	nouveau_display.c	407 if (disp->disp.oclass < NV50_DISP) nouveau_display_create_properties() 410 if (disp->disp.oclass < GF110_DISP) nouveau_display_create_properties() 481 static const u16 oclass[] = { nouveau_display_create() local 496 for (i = 0, ret = -ENODEV; ret && i < ARRAY_SIZE(oclass); i++) { nouveau_display_create() 498 NVDRM_DISPLAY, oclass[i], nouveau_display_create() 504 if (disp->disp.oclass < NV50_DISP) nouveau_display_create()
H A D	nouveau_abi16.c	380 .new.oclass = init->class, nouveau_abi16_ioctl_grobj_alloc() 422 .new.oclass = NV_DMA_IN_MEMORY, nouveau_abi16_ioctl_notifierobj_alloc()
H A D	nouveau_dma.h	61 /* Object handles - for stuff that's doesn't use handle == oclass. */
H A D	nv04_fbcon.c	252 if (device->info.chipset >= 0x11 /*XXX: oclass == 0x009f*/) { nv04_fbcon_accel_init()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/
H A D	base.c	187 const struct nvkm_pmu_impl *impl = (void *)object->oclass; _nvkm_pmu_init() 243 struct nvkm_oclass *oclass, int length, void **pobject) nvkm_pmu_create_() 248 ret = nvkm_subdev_create_(parent, engine, oclass, 0, "PMU", nvkm_pmu_create_() 261 struct nvkm_oclass *oclass, void *data, u32 size, _nvkm_pmu_ctor() 265 int ret = nvkm_pmu_create(parent, engine, oclass, &pmu); _nvkm_pmu_ctor() 242 nvkm_pmu_create_(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, int length, void **pobject) nvkm_pmu_create_() argument 260 _nvkm_pmu_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) _nvkm_pmu_ctor() argument
H A D	gk20a.c	204 struct nvkm_oclass *oclass, void *data, u32 size, gk20a_pmu_ctor() 210 ret = nvkm_pmu_create(parent, engine, oclass, &priv); gk20a_pmu_ctor() 203 gk20a_pmu_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) gk20a_pmu_ctor() argument
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/
H A D	base.c	100 struct nvkm_oclass *oclass, int length, void **pobject) nvkm_ltc_create_() 102 const struct nvkm_ltc_impl *impl = (void *)oclass; nvkm_ltc_create_() 106 ret = nvkm_subdev_create_(parent, engine, oclass, 0, "PLTCG", nvkm_ltc_create_() 99 nvkm_ltc_create_(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, int length, void **pobject) nvkm_ltc_create_() argument
H A D	gm107.c	110 struct nvkm_oclass *oclass, void *data, u32 size, gm107_ltc_ctor() 118 ret = nvkm_ltc_create(parent, engine, oclass, &priv); gm107_ltc_ctor() 109 gm107_ltc_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) gm107_ltc_ctor() argument
H A D	gf100.c	200 struct nvkm_oclass *oclass, void *data, u32 size, gf100_ltc_ctor() 208 ret = nvkm_ltc_create(parent, engine, oclass, &priv); gf100_ltc_ctor() 199 gf100_ltc_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) gf100_ltc_ctor() argument
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
H A D	nv04.c	77 struct nvkm_oclass *oclass, void *data, u32 size, nv04_clk_ctor() 83 ret = nvkm_clk_create(parent, engine, oclass, nv04_domain, nv04_clk_ctor() 76 nv04_clk_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv04_clk_ctor() argument
H A D	nv40.c	211 struct nvkm_oclass *oclass, void *data, u32 size, nv40_clk_ctor() 217 ret = nvkm_clk_create(parent, engine, oclass, nv40_domain, nv40_clk_ctor() 210 nv40_clk_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv40_clk_ctor() argument
H A D	nv50.c	504 struct nvkm_oclass *oclass, void *data, u32 size, nv50_clk_ctor() 507 struct nv50_clk_oclass *pclass = (void *)oclass; nv50_clk_ctor() 511 ret = nvkm_clk_create(parent, engine, oclass, pclass->domains, nv50_clk_ctor() 503 nv50_clk_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv50_clk_ctor() argument
H A D	gf100.c	434 struct nvkm_oclass *oclass, void *data, u32 size, gf100_clk_ctor() 440 ret = nvkm_clk_create(parent, engine, oclass, gf100_domain, gf100_clk_ctor() 433 gf100_clk_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) gf100_clk_ctor() argument
H A D	mcp77.c	401 struct nvkm_oclass *oclass, void *data, u32 size, mcp77_clk_ctor() 407 ret = nvkm_clk_create(parent, engine, oclass, mcp77_domains, mcp77_clk_ctor() 400 mcp77_clk_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) mcp77_clk_ctor() argument
H A D	base.c	533 struct nvkm_oclass *oclass, struct nvkm_domain *clocks, nvkm_clk_create_() 542 ret = nvkm_subdev_create_(parent, engine, oclass, 0, "CLK", nvkm_clk_create_() 532 nvkm_clk_create_(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, struct nvkm_domain *clocks, struct nvkm_pstate *pstates, int nb_pstates, bool allow_reclock, int length, void **object) nvkm_clk_create_() argument
H A D	gk104.c	472 struct nvkm_oclass *oclass, void *data, u32 size, gk104_clk_ctor() 478 ret = nvkm_clk_create(parent, engine, oclass, gk104_domain, gk104_clk_ctor() 471 gk104_clk_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) gk104_clk_ctor() argument
H A D	gk20a.c	637 struct nvkm_oclass *oclass, void *data, u32 size, gk20a_clk_ctor() 651 ret = nvkm_clk_create(parent, engine, oclass, gk20a_domains, gk20a_clk_ctor() 636 gk20a_clk_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) gk20a_clk_ctor() argument
H A D	gt215.c	505 struct nvkm_oclass *oclass, void *data, u32 size, gt215_clk_ctor() 511 ret = nvkm_clk_create(parent, engine, oclass, gt215_domain, gt215_clk_ctor() 504 gt215_clk_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) gt215_clk_ctor() argument
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/
H A D	gf100.c	98 struct nvkm_oclass *oclass, void *data, u32 size, gf100_ibus_ctor() 104 ret = nvkm_ibus_create(parent, engine, oclass, &priv); gf100_ibus_ctor() 97 gf100_ibus_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) gf100_ibus_ctor() argument
H A D	gk20a.c	78 struct nvkm_oclass *oclass, void *data, u32 size, gk20a_ibus_ctor() 84 ret = nvkm_ibus_create(parent, engine, oclass, &priv); gk20a_ibus_ctor() 77 gk20a_ibus_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) gk20a_ibus_ctor() argument
H A D	gk104.c	115 struct nvkm_oclass *oclass, void *data, u32 size, gk104_ibus_ctor() 121 ret = nvkm_ibus_create(parent, engine, oclass, &priv); gk104_ibus_ctor() 114 gk104_ibus_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) gk104_ibus_ctor() argument
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/
H A D	nv04.c	85 struct nvkm_oclass *oclass, void *data, u32 size, nv04_mmu_ctor() 92 ret = nvkm_mmu_create(parent, engine, oclass, "PCIGART", nv04_mmu_ctor() 84 nv04_mmu_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv04_mmu_ctor() argument
H A D	nv41.c	86 struct nvkm_oclass *oclass, void *data, u32 size, nv41_mmu_ctor() 99 ret = nvkm_mmu_create(parent, engine, oclass, "PCIEGART", nv41_mmu_ctor() 85 nv41_mmu_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv41_mmu_ctor() argument
H A D	gf100.c	203 struct nvkm_oclass *oclass, void *data, u32 size, gf100_mmu_ctor() 209 ret = nvkm_mmu_create(parent, engine, oclass, "VM", "vm", &priv); gf100_mmu_ctor() 202 gf100_mmu_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) gf100_mmu_ctor() argument
H A D	nv44.c	157 struct nvkm_oclass *oclass, void *data, u32 size, nv44_mmu_ctor() 170 ret = nvkm_mmu_create(parent, engine, oclass, "PCIEGART", nv44_mmu_ctor() 156 nv44_mmu_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv44_mmu_ctor() argument
H A D	nv50.c	207 struct nvkm_oclass *oclass, void *data, u32 size, nv50_mmu_ctor() 213 ret = nvkm_mmu_create(parent, engine, oclass, "VM", "vm", &priv); nv50_mmu_ctor() 206 nv50_mmu_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv50_mmu_ctor() argument
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/therm/
H A D	gm107.c	63 struct nvkm_oclass *oclass, void *data, u32 size, gm107_therm_ctor() 69 ret = nvkm_therm_create(parent, engine, oclass, &priv); gm107_therm_ctor() 62 gm107_therm_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) gm107_therm_ctor() argument
H A D	gt215.c	70 struct nvkm_oclass *oclass, void *data, u32 size, gt215_therm_ctor() 76 ret = nvkm_therm_create(parent, engine, oclass, &priv); gt215_therm_ctor() 69 gt215_therm_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) gt215_therm_ctor() argument
H A D	gf110.c	142 struct nvkm_oclass *oclass, void *data, u32 size, gf110_therm_ctor() 148 ret = nvkm_therm_create(parent, engine, oclass, &priv); gf110_therm_ctor() 141 gf110_therm_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) gf110_therm_ctor() argument
H A D	nv50.c	157 struct nvkm_oclass *oclass, void *data, u32 size, nv50_therm_ctor() 163 ret = nvkm_therm_create(parent, engine, oclass, &priv); nv50_therm_ctor() 155 nv50_therm_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv50_therm_ctor() argument
H A D	g84.c	208 struct nvkm_oclass *oclass, void *data, u32 size, g84_therm_ctor() 214 ret = nvkm_therm_create(parent, engine, oclass, &priv); g84_therm_ctor() 207 g84_therm_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) g84_therm_ctor() argument
H A D	nv40.c	186 struct nvkm_oclass *oclass, void *data, u32 size, nv40_therm_ctor() 192 ret = nvkm_therm_create(parent, engine, oclass, &priv); nv40_therm_ctor() 184 nv40_therm_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv40_therm_ctor() argument
H A D	base.c	325 struct nvkm_oclass *oclass, int length, void **pobject) nvkm_therm_create_() 330 ret = nvkm_subdev_create_(parent, engine, oclass, 0, "PTHERM", nvkm_therm_create_() 324 nvkm_therm_create_(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, int length, void **pobject) nvkm_therm_create_() argument
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/sec/
H A D	g98.c	115 struct nvkm_oclass *oclass, void *data, u32 size, g98_sec_ctor() 121 ret = nvkm_falcon_create(parent, engine, oclass, 0x087000, true, g98_sec_ctor() 114 g98_sec_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) g98_sec_ctor() argument
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/mxm/
H A D	base.c	227 struct nvkm_oclass *oclass, int length, void **pobject) nvkm_mxm_create_() 236 ret = nvkm_subdev_create_(parent, engine, oclass, 0, "MXM", "mxm", nvkm_mxm_create_() 226 nvkm_mxm_create_(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, int length, void **pobject) nvkm_mxm_create_() argument
H A D	nv50.c	206 struct nvkm_oclass *oclass, void *data, u32 size, nv50_mxm_ctor() 212 ret = nvkm_mxm_create(parent, engine, oclass, &priv); nv50_mxm_ctor() 205 nv50_mxm_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv50_mxm_ctor() argument
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/timer/
H A D	nv04.c	231 struct nvkm_oclass *oclass, void *data, u32 size, nv04_timer_ctor() 237 ret = nvkm_timer_create(parent, engine, oclass, &priv); nv04_timer_ctor() 230 nv04_timer_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv04_timer_ctor() argument

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