1/*
2 * Copyright 2012 Nouveau Community
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Martin Peres <martin.peres@labri.fr>
23 *          Ben Skeggs
24 */
25#include "nv04.h"
26
27static void
28nv04_bus_intr(struct nvkm_subdev *subdev)
29{
30	struct nvkm_bus *pbus = nvkm_bus(subdev);
31	u32 stat = nv_rd32(pbus, 0x001100) & nv_rd32(pbus, 0x001140);
32
33	if (stat & 0x00000001) {
34		nv_error(pbus, "BUS ERROR\n");
35		stat &= ~0x00000001;
36		nv_wr32(pbus, 0x001100, 0x00000001);
37	}
38
39	if (stat & 0x00000110) {
40		subdev = nvkm_subdev(subdev, NVDEV_SUBDEV_GPIO);
41		if (subdev && subdev->intr)
42			subdev->intr(subdev);
43		stat &= ~0x00000110;
44		nv_wr32(pbus, 0x001100, 0x00000110);
45	}
46
47	if (stat) {
48		nv_error(pbus, "unknown intr 0x%08x\n", stat);
49		nv_mask(pbus, 0x001140, stat, 0x00000000);
50	}
51}
52
53static int
54nv04_bus_init(struct nvkm_object *object)
55{
56	struct nv04_bus_priv *priv = (void *)object;
57
58	nv_wr32(priv, 0x001100, 0xffffffff);
59	nv_wr32(priv, 0x001140, 0x00000111);
60
61	return nvkm_bus_init(&priv->base);
62}
63
64int
65nv04_bus_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
66	      struct nvkm_oclass *oclass, void *data, u32 size,
67	      struct nvkm_object **pobject)
68{
69	struct nv04_bus_impl *impl = (void *)oclass;
70	struct nv04_bus_priv *priv;
71	int ret;
72
73	ret = nvkm_bus_create(parent, engine, oclass, &priv);
74	*pobject = nv_object(priv);
75	if (ret)
76		return ret;
77
78	nv_subdev(priv)->intr = impl->intr;
79	priv->base.hwsq_exec = impl->hwsq_exec;
80	priv->base.hwsq_size = impl->hwsq_size;
81	return 0;
82}
83
84struct nvkm_oclass *
85nv04_bus_oclass = &(struct nv04_bus_impl) {
86	.base.handle = NV_SUBDEV(BUS, 0x04),
87	.base.ofuncs = &(struct nvkm_ofuncs) {
88		.ctor = nv04_bus_ctor,
89		.dtor = _nvkm_bus_dtor,
90		.init = nv04_bus_init,
91		.fini = _nvkm_bus_fini,
92	},
93	.intr = nv04_bus_intr,
94}.base;
95