1/*
2 * Copyright 2013 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs <bskeggs@redhat.com>
23 */
24#include "gf100.h"
25#include "ctxgf100.h"
26
27#include <subdev/pmu.h>
28
29#include <nvif/class.h>
30
31/*******************************************************************************
32 * Graphics object classes
33 ******************************************************************************/
34
35static struct nvkm_oclass
36gk104_gr_sclass[] = {
37	{ FERMI_TWOD_A, &nvkm_object_ofuncs },
38	{ KEPLER_INLINE_TO_MEMORY_A, &nvkm_object_ofuncs },
39	{ KEPLER_A, &gf100_fermi_ofuncs, gf100_gr_9097_omthds },
40	{ KEPLER_COMPUTE_A, &nvkm_object_ofuncs, gf100_gr_90c0_omthds },
41	{}
42};
43
44/*******************************************************************************
45 * PGRAPH register lists
46 ******************************************************************************/
47
48const struct gf100_gr_init
49gk104_gr_init_main_0[] = {
50	{ 0x400080,   1, 0x04, 0x003083c2 },
51	{ 0x400088,   1, 0x04, 0x0001ffe7 },
52	{ 0x40008c,   1, 0x04, 0x00000000 },
53	{ 0x400090,   1, 0x04, 0x00000030 },
54	{ 0x40013c,   1, 0x04, 0x003901f7 },
55	{ 0x400140,   1, 0x04, 0x00000100 },
56	{ 0x400144,   1, 0x04, 0x00000000 },
57	{ 0x400148,   1, 0x04, 0x00000110 },
58	{ 0x400138,   1, 0x04, 0x00000000 },
59	{ 0x400130,   2, 0x04, 0x00000000 },
60	{ 0x400124,   1, 0x04, 0x00000002 },
61	{}
62};
63
64static const struct gf100_gr_init
65gk104_gr_init_ds_0[] = {
66	{ 0x405844,   1, 0x04, 0x00ffffff },
67	{ 0x405850,   1, 0x04, 0x00000000 },
68	{ 0x405900,   1, 0x04, 0x0000ff34 },
69	{ 0x405908,   1, 0x04, 0x00000000 },
70	{ 0x405928,   2, 0x04, 0x00000000 },
71	{}
72};
73
74static const struct gf100_gr_init
75gk104_gr_init_sked_0[] = {
76	{ 0x407010,   1, 0x04, 0x00000000 },
77	{}
78};
79
80static const struct gf100_gr_init
81gk104_gr_init_cwd_0[] = {
82	{ 0x405b50,   1, 0x04, 0x00000000 },
83	{}
84};
85
86static const struct gf100_gr_init
87gk104_gr_init_gpc_unk_1[] = {
88	{ 0x418d00,   1, 0x04, 0x00000000 },
89	{ 0x418d28,   2, 0x04, 0x00000000 },
90	{ 0x418f00,   1, 0x04, 0x00000000 },
91	{ 0x418f08,   1, 0x04, 0x00000000 },
92	{ 0x418f20,   2, 0x04, 0x00000000 },
93	{ 0x418e00,   1, 0x04, 0x00000060 },
94	{ 0x418e08,   1, 0x04, 0x00000000 },
95	{ 0x418e1c,   2, 0x04, 0x00000000 },
96	{}
97};
98
99const struct gf100_gr_init
100gk104_gr_init_tpccs_0[] = {
101	{ 0x419d0c,   1, 0x04, 0x00000000 },
102	{ 0x419d10,   1, 0x04, 0x00000014 },
103	{}
104};
105
106const struct gf100_gr_init
107gk104_gr_init_pe_0[] = {
108	{ 0x41980c,   1, 0x04, 0x00000010 },
109	{ 0x419844,   1, 0x04, 0x00000000 },
110	{ 0x419850,   1, 0x04, 0x00000004 },
111	{ 0x419854,   2, 0x04, 0x00000000 },
112	{}
113};
114
115static const struct gf100_gr_init
116gk104_gr_init_l1c_0[] = {
117	{ 0x419c98,   1, 0x04, 0x00000000 },
118	{ 0x419ca8,   1, 0x04, 0x00000000 },
119	{ 0x419cb0,   1, 0x04, 0x01000000 },
120	{ 0x419cb4,   1, 0x04, 0x00000000 },
121	{ 0x419cb8,   1, 0x04, 0x00b08bea },
122	{ 0x419c84,   1, 0x04, 0x00010384 },
123	{ 0x419cbc,   1, 0x04, 0x28137646 },
124	{ 0x419cc0,   2, 0x04, 0x00000000 },
125	{ 0x419c80,   1, 0x04, 0x00020232 },
126	{}
127};
128
129static const struct gf100_gr_init
130gk104_gr_init_sm_0[] = {
131	{ 0x419e00,   1, 0x04, 0x00000000 },
132	{ 0x419ea0,   1, 0x04, 0x00000000 },
133	{ 0x419ee4,   1, 0x04, 0x00000000 },
134	{ 0x419ea4,   1, 0x04, 0x00000100 },
135	{ 0x419ea8,   1, 0x04, 0x00000000 },
136	{ 0x419eb4,   4, 0x04, 0x00000000 },
137	{ 0x419edc,   1, 0x04, 0x00000000 },
138	{ 0x419f00,   1, 0x04, 0x00000000 },
139	{ 0x419f74,   1, 0x04, 0x00000555 },
140	{}
141};
142
143const struct gf100_gr_init
144gk104_gr_init_be_0[] = {
145	{ 0x40880c,   1, 0x04, 0x00000000 },
146	{ 0x408850,   1, 0x04, 0x00000004 },
147	{ 0x408910,   9, 0x04, 0x00000000 },
148	{ 0x408950,   1, 0x04, 0x00000000 },
149	{ 0x408954,   1, 0x04, 0x0000ffff },
150	{ 0x408958,   1, 0x04, 0x00000034 },
151	{ 0x408984,   1, 0x04, 0x00000000 },
152	{ 0x408988,   1, 0x04, 0x08040201 },
153	{ 0x40898c,   1, 0x04, 0x80402010 },
154	{}
155};
156
157const struct gf100_gr_pack
158gk104_gr_pack_mmio[] = {
159	{ gk104_gr_init_main_0 },
160	{ gf100_gr_init_fe_0 },
161	{ gf100_gr_init_pri_0 },
162	{ gf100_gr_init_rstr2d_0 },
163	{ gf119_gr_init_pd_0 },
164	{ gk104_gr_init_ds_0 },
165	{ gf100_gr_init_scc_0 },
166	{ gk104_gr_init_sked_0 },
167	{ gk104_gr_init_cwd_0 },
168	{ gf119_gr_init_prop_0 },
169	{ gf108_gr_init_gpc_unk_0 },
170	{ gf100_gr_init_setup_0 },
171	{ gf100_gr_init_crstr_0 },
172	{ gf108_gr_init_setup_1 },
173	{ gf100_gr_init_zcull_0 },
174	{ gf119_gr_init_gpm_0 },
175	{ gk104_gr_init_gpc_unk_1 },
176	{ gf100_gr_init_gcc_0 },
177	{ gk104_gr_init_tpccs_0 },
178	{ gf119_gr_init_tex_0 },
179	{ gk104_gr_init_pe_0 },
180	{ gk104_gr_init_l1c_0 },
181	{ gf100_gr_init_mpc_0 },
182	{ gk104_gr_init_sm_0 },
183	{ gf117_gr_init_pes_0 },
184	{ gf117_gr_init_wwdx_0 },
185	{ gf117_gr_init_cbm_0 },
186	{ gk104_gr_init_be_0 },
187	{ gf100_gr_init_fe_1 },
188	{}
189};
190
191/*******************************************************************************
192 * PGRAPH engine/subdev functions
193 ******************************************************************************/
194
195int
196gk104_gr_init(struct nvkm_object *object)
197{
198	struct gf100_gr_oclass *oclass = (void *)object->oclass;
199	struct gf100_gr_priv *priv = (void *)object;
200	struct nvkm_pmu *pmu = nvkm_pmu(priv);
201	const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, priv->tpc_total);
202	u32 data[TPC_MAX / 8] = {};
203	u8  tpcnr[GPC_MAX];
204	int gpc, tpc, rop;
205	int ret, i;
206
207	if (pmu)
208		pmu->pgob(pmu, false);
209
210	ret = nvkm_gr_init(&priv->base);
211	if (ret)
212		return ret;
213
214	nv_wr32(priv, GPC_BCAST(0x0880), 0x00000000);
215	nv_wr32(priv, GPC_BCAST(0x08a4), 0x00000000);
216	nv_wr32(priv, GPC_BCAST(0x0888), 0x00000000);
217	nv_wr32(priv, GPC_BCAST(0x088c), 0x00000000);
218	nv_wr32(priv, GPC_BCAST(0x0890), 0x00000000);
219	nv_wr32(priv, GPC_BCAST(0x0894), 0x00000000);
220	nv_wr32(priv, GPC_BCAST(0x08b4), priv->unk4188b4->addr >> 8);
221	nv_wr32(priv, GPC_BCAST(0x08b8), priv->unk4188b8->addr >> 8);
222
223	gf100_gr_mmio(priv, oclass->mmio);
224
225	nv_wr32(priv, GPC_UNIT(0, 0x3018), 0x00000001);
226
227	memset(data, 0x00, sizeof(data));
228	memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr));
229	for (i = 0, gpc = -1; i < priv->tpc_total; i++) {
230		do {
231			gpc = (gpc + 1) % priv->gpc_nr;
232		} while (!tpcnr[gpc]);
233		tpc = priv->tpc_nr[gpc] - tpcnr[gpc]--;
234
235		data[i / 8] |= tpc << ((i % 8) * 4);
236	}
237
238	nv_wr32(priv, GPC_BCAST(0x0980), data[0]);
239	nv_wr32(priv, GPC_BCAST(0x0984), data[1]);
240	nv_wr32(priv, GPC_BCAST(0x0988), data[2]);
241	nv_wr32(priv, GPC_BCAST(0x098c), data[3]);
242
243	for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
244		nv_wr32(priv, GPC_UNIT(gpc, 0x0914),
245			priv->magic_not_rop_nr << 8 | priv->tpc_nr[gpc]);
246		nv_wr32(priv, GPC_UNIT(gpc, 0x0910), 0x00040000 |
247			priv->tpc_total);
248		nv_wr32(priv, GPC_UNIT(gpc, 0x0918), magicgpc918);
249	}
250
251	nv_wr32(priv, GPC_BCAST(0x3fd4), magicgpc918);
252	nv_wr32(priv, GPC_BCAST(0x08ac), nv_rd32(priv, 0x100800));
253
254	nv_wr32(priv, 0x400500, 0x00010001);
255
256	nv_wr32(priv, 0x400100, 0xffffffff);
257	nv_wr32(priv, 0x40013c, 0xffffffff);
258
259	nv_wr32(priv, 0x409ffc, 0x00000000);
260	nv_wr32(priv, 0x409c14, 0x00003e3e);
261	nv_wr32(priv, 0x409c24, 0x000f0001);
262	nv_wr32(priv, 0x404000, 0xc0000000);
263	nv_wr32(priv, 0x404600, 0xc0000000);
264	nv_wr32(priv, 0x408030, 0xc0000000);
265	nv_wr32(priv, 0x404490, 0xc0000000);
266	nv_wr32(priv, 0x406018, 0xc0000000);
267	nv_wr32(priv, 0x407020, 0x40000000);
268	nv_wr32(priv, 0x405840, 0xc0000000);
269	nv_wr32(priv, 0x405844, 0x00ffffff);
270	nv_mask(priv, 0x419cc0, 0x00000008, 0x00000008);
271	nv_mask(priv, 0x419eb4, 0x00001000, 0x00001000);
272
273	for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
274		nv_wr32(priv, GPC_UNIT(gpc, 0x3038), 0xc0000000);
275		nv_wr32(priv, GPC_UNIT(gpc, 0x0420), 0xc0000000);
276		nv_wr32(priv, GPC_UNIT(gpc, 0x0900), 0xc0000000);
277		nv_wr32(priv, GPC_UNIT(gpc, 0x1028), 0xc0000000);
278		nv_wr32(priv, GPC_UNIT(gpc, 0x0824), 0xc0000000);
279		for (tpc = 0; tpc < priv->tpc_nr[gpc]; tpc++) {
280			nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff);
281			nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff);
282			nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000);
283			nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000);
284			nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000);
285			nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x644), 0x001ffffe);
286			nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x64c), 0x0000000f);
287		}
288		nv_wr32(priv, GPC_UNIT(gpc, 0x2c90), 0xffffffff);
289		nv_wr32(priv, GPC_UNIT(gpc, 0x2c94), 0xffffffff);
290	}
291
292	for (rop = 0; rop < priv->rop_nr; rop++) {
293		nv_wr32(priv, ROP_UNIT(rop, 0x144), 0xc0000000);
294		nv_wr32(priv, ROP_UNIT(rop, 0x070), 0xc0000000);
295		nv_wr32(priv, ROP_UNIT(rop, 0x204), 0xffffffff);
296		nv_wr32(priv, ROP_UNIT(rop, 0x208), 0xffffffff);
297	}
298
299	nv_wr32(priv, 0x400108, 0xffffffff);
300	nv_wr32(priv, 0x400138, 0xffffffff);
301	nv_wr32(priv, 0x400118, 0xffffffff);
302	nv_wr32(priv, 0x400130, 0xffffffff);
303	nv_wr32(priv, 0x40011c, 0xffffffff);
304	nv_wr32(priv, 0x400134, 0xffffffff);
305
306	nv_wr32(priv, 0x400054, 0x34ce3464);
307
308	gf100_gr_zbc_init(priv);
309
310	return gf100_gr_init_ctxctl(priv);
311}
312
313int
314gk104_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
315	      struct nvkm_oclass *oclass, void *data, u32 size,
316	      struct nvkm_object **pobject)
317{
318	struct nvkm_pmu *pmu = nvkm_pmu(parent);
319	if (pmu)
320		pmu->pgob(pmu, false);
321	return gf100_gr_ctor(parent, engine, oclass, data, size, pobject);
322}
323
324#include "fuc/hubgk104.fuc3.h"
325
326static struct gf100_gr_ucode
327gk104_gr_fecs_ucode = {
328	.code.data = gk104_grhub_code,
329	.code.size = sizeof(gk104_grhub_code),
330	.data.data = gk104_grhub_data,
331	.data.size = sizeof(gk104_grhub_data),
332};
333
334#include "fuc/gpcgk104.fuc3.h"
335
336static struct gf100_gr_ucode
337gk104_gr_gpccs_ucode = {
338	.code.data = gk104_grgpc_code,
339	.code.size = sizeof(gk104_grgpc_code),
340	.data.data = gk104_grgpc_data,
341	.data.size = sizeof(gk104_grgpc_data),
342};
343
344struct nvkm_oclass *
345gk104_gr_oclass = &(struct gf100_gr_oclass) {
346	.base.handle = NV_ENGINE(GR, 0xe4),
347	.base.ofuncs = &(struct nvkm_ofuncs) {
348		.ctor = gk104_gr_ctor,
349		.dtor = gf100_gr_dtor,
350		.init = gk104_gr_init,
351		.fini = _nvkm_gr_fini,
352	},
353	.cclass = &gk104_grctx_oclass,
354	.sclass = gk104_gr_sclass,
355	.mmio = gk104_gr_pack_mmio,
356	.fecs.ucode = &gk104_gr_fecs_ucode,
357	.gpccs.ucode = &gk104_gr_gpccs_ucode,
358	.ppc_nr = 1,
359}.base;
360