1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24#include <engine/mpeg.h>
25
26#include <subdev/bar.h>
27#include <subdev/timer.h>
28
29struct nv50_mpeg_priv {
30	struct nvkm_mpeg base;
31};
32
33struct nv50_mpeg_chan {
34	struct nvkm_mpeg_chan base;
35};
36
37/*******************************************************************************
38 * MPEG object classes
39 ******************************************************************************/
40
41static int
42nv50_mpeg_object_ctor(struct nvkm_object *parent,
43		      struct nvkm_object *engine,
44		      struct nvkm_oclass *oclass, void *data, u32 size,
45		      struct nvkm_object **pobject)
46{
47	struct nvkm_gpuobj *obj;
48	int ret;
49
50	ret = nvkm_gpuobj_create(parent, engine, oclass, 0, parent,
51				 16, 16, 0, &obj);
52	*pobject = nv_object(obj);
53	if (ret)
54		return ret;
55
56	nv_wo32(obj, 0x00, nv_mclass(obj));
57	nv_wo32(obj, 0x04, 0x00000000);
58	nv_wo32(obj, 0x08, 0x00000000);
59	nv_wo32(obj, 0x0c, 0x00000000);
60	return 0;
61}
62
63struct nvkm_ofuncs
64nv50_mpeg_ofuncs = {
65	.ctor = nv50_mpeg_object_ctor,
66	.dtor = _nvkm_gpuobj_dtor,
67	.init = _nvkm_gpuobj_init,
68	.fini = _nvkm_gpuobj_fini,
69	.rd32 = _nvkm_gpuobj_rd32,
70	.wr32 = _nvkm_gpuobj_wr32,
71};
72
73static struct nvkm_oclass
74nv50_mpeg_sclass[] = {
75	{ 0x3174, &nv50_mpeg_ofuncs },
76	{}
77};
78
79/*******************************************************************************
80 * PMPEG context
81 ******************************************************************************/
82
83int
84nv50_mpeg_context_ctor(struct nvkm_object *parent,
85		       struct nvkm_object *engine,
86		       struct nvkm_oclass *oclass, void *data, u32 size,
87		       struct nvkm_object **pobject)
88{
89	struct nvkm_bar *bar = nvkm_bar(parent);
90	struct nv50_mpeg_chan *chan;
91	int ret;
92
93	ret = nvkm_mpeg_context_create(parent, engine, oclass, NULL, 128 * 4,
94				       0, NVOBJ_FLAG_ZERO_ALLOC, &chan);
95	*pobject = nv_object(chan);
96	if (ret)
97		return ret;
98
99	nv_wo32(chan, 0x0070, 0x00801ec1);
100	nv_wo32(chan, 0x007c, 0x0000037c);
101	bar->flush(bar);
102	return 0;
103}
104
105static struct nvkm_oclass
106nv50_mpeg_cclass = {
107	.handle = NV_ENGCTX(MPEG, 0x50),
108	.ofuncs = &(struct nvkm_ofuncs) {
109		.ctor = nv50_mpeg_context_ctor,
110		.dtor = _nvkm_mpeg_context_dtor,
111		.init = _nvkm_mpeg_context_init,
112		.fini = _nvkm_mpeg_context_fini,
113		.rd32 = _nvkm_mpeg_context_rd32,
114		.wr32 = _nvkm_mpeg_context_wr32,
115	},
116};
117
118/*******************************************************************************
119 * PMPEG engine/subdev functions
120 ******************************************************************************/
121
122void
123nv50_mpeg_intr(struct nvkm_subdev *subdev)
124{
125	struct nv50_mpeg_priv *priv = (void *)subdev;
126	u32 stat = nv_rd32(priv, 0x00b100);
127	u32 type = nv_rd32(priv, 0x00b230);
128	u32 mthd = nv_rd32(priv, 0x00b234);
129	u32 data = nv_rd32(priv, 0x00b238);
130	u32 show = stat;
131
132	if (stat & 0x01000000) {
133		/* happens on initial binding of the object */
134		if (type == 0x00000020 && mthd == 0x0000) {
135			nv_wr32(priv, 0x00b308, 0x00000100);
136			show &= ~0x01000000;
137		}
138	}
139
140	if (show) {
141		nv_info(priv, "0x%08x 0x%08x 0x%08x 0x%08x\n",
142			stat, type, mthd, data);
143	}
144
145	nv_wr32(priv, 0x00b100, stat);
146	nv_wr32(priv, 0x00b230, 0x00000001);
147}
148
149static void
150nv50_vpe_intr(struct nvkm_subdev *subdev)
151{
152	struct nv50_mpeg_priv *priv = (void *)subdev;
153
154	if (nv_rd32(priv, 0x00b100))
155		nv50_mpeg_intr(subdev);
156
157	if (nv_rd32(priv, 0x00b800)) {
158		u32 stat = nv_rd32(priv, 0x00b800);
159		nv_info(priv, "PMSRCH: 0x%08x\n", stat);
160		nv_wr32(priv, 0xb800, stat);
161	}
162}
163
164static int
165nv50_mpeg_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
166	       struct nvkm_oclass *oclass, void *data, u32 size,
167	       struct nvkm_object **pobject)
168{
169	struct nv50_mpeg_priv *priv;
170	int ret;
171
172	ret = nvkm_mpeg_create(parent, engine, oclass, &priv);
173	*pobject = nv_object(priv);
174	if (ret)
175		return ret;
176
177	nv_subdev(priv)->unit = 0x00400002;
178	nv_subdev(priv)->intr = nv50_vpe_intr;
179	nv_engine(priv)->cclass = &nv50_mpeg_cclass;
180	nv_engine(priv)->sclass = nv50_mpeg_sclass;
181	return 0;
182}
183
184int
185nv50_mpeg_init(struct nvkm_object *object)
186{
187	struct nv50_mpeg_priv *priv = (void *)object;
188	int ret;
189
190	ret = nvkm_mpeg_init(&priv->base);
191	if (ret)
192		return ret;
193
194	nv_wr32(priv, 0x00b32c, 0x00000000);
195	nv_wr32(priv, 0x00b314, 0x00000100);
196	nv_wr32(priv, 0x00b0e0, 0x0000001a);
197
198	nv_wr32(priv, 0x00b220, 0x00000044);
199	nv_wr32(priv, 0x00b300, 0x00801ec1);
200	nv_wr32(priv, 0x00b390, 0x00000000);
201	nv_wr32(priv, 0x00b394, 0x00000000);
202	nv_wr32(priv, 0x00b398, 0x00000000);
203	nv_mask(priv, 0x00b32c, 0x00000001, 0x00000001);
204
205	nv_wr32(priv, 0x00b100, 0xffffffff);
206	nv_wr32(priv, 0x00b140, 0xffffffff);
207
208	if (!nv_wait(priv, 0x00b200, 0x00000001, 0x00000000)) {
209		nv_error(priv, "timeout 0x%08x\n", nv_rd32(priv, 0x00b200));
210		return -EBUSY;
211	}
212
213	return 0;
214}
215
216struct nvkm_oclass
217nv50_mpeg_oclass = {
218	.handle = NV_ENGINE(MPEG, 0x50),
219	.ofuncs = &(struct nvkm_ofuncs) {
220		.ctor = nv50_mpeg_ctor,
221		.dtor = _nvkm_mpeg_dtor,
222		.init = nv50_mpeg_init,
223		.fini = _nvkm_mpeg_fini,
224	},
225};
226