1/* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24#include "gf100.h" 25#include "ctxgf100.h" 26#include "fuc/os.h" 27 28#include <core/client.h> 29#include <core/device.h> 30#include <core/handle.h> 31#include <core/option.h> 32#include <engine/fifo.h> 33#include <subdev/fb.h> 34#include <subdev/mc.h> 35#include <subdev/timer.h> 36 37#include <nvif/class.h> 38#include <nvif/unpack.h> 39 40/******************************************************************************* 41 * Zero Bandwidth Clear 42 ******************************************************************************/ 43 44static void 45gf100_gr_zbc_clear_color(struct gf100_gr_priv *priv, int zbc) 46{ 47 if (priv->zbc_color[zbc].format) { 48 nv_wr32(priv, 0x405804, priv->zbc_color[zbc].ds[0]); 49 nv_wr32(priv, 0x405808, priv->zbc_color[zbc].ds[1]); 50 nv_wr32(priv, 0x40580c, priv->zbc_color[zbc].ds[2]); 51 nv_wr32(priv, 0x405810, priv->zbc_color[zbc].ds[3]); 52 } 53 nv_wr32(priv, 0x405814, priv->zbc_color[zbc].format); 54 nv_wr32(priv, 0x405820, zbc); 55 nv_wr32(priv, 0x405824, 0x00000004); /* TRIGGER | WRITE | COLOR */ 56} 57 58static int 59gf100_gr_zbc_color_get(struct gf100_gr_priv *priv, int format, 60 const u32 ds[4], const u32 l2[4]) 61{ 62 struct nvkm_ltc *ltc = nvkm_ltc(priv); 63 int zbc = -ENOSPC, i; 64 65 for (i = ltc->zbc_min; i <= ltc->zbc_max; i++) { 66 if (priv->zbc_color[i].format) { 67 if (priv->zbc_color[i].format != format) 68 continue; 69 if (memcmp(priv->zbc_color[i].ds, ds, sizeof( 70 priv->zbc_color[i].ds))) 71 continue; 72 if (memcmp(priv->zbc_color[i].l2, l2, sizeof( 73 priv->zbc_color[i].l2))) { 74 WARN_ON(1); 75 return -EINVAL; 76 } 77 return i; 78 } else { 79 zbc = (zbc < 0) ? i : zbc; 80 } 81 } 82 83 if (zbc < 0) 84 return zbc; 85 86 memcpy(priv->zbc_color[zbc].ds, ds, sizeof(priv->zbc_color[zbc].ds)); 87 memcpy(priv->zbc_color[zbc].l2, l2, sizeof(priv->zbc_color[zbc].l2)); 88 priv->zbc_color[zbc].format = format; 89 ltc->zbc_color_get(ltc, zbc, l2); 90 gf100_gr_zbc_clear_color(priv, zbc); 91 return zbc; 92} 93 94static void 95gf100_gr_zbc_clear_depth(struct gf100_gr_priv *priv, int zbc) 96{ 97 if (priv->zbc_depth[zbc].format) 98 nv_wr32(priv, 0x405818, priv->zbc_depth[zbc].ds); 99 nv_wr32(priv, 0x40581c, priv->zbc_depth[zbc].format); 100 nv_wr32(priv, 0x405820, zbc); 101 nv_wr32(priv, 0x405824, 0x00000005); /* TRIGGER | WRITE | DEPTH */ 102} 103 104static int 105gf100_gr_zbc_depth_get(struct gf100_gr_priv *priv, int format, 106 const u32 ds, const u32 l2) 107{ 108 struct nvkm_ltc *ltc = nvkm_ltc(priv); 109 int zbc = -ENOSPC, i; 110 111 for (i = ltc->zbc_min; i <= ltc->zbc_max; i++) { 112 if (priv->zbc_depth[i].format) { 113 if (priv->zbc_depth[i].format != format) 114 continue; 115 if (priv->zbc_depth[i].ds != ds) 116 continue; 117 if (priv->zbc_depth[i].l2 != l2) { 118 WARN_ON(1); 119 return -EINVAL; 120 } 121 return i; 122 } else { 123 zbc = (zbc < 0) ? i : zbc; 124 } 125 } 126 127 if (zbc < 0) 128 return zbc; 129 130 priv->zbc_depth[zbc].format = format; 131 priv->zbc_depth[zbc].ds = ds; 132 priv->zbc_depth[zbc].l2 = l2; 133 ltc->zbc_depth_get(ltc, zbc, l2); 134 gf100_gr_zbc_clear_depth(priv, zbc); 135 return zbc; 136} 137 138/******************************************************************************* 139 * Graphics object classes 140 ******************************************************************************/ 141 142static int 143gf100_fermi_mthd_zbc_color(struct nvkm_object *object, void *data, u32 size) 144{ 145 struct gf100_gr_priv *priv = (void *)object->engine; 146 union { 147 struct fermi_a_zbc_color_v0 v0; 148 } *args = data; 149 int ret; 150 151 if (nvif_unpack(args->v0, 0, 0, false)) { 152 switch (args->v0.format) { 153 case FERMI_A_ZBC_COLOR_V0_FMT_ZERO: 154 case FERMI_A_ZBC_COLOR_V0_FMT_UNORM_ONE: 155 case FERMI_A_ZBC_COLOR_V0_FMT_RF32_GF32_BF32_AF32: 156 case FERMI_A_ZBC_COLOR_V0_FMT_R16_G16_B16_A16: 157 case FERMI_A_ZBC_COLOR_V0_FMT_RN16_GN16_BN16_AN16: 158 case FERMI_A_ZBC_COLOR_V0_FMT_RS16_GS16_BS16_AS16: 159 case FERMI_A_ZBC_COLOR_V0_FMT_RU16_GU16_BU16_AU16: 160 case FERMI_A_ZBC_COLOR_V0_FMT_RF16_GF16_BF16_AF16: 161 case FERMI_A_ZBC_COLOR_V0_FMT_A8R8G8B8: 162 case FERMI_A_ZBC_COLOR_V0_FMT_A8RL8GL8BL8: 163 case FERMI_A_ZBC_COLOR_V0_FMT_A2B10G10R10: 164 case FERMI_A_ZBC_COLOR_V0_FMT_AU2BU10GU10RU10: 165 case FERMI_A_ZBC_COLOR_V0_FMT_A8B8G8R8: 166 case FERMI_A_ZBC_COLOR_V0_FMT_A8BL8GL8RL8: 167 case FERMI_A_ZBC_COLOR_V0_FMT_AN8BN8GN8RN8: 168 case FERMI_A_ZBC_COLOR_V0_FMT_AS8BS8GS8RS8: 169 case FERMI_A_ZBC_COLOR_V0_FMT_AU8BU8GU8RU8: 170 case FERMI_A_ZBC_COLOR_V0_FMT_A2R10G10B10: 171 case FERMI_A_ZBC_COLOR_V0_FMT_BF10GF11RF11: 172 ret = gf100_gr_zbc_color_get(priv, args->v0.format, 173 args->v0.ds, 174 args->v0.l2); 175 if (ret >= 0) { 176 args->v0.index = ret; 177 return 0; 178 } 179 break; 180 default: 181 return -EINVAL; 182 } 183 } 184 185 return ret; 186} 187 188static int 189gf100_fermi_mthd_zbc_depth(struct nvkm_object *object, void *data, u32 size) 190{ 191 struct gf100_gr_priv *priv = (void *)object->engine; 192 union { 193 struct fermi_a_zbc_depth_v0 v0; 194 } *args = data; 195 int ret; 196 197 if (nvif_unpack(args->v0, 0, 0, false)) { 198 switch (args->v0.format) { 199 case FERMI_A_ZBC_DEPTH_V0_FMT_FP32: 200 ret = gf100_gr_zbc_depth_get(priv, args->v0.format, 201 args->v0.ds, 202 args->v0.l2); 203 return (ret >= 0) ? 0 : -ENOSPC; 204 default: 205 return -EINVAL; 206 } 207 } 208 209 return ret; 210} 211 212static int 213gf100_fermi_mthd(struct nvkm_object *object, u32 mthd, void *data, u32 size) 214{ 215 switch (mthd) { 216 case FERMI_A_ZBC_COLOR: 217 return gf100_fermi_mthd_zbc_color(object, data, size); 218 case FERMI_A_ZBC_DEPTH: 219 return gf100_fermi_mthd_zbc_depth(object, data, size); 220 default: 221 break; 222 } 223 return -EINVAL; 224} 225 226struct nvkm_ofuncs 227gf100_fermi_ofuncs = { 228 .ctor = _nvkm_object_ctor, 229 .dtor = nvkm_object_destroy, 230 .init = nvkm_object_init, 231 .fini = nvkm_object_fini, 232 .mthd = gf100_fermi_mthd, 233}; 234 235static int 236gf100_gr_set_shader_exceptions(struct nvkm_object *object, u32 mthd, 237 void *pdata, u32 size) 238{ 239 struct gf100_gr_priv *priv = (void *)object->engine; 240 if (size >= sizeof(u32)) { 241 u32 data = *(u32 *)pdata ? 0xffffffff : 0x00000000; 242 nv_wr32(priv, 0x419e44, data); 243 nv_wr32(priv, 0x419e4c, data); 244 return 0; 245 } 246 return -EINVAL; 247} 248 249struct nvkm_omthds 250gf100_gr_9097_omthds[] = { 251 { 0x1528, 0x1528, gf100_gr_set_shader_exceptions }, 252 {} 253}; 254 255struct nvkm_omthds 256gf100_gr_90c0_omthds[] = { 257 { 0x1528, 0x1528, gf100_gr_set_shader_exceptions }, 258 {} 259}; 260 261struct nvkm_oclass 262gf100_gr_sclass[] = { 263 { FERMI_TWOD_A, &nvkm_object_ofuncs }, 264 { FERMI_MEMORY_TO_MEMORY_FORMAT_A, &nvkm_object_ofuncs }, 265 { FERMI_A, &gf100_fermi_ofuncs, gf100_gr_9097_omthds }, 266 { FERMI_COMPUTE_A, &nvkm_object_ofuncs, gf100_gr_90c0_omthds }, 267 {} 268}; 269 270/******************************************************************************* 271 * PGRAPH context 272 ******************************************************************************/ 273 274int 275gf100_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 276 struct nvkm_oclass *oclass, void *args, u32 size, 277 struct nvkm_object **pobject) 278{ 279 struct nvkm_vm *vm = nvkm_client(parent)->vm; 280 struct gf100_gr_priv *priv = (void *)engine; 281 struct gf100_gr_data *data = priv->mmio_data; 282 struct gf100_gr_mmio *mmio = priv->mmio_list; 283 struct gf100_gr_chan *chan; 284 int ret, i; 285 286 /* allocate memory for context, and fill with default values */ 287 ret = nvkm_gr_context_create(parent, engine, oclass, NULL, 288 priv->size, 0x100, 289 NVOBJ_FLAG_ZERO_ALLOC, &chan); 290 *pobject = nv_object(chan); 291 if (ret) 292 return ret; 293 294 /* allocate memory for a "mmio list" buffer that's used by the HUB 295 * fuc to modify some per-context register settings on first load 296 * of the context. 297 */ 298 ret = nvkm_gpuobj_new(nv_object(chan), NULL, 0x1000, 0x100, 0, 299 &chan->mmio); 300 if (ret) 301 return ret; 302 303 ret = nvkm_gpuobj_map_vm(nv_gpuobj(chan->mmio), vm, 304 NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS, 305 &chan->mmio_vma); 306 if (ret) 307 return ret; 308 309 /* allocate buffers referenced by mmio list */ 310 for (i = 0; data->size && i < ARRAY_SIZE(priv->mmio_data); i++) { 311 ret = nvkm_gpuobj_new(nv_object(chan), NULL, data->size, 312 data->align, 0, &chan->data[i].mem); 313 if (ret) 314 return ret; 315 316 ret = nvkm_gpuobj_map_vm(chan->data[i].mem, vm, data->access, 317 &chan->data[i].vma); 318 if (ret) 319 return ret; 320 321 data++; 322 } 323 324 /* finally, fill in the mmio list and point the context at it */ 325 for (i = 0; mmio->addr && i < ARRAY_SIZE(priv->mmio_list); i++) { 326 u32 addr = mmio->addr; 327 u32 data = mmio->data; 328 329 if (mmio->buffer >= 0) { 330 u64 info = chan->data[mmio->buffer].vma.offset; 331 data |= info >> mmio->shift; 332 } 333 334 nv_wo32(chan->mmio, chan->mmio_nr++ * 4, addr); 335 nv_wo32(chan->mmio, chan->mmio_nr++ * 4, data); 336 mmio++; 337 } 338 339 for (i = 0; i < priv->size; i += 4) 340 nv_wo32(chan, i, priv->data[i / 4]); 341 342 if (!priv->firmware) { 343 nv_wo32(chan, 0x00, chan->mmio_nr / 2); 344 nv_wo32(chan, 0x04, chan->mmio_vma.offset >> 8); 345 } else { 346 nv_wo32(chan, 0xf4, 0); 347 nv_wo32(chan, 0xf8, 0); 348 nv_wo32(chan, 0x10, chan->mmio_nr / 2); 349 nv_wo32(chan, 0x14, lower_32_bits(chan->mmio_vma.offset)); 350 nv_wo32(chan, 0x18, upper_32_bits(chan->mmio_vma.offset)); 351 nv_wo32(chan, 0x1c, 1); 352 nv_wo32(chan, 0x20, 0); 353 nv_wo32(chan, 0x28, 0); 354 nv_wo32(chan, 0x2c, 0); 355 } 356 357 return 0; 358} 359 360void 361gf100_gr_context_dtor(struct nvkm_object *object) 362{ 363 struct gf100_gr_chan *chan = (void *)object; 364 int i; 365 366 for (i = 0; i < ARRAY_SIZE(chan->data); i++) { 367 nvkm_gpuobj_unmap(&chan->data[i].vma); 368 nvkm_gpuobj_ref(NULL, &chan->data[i].mem); 369 } 370 371 nvkm_gpuobj_unmap(&chan->mmio_vma); 372 nvkm_gpuobj_ref(NULL, &chan->mmio); 373 374 nvkm_gr_context_destroy(&chan->base); 375} 376 377/******************************************************************************* 378 * PGRAPH register lists 379 ******************************************************************************/ 380 381const struct gf100_gr_init 382gf100_gr_init_main_0[] = { 383 { 0x400080, 1, 0x04, 0x003083c2 }, 384 { 0x400088, 1, 0x04, 0x00006fe7 }, 385 { 0x40008c, 1, 0x04, 0x00000000 }, 386 { 0x400090, 1, 0x04, 0x00000030 }, 387 { 0x40013c, 1, 0x04, 0x013901f7 }, 388 { 0x400140, 1, 0x04, 0x00000100 }, 389 { 0x400144, 1, 0x04, 0x00000000 }, 390 { 0x400148, 1, 0x04, 0x00000110 }, 391 { 0x400138, 1, 0x04, 0x00000000 }, 392 { 0x400130, 2, 0x04, 0x00000000 }, 393 { 0x400124, 1, 0x04, 0x00000002 }, 394 {} 395}; 396 397const struct gf100_gr_init 398gf100_gr_init_fe_0[] = { 399 { 0x40415c, 1, 0x04, 0x00000000 }, 400 { 0x404170, 1, 0x04, 0x00000000 }, 401 {} 402}; 403 404const struct gf100_gr_init 405gf100_gr_init_pri_0[] = { 406 { 0x404488, 2, 0x04, 0x00000000 }, 407 {} 408}; 409 410const struct gf100_gr_init 411gf100_gr_init_rstr2d_0[] = { 412 { 0x407808, 1, 0x04, 0x00000000 }, 413 {} 414}; 415 416const struct gf100_gr_init 417gf100_gr_init_pd_0[] = { 418 { 0x406024, 1, 0x04, 0x00000000 }, 419 {} 420}; 421 422const struct gf100_gr_init 423gf100_gr_init_ds_0[] = { 424 { 0x405844, 1, 0x04, 0x00ffffff }, 425 { 0x405850, 1, 0x04, 0x00000000 }, 426 { 0x405908, 1, 0x04, 0x00000000 }, 427 {} 428}; 429 430const struct gf100_gr_init 431gf100_gr_init_scc_0[] = { 432 { 0x40803c, 1, 0x04, 0x00000000 }, 433 {} 434}; 435 436const struct gf100_gr_init 437gf100_gr_init_prop_0[] = { 438 { 0x4184a0, 1, 0x04, 0x00000000 }, 439 {} 440}; 441 442const struct gf100_gr_init 443gf100_gr_init_gpc_unk_0[] = { 444 { 0x418604, 1, 0x04, 0x00000000 }, 445 { 0x418680, 1, 0x04, 0x00000000 }, 446 { 0x418714, 1, 0x04, 0x80000000 }, 447 { 0x418384, 1, 0x04, 0x00000000 }, 448 {} 449}; 450 451const struct gf100_gr_init 452gf100_gr_init_setup_0[] = { 453 { 0x418814, 3, 0x04, 0x00000000 }, 454 {} 455}; 456 457const struct gf100_gr_init 458gf100_gr_init_crstr_0[] = { 459 { 0x418b04, 1, 0x04, 0x00000000 }, 460 {} 461}; 462 463const struct gf100_gr_init 464gf100_gr_init_setup_1[] = { 465 { 0x4188c8, 1, 0x04, 0x80000000 }, 466 { 0x4188cc, 1, 0x04, 0x00000000 }, 467 { 0x4188d0, 1, 0x04, 0x00010000 }, 468 { 0x4188d4, 1, 0x04, 0x00000001 }, 469 {} 470}; 471 472const struct gf100_gr_init 473gf100_gr_init_zcull_0[] = { 474 { 0x418910, 1, 0x04, 0x00010001 }, 475 { 0x418914, 1, 0x04, 0x00000301 }, 476 { 0x418918, 1, 0x04, 0x00800000 }, 477 { 0x418980, 1, 0x04, 0x77777770 }, 478 { 0x418984, 3, 0x04, 0x77777777 }, 479 {} 480}; 481 482const struct gf100_gr_init 483gf100_gr_init_gpm_0[] = { 484 { 0x418c04, 1, 0x04, 0x00000000 }, 485 { 0x418c88, 1, 0x04, 0x00000000 }, 486 {} 487}; 488 489const struct gf100_gr_init 490gf100_gr_init_gpc_unk_1[] = { 491 { 0x418d00, 1, 0x04, 0x00000000 }, 492 { 0x418f08, 1, 0x04, 0x00000000 }, 493 { 0x418e00, 1, 0x04, 0x00000050 }, 494 { 0x418e08, 1, 0x04, 0x00000000 }, 495 {} 496}; 497 498const struct gf100_gr_init 499gf100_gr_init_gcc_0[] = { 500 { 0x41900c, 1, 0x04, 0x00000000 }, 501 { 0x419018, 1, 0x04, 0x00000000 }, 502 {} 503}; 504 505const struct gf100_gr_init 506gf100_gr_init_tpccs_0[] = { 507 { 0x419d08, 2, 0x04, 0x00000000 }, 508 { 0x419d10, 1, 0x04, 0x00000014 }, 509 {} 510}; 511 512const struct gf100_gr_init 513gf100_gr_init_tex_0[] = { 514 { 0x419ab0, 1, 0x04, 0x00000000 }, 515 { 0x419ab8, 1, 0x04, 0x000000e7 }, 516 { 0x419abc, 2, 0x04, 0x00000000 }, 517 {} 518}; 519 520const struct gf100_gr_init 521gf100_gr_init_pe_0[] = { 522 { 0x41980c, 3, 0x04, 0x00000000 }, 523 { 0x419844, 1, 0x04, 0x00000000 }, 524 { 0x41984c, 1, 0x04, 0x00005bc5 }, 525 { 0x419850, 4, 0x04, 0x00000000 }, 526 {} 527}; 528 529const struct gf100_gr_init 530gf100_gr_init_l1c_0[] = { 531 { 0x419c98, 1, 0x04, 0x00000000 }, 532 { 0x419ca8, 1, 0x04, 0x80000000 }, 533 { 0x419cb4, 1, 0x04, 0x00000000 }, 534 { 0x419cb8, 1, 0x04, 0x00008bf4 }, 535 { 0x419cbc, 1, 0x04, 0x28137606 }, 536 { 0x419cc0, 2, 0x04, 0x00000000 }, 537 {} 538}; 539 540const struct gf100_gr_init 541gf100_gr_init_wwdx_0[] = { 542 { 0x419bd4, 1, 0x04, 0x00800000 }, 543 { 0x419bdc, 1, 0x04, 0x00000000 }, 544 {} 545}; 546 547const struct gf100_gr_init 548gf100_gr_init_tpccs_1[] = { 549 { 0x419d2c, 1, 0x04, 0x00000000 }, 550 {} 551}; 552 553const struct gf100_gr_init 554gf100_gr_init_mpc_0[] = { 555 { 0x419c0c, 1, 0x04, 0x00000000 }, 556 {} 557}; 558 559static const struct gf100_gr_init 560gf100_gr_init_sm_0[] = { 561 { 0x419e00, 1, 0x04, 0x00000000 }, 562 { 0x419ea0, 1, 0x04, 0x00000000 }, 563 { 0x419ea4, 1, 0x04, 0x00000100 }, 564 { 0x419ea8, 1, 0x04, 0x00001100 }, 565 { 0x419eac, 1, 0x04, 0x11100702 }, 566 { 0x419eb0, 1, 0x04, 0x00000003 }, 567 { 0x419eb4, 4, 0x04, 0x00000000 }, 568 { 0x419ec8, 1, 0x04, 0x06060618 }, 569 { 0x419ed0, 1, 0x04, 0x0eff0e38 }, 570 { 0x419ed4, 1, 0x04, 0x011104f1 }, 571 { 0x419edc, 1, 0x04, 0x00000000 }, 572 { 0x419f00, 1, 0x04, 0x00000000 }, 573 { 0x419f2c, 1, 0x04, 0x00000000 }, 574 {} 575}; 576 577const struct gf100_gr_init 578gf100_gr_init_be_0[] = { 579 { 0x40880c, 1, 0x04, 0x00000000 }, 580 { 0x408910, 9, 0x04, 0x00000000 }, 581 { 0x408950, 1, 0x04, 0x00000000 }, 582 { 0x408954, 1, 0x04, 0x0000ffff }, 583 { 0x408984, 1, 0x04, 0x00000000 }, 584 { 0x408988, 1, 0x04, 0x08040201 }, 585 { 0x40898c, 1, 0x04, 0x80402010 }, 586 {} 587}; 588 589const struct gf100_gr_init 590gf100_gr_init_fe_1[] = { 591 { 0x4040f0, 1, 0x04, 0x00000000 }, 592 {} 593}; 594 595const struct gf100_gr_init 596gf100_gr_init_pe_1[] = { 597 { 0x419880, 1, 0x04, 0x00000002 }, 598 {} 599}; 600 601static const struct gf100_gr_pack 602gf100_gr_pack_mmio[] = { 603 { gf100_gr_init_main_0 }, 604 { gf100_gr_init_fe_0 }, 605 { gf100_gr_init_pri_0 }, 606 { gf100_gr_init_rstr2d_0 }, 607 { gf100_gr_init_pd_0 }, 608 { gf100_gr_init_ds_0 }, 609 { gf100_gr_init_scc_0 }, 610 { gf100_gr_init_prop_0 }, 611 { gf100_gr_init_gpc_unk_0 }, 612 { gf100_gr_init_setup_0 }, 613 { gf100_gr_init_crstr_0 }, 614 { gf100_gr_init_setup_1 }, 615 { gf100_gr_init_zcull_0 }, 616 { gf100_gr_init_gpm_0 }, 617 { gf100_gr_init_gpc_unk_1 }, 618 { gf100_gr_init_gcc_0 }, 619 { gf100_gr_init_tpccs_0 }, 620 { gf100_gr_init_tex_0 }, 621 { gf100_gr_init_pe_0 }, 622 { gf100_gr_init_l1c_0 }, 623 { gf100_gr_init_wwdx_0 }, 624 { gf100_gr_init_tpccs_1 }, 625 { gf100_gr_init_mpc_0 }, 626 { gf100_gr_init_sm_0 }, 627 { gf100_gr_init_be_0 }, 628 { gf100_gr_init_fe_1 }, 629 { gf100_gr_init_pe_1 }, 630 {} 631}; 632 633/******************************************************************************* 634 * PGRAPH engine/subdev functions 635 ******************************************************************************/ 636 637void 638gf100_gr_zbc_init(struct gf100_gr_priv *priv) 639{ 640 const u32 zero[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 641 0x00000000, 0x00000000, 0x00000000, 0x00000000 }; 642 const u32 one[] = { 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000, 643 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff }; 644 const u32 f32_0[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 645 0x00000000, 0x00000000, 0x00000000, 0x00000000 }; 646 const u32 f32_1[] = { 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000, 647 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000 }; 648 struct nvkm_ltc *ltc = nvkm_ltc(priv); 649 int index; 650 651 if (!priv->zbc_color[0].format) { 652 gf100_gr_zbc_color_get(priv, 1, & zero[0], &zero[4]); 653 gf100_gr_zbc_color_get(priv, 2, & one[0], &one[4]); 654 gf100_gr_zbc_color_get(priv, 4, &f32_0[0], &f32_0[4]); 655 gf100_gr_zbc_color_get(priv, 4, &f32_1[0], &f32_1[4]); 656 gf100_gr_zbc_depth_get(priv, 1, 0x00000000, 0x00000000); 657 gf100_gr_zbc_depth_get(priv, 1, 0x3f800000, 0x3f800000); 658 } 659 660 for (index = ltc->zbc_min; index <= ltc->zbc_max; index++) 661 gf100_gr_zbc_clear_color(priv, index); 662 for (index = ltc->zbc_min; index <= ltc->zbc_max; index++) 663 gf100_gr_zbc_clear_depth(priv, index); 664} 665 666void 667gf100_gr_mmio(struct gf100_gr_priv *priv, const struct gf100_gr_pack *p) 668{ 669 const struct gf100_gr_pack *pack; 670 const struct gf100_gr_init *init; 671 672 pack_for_each_init(init, pack, p) { 673 u32 next = init->addr + init->count * init->pitch; 674 u32 addr = init->addr; 675 while (addr < next) { 676 nv_wr32(priv, addr, init->data); 677 addr += init->pitch; 678 } 679 } 680} 681 682void 683gf100_gr_icmd(struct gf100_gr_priv *priv, const struct gf100_gr_pack *p) 684{ 685 const struct gf100_gr_pack *pack; 686 const struct gf100_gr_init *init; 687 u32 data = 0; 688 689 nv_wr32(priv, 0x400208, 0x80000000); 690 691 pack_for_each_init(init, pack, p) { 692 u32 next = init->addr + init->count * init->pitch; 693 u32 addr = init->addr; 694 695 if ((pack == p && init == p->init) || data != init->data) { 696 nv_wr32(priv, 0x400204, init->data); 697 data = init->data; 698 } 699 700 while (addr < next) { 701 nv_wr32(priv, 0x400200, addr); 702 nv_wait(priv, 0x400700, 0x00000002, 0x00000000); 703 addr += init->pitch; 704 } 705 } 706 707 nv_wr32(priv, 0x400208, 0x00000000); 708} 709 710void 711gf100_gr_mthd(struct gf100_gr_priv *priv, const struct gf100_gr_pack *p) 712{ 713 const struct gf100_gr_pack *pack; 714 const struct gf100_gr_init *init; 715 u32 data = 0; 716 717 pack_for_each_init(init, pack, p) { 718 u32 ctrl = 0x80000000 | pack->type; 719 u32 next = init->addr + init->count * init->pitch; 720 u32 addr = init->addr; 721 722 if ((pack == p && init == p->init) || data != init->data) { 723 nv_wr32(priv, 0x40448c, init->data); 724 data = init->data; 725 } 726 727 while (addr < next) { 728 nv_wr32(priv, 0x404488, ctrl | (addr << 14)); 729 addr += init->pitch; 730 } 731 } 732} 733 734u64 735gf100_gr_units(struct nvkm_gr *gr) 736{ 737 struct gf100_gr_priv *priv = (void *)gr; 738 u64 cfg; 739 740 cfg = (u32)priv->gpc_nr; 741 cfg |= (u32)priv->tpc_total << 8; 742 cfg |= (u64)priv->rop_nr << 32; 743 744 return cfg; 745} 746 747static const struct nvkm_enum gk104_sked_error[] = { 748 { 7, "CONSTANT_BUFFER_SIZE" }, 749 { 9, "LOCAL_MEMORY_SIZE_POS" }, 750 { 10, "LOCAL_MEMORY_SIZE_NEG" }, 751 { 11, "WARP_CSTACK_SIZE" }, 752 { 12, "TOTAL_TEMP_SIZE" }, 753 { 13, "REGISTER_COUNT" }, 754 { 18, "TOTAL_THREADS" }, 755 { 20, "PROGRAM_OFFSET" }, 756 { 21, "SHARED_MEMORY_SIZE" }, 757 { 25, "SHARED_CONFIG_TOO_SMALL" }, 758 { 26, "TOTAL_REGISTER_COUNT" }, 759 {} 760}; 761 762static const struct nvkm_enum gf100_gpc_rop_error[] = { 763 { 1, "RT_PITCH_OVERRUN" }, 764 { 4, "RT_WIDTH_OVERRUN" }, 765 { 5, "RT_HEIGHT_OVERRUN" }, 766 { 7, "ZETA_STORAGE_TYPE_MISMATCH" }, 767 { 8, "RT_STORAGE_TYPE_MISMATCH" }, 768 { 10, "RT_LINEAR_MISMATCH" }, 769 {} 770}; 771 772static void 773gf100_gr_trap_gpc_rop(struct gf100_gr_priv *priv, int gpc) 774{ 775 u32 trap[4]; 776 int i; 777 778 trap[0] = nv_rd32(priv, GPC_UNIT(gpc, 0x0420)); 779 trap[1] = nv_rd32(priv, GPC_UNIT(gpc, 0x0434)); 780 trap[2] = nv_rd32(priv, GPC_UNIT(gpc, 0x0438)); 781 trap[3] = nv_rd32(priv, GPC_UNIT(gpc, 0x043c)); 782 783 nv_error(priv, "GPC%d/PROP trap:", gpc); 784 for (i = 0; i <= 29; ++i) { 785 if (!(trap[0] & (1 << i))) 786 continue; 787 pr_cont(" "); 788 nvkm_enum_print(gf100_gpc_rop_error, i); 789 } 790 pr_cont("\n"); 791 792 nv_error(priv, "x = %u, y = %u, format = %x, storage type = %x\n", 793 trap[1] & 0xffff, trap[1] >> 16, (trap[2] >> 8) & 0x3f, 794 trap[3] & 0xff); 795 nv_wr32(priv, GPC_UNIT(gpc, 0x0420), 0xc0000000); 796} 797 798static const struct nvkm_enum gf100_mp_warp_error[] = { 799 { 0x01, "STACK_ERROR" }, 800 { 0x02, "API_STACK_ERROR" }, 801 { 0x03, "RET_EMPTY_STACK_ERROR" }, 802 { 0x04, "PC_WRAP" }, 803 { 0x05, "MISALIGNED_PC" }, 804 { 0x06, "PC_OVERFLOW" }, 805 { 0x07, "MISALIGNED_IMMC_ADDR" }, 806 { 0x08, "MISALIGNED_REG" }, 807 { 0x09, "ILLEGAL_INSTR_ENCODING" }, 808 { 0x0a, "ILLEGAL_SPH_INSTR_COMBO" }, 809 { 0x0b, "ILLEGAL_INSTR_PARAM" }, 810 { 0x0c, "INVALID_CONST_ADDR" }, 811 { 0x0d, "OOR_REG" }, 812 { 0x0e, "OOR_ADDR" }, 813 { 0x0f, "MISALIGNED_ADDR" }, 814 { 0x10, "INVALID_ADDR_SPACE" }, 815 { 0x11, "ILLEGAL_INSTR_PARAM2" }, 816 { 0x12, "INVALID_CONST_ADDR_LDC" }, 817 { 0x13, "GEOMETRY_SM_ERROR" }, 818 { 0x14, "DIVERGENT" }, 819 { 0x15, "WARP_EXIT" }, 820 {} 821}; 822 823static const struct nvkm_bitfield gf100_mp_global_error[] = { 824 { 0x00000001, "SM_TO_SM_FAULT" }, 825 { 0x00000002, "L1_ERROR" }, 826 { 0x00000004, "MULTIPLE_WARP_ERRORS" }, 827 { 0x00000008, "PHYSICAL_STACK_OVERFLOW" }, 828 { 0x00000010, "BPT_INT" }, 829 { 0x00000020, "BPT_PAUSE" }, 830 { 0x00000040, "SINGLE_STEP_COMPLETE" }, 831 { 0x20000000, "ECC_SEC_ERROR" }, 832 { 0x40000000, "ECC_DED_ERROR" }, 833 { 0x80000000, "TIMEOUT" }, 834 {} 835}; 836 837static void 838gf100_gr_trap_mp(struct gf100_gr_priv *priv, int gpc, int tpc) 839{ 840 u32 werr = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x648)); 841 u32 gerr = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x650)); 842 843 nv_error(priv, "GPC%i/TPC%i/MP trap:", gpc, tpc); 844 nvkm_bitfield_print(gf100_mp_global_error, gerr); 845 if (werr) { 846 pr_cont(" "); 847 nvkm_enum_print(gf100_mp_warp_error, werr & 0xffff); 848 } 849 pr_cont("\n"); 850 851 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x648), 0x00000000); 852 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x650), gerr); 853} 854 855static void 856gf100_gr_trap_tpc(struct gf100_gr_priv *priv, int gpc, int tpc) 857{ 858 u32 stat = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x0508)); 859 860 if (stat & 0x00000001) { 861 u32 trap = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x0224)); 862 nv_error(priv, "GPC%d/TPC%d/TEX: 0x%08x\n", gpc, tpc, trap); 863 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x0224), 0xc0000000); 864 stat &= ~0x00000001; 865 } 866 867 if (stat & 0x00000002) { 868 gf100_gr_trap_mp(priv, gpc, tpc); 869 stat &= ~0x00000002; 870 } 871 872 if (stat & 0x00000004) { 873 u32 trap = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x0084)); 874 nv_error(priv, "GPC%d/TPC%d/POLY: 0x%08x\n", gpc, tpc, trap); 875 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x0084), 0xc0000000); 876 stat &= ~0x00000004; 877 } 878 879 if (stat & 0x00000008) { 880 u32 trap = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x048c)); 881 nv_error(priv, "GPC%d/TPC%d/L1C: 0x%08x\n", gpc, tpc, trap); 882 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x048c), 0xc0000000); 883 stat &= ~0x00000008; 884 } 885 886 if (stat) { 887 nv_error(priv, "GPC%d/TPC%d/0x%08x: unknown\n", gpc, tpc, stat); 888 } 889} 890 891static void 892gf100_gr_trap_gpc(struct gf100_gr_priv *priv, int gpc) 893{ 894 u32 stat = nv_rd32(priv, GPC_UNIT(gpc, 0x2c90)); 895 int tpc; 896 897 if (stat & 0x00000001) { 898 gf100_gr_trap_gpc_rop(priv, gpc); 899 stat &= ~0x00000001; 900 } 901 902 if (stat & 0x00000002) { 903 u32 trap = nv_rd32(priv, GPC_UNIT(gpc, 0x0900)); 904 nv_error(priv, "GPC%d/ZCULL: 0x%08x\n", gpc, trap); 905 nv_wr32(priv, GPC_UNIT(gpc, 0x0900), 0xc0000000); 906 stat &= ~0x00000002; 907 } 908 909 if (stat & 0x00000004) { 910 u32 trap = nv_rd32(priv, GPC_UNIT(gpc, 0x1028)); 911 nv_error(priv, "GPC%d/CCACHE: 0x%08x\n", gpc, trap); 912 nv_wr32(priv, GPC_UNIT(gpc, 0x1028), 0xc0000000); 913 stat &= ~0x00000004; 914 } 915 916 if (stat & 0x00000008) { 917 u32 trap = nv_rd32(priv, GPC_UNIT(gpc, 0x0824)); 918 nv_error(priv, "GPC%d/ESETUP: 0x%08x\n", gpc, trap); 919 nv_wr32(priv, GPC_UNIT(gpc, 0x0824), 0xc0000000); 920 stat &= ~0x00000009; 921 } 922 923 for (tpc = 0; tpc < priv->tpc_nr[gpc]; tpc++) { 924 u32 mask = 0x00010000 << tpc; 925 if (stat & mask) { 926 gf100_gr_trap_tpc(priv, gpc, tpc); 927 nv_wr32(priv, GPC_UNIT(gpc, 0x2c90), mask); 928 stat &= ~mask; 929 } 930 } 931 932 if (stat) { 933 nv_error(priv, "GPC%d/0x%08x: unknown\n", gpc, stat); 934 } 935} 936 937static void 938gf100_gr_trap_intr(struct gf100_gr_priv *priv) 939{ 940 u32 trap = nv_rd32(priv, 0x400108); 941 int rop, gpc, i; 942 943 if (trap & 0x00000001) { 944 u32 stat = nv_rd32(priv, 0x404000); 945 nv_error(priv, "DISPATCH 0x%08x\n", stat); 946 nv_wr32(priv, 0x404000, 0xc0000000); 947 nv_wr32(priv, 0x400108, 0x00000001); 948 trap &= ~0x00000001; 949 } 950 951 if (trap & 0x00000002) { 952 u32 stat = nv_rd32(priv, 0x404600); 953 nv_error(priv, "M2MF 0x%08x\n", stat); 954 nv_wr32(priv, 0x404600, 0xc0000000); 955 nv_wr32(priv, 0x400108, 0x00000002); 956 trap &= ~0x00000002; 957 } 958 959 if (trap & 0x00000008) { 960 u32 stat = nv_rd32(priv, 0x408030); 961 nv_error(priv, "CCACHE 0x%08x\n", stat); 962 nv_wr32(priv, 0x408030, 0xc0000000); 963 nv_wr32(priv, 0x400108, 0x00000008); 964 trap &= ~0x00000008; 965 } 966 967 if (trap & 0x00000010) { 968 u32 stat = nv_rd32(priv, 0x405840); 969 nv_error(priv, "SHADER 0x%08x\n", stat); 970 nv_wr32(priv, 0x405840, 0xc0000000); 971 nv_wr32(priv, 0x400108, 0x00000010); 972 trap &= ~0x00000010; 973 } 974 975 if (trap & 0x00000040) { 976 u32 stat = nv_rd32(priv, 0x40601c); 977 nv_error(priv, "UNK6 0x%08x\n", stat); 978 nv_wr32(priv, 0x40601c, 0xc0000000); 979 nv_wr32(priv, 0x400108, 0x00000040); 980 trap &= ~0x00000040; 981 } 982 983 if (trap & 0x00000080) { 984 u32 stat = nv_rd32(priv, 0x404490); 985 nv_error(priv, "MACRO 0x%08x\n", stat); 986 nv_wr32(priv, 0x404490, 0xc0000000); 987 nv_wr32(priv, 0x400108, 0x00000080); 988 trap &= ~0x00000080; 989 } 990 991 if (trap & 0x00000100) { 992 u32 stat = nv_rd32(priv, 0x407020); 993 994 nv_error(priv, "SKED:"); 995 for (i = 0; i <= 29; ++i) { 996 if (!(stat & (1 << i))) 997 continue; 998 pr_cont(" "); 999 nvkm_enum_print(gk104_sked_error, i); 1000 } 1001 pr_cont("\n"); 1002 1003 if (stat & 0x3fffffff) 1004 nv_wr32(priv, 0x407020, 0x40000000); 1005 nv_wr32(priv, 0x400108, 0x00000100); 1006 trap &= ~0x00000100; 1007 } 1008 1009 if (trap & 0x01000000) { 1010 u32 stat = nv_rd32(priv, 0x400118); 1011 for (gpc = 0; stat && gpc < priv->gpc_nr; gpc++) { 1012 u32 mask = 0x00000001 << gpc; 1013 if (stat & mask) { 1014 gf100_gr_trap_gpc(priv, gpc); 1015 nv_wr32(priv, 0x400118, mask); 1016 stat &= ~mask; 1017 } 1018 } 1019 nv_wr32(priv, 0x400108, 0x01000000); 1020 trap &= ~0x01000000; 1021 } 1022 1023 if (trap & 0x02000000) { 1024 for (rop = 0; rop < priv->rop_nr; rop++) { 1025 u32 statz = nv_rd32(priv, ROP_UNIT(rop, 0x070)); 1026 u32 statc = nv_rd32(priv, ROP_UNIT(rop, 0x144)); 1027 nv_error(priv, "ROP%d 0x%08x 0x%08x\n", 1028 rop, statz, statc); 1029 nv_wr32(priv, ROP_UNIT(rop, 0x070), 0xc0000000); 1030 nv_wr32(priv, ROP_UNIT(rop, 0x144), 0xc0000000); 1031 } 1032 nv_wr32(priv, 0x400108, 0x02000000); 1033 trap &= ~0x02000000; 1034 } 1035 1036 if (trap) { 1037 nv_error(priv, "TRAP UNHANDLED 0x%08x\n", trap); 1038 nv_wr32(priv, 0x400108, trap); 1039 } 1040} 1041 1042static void 1043gf100_gr_ctxctl_debug_unit(struct gf100_gr_priv *priv, u32 base) 1044{ 1045 nv_error(priv, "%06x - done 0x%08x\n", base, 1046 nv_rd32(priv, base + 0x400)); 1047 nv_error(priv, "%06x - stat 0x%08x 0x%08x 0x%08x 0x%08x\n", base, 1048 nv_rd32(priv, base + 0x800), nv_rd32(priv, base + 0x804), 1049 nv_rd32(priv, base + 0x808), nv_rd32(priv, base + 0x80c)); 1050 nv_error(priv, "%06x - stat 0x%08x 0x%08x 0x%08x 0x%08x\n", base, 1051 nv_rd32(priv, base + 0x810), nv_rd32(priv, base + 0x814), 1052 nv_rd32(priv, base + 0x818), nv_rd32(priv, base + 0x81c)); 1053} 1054 1055void 1056gf100_gr_ctxctl_debug(struct gf100_gr_priv *priv) 1057{ 1058 u32 gpcnr = nv_rd32(priv, 0x409604) & 0xffff; 1059 u32 gpc; 1060 1061 gf100_gr_ctxctl_debug_unit(priv, 0x409000); 1062 for (gpc = 0; gpc < gpcnr; gpc++) 1063 gf100_gr_ctxctl_debug_unit(priv, 0x502000 + (gpc * 0x8000)); 1064} 1065 1066static void 1067gf100_gr_ctxctl_isr(struct gf100_gr_priv *priv) 1068{ 1069 u32 stat = nv_rd32(priv, 0x409c18); 1070 1071 if (stat & 0x00000001) { 1072 u32 code = nv_rd32(priv, 0x409814); 1073 if (code == E_BAD_FWMTHD) { 1074 u32 class = nv_rd32(priv, 0x409808); 1075 u32 addr = nv_rd32(priv, 0x40980c); 1076 u32 subc = (addr & 0x00070000) >> 16; 1077 u32 mthd = (addr & 0x00003ffc); 1078 u32 data = nv_rd32(priv, 0x409810); 1079 1080 nv_error(priv, "FECS MTHD subc %d class 0x%04x " 1081 "mthd 0x%04x data 0x%08x\n", 1082 subc, class, mthd, data); 1083 1084 nv_wr32(priv, 0x409c20, 0x00000001); 1085 stat &= ~0x00000001; 1086 } else { 1087 nv_error(priv, "FECS ucode error %d\n", code); 1088 } 1089 } 1090 1091 if (stat & 0x00080000) { 1092 nv_error(priv, "FECS watchdog timeout\n"); 1093 gf100_gr_ctxctl_debug(priv); 1094 nv_wr32(priv, 0x409c20, 0x00080000); 1095 stat &= ~0x00080000; 1096 } 1097 1098 if (stat) { 1099 nv_error(priv, "FECS 0x%08x\n", stat); 1100 gf100_gr_ctxctl_debug(priv); 1101 nv_wr32(priv, 0x409c20, stat); 1102 } 1103} 1104 1105static void 1106gf100_gr_intr(struct nvkm_subdev *subdev) 1107{ 1108 struct nvkm_fifo *pfifo = nvkm_fifo(subdev); 1109 struct nvkm_engine *engine = nv_engine(subdev); 1110 struct nvkm_object *engctx; 1111 struct nvkm_handle *handle; 1112 struct gf100_gr_priv *priv = (void *)subdev; 1113 u64 inst = nv_rd32(priv, 0x409b00) & 0x0fffffff; 1114 u32 stat = nv_rd32(priv, 0x400100); 1115 u32 addr = nv_rd32(priv, 0x400704); 1116 u32 mthd = (addr & 0x00003ffc); 1117 u32 subc = (addr & 0x00070000) >> 16; 1118 u32 data = nv_rd32(priv, 0x400708); 1119 u32 code = nv_rd32(priv, 0x400110); 1120 u32 class; 1121 int chid; 1122 1123 if (nv_device(priv)->card_type < NV_E0 || subc < 4) 1124 class = nv_rd32(priv, 0x404200 + (subc * 4)); 1125 else 1126 class = 0x0000; 1127 1128 engctx = nvkm_engctx_get(engine, inst); 1129 chid = pfifo->chid(pfifo, engctx); 1130 1131 if (stat & 0x00000001) { 1132 /* 1133 * notifier interrupt, only needed for cyclestats 1134 * can be safely ignored 1135 */ 1136 nv_wr32(priv, 0x400100, 0x00000001); 1137 stat &= ~0x00000001; 1138 } 1139 1140 if (stat & 0x00000010) { 1141 handle = nvkm_handle_get_class(engctx, class); 1142 if (!handle || nv_call(handle->object, mthd, data)) { 1143 nv_error(priv, 1144 "ILLEGAL_MTHD ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n", 1145 chid, inst << 12, nvkm_client_name(engctx), 1146 subc, class, mthd, data); 1147 } 1148 nvkm_handle_put(handle); 1149 nv_wr32(priv, 0x400100, 0x00000010); 1150 stat &= ~0x00000010; 1151 } 1152 1153 if (stat & 0x00000020) { 1154 nv_error(priv, 1155 "ILLEGAL_CLASS ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n", 1156 chid, inst << 12, nvkm_client_name(engctx), subc, 1157 class, mthd, data); 1158 nv_wr32(priv, 0x400100, 0x00000020); 1159 stat &= ~0x00000020; 1160 } 1161 1162 if (stat & 0x00100000) { 1163 nv_error(priv, "DATA_ERROR ["); 1164 nvkm_enum_print(nv50_data_error_names, code); 1165 pr_cont("] ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n", 1166 chid, inst << 12, nvkm_client_name(engctx), subc, 1167 class, mthd, data); 1168 nv_wr32(priv, 0x400100, 0x00100000); 1169 stat &= ~0x00100000; 1170 } 1171 1172 if (stat & 0x00200000) { 1173 nv_error(priv, "TRAP ch %d [0x%010llx %s]\n", chid, inst << 12, 1174 nvkm_client_name(engctx)); 1175 gf100_gr_trap_intr(priv); 1176 nv_wr32(priv, 0x400100, 0x00200000); 1177 stat &= ~0x00200000; 1178 } 1179 1180 if (stat & 0x00080000) { 1181 gf100_gr_ctxctl_isr(priv); 1182 nv_wr32(priv, 0x400100, 0x00080000); 1183 stat &= ~0x00080000; 1184 } 1185 1186 if (stat) { 1187 nv_error(priv, "unknown stat 0x%08x\n", stat); 1188 nv_wr32(priv, 0x400100, stat); 1189 } 1190 1191 nv_wr32(priv, 0x400500, 0x00010001); 1192 nvkm_engctx_put(engctx); 1193} 1194 1195void 1196gf100_gr_init_fw(struct gf100_gr_priv *priv, u32 fuc_base, 1197 struct gf100_gr_fuc *code, struct gf100_gr_fuc *data) 1198{ 1199 int i; 1200 1201 nv_wr32(priv, fuc_base + 0x01c0, 0x01000000); 1202 for (i = 0; i < data->size / 4; i++) 1203 nv_wr32(priv, fuc_base + 0x01c4, data->data[i]); 1204 1205 nv_wr32(priv, fuc_base + 0x0180, 0x01000000); 1206 for (i = 0; i < code->size / 4; i++) { 1207 if ((i & 0x3f) == 0) 1208 nv_wr32(priv, fuc_base + 0x0188, i >> 6); 1209 nv_wr32(priv, fuc_base + 0x0184, code->data[i]); 1210 } 1211 1212 /* code must be padded to 0x40 words */ 1213 for (; i & 0x3f; i++) 1214 nv_wr32(priv, fuc_base + 0x0184, 0); 1215} 1216 1217static void 1218gf100_gr_init_csdata(struct gf100_gr_priv *priv, 1219 const struct gf100_gr_pack *pack, 1220 u32 falcon, u32 starstar, u32 base) 1221{ 1222 const struct gf100_gr_pack *iter; 1223 const struct gf100_gr_init *init; 1224 u32 addr = ~0, prev = ~0, xfer = 0; 1225 u32 star, temp; 1226 1227 nv_wr32(priv, falcon + 0x01c0, 0x02000000 + starstar); 1228 star = nv_rd32(priv, falcon + 0x01c4); 1229 temp = nv_rd32(priv, falcon + 0x01c4); 1230 if (temp > star) 1231 star = temp; 1232 nv_wr32(priv, falcon + 0x01c0, 0x01000000 + star); 1233 1234 pack_for_each_init(init, iter, pack) { 1235 u32 head = init->addr - base; 1236 u32 tail = head + init->count * init->pitch; 1237 while (head < tail) { 1238 if (head != prev + 4 || xfer >= 32) { 1239 if (xfer) { 1240 u32 data = ((--xfer << 26) | addr); 1241 nv_wr32(priv, falcon + 0x01c4, data); 1242 star += 4; 1243 } 1244 addr = head; 1245 xfer = 0; 1246 } 1247 prev = head; 1248 xfer = xfer + 1; 1249 head = head + init->pitch; 1250 } 1251 } 1252 1253 nv_wr32(priv, falcon + 0x01c4, (--xfer << 26) | addr); 1254 nv_wr32(priv, falcon + 0x01c0, 0x01000004 + starstar); 1255 nv_wr32(priv, falcon + 0x01c4, star + 4); 1256} 1257 1258int 1259gf100_gr_init_ctxctl(struct gf100_gr_priv *priv) 1260{ 1261 struct gf100_gr_oclass *oclass = (void *)nv_object(priv)->oclass; 1262 struct gf100_grctx_oclass *cclass = (void *)nv_engine(priv)->cclass; 1263 int i; 1264 1265 if (priv->firmware) { 1266 /* load fuc microcode */ 1267 nvkm_mc(priv)->unk260(nvkm_mc(priv), 0); 1268 gf100_gr_init_fw(priv, 0x409000, &priv->fuc409c, 1269 &priv->fuc409d); 1270 gf100_gr_init_fw(priv, 0x41a000, &priv->fuc41ac, 1271 &priv->fuc41ad); 1272 nvkm_mc(priv)->unk260(nvkm_mc(priv), 1); 1273 1274 /* start both of them running */ 1275 nv_wr32(priv, 0x409840, 0xffffffff); 1276 nv_wr32(priv, 0x41a10c, 0x00000000); 1277 nv_wr32(priv, 0x40910c, 0x00000000); 1278 nv_wr32(priv, 0x41a100, 0x00000002); 1279 nv_wr32(priv, 0x409100, 0x00000002); 1280 if (!nv_wait(priv, 0x409800, 0x00000001, 0x00000001)) 1281 nv_warn(priv, "0x409800 wait failed\n"); 1282 1283 nv_wr32(priv, 0x409840, 0xffffffff); 1284 nv_wr32(priv, 0x409500, 0x7fffffff); 1285 nv_wr32(priv, 0x409504, 0x00000021); 1286 1287 nv_wr32(priv, 0x409840, 0xffffffff); 1288 nv_wr32(priv, 0x409500, 0x00000000); 1289 nv_wr32(priv, 0x409504, 0x00000010); 1290 if (!nv_wait_ne(priv, 0x409800, 0xffffffff, 0x00000000)) { 1291 nv_error(priv, "fuc09 req 0x10 timeout\n"); 1292 return -EBUSY; 1293 } 1294 priv->size = nv_rd32(priv, 0x409800); 1295 1296 nv_wr32(priv, 0x409840, 0xffffffff); 1297 nv_wr32(priv, 0x409500, 0x00000000); 1298 nv_wr32(priv, 0x409504, 0x00000016); 1299 if (!nv_wait_ne(priv, 0x409800, 0xffffffff, 0x00000000)) { 1300 nv_error(priv, "fuc09 req 0x16 timeout\n"); 1301 return -EBUSY; 1302 } 1303 1304 nv_wr32(priv, 0x409840, 0xffffffff); 1305 nv_wr32(priv, 0x409500, 0x00000000); 1306 nv_wr32(priv, 0x409504, 0x00000025); 1307 if (!nv_wait_ne(priv, 0x409800, 0xffffffff, 0x00000000)) { 1308 nv_error(priv, "fuc09 req 0x25 timeout\n"); 1309 return -EBUSY; 1310 } 1311 1312 if (nv_device(priv)->chipset >= 0xe0) { 1313 nv_wr32(priv, 0x409800, 0x00000000); 1314 nv_wr32(priv, 0x409500, 0x00000001); 1315 nv_wr32(priv, 0x409504, 0x00000030); 1316 if (!nv_wait_ne(priv, 0x409800, 0xffffffff, 0x00000000)) { 1317 nv_error(priv, "fuc09 req 0x30 timeout\n"); 1318 return -EBUSY; 1319 } 1320 1321 nv_wr32(priv, 0x409810, 0xb00095c8); 1322 nv_wr32(priv, 0x409800, 0x00000000); 1323 nv_wr32(priv, 0x409500, 0x00000001); 1324 nv_wr32(priv, 0x409504, 0x00000031); 1325 if (!nv_wait_ne(priv, 0x409800, 0xffffffff, 0x00000000)) { 1326 nv_error(priv, "fuc09 req 0x31 timeout\n"); 1327 return -EBUSY; 1328 } 1329 1330 nv_wr32(priv, 0x409810, 0x00080420); 1331 nv_wr32(priv, 0x409800, 0x00000000); 1332 nv_wr32(priv, 0x409500, 0x00000001); 1333 nv_wr32(priv, 0x409504, 0x00000032); 1334 if (!nv_wait_ne(priv, 0x409800, 0xffffffff, 0x00000000)) { 1335 nv_error(priv, "fuc09 req 0x32 timeout\n"); 1336 return -EBUSY; 1337 } 1338 1339 nv_wr32(priv, 0x409614, 0x00000070); 1340 nv_wr32(priv, 0x409614, 0x00000770); 1341 nv_wr32(priv, 0x40802c, 0x00000001); 1342 } 1343 1344 if (priv->data == NULL) { 1345 int ret = gf100_grctx_generate(priv); 1346 if (ret) { 1347 nv_error(priv, "failed to construct context\n"); 1348 return ret; 1349 } 1350 } 1351 1352 return 0; 1353 } else 1354 if (!oclass->fecs.ucode) { 1355 return -ENOSYS; 1356 } 1357 1358 /* load HUB microcode */ 1359 nvkm_mc(priv)->unk260(nvkm_mc(priv), 0); 1360 nv_wr32(priv, 0x4091c0, 0x01000000); 1361 for (i = 0; i < oclass->fecs.ucode->data.size / 4; i++) 1362 nv_wr32(priv, 0x4091c4, oclass->fecs.ucode->data.data[i]); 1363 1364 nv_wr32(priv, 0x409180, 0x01000000); 1365 for (i = 0; i < oclass->fecs.ucode->code.size / 4; i++) { 1366 if ((i & 0x3f) == 0) 1367 nv_wr32(priv, 0x409188, i >> 6); 1368 nv_wr32(priv, 0x409184, oclass->fecs.ucode->code.data[i]); 1369 } 1370 1371 /* load GPC microcode */ 1372 nv_wr32(priv, 0x41a1c0, 0x01000000); 1373 for (i = 0; i < oclass->gpccs.ucode->data.size / 4; i++) 1374 nv_wr32(priv, 0x41a1c4, oclass->gpccs.ucode->data.data[i]); 1375 1376 nv_wr32(priv, 0x41a180, 0x01000000); 1377 for (i = 0; i < oclass->gpccs.ucode->code.size / 4; i++) { 1378 if ((i & 0x3f) == 0) 1379 nv_wr32(priv, 0x41a188, i >> 6); 1380 nv_wr32(priv, 0x41a184, oclass->gpccs.ucode->code.data[i]); 1381 } 1382 nvkm_mc(priv)->unk260(nvkm_mc(priv), 1); 1383 1384 /* load register lists */ 1385 gf100_gr_init_csdata(priv, cclass->hub, 0x409000, 0x000, 0x000000); 1386 gf100_gr_init_csdata(priv, cclass->gpc, 0x41a000, 0x000, 0x418000); 1387 gf100_gr_init_csdata(priv, cclass->tpc, 0x41a000, 0x004, 0x419800); 1388 gf100_gr_init_csdata(priv, cclass->ppc, 0x41a000, 0x008, 0x41be00); 1389 1390 /* start HUB ucode running, it'll init the GPCs */ 1391 nv_wr32(priv, 0x40910c, 0x00000000); 1392 nv_wr32(priv, 0x409100, 0x00000002); 1393 if (!nv_wait(priv, 0x409800, 0x80000000, 0x80000000)) { 1394 nv_error(priv, "HUB_INIT timed out\n"); 1395 gf100_gr_ctxctl_debug(priv); 1396 return -EBUSY; 1397 } 1398 1399 priv->size = nv_rd32(priv, 0x409804); 1400 if (priv->data == NULL) { 1401 int ret = gf100_grctx_generate(priv); 1402 if (ret) { 1403 nv_error(priv, "failed to construct context\n"); 1404 return ret; 1405 } 1406 } 1407 1408 return 0; 1409} 1410 1411int 1412gf100_gr_init(struct nvkm_object *object) 1413{ 1414 struct gf100_gr_oclass *oclass = (void *)object->oclass; 1415 struct gf100_gr_priv *priv = (void *)object; 1416 const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, priv->tpc_total); 1417 u32 data[TPC_MAX / 8] = {}; 1418 u8 tpcnr[GPC_MAX]; 1419 int gpc, tpc, rop; 1420 int ret, i; 1421 1422 ret = nvkm_gr_init(&priv->base); 1423 if (ret) 1424 return ret; 1425 1426 nv_wr32(priv, GPC_BCAST(0x0880), 0x00000000); 1427 nv_wr32(priv, GPC_BCAST(0x08a4), 0x00000000); 1428 nv_wr32(priv, GPC_BCAST(0x0888), 0x00000000); 1429 nv_wr32(priv, GPC_BCAST(0x088c), 0x00000000); 1430 nv_wr32(priv, GPC_BCAST(0x0890), 0x00000000); 1431 nv_wr32(priv, GPC_BCAST(0x0894), 0x00000000); 1432 nv_wr32(priv, GPC_BCAST(0x08b4), priv->unk4188b4->addr >> 8); 1433 nv_wr32(priv, GPC_BCAST(0x08b8), priv->unk4188b8->addr >> 8); 1434 1435 gf100_gr_mmio(priv, oclass->mmio); 1436 1437 memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr)); 1438 for (i = 0, gpc = -1; i < priv->tpc_total; i++) { 1439 do { 1440 gpc = (gpc + 1) % priv->gpc_nr; 1441 } while (!tpcnr[gpc]); 1442 tpc = priv->tpc_nr[gpc] - tpcnr[gpc]--; 1443 1444 data[i / 8] |= tpc << ((i % 8) * 4); 1445 } 1446 1447 nv_wr32(priv, GPC_BCAST(0x0980), data[0]); 1448 nv_wr32(priv, GPC_BCAST(0x0984), data[1]); 1449 nv_wr32(priv, GPC_BCAST(0x0988), data[2]); 1450 nv_wr32(priv, GPC_BCAST(0x098c), data[3]); 1451 1452 for (gpc = 0; gpc < priv->gpc_nr; gpc++) { 1453 nv_wr32(priv, GPC_UNIT(gpc, 0x0914), 1454 priv->magic_not_rop_nr << 8 | priv->tpc_nr[gpc]); 1455 nv_wr32(priv, GPC_UNIT(gpc, 0x0910), 0x00040000 | 1456 priv->tpc_total); 1457 nv_wr32(priv, GPC_UNIT(gpc, 0x0918), magicgpc918); 1458 } 1459 1460 if (nv_device(priv)->chipset != 0xd7) 1461 nv_wr32(priv, GPC_BCAST(0x1bd4), magicgpc918); 1462 else 1463 nv_wr32(priv, GPC_BCAST(0x3fd4), magicgpc918); 1464 1465 nv_wr32(priv, GPC_BCAST(0x08ac), nv_rd32(priv, 0x100800)); 1466 1467 nv_wr32(priv, 0x400500, 0x00010001); 1468 1469 nv_wr32(priv, 0x400100, 0xffffffff); 1470 nv_wr32(priv, 0x40013c, 0xffffffff); 1471 1472 nv_wr32(priv, 0x409c24, 0x000f0000); 1473 nv_wr32(priv, 0x404000, 0xc0000000); 1474 nv_wr32(priv, 0x404600, 0xc0000000); 1475 nv_wr32(priv, 0x408030, 0xc0000000); 1476 nv_wr32(priv, 0x40601c, 0xc0000000); 1477 nv_wr32(priv, 0x404490, 0xc0000000); 1478 nv_wr32(priv, 0x406018, 0xc0000000); 1479 nv_wr32(priv, 0x405840, 0xc0000000); 1480 nv_wr32(priv, 0x405844, 0x00ffffff); 1481 nv_mask(priv, 0x419cc0, 0x00000008, 0x00000008); 1482 nv_mask(priv, 0x419eb4, 0x00001000, 0x00001000); 1483 1484 for (gpc = 0; gpc < priv->gpc_nr; gpc++) { 1485 nv_wr32(priv, GPC_UNIT(gpc, 0x0420), 0xc0000000); 1486 nv_wr32(priv, GPC_UNIT(gpc, 0x0900), 0xc0000000); 1487 nv_wr32(priv, GPC_UNIT(gpc, 0x1028), 0xc0000000); 1488 nv_wr32(priv, GPC_UNIT(gpc, 0x0824), 0xc0000000); 1489 for (tpc = 0; tpc < priv->tpc_nr[gpc]; tpc++) { 1490 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff); 1491 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff); 1492 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000); 1493 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000); 1494 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000); 1495 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x644), 0x001ffffe); 1496 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x64c), 0x0000000f); 1497 } 1498 nv_wr32(priv, GPC_UNIT(gpc, 0x2c90), 0xffffffff); 1499 nv_wr32(priv, GPC_UNIT(gpc, 0x2c94), 0xffffffff); 1500 } 1501 1502 for (rop = 0; rop < priv->rop_nr; rop++) { 1503 nv_wr32(priv, ROP_UNIT(rop, 0x144), 0xc0000000); 1504 nv_wr32(priv, ROP_UNIT(rop, 0x070), 0xc0000000); 1505 nv_wr32(priv, ROP_UNIT(rop, 0x204), 0xffffffff); 1506 nv_wr32(priv, ROP_UNIT(rop, 0x208), 0xffffffff); 1507 } 1508 1509 nv_wr32(priv, 0x400108, 0xffffffff); 1510 nv_wr32(priv, 0x400138, 0xffffffff); 1511 nv_wr32(priv, 0x400118, 0xffffffff); 1512 nv_wr32(priv, 0x400130, 0xffffffff); 1513 nv_wr32(priv, 0x40011c, 0xffffffff); 1514 nv_wr32(priv, 0x400134, 0xffffffff); 1515 1516 nv_wr32(priv, 0x400054, 0x34ce3464); 1517 1518 gf100_gr_zbc_init(priv); 1519 1520 return gf100_gr_init_ctxctl(priv); 1521} 1522 1523static void 1524gf100_gr_dtor_fw(struct gf100_gr_fuc *fuc) 1525{ 1526 kfree(fuc->data); 1527 fuc->data = NULL; 1528} 1529 1530int 1531gf100_gr_ctor_fw(struct gf100_gr_priv *priv, const char *fwname, 1532 struct gf100_gr_fuc *fuc) 1533{ 1534 struct nvkm_device *device = nv_device(priv); 1535 const struct firmware *fw; 1536 char f[32]; 1537 int ret; 1538 1539 snprintf(f, sizeof(f), "nouveau/nv%02x_%s", device->chipset, fwname); 1540 ret = request_firmware(&fw, f, nv_device_base(device)); 1541 if (ret) { 1542 snprintf(f, sizeof(f), "nouveau/%s", fwname); 1543 ret = request_firmware(&fw, f, nv_device_base(device)); 1544 if (ret) { 1545 nv_error(priv, "failed to load %s\n", fwname); 1546 return ret; 1547 } 1548 } 1549 1550 fuc->size = fw->size; 1551 fuc->data = kmemdup(fw->data, fuc->size, GFP_KERNEL); 1552 release_firmware(fw); 1553 return (fuc->data != NULL) ? 0 : -ENOMEM; 1554} 1555 1556void 1557gf100_gr_dtor(struct nvkm_object *object) 1558{ 1559 struct gf100_gr_priv *priv = (void *)object; 1560 1561 kfree(priv->data); 1562 1563 gf100_gr_dtor_fw(&priv->fuc409c); 1564 gf100_gr_dtor_fw(&priv->fuc409d); 1565 gf100_gr_dtor_fw(&priv->fuc41ac); 1566 gf100_gr_dtor_fw(&priv->fuc41ad); 1567 1568 nvkm_gpuobj_ref(NULL, &priv->unk4188b8); 1569 nvkm_gpuobj_ref(NULL, &priv->unk4188b4); 1570 1571 nvkm_gr_destroy(&priv->base); 1572} 1573 1574int 1575gf100_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 1576 struct nvkm_oclass *bclass, void *data, u32 size, 1577 struct nvkm_object **pobject) 1578{ 1579 struct gf100_gr_oclass *oclass = (void *)bclass; 1580 struct nvkm_device *device = nv_device(parent); 1581 struct gf100_gr_priv *priv; 1582 bool use_ext_fw, enable; 1583 int ret, i, j; 1584 1585 use_ext_fw = nvkm_boolopt(device->cfgopt, "NvGrUseFW", 1586 oclass->fecs.ucode == NULL); 1587 enable = use_ext_fw || oclass->fecs.ucode != NULL; 1588 1589 ret = nvkm_gr_create(parent, engine, bclass, enable, &priv); 1590 *pobject = nv_object(priv); 1591 if (ret) 1592 return ret; 1593 1594 nv_subdev(priv)->unit = 0x08001000; 1595 nv_subdev(priv)->intr = gf100_gr_intr; 1596 1597 priv->base.units = gf100_gr_units; 1598 1599 if (use_ext_fw) { 1600 nv_info(priv, "using external firmware\n"); 1601 if (gf100_gr_ctor_fw(priv, "fuc409c", &priv->fuc409c) || 1602 gf100_gr_ctor_fw(priv, "fuc409d", &priv->fuc409d) || 1603 gf100_gr_ctor_fw(priv, "fuc41ac", &priv->fuc41ac) || 1604 gf100_gr_ctor_fw(priv, "fuc41ad", &priv->fuc41ad)) 1605 return -ENODEV; 1606 priv->firmware = true; 1607 } 1608 1609 ret = nvkm_gpuobj_new(nv_object(priv), NULL, 0x1000, 256, 0, 1610 &priv->unk4188b4); 1611 if (ret) 1612 return ret; 1613 1614 ret = nvkm_gpuobj_new(nv_object(priv), NULL, 0x1000, 256, 0, 1615 &priv->unk4188b8); 1616 if (ret) 1617 return ret; 1618 1619 for (i = 0; i < 0x1000; i += 4) { 1620 nv_wo32(priv->unk4188b4, i, 0x00000010); 1621 nv_wo32(priv->unk4188b8, i, 0x00000010); 1622 } 1623 1624 priv->rop_nr = (nv_rd32(priv, 0x409604) & 0x001f0000) >> 16; 1625 priv->gpc_nr = nv_rd32(priv, 0x409604) & 0x0000001f; 1626 for (i = 0; i < priv->gpc_nr; i++) { 1627 priv->tpc_nr[i] = nv_rd32(priv, GPC_UNIT(i, 0x2608)); 1628 priv->tpc_total += priv->tpc_nr[i]; 1629 priv->ppc_nr[i] = oclass->ppc_nr; 1630 for (j = 0; j < priv->ppc_nr[i]; j++) { 1631 u8 mask = nv_rd32(priv, GPC_UNIT(i, 0x0c30 + (j * 4))); 1632 priv->ppc_tpc_nr[i][j] = hweight8(mask); 1633 } 1634 } 1635 1636 /*XXX: these need figuring out... though it might not even matter */ 1637 switch (nv_device(priv)->chipset) { 1638 case 0xc0: 1639 if (priv->tpc_total == 11) { /* 465, 3/4/4/0, 4 */ 1640 priv->magic_not_rop_nr = 0x07; 1641 } else 1642 if (priv->tpc_total == 14) { /* 470, 3/3/4/4, 5 */ 1643 priv->magic_not_rop_nr = 0x05; 1644 } else 1645 if (priv->tpc_total == 15) { /* 480, 3/4/4/4, 6 */ 1646 priv->magic_not_rop_nr = 0x06; 1647 } 1648 break; 1649 case 0xc3: /* 450, 4/0/0/0, 2 */ 1650 priv->magic_not_rop_nr = 0x03; 1651 break; 1652 case 0xc4: /* 460, 3/4/0/0, 4 */ 1653 priv->magic_not_rop_nr = 0x01; 1654 break; 1655 case 0xc1: /* 2/0/0/0, 1 */ 1656 priv->magic_not_rop_nr = 0x01; 1657 break; 1658 case 0xc8: /* 4/4/3/4, 5 */ 1659 priv->magic_not_rop_nr = 0x06; 1660 break; 1661 case 0xce: /* 4/4/0/0, 4 */ 1662 priv->magic_not_rop_nr = 0x03; 1663 break; 1664 case 0xcf: /* 4/0/0/0, 3 */ 1665 priv->magic_not_rop_nr = 0x03; 1666 break; 1667 case 0xd7: 1668 case 0xd9: /* 1/0/0/0, 1 */ 1669 priv->magic_not_rop_nr = 0x01; 1670 break; 1671 } 1672 1673 nv_engine(priv)->cclass = *oclass->cclass; 1674 nv_engine(priv)->sclass = oclass->sclass; 1675 return 0; 1676} 1677 1678#include "fuc/hubgf100.fuc3.h" 1679 1680struct gf100_gr_ucode 1681gf100_gr_fecs_ucode = { 1682 .code.data = gf100_grhub_code, 1683 .code.size = sizeof(gf100_grhub_code), 1684 .data.data = gf100_grhub_data, 1685 .data.size = sizeof(gf100_grhub_data), 1686}; 1687 1688#include "fuc/gpcgf100.fuc3.h" 1689 1690struct gf100_gr_ucode 1691gf100_gr_gpccs_ucode = { 1692 .code.data = gf100_grgpc_code, 1693 .code.size = sizeof(gf100_grgpc_code), 1694 .data.data = gf100_grgpc_data, 1695 .data.size = sizeof(gf100_grgpc_data), 1696}; 1697 1698struct nvkm_oclass * 1699gf100_gr_oclass = &(struct gf100_gr_oclass) { 1700 .base.handle = NV_ENGINE(GR, 0xc0), 1701 .base.ofuncs = &(struct nvkm_ofuncs) { 1702 .ctor = gf100_gr_ctor, 1703 .dtor = gf100_gr_dtor, 1704 .init = gf100_gr_init, 1705 .fini = _nvkm_gr_fini, 1706 }, 1707 .cclass = &gf100_grctx_oclass, 1708 .sclass = gf100_gr_sclass, 1709 .mmio = gf100_gr_pack_mmio, 1710 .fecs.ucode = &gf100_gr_fecs_ucode, 1711 .gpccs.ucode = &gf100_gr_gpccs_ucode, 1712}.base; 1713