1/* 2 * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 20 * DEALINGS IN THE SOFTWARE. 21 */ 22#include <subdev/volt.h> 23#ifdef __KERNEL__ 24#include <nouveau_platform.h> 25#endif 26 27struct cvb_coef { 28 int c0; 29 int c1; 30 int c2; 31 int c3; 32 int c4; 33 int c5; 34}; 35 36struct gk20a_volt_priv { 37 struct nvkm_volt base; 38 struct regulator *vdd; 39}; 40 41const struct cvb_coef gk20a_cvb_coef[] = { 42 /* MHz, c0, c1, c2, c3, c4, c5 */ 43 /* 72 */ { 1209886, -36468, 515, 417, -13123, 203}, 44 /* 108 */ { 1130804, -27659, 296, 298, -10834, 221}, 45 /* 180 */ { 1162871, -27110, 247, 238, -10681, 268}, 46 /* 252 */ { 1220458, -28654, 247, 179, -10376, 298}, 47 /* 324 */ { 1280953, -30204, 247, 119, -9766, 304}, 48 /* 396 */ { 1344547, -31777, 247, 119, -8545, 292}, 49 /* 468 */ { 1420168, -34227, 269, 60, -7172, 256}, 50 /* 540 */ { 1490757, -35955, 274, 60, -5188, 197}, 51 /* 612 */ { 1599112, -42583, 398, 0, -1831, 119}, 52 /* 648 */ { 1366986, -16459, -274, 0, -3204, 72}, 53 /* 684 */ { 1391884, -17078, -274, -60, -1526, 30}, 54 /* 708 */ { 1415522, -17497, -274, -60, -458, 0}, 55 /* 756 */ { 1464061, -18331, -274, -119, 1831, -72}, 56 /* 804 */ { 1524225, -20064, -254, -119, 4272, -155}, 57 /* 852 */ { 1608418, -21643, -269, 0, 763, -48}, 58}; 59 60/** 61 * cvb_mv = ((c2 * speedo / s_scale + c1) * speedo / s_scale + c0) 62 */ 63static inline int 64gk20a_volt_get_cvb_voltage(int speedo, int s_scale, const struct cvb_coef *coef) 65{ 66 int mv; 67 68 mv = DIV_ROUND_CLOSEST(coef->c2 * speedo, s_scale); 69 mv = DIV_ROUND_CLOSEST((mv + coef->c1) * speedo, s_scale) + coef->c0; 70 return mv; 71} 72 73/** 74 * cvb_t_mv = 75 * ((c2 * speedo / s_scale + c1) * speedo / s_scale + c0) + 76 * ((c3 * speedo / s_scale + c4 + c5 * T / t_scale) * T / t_scale) 77 */ 78static inline int 79gk20a_volt_get_cvb_t_voltage(int speedo, int temp, int s_scale, int t_scale, 80 const struct cvb_coef *coef) 81{ 82 int cvb_mv, mv; 83 84 cvb_mv = gk20a_volt_get_cvb_voltage(speedo, s_scale, coef); 85 86 mv = DIV_ROUND_CLOSEST(coef->c3 * speedo, s_scale) + coef->c4 + 87 DIV_ROUND_CLOSEST(coef->c5 * temp, t_scale); 88 mv = DIV_ROUND_CLOSEST(mv * temp, t_scale) + cvb_mv; 89 return mv; 90} 91 92static int 93gk20a_volt_calc_voltage(const struct cvb_coef *coef, int speedo) 94{ 95 int mv; 96 97 mv = gk20a_volt_get_cvb_t_voltage(speedo, -10, 100, 10, coef); 98 mv = DIV_ROUND_UP(mv, 1000); 99 100 return mv * 1000; 101} 102 103static int 104gk20a_volt_vid_get(struct nvkm_volt *volt) 105{ 106 struct gk20a_volt_priv *priv = (void *)volt; 107 int i, uv; 108 109 uv = regulator_get_voltage(priv->vdd); 110 111 for (i = 0; i < volt->vid_nr; i++) 112 if (volt->vid[i].uv >= uv) 113 return i; 114 115 return -EINVAL; 116} 117 118static int 119gk20a_volt_vid_set(struct nvkm_volt *volt, u8 vid) 120{ 121 struct gk20a_volt_priv *priv = (void *)volt; 122 123 nv_debug(volt, "set voltage as %duv\n", volt->vid[vid].uv); 124 return regulator_set_voltage(priv->vdd, volt->vid[vid].uv, 1200000); 125} 126 127static int 128gk20a_volt_set_id(struct nvkm_volt *volt, u8 id, int condition) 129{ 130 struct gk20a_volt_priv *priv = (void *)volt; 131 int prev_uv = regulator_get_voltage(priv->vdd); 132 int target_uv = volt->vid[id].uv; 133 int ret; 134 135 nv_debug(volt, "prev=%d, target=%d, condition=%d\n", 136 prev_uv, target_uv, condition); 137 if (!condition || 138 (condition < 0 && target_uv < prev_uv) || 139 (condition > 0 && target_uv > prev_uv)) { 140 ret = gk20a_volt_vid_set(volt, volt->vid[id].vid); 141 } else { 142 ret = 0; 143 } 144 145 return ret; 146} 147 148static int 149gk20a_volt_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 150 struct nvkm_oclass *oclass, void *data, u32 size, 151 struct nvkm_object **pobject) 152{ 153 struct gk20a_volt_priv *priv; 154 struct nvkm_volt *volt; 155 struct nouveau_platform_device *plat; 156 int i, ret, uv; 157 158 ret = nvkm_volt_create(parent, engine, oclass, &priv); 159 *pobject = nv_object(priv); 160 if (ret) 161 return ret; 162 163 volt = &priv->base; 164 165 plat = nv_device_to_platform(nv_device(parent)); 166 167 uv = regulator_get_voltage(plat->gpu->vdd); 168 nv_info(priv, "The default voltage is %duV\n", uv); 169 170 priv->vdd = plat->gpu->vdd; 171 priv->base.vid_get = gk20a_volt_vid_get; 172 priv->base.vid_set = gk20a_volt_vid_set; 173 priv->base.set_id = gk20a_volt_set_id; 174 175 volt->vid_nr = ARRAY_SIZE(gk20a_cvb_coef); 176 nv_debug(priv, "%s - vid_nr = %d\n", __func__, volt->vid_nr); 177 for (i = 0; i < volt->vid_nr; i++) { 178 volt->vid[i].vid = i; 179 volt->vid[i].uv = gk20a_volt_calc_voltage(&gk20a_cvb_coef[i], 180 plat->gpu_speedo); 181 nv_debug(priv, "%2d: vid=%d, uv=%d\n", i, volt->vid[i].vid, 182 volt->vid[i].uv); 183 } 184 185 return 0; 186} 187 188struct nvkm_oclass 189gk20a_volt_oclass = { 190 .handle = NV_SUBDEV(VOLT, 0xea), 191 .ofuncs = &(struct nvkm_ofuncs) { 192 .ctor = gk20a_volt_ctor, 193 .dtor = _nvkm_volt_dtor, 194 .init = _nvkm_volt_init, 195 .fini = _nvkm_volt_fini, 196 }, 197}; 198