1/* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24#include "priv.h" 25 26#include <subdev/bios.h> 27#include <subdev/bus.h> 28#include <subdev/gpio.h> 29#include <subdev/i2c.h> 30#include <subdev/clk.h> 31#include <subdev/devinit.h> 32#include <subdev/mc.h> 33#include <subdev/timer.h> 34#include <subdev/fb.h> 35#include <subdev/instmem.h> 36#include <subdev/mmu.h> 37 38#include <engine/dmaobj.h> 39#include <engine/fifo.h> 40#include <engine/sw.h> 41#include <engine/gr.h> 42#include <engine/disp.h> 43 44int 45nv10_identify(struct nvkm_device *device) 46{ 47 switch (device->chipset) { 48 case 0x10: 49 device->cname = "NV10"; 50 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; 51 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; 52 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; 53 device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass; 54 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass; 55 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; 56 device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; 57 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 58 device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; 59 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; 60 device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; 61 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 62 device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; 63 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; 64 break; 65 case 0x15: 66 device->cname = "NV15"; 67 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; 68 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; 69 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; 70 device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass; 71 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass; 72 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; 73 device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; 74 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 75 device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; 76 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; 77 device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; 78 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 79 device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; 80 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; 81 device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; 82 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; 83 break; 84 case 0x16: 85 device->cname = "NV16"; 86 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; 87 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; 88 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; 89 device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass; 90 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass; 91 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; 92 device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; 93 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 94 device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; 95 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; 96 device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; 97 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 98 device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; 99 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; 100 device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; 101 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; 102 break; 103 case 0x1a: 104 device->cname = "nForce"; 105 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; 106 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; 107 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; 108 device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass; 109 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; 110 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; 111 device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; 112 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 113 device->oclass[NVDEV_SUBDEV_FB ] = nv1a_fb_oclass; 114 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; 115 device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; 116 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 117 device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; 118 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; 119 device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; 120 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; 121 break; 122 case 0x11: 123 device->cname = "NV11"; 124 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; 125 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; 126 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; 127 device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass; 128 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass; 129 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; 130 device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; 131 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 132 device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; 133 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; 134 device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; 135 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 136 device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; 137 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; 138 device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; 139 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; 140 break; 141 case 0x17: 142 device->cname = "NV17"; 143 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; 144 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; 145 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; 146 device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass; 147 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass; 148 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; 149 device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; 150 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 151 device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; 152 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; 153 device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; 154 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 155 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; 156 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; 157 device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; 158 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; 159 break; 160 case 0x1f: 161 device->cname = "nForce2"; 162 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; 163 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; 164 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; 165 device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass; 166 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; 167 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; 168 device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; 169 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 170 device->oclass[NVDEV_SUBDEV_FB ] = nv1a_fb_oclass; 171 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; 172 device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; 173 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 174 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; 175 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; 176 device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; 177 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; 178 break; 179 case 0x18: 180 device->cname = "NV18"; 181 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; 182 device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; 183 device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; 184 device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass; 185 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass; 186 device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; 187 device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; 188 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; 189 device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; 190 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; 191 device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; 192 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 193 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; 194 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; 195 device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; 196 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; 197 break; 198 default: 199 nv_fatal(device, "unknown Celsius chipset\n"); 200 return -EINVAL; 201 } 202 203 return 0; 204} 205