1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24#include "priv.h"
25
26#include <subdev/bios.h>
27#include <subdev/bus.h>
28#include <subdev/i2c.h>
29#include <subdev/clk.h>
30#include <subdev/devinit.h>
31#include <subdev/mc.h>
32#include <subdev/timer.h>
33#include <subdev/fb.h>
34#include <subdev/instmem.h>
35#include <subdev/mmu.h>
36
37#include <engine/dmaobj.h>
38#include <engine/fifo.h>
39#include <engine/sw.h>
40#include <engine/gr.h>
41#include <engine/disp.h>
42
43int
44nv04_identify(struct nvkm_device *device)
45{
46	switch (device->chipset) {
47	case 0x04:
48		device->cname = "NV04";
49		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nvkm_bios_oclass;
50		device->oclass[NVDEV_SUBDEV_I2C    ] =  nv04_i2c_oclass;
51		device->oclass[NVDEV_SUBDEV_CLK    ] = &nv04_clk_oclass;
52		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv04_devinit_oclass;
53		device->oclass[NVDEV_SUBDEV_MC     ] =  nv04_mc_oclass;
54		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv04_bus_oclass;
55		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
56		device->oclass[NVDEV_SUBDEV_FB     ] =  nv04_fb_oclass;
57		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv04_instmem_oclass;
58		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv04_mmu_oclass;
59		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
60		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv04_fifo_oclass;
61		device->oclass[NVDEV_ENGINE_SW     ] =  nv04_sw_oclass;
62		device->oclass[NVDEV_ENGINE_GR     ] = &nv04_gr_oclass;
63		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
64		break;
65	case 0x05:
66		device->cname = "NV05";
67		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nvkm_bios_oclass;
68		device->oclass[NVDEV_SUBDEV_I2C    ] =  nv04_i2c_oclass;
69		device->oclass[NVDEV_SUBDEV_CLK    ] = &nv04_clk_oclass;
70		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv05_devinit_oclass;
71		device->oclass[NVDEV_SUBDEV_MC     ] =  nv04_mc_oclass;
72		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv04_bus_oclass;
73		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
74		device->oclass[NVDEV_SUBDEV_FB     ] =  nv04_fb_oclass;
75		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv04_instmem_oclass;
76		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv04_mmu_oclass;
77		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
78		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv04_fifo_oclass;
79		device->oclass[NVDEV_ENGINE_SW     ] =  nv04_sw_oclass;
80		device->oclass[NVDEV_ENGINE_GR     ] = &nv04_gr_oclass;
81		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
82		break;
83	default:
84		nv_fatal(device, "unknown RIVA chipset\n");
85		return -EINVAL;
86	}
87
88	return 0;
89}
90