1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24#include "nv04.h"
25
26#include <core/ramht.h>
27
28/******************************************************************************
29 * instmem object implementation
30 *****************************************************************************/
31
32static u32
33nv04_instobj_rd32(struct nvkm_object *object, u64 addr)
34{
35	struct nv04_instmem_priv *priv = (void *)nvkm_instmem(object);
36	struct nv04_instobj_priv *node = (void *)object;
37	return nv_ro32(priv, node->mem->offset + addr);
38}
39
40static void
41nv04_instobj_wr32(struct nvkm_object *object, u64 addr, u32 data)
42{
43	struct nv04_instmem_priv *priv = (void *)nvkm_instmem(object);
44	struct nv04_instobj_priv *node = (void *)object;
45	nv_wo32(priv, node->mem->offset + addr, data);
46}
47
48static void
49nv04_instobj_dtor(struct nvkm_object *object)
50{
51	struct nv04_instmem_priv *priv = (void *)nvkm_instmem(object);
52	struct nv04_instobj_priv *node = (void *)object;
53	struct nvkm_subdev *subdev = (void *)priv;
54
55	mutex_lock(&subdev->mutex);
56	nvkm_mm_free(&priv->heap, &node->mem);
57	mutex_unlock(&subdev->mutex);
58
59	nvkm_instobj_destroy(&node->base);
60}
61
62static int
63nv04_instobj_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
64		  struct nvkm_oclass *oclass, void *data, u32 size,
65		  struct nvkm_object **pobject)
66{
67	struct nv04_instmem_priv *priv = (void *)nvkm_instmem(parent);
68	struct nv04_instobj_priv *node;
69	struct nvkm_instobj_args *args = data;
70	struct nvkm_subdev *subdev = (void *)priv;
71	int ret;
72
73	if (!args->align)
74		args->align = 1;
75
76	ret = nvkm_instobj_create(parent, engine, oclass, &node);
77	*pobject = nv_object(node);
78	if (ret)
79		return ret;
80
81	mutex_lock(&subdev->mutex);
82	ret = nvkm_mm_head(&priv->heap, 0, 1, args->size, args->size,
83			   args->align, &node->mem);
84	mutex_unlock(&subdev->mutex);
85	if (ret)
86		return ret;
87
88	node->base.addr = node->mem->offset;
89	node->base.size = node->mem->length;
90	return 0;
91}
92
93struct nvkm_instobj_impl
94nv04_instobj_oclass = {
95	.base.ofuncs = &(struct nvkm_ofuncs) {
96		.ctor = nv04_instobj_ctor,
97		.dtor = nv04_instobj_dtor,
98		.init = _nvkm_instobj_init,
99		.fini = _nvkm_instobj_fini,
100		.rd32 = nv04_instobj_rd32,
101		.wr32 = nv04_instobj_wr32,
102	},
103};
104
105/******************************************************************************
106 * instmem subdev implementation
107 *****************************************************************************/
108
109static u32
110nv04_instmem_rd32(struct nvkm_object *object, u64 addr)
111{
112	return nv_rd32(object, 0x700000 + addr);
113}
114
115static void
116nv04_instmem_wr32(struct nvkm_object *object, u64 addr, u32 data)
117{
118	return nv_wr32(object, 0x700000 + addr, data);
119}
120
121void
122nv04_instmem_dtor(struct nvkm_object *object)
123{
124	struct nv04_instmem_priv *priv = (void *)object;
125	nvkm_gpuobj_ref(NULL, &priv->ramfc);
126	nvkm_gpuobj_ref(NULL, &priv->ramro);
127	nvkm_ramht_ref(NULL, &priv->ramht);
128	nvkm_gpuobj_ref(NULL, &priv->vbios);
129	nvkm_mm_fini(&priv->heap);
130	if (priv->iomem)
131		iounmap(priv->iomem);
132	nvkm_instmem_destroy(&priv->base);
133}
134
135static int
136nv04_instmem_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
137		  struct nvkm_oclass *oclass, void *data, u32 size,
138		  struct nvkm_object **pobject)
139{
140	struct nv04_instmem_priv *priv;
141	int ret;
142
143	ret = nvkm_instmem_create(parent, engine, oclass, &priv);
144	*pobject = nv_object(priv);
145	if (ret)
146		return ret;
147
148	/* PRAMIN aperture maps over the end of VRAM, reserve it */
149	priv->base.reserved = 512 * 1024;
150
151	ret = nvkm_mm_init(&priv->heap, 0, priv->base.reserved, 1);
152	if (ret)
153		return ret;
154
155	/* 0x00000-0x10000: reserve for probable vbios image */
156	ret = nvkm_gpuobj_new(nv_object(priv), NULL, 0x10000, 0, 0,
157			      &priv->vbios);
158	if (ret)
159		return ret;
160
161	/* 0x10000-0x18000: reserve for RAMHT */
162	ret = nvkm_ramht_new(nv_object(priv), NULL, 0x08000, 0, &priv->ramht);
163	if (ret)
164		return ret;
165
166	/* 0x18000-0x18800: reserve for RAMFC (enough for 32 nv30 channels) */
167	ret = nvkm_gpuobj_new(nv_object(priv), NULL, 0x00800, 0,
168			      NVOBJ_FLAG_ZERO_ALLOC, &priv->ramfc);
169	if (ret)
170		return ret;
171
172	/* 0x18800-0x18a00: reserve for RAMRO */
173	ret = nvkm_gpuobj_new(nv_object(priv), NULL, 0x00200, 0, 0,
174			      &priv->ramro);
175	if (ret)
176		return ret;
177
178	return 0;
179}
180
181struct nvkm_oclass *
182nv04_instmem_oclass = &(struct nvkm_instmem_impl) {
183	.base.handle = NV_SUBDEV(INSTMEM, 0x04),
184	.base.ofuncs = &(struct nvkm_ofuncs) {
185		.ctor = nv04_instmem_ctor,
186		.dtor = nv04_instmem_dtor,
187		.init = _nvkm_instmem_init,
188		.fini = _nvkm_instmem_fini,
189		.rd32 = nv04_instmem_rd32,
190		.wr32 = nv04_instmem_wr32,
191	},
192	.instobj = &nv04_instobj_oclass.base,
193}.base;
194