1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24#include "priv.h"
25
26#include <subdev/bios.h>
27#include <subdev/bus.h>
28#include <subdev/gpio.h>
29#include <subdev/i2c.h>
30#include <subdev/fuse.h>
31#include <subdev/clk.h>
32#include <subdev/therm.h>
33#include <subdev/mxm.h>
34#include <subdev/devinit.h>
35#include <subdev/mc.h>
36#include <subdev/timer.h>
37#include <subdev/fb.h>
38#include <subdev/instmem.h>
39#include <subdev/mmu.h>
40#include <subdev/bar.h>
41#include <subdev/pmu.h>
42#include <subdev/volt.h>
43
44#include <engine/dmaobj.h>
45#include <engine/fifo.h>
46#include <engine/sw.h>
47#include <engine/gr.h>
48#include <engine/mpeg.h>
49#include <engine/vp.h>
50#include <engine/cipher.h>
51#include <engine/sec.h>
52#include <engine/bsp.h>
53#include <engine/msvld.h>
54#include <engine/mspdec.h>
55#include <engine/msppp.h>
56#include <engine/ce.h>
57#include <engine/disp.h>
58#include <engine/pm.h>
59
60int
61nv50_identify(struct nvkm_device *device)
62{
63	switch (device->chipset) {
64	case 0x50:
65		device->cname = "G80";
66		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nvkm_bios_oclass;
67		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv50_gpio_oclass;
68		device->oclass[NVDEV_SUBDEV_I2C    ] =  nv50_i2c_oclass;
69		device->oclass[NVDEV_SUBDEV_FUSE   ] =  &nv50_fuse_oclass;
70		device->oclass[NVDEV_SUBDEV_CLK    ] =  nv50_clk_oclass;
71		device->oclass[NVDEV_SUBDEV_THERM  ] = &nv50_therm_oclass;
72		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
73		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv50_devinit_oclass;
74		device->oclass[NVDEV_SUBDEV_MC     ] =  nv50_mc_oclass;
75		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv50_bus_oclass;
76		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
77		device->oclass[NVDEV_SUBDEV_FB     ] =  nv50_fb_oclass;
78		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
79		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv50_mmu_oclass;
80		device->oclass[NVDEV_SUBDEV_BAR    ] = &nv50_bar_oclass;
81		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
82		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
83		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv50_fifo_oclass;
84		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;
85		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
86		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv50_mpeg_oclass;
87		device->oclass[NVDEV_ENGINE_DISP   ] =  nv50_disp_oclass;
88		device->oclass[NVDEV_ENGINE_PM     ] =  nv50_pm_oclass;
89		break;
90	case 0x84:
91		device->cname = "G84";
92		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nvkm_bios_oclass;
93		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv50_gpio_oclass;
94		device->oclass[NVDEV_SUBDEV_I2C    ] =  nv50_i2c_oclass;
95		device->oclass[NVDEV_SUBDEV_FUSE   ] =  &nv50_fuse_oclass;
96		device->oclass[NVDEV_SUBDEV_CLK    ] =  g84_clk_oclass;
97		device->oclass[NVDEV_SUBDEV_THERM  ] = &g84_therm_oclass;
98		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
99		device->oclass[NVDEV_SUBDEV_DEVINIT] =  g84_devinit_oclass;
100		device->oclass[NVDEV_SUBDEV_MC     ] =  nv50_mc_oclass;
101		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv50_bus_oclass;
102		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
103		device->oclass[NVDEV_SUBDEV_FB     ] =  g84_fb_oclass;
104		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
105		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv50_mmu_oclass;
106		device->oclass[NVDEV_SUBDEV_BAR    ] = &nv50_bar_oclass;
107		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
108		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
109		device->oclass[NVDEV_ENGINE_FIFO   ] =  g84_fifo_oclass;
110		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;
111		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
112		device->oclass[NVDEV_ENGINE_MPEG   ] = &g84_mpeg_oclass;
113		device->oclass[NVDEV_ENGINE_VP     ] = &g84_vp_oclass;
114		device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
115		device->oclass[NVDEV_ENGINE_BSP    ] = &g84_bsp_oclass;
116		device->oclass[NVDEV_ENGINE_DISP   ] =  g84_disp_oclass;
117		device->oclass[NVDEV_ENGINE_PM     ] =  g84_pm_oclass;
118		break;
119	case 0x86:
120		device->cname = "G86";
121		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nvkm_bios_oclass;
122		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv50_gpio_oclass;
123		device->oclass[NVDEV_SUBDEV_I2C    ] =  nv50_i2c_oclass;
124		device->oclass[NVDEV_SUBDEV_FUSE   ] =  &nv50_fuse_oclass;
125		device->oclass[NVDEV_SUBDEV_CLK    ] =  g84_clk_oclass;
126		device->oclass[NVDEV_SUBDEV_THERM  ] = &g84_therm_oclass;
127		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
128		device->oclass[NVDEV_SUBDEV_DEVINIT] =  g84_devinit_oclass;
129		device->oclass[NVDEV_SUBDEV_MC     ] =  nv50_mc_oclass;
130		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv50_bus_oclass;
131		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
132		device->oclass[NVDEV_SUBDEV_FB     ] =  g84_fb_oclass;
133		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
134		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv50_mmu_oclass;
135		device->oclass[NVDEV_SUBDEV_BAR    ] = &nv50_bar_oclass;
136		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
137		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
138		device->oclass[NVDEV_ENGINE_FIFO   ] =  g84_fifo_oclass;
139		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;
140		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
141		device->oclass[NVDEV_ENGINE_MPEG   ] = &g84_mpeg_oclass;
142		device->oclass[NVDEV_ENGINE_VP     ] = &g84_vp_oclass;
143		device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
144		device->oclass[NVDEV_ENGINE_BSP    ] = &g84_bsp_oclass;
145		device->oclass[NVDEV_ENGINE_DISP   ] =  g84_disp_oclass;
146		device->oclass[NVDEV_ENGINE_PM     ] =  g84_pm_oclass;
147		break;
148	case 0x92:
149		device->cname = "G92";
150		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nvkm_bios_oclass;
151		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv50_gpio_oclass;
152		device->oclass[NVDEV_SUBDEV_I2C    ] =  nv50_i2c_oclass;
153		device->oclass[NVDEV_SUBDEV_FUSE   ] =  &nv50_fuse_oclass;
154		device->oclass[NVDEV_SUBDEV_CLK    ] =  g84_clk_oclass;
155		device->oclass[NVDEV_SUBDEV_THERM  ] = &g84_therm_oclass;
156		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
157		device->oclass[NVDEV_SUBDEV_DEVINIT] =  g84_devinit_oclass;
158		device->oclass[NVDEV_SUBDEV_MC     ] =  nv50_mc_oclass;
159		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv50_bus_oclass;
160		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
161		device->oclass[NVDEV_SUBDEV_FB     ] =  g84_fb_oclass;
162		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
163		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv50_mmu_oclass;
164		device->oclass[NVDEV_SUBDEV_BAR    ] = &nv50_bar_oclass;
165		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
166		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
167		device->oclass[NVDEV_ENGINE_FIFO   ] =  g84_fifo_oclass;
168		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;
169		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
170		device->oclass[NVDEV_ENGINE_MPEG   ] = &g84_mpeg_oclass;
171		device->oclass[NVDEV_ENGINE_VP     ] = &g84_vp_oclass;
172		device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
173		device->oclass[NVDEV_ENGINE_BSP    ] = &g84_bsp_oclass;
174		device->oclass[NVDEV_ENGINE_DISP   ] =  g84_disp_oclass;
175		device->oclass[NVDEV_ENGINE_PM     ] =  g84_pm_oclass;
176		break;
177	case 0x94:
178		device->cname = "G94";
179		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nvkm_bios_oclass;
180		device->oclass[NVDEV_SUBDEV_GPIO   ] =  g94_gpio_oclass;
181		device->oclass[NVDEV_SUBDEV_I2C    ] =  g94_i2c_oclass;
182		device->oclass[NVDEV_SUBDEV_FUSE   ] =  &nv50_fuse_oclass;
183		device->oclass[NVDEV_SUBDEV_CLK    ] =  g84_clk_oclass;
184		device->oclass[NVDEV_SUBDEV_THERM  ] = &g84_therm_oclass;
185		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
186		device->oclass[NVDEV_SUBDEV_DEVINIT] =  g84_devinit_oclass;
187		device->oclass[NVDEV_SUBDEV_MC     ] =  g94_mc_oclass;
188		device->oclass[NVDEV_SUBDEV_BUS    ] =  g94_bus_oclass;
189		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
190		device->oclass[NVDEV_SUBDEV_FB     ] =  g84_fb_oclass;
191		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
192		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv50_mmu_oclass;
193		device->oclass[NVDEV_SUBDEV_BAR    ] = &nv50_bar_oclass;
194		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
195		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
196		device->oclass[NVDEV_ENGINE_FIFO   ] =  g84_fifo_oclass;
197		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;
198		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
199		device->oclass[NVDEV_ENGINE_MPEG   ] = &g84_mpeg_oclass;
200		device->oclass[NVDEV_ENGINE_VP     ] = &g84_vp_oclass;
201		device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
202		device->oclass[NVDEV_ENGINE_BSP    ] = &g84_bsp_oclass;
203		device->oclass[NVDEV_ENGINE_DISP   ] =  g94_disp_oclass;
204		device->oclass[NVDEV_ENGINE_PM     ] =  g84_pm_oclass;
205		break;
206	case 0x96:
207		device->cname = "G96";
208		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nvkm_bios_oclass;
209		device->oclass[NVDEV_SUBDEV_GPIO   ] =  g94_gpio_oclass;
210		device->oclass[NVDEV_SUBDEV_I2C    ] =  g94_i2c_oclass;
211		device->oclass[NVDEV_SUBDEV_FUSE   ] =  &nv50_fuse_oclass;
212		device->oclass[NVDEV_SUBDEV_CLK    ] =  g84_clk_oclass;
213		device->oclass[NVDEV_SUBDEV_THERM  ] = &g84_therm_oclass;
214		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
215		device->oclass[NVDEV_SUBDEV_DEVINIT] =  g84_devinit_oclass;
216		device->oclass[NVDEV_SUBDEV_MC     ] =  g94_mc_oclass;
217		device->oclass[NVDEV_SUBDEV_BUS    ] =  g94_bus_oclass;
218		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
219		device->oclass[NVDEV_SUBDEV_FB     ] =  g84_fb_oclass;
220		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
221		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv50_mmu_oclass;
222		device->oclass[NVDEV_SUBDEV_BAR    ] = &nv50_bar_oclass;
223		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
224		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
225		device->oclass[NVDEV_ENGINE_FIFO   ] =  g84_fifo_oclass;
226		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;
227		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
228		device->oclass[NVDEV_ENGINE_MPEG   ] = &g84_mpeg_oclass;
229		device->oclass[NVDEV_ENGINE_VP     ] = &g84_vp_oclass;
230		device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
231		device->oclass[NVDEV_ENGINE_BSP    ] = &g84_bsp_oclass;
232		device->oclass[NVDEV_ENGINE_DISP   ] =  g94_disp_oclass;
233		device->oclass[NVDEV_ENGINE_PM     ] =  g84_pm_oclass;
234		break;
235	case 0x98:
236		device->cname = "G98";
237		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nvkm_bios_oclass;
238		device->oclass[NVDEV_SUBDEV_GPIO   ] =  g94_gpio_oclass;
239		device->oclass[NVDEV_SUBDEV_I2C    ] =  g94_i2c_oclass;
240		device->oclass[NVDEV_SUBDEV_FUSE   ] =  &nv50_fuse_oclass;
241		device->oclass[NVDEV_SUBDEV_CLK    ] =  g84_clk_oclass;
242		device->oclass[NVDEV_SUBDEV_THERM  ] = &g84_therm_oclass;
243		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
244		device->oclass[NVDEV_SUBDEV_DEVINIT] =  g98_devinit_oclass;
245		device->oclass[NVDEV_SUBDEV_MC     ] =  g98_mc_oclass;
246		device->oclass[NVDEV_SUBDEV_BUS    ] =  g94_bus_oclass;
247		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
248		device->oclass[NVDEV_SUBDEV_FB     ] =  g84_fb_oclass;
249		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
250		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv50_mmu_oclass;
251		device->oclass[NVDEV_SUBDEV_BAR    ] = &nv50_bar_oclass;
252		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
253		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
254		device->oclass[NVDEV_ENGINE_FIFO   ] =  g84_fifo_oclass;
255		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;
256		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
257		device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
258		device->oclass[NVDEV_ENGINE_SEC    ] = &g98_sec_oclass;
259		device->oclass[NVDEV_ENGINE_MSVLD  ] = &g98_msvld_oclass;
260		device->oclass[NVDEV_ENGINE_MSPPP  ] = &g98_msppp_oclass;
261		device->oclass[NVDEV_ENGINE_DISP   ] =  g94_disp_oclass;
262		device->oclass[NVDEV_ENGINE_PM     ] =  g84_pm_oclass;
263		break;
264	case 0xa0:
265		device->cname = "G200";
266		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nvkm_bios_oclass;
267		device->oclass[NVDEV_SUBDEV_GPIO   ] =  g94_gpio_oclass;
268		device->oclass[NVDEV_SUBDEV_I2C    ] =  nv50_i2c_oclass;
269		device->oclass[NVDEV_SUBDEV_FUSE   ] =  &nv50_fuse_oclass;
270		device->oclass[NVDEV_SUBDEV_CLK    ] =  g84_clk_oclass;
271		device->oclass[NVDEV_SUBDEV_THERM  ] = &g84_therm_oclass;
272		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
273		device->oclass[NVDEV_SUBDEV_DEVINIT] =  g84_devinit_oclass;
274		device->oclass[NVDEV_SUBDEV_MC     ] =  g98_mc_oclass;
275		device->oclass[NVDEV_SUBDEV_BUS    ] =  g94_bus_oclass;
276		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
277		device->oclass[NVDEV_SUBDEV_FB     ] =  g84_fb_oclass;
278		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
279		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv50_mmu_oclass;
280		device->oclass[NVDEV_SUBDEV_BAR    ] = &nv50_bar_oclass;
281		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
282		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
283		device->oclass[NVDEV_ENGINE_FIFO   ] =  g84_fifo_oclass;
284		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;
285		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
286		device->oclass[NVDEV_ENGINE_MPEG   ] = &g84_mpeg_oclass;
287		device->oclass[NVDEV_ENGINE_VP     ] = &g84_vp_oclass;
288		device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
289		device->oclass[NVDEV_ENGINE_BSP    ] = &g84_bsp_oclass;
290		device->oclass[NVDEV_ENGINE_DISP   ] =  gt200_disp_oclass;
291		device->oclass[NVDEV_ENGINE_PM     ] =  g84_pm_oclass;
292		break;
293	case 0xaa:
294		device->cname = "MCP77/MCP78";
295		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nvkm_bios_oclass;
296		device->oclass[NVDEV_SUBDEV_GPIO   ] =  g94_gpio_oclass;
297		device->oclass[NVDEV_SUBDEV_I2C    ] =  g94_i2c_oclass;
298		device->oclass[NVDEV_SUBDEV_FUSE   ] =  &nv50_fuse_oclass;
299		device->oclass[NVDEV_SUBDEV_CLK    ] =  mcp77_clk_oclass;
300		device->oclass[NVDEV_SUBDEV_THERM  ] = &g84_therm_oclass;
301		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
302		device->oclass[NVDEV_SUBDEV_DEVINIT] =  g98_devinit_oclass;
303		device->oclass[NVDEV_SUBDEV_MC     ] =  g98_mc_oclass;
304		device->oclass[NVDEV_SUBDEV_BUS    ] =  g94_bus_oclass;
305		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
306		device->oclass[NVDEV_SUBDEV_FB     ] =  mcp77_fb_oclass;
307		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
308		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv50_mmu_oclass;
309		device->oclass[NVDEV_SUBDEV_BAR    ] = &nv50_bar_oclass;
310		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
311		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
312		device->oclass[NVDEV_ENGINE_FIFO   ] =  g84_fifo_oclass;
313		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;
314		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
315		device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
316		device->oclass[NVDEV_ENGINE_SEC    ] = &g98_sec_oclass;
317		device->oclass[NVDEV_ENGINE_MSVLD  ] = &g98_msvld_oclass;
318		device->oclass[NVDEV_ENGINE_MSPPP  ] = &g98_msppp_oclass;
319		device->oclass[NVDEV_ENGINE_DISP   ] =  g94_disp_oclass;
320		device->oclass[NVDEV_ENGINE_PM     ] =  g84_pm_oclass;
321		break;
322	case 0xac:
323		device->cname = "MCP79/MCP7A";
324		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nvkm_bios_oclass;
325		device->oclass[NVDEV_SUBDEV_GPIO   ] =  g94_gpio_oclass;
326		device->oclass[NVDEV_SUBDEV_I2C    ] =  g94_i2c_oclass;
327		device->oclass[NVDEV_SUBDEV_FUSE   ] =  &nv50_fuse_oclass;
328		device->oclass[NVDEV_SUBDEV_CLK    ] =  mcp77_clk_oclass;
329		device->oclass[NVDEV_SUBDEV_THERM  ] = &g84_therm_oclass;
330		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
331		device->oclass[NVDEV_SUBDEV_DEVINIT] =  g98_devinit_oclass;
332		device->oclass[NVDEV_SUBDEV_MC     ] =  g98_mc_oclass;
333		device->oclass[NVDEV_SUBDEV_BUS    ] =  g94_bus_oclass;
334		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
335		device->oclass[NVDEV_SUBDEV_FB     ] =  mcp77_fb_oclass;
336		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
337		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv50_mmu_oclass;
338		device->oclass[NVDEV_SUBDEV_BAR    ] = &nv50_bar_oclass;
339		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
340		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
341		device->oclass[NVDEV_ENGINE_FIFO   ] =  g84_fifo_oclass;
342		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;
343		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
344		device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
345		device->oclass[NVDEV_ENGINE_SEC    ] = &g98_sec_oclass;
346		device->oclass[NVDEV_ENGINE_MSVLD  ] = &g98_msvld_oclass;
347		device->oclass[NVDEV_ENGINE_MSPPP  ] = &g98_msppp_oclass;
348		device->oclass[NVDEV_ENGINE_DISP   ] =  g94_disp_oclass;
349		device->oclass[NVDEV_ENGINE_PM     ] =  g84_pm_oclass;
350		break;
351	case 0xa3:
352		device->cname = "GT215";
353		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nvkm_bios_oclass;
354		device->oclass[NVDEV_SUBDEV_GPIO   ] =  g94_gpio_oclass;
355		device->oclass[NVDEV_SUBDEV_I2C    ] =  g94_i2c_oclass;
356		device->oclass[NVDEV_SUBDEV_FUSE   ] =  &nv50_fuse_oclass;
357		device->oclass[NVDEV_SUBDEV_CLK    ] = &gt215_clk_oclass;
358		device->oclass[NVDEV_SUBDEV_THERM  ] = &gt215_therm_oclass;
359		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
360		device->oclass[NVDEV_SUBDEV_DEVINIT] =  gt215_devinit_oclass;
361		device->oclass[NVDEV_SUBDEV_MC     ] =  g98_mc_oclass;
362		device->oclass[NVDEV_SUBDEV_BUS    ] =  g94_bus_oclass;
363		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
364		device->oclass[NVDEV_SUBDEV_FB     ] =  gt215_fb_oclass;
365		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
366		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv50_mmu_oclass;
367		device->oclass[NVDEV_SUBDEV_BAR    ] = &nv50_bar_oclass;
368		device->oclass[NVDEV_SUBDEV_PMU    ] =  gt215_pmu_oclass;
369		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
370		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
371		device->oclass[NVDEV_ENGINE_FIFO   ] =  g84_fifo_oclass;
372		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;
373		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
374		device->oclass[NVDEV_ENGINE_MPEG   ] = &g84_mpeg_oclass;
375		device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
376		device->oclass[NVDEV_ENGINE_MSVLD  ] = &g98_msvld_oclass;
377		device->oclass[NVDEV_ENGINE_MSPPP  ] = &g98_msppp_oclass;
378		device->oclass[NVDEV_ENGINE_CE0    ] = &gt215_ce_oclass;
379		device->oclass[NVDEV_ENGINE_DISP   ] =  gt215_disp_oclass;
380		device->oclass[NVDEV_ENGINE_PM     ] =  gt215_pm_oclass;
381		break;
382	case 0xa5:
383		device->cname = "GT216";
384		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nvkm_bios_oclass;
385		device->oclass[NVDEV_SUBDEV_GPIO   ] =  g94_gpio_oclass;
386		device->oclass[NVDEV_SUBDEV_I2C    ] =  g94_i2c_oclass;
387		device->oclass[NVDEV_SUBDEV_FUSE   ] =  &nv50_fuse_oclass;
388		device->oclass[NVDEV_SUBDEV_CLK    ] = &gt215_clk_oclass;
389		device->oclass[NVDEV_SUBDEV_THERM  ] = &gt215_therm_oclass;
390		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
391		device->oclass[NVDEV_SUBDEV_DEVINIT] =  gt215_devinit_oclass;
392		device->oclass[NVDEV_SUBDEV_MC     ] =  g98_mc_oclass;
393		device->oclass[NVDEV_SUBDEV_BUS    ] =  g94_bus_oclass;
394		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
395		device->oclass[NVDEV_SUBDEV_FB     ] =  gt215_fb_oclass;
396		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
397		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv50_mmu_oclass;
398		device->oclass[NVDEV_SUBDEV_BAR    ] = &nv50_bar_oclass;
399		device->oclass[NVDEV_SUBDEV_PMU    ] =  gt215_pmu_oclass;
400		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
401		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
402		device->oclass[NVDEV_ENGINE_FIFO   ] =  g84_fifo_oclass;
403		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;
404		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
405		device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
406		device->oclass[NVDEV_ENGINE_MSVLD  ] = &g98_msvld_oclass;
407		device->oclass[NVDEV_ENGINE_MSPPP  ] = &g98_msppp_oclass;
408		device->oclass[NVDEV_ENGINE_CE0    ] = &gt215_ce_oclass;
409		device->oclass[NVDEV_ENGINE_DISP   ] =  gt215_disp_oclass;
410		device->oclass[NVDEV_ENGINE_PM     ] =  gt215_pm_oclass;
411		break;
412	case 0xa8:
413		device->cname = "GT218";
414		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nvkm_bios_oclass;
415		device->oclass[NVDEV_SUBDEV_GPIO   ] =  g94_gpio_oclass;
416		device->oclass[NVDEV_SUBDEV_I2C    ] =  g94_i2c_oclass;
417		device->oclass[NVDEV_SUBDEV_FUSE   ] =  &nv50_fuse_oclass;
418		device->oclass[NVDEV_SUBDEV_CLK    ] = &gt215_clk_oclass;
419		device->oclass[NVDEV_SUBDEV_THERM  ] = &gt215_therm_oclass;
420		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
421		device->oclass[NVDEV_SUBDEV_DEVINIT] =  gt215_devinit_oclass;
422		device->oclass[NVDEV_SUBDEV_MC     ] =  g98_mc_oclass;
423		device->oclass[NVDEV_SUBDEV_BUS    ] =  g94_bus_oclass;
424		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
425		device->oclass[NVDEV_SUBDEV_FB     ] =  gt215_fb_oclass;
426		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
427		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv50_mmu_oclass;
428		device->oclass[NVDEV_SUBDEV_BAR    ] = &nv50_bar_oclass;
429		device->oclass[NVDEV_SUBDEV_PMU    ] =  gt215_pmu_oclass;
430		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
431		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
432		device->oclass[NVDEV_ENGINE_FIFO   ] =  g84_fifo_oclass;
433		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;
434		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
435		device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
436		device->oclass[NVDEV_ENGINE_MSVLD  ] = &g98_msvld_oclass;
437		device->oclass[NVDEV_ENGINE_MSPPP  ] = &g98_msppp_oclass;
438		device->oclass[NVDEV_ENGINE_CE0    ] = &gt215_ce_oclass;
439		device->oclass[NVDEV_ENGINE_DISP   ] =  gt215_disp_oclass;
440		device->oclass[NVDEV_ENGINE_PM     ] =  gt215_pm_oclass;
441		break;
442	case 0xaf:
443		device->cname = "MCP89";
444		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nvkm_bios_oclass;
445		device->oclass[NVDEV_SUBDEV_GPIO   ] =  g94_gpio_oclass;
446		device->oclass[NVDEV_SUBDEV_I2C    ] =  g94_i2c_oclass;
447		device->oclass[NVDEV_SUBDEV_FUSE   ] =  &nv50_fuse_oclass;
448		device->oclass[NVDEV_SUBDEV_CLK    ] = &gt215_clk_oclass;
449		device->oclass[NVDEV_SUBDEV_THERM  ] = &gt215_therm_oclass;
450		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
451		device->oclass[NVDEV_SUBDEV_DEVINIT] =  mcp89_devinit_oclass;
452		device->oclass[NVDEV_SUBDEV_MC     ] =  g98_mc_oclass;
453		device->oclass[NVDEV_SUBDEV_BUS    ] =  g94_bus_oclass;
454		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
455		device->oclass[NVDEV_SUBDEV_FB     ] =  mcp89_fb_oclass;
456		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
457		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv50_mmu_oclass;
458		device->oclass[NVDEV_SUBDEV_BAR    ] = &nv50_bar_oclass;
459		device->oclass[NVDEV_SUBDEV_PMU    ] =  gt215_pmu_oclass;
460		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
461		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
462		device->oclass[NVDEV_ENGINE_FIFO   ] =  g84_fifo_oclass;
463		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;
464		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
465		device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
466		device->oclass[NVDEV_ENGINE_MSVLD  ] = &g98_msvld_oclass;
467		device->oclass[NVDEV_ENGINE_MSPPP  ] = &g98_msppp_oclass;
468		device->oclass[NVDEV_ENGINE_CE0    ] = &gt215_ce_oclass;
469		device->oclass[NVDEV_ENGINE_DISP   ] =  gt215_disp_oclass;
470		device->oclass[NVDEV_ENGINE_PM     ] =  gt215_pm_oclass;
471		break;
472	default:
473		nv_fatal(device, "unknown Tesla chipset\n");
474		return -EINVAL;
475	}
476
477	return 0;
478}
479