1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24#include "priv.h"
25
26#include <core/client.h>
27#include <core/gpuobj.h>
28#include <subdev/fb.h>
29
30#include <nvif/class.h>
31#include <nvif/unpack.h>
32
33struct gf100_dmaobj_priv {
34	struct nvkm_dmaobj base;
35	u32 flags0;
36	u32 flags5;
37};
38
39static int
40gf100_dmaobj_bind(struct nvkm_dmaobj *dmaobj, struct nvkm_object *parent,
41		  struct nvkm_gpuobj **pgpuobj)
42{
43	struct gf100_dmaobj_priv *priv = (void *)dmaobj;
44	int ret;
45
46	if (!nv_iclass(parent, NV_ENGCTX_CLASS)) {
47		switch (nv_mclass(parent->parent)) {
48		case GT214_DISP_CORE_CHANNEL_DMA:
49		case GT214_DISP_BASE_CHANNEL_DMA:
50		case GT214_DISP_OVERLAY_CHANNEL_DMA:
51			break;
52		default:
53			return -EINVAL;
54		}
55	} else
56		return 0;
57
58	ret = nvkm_gpuobj_new(parent, parent, 24, 32, 0, pgpuobj);
59	if (ret == 0) {
60		nv_wo32(*pgpuobj, 0x00, priv->flags0 | nv_mclass(dmaobj));
61		nv_wo32(*pgpuobj, 0x04, lower_32_bits(priv->base.limit));
62		nv_wo32(*pgpuobj, 0x08, lower_32_bits(priv->base.start));
63		nv_wo32(*pgpuobj, 0x0c, upper_32_bits(priv->base.limit) << 24 |
64					upper_32_bits(priv->base.start));
65		nv_wo32(*pgpuobj, 0x10, 0x00000000);
66		nv_wo32(*pgpuobj, 0x14, priv->flags5);
67	}
68
69	return ret;
70}
71
72static int
73gf100_dmaobj_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
74		  struct nvkm_oclass *oclass, void *data, u32 size,
75		  struct nvkm_object **pobject)
76{
77	struct nvkm_dmaeng *dmaeng = (void *)engine;
78	union {
79		struct gf100_dma_v0 v0;
80	} *args;
81	struct gf100_dmaobj_priv *priv;
82	u32 kind, user, unkn;
83	int ret;
84
85	ret = nvkm_dmaobj_create(parent, engine, oclass, &data, &size, &priv);
86	*pobject = nv_object(priv);
87	if (ret)
88		return ret;
89	args = data;
90
91	nv_ioctl(parent, "create gf100 dma size %d\n", size);
92	if (nvif_unpack(args->v0, 0, 0, false)) {
93		nv_ioctl(parent, "create gf100 dma vers %d priv %d kind %02x\n",
94			 args->v0.version, args->v0.priv, args->v0.kind);
95		kind = args->v0.kind;
96		user = args->v0.priv;
97		unkn = 0;
98	} else
99	if (size == 0) {
100		if (priv->base.target != NV_MEM_TARGET_VM) {
101			kind = GF100_DMA_V0_KIND_PITCH;
102			user = GF100_DMA_V0_PRIV_US;
103			unkn = 2;
104		} else {
105			kind = GF100_DMA_V0_KIND_VM;
106			user = GF100_DMA_V0_PRIV_VM;
107			unkn = 0;
108		}
109	} else
110		return ret;
111
112	if (user > 2)
113		return -EINVAL;
114	priv->flags0 |= (kind << 22) | (user << 20);
115	priv->flags5 |= (unkn << 16);
116
117	switch (priv->base.target) {
118	case NV_MEM_TARGET_VM:
119		priv->flags0 |= 0x00000000;
120		break;
121	case NV_MEM_TARGET_VRAM:
122		priv->flags0 |= 0x00010000;
123		break;
124	case NV_MEM_TARGET_PCI:
125		priv->flags0 |= 0x00020000;
126		break;
127	case NV_MEM_TARGET_PCI_NOSNOOP:
128		priv->flags0 |= 0x00030000;
129		break;
130	default:
131		return -EINVAL;
132	}
133
134	switch (priv->base.access) {
135	case NV_MEM_ACCESS_VM:
136		break;
137	case NV_MEM_ACCESS_RO:
138		priv->flags0 |= 0x00040000;
139		break;
140	case NV_MEM_ACCESS_WO:
141	case NV_MEM_ACCESS_RW:
142		priv->flags0 |= 0x00080000;
143		break;
144	}
145
146	return dmaeng->bind(&priv->base, nv_object(priv), (void *)pobject);
147}
148
149static struct nvkm_ofuncs
150gf100_dmaobj_ofuncs = {
151	.ctor =  gf100_dmaobj_ctor,
152	.dtor = _nvkm_dmaobj_dtor,
153	.init = _nvkm_dmaobj_init,
154	.fini = _nvkm_dmaobj_fini,
155};
156
157static struct nvkm_oclass
158gf100_dmaeng_sclass[] = {
159	{ NV_DMA_FROM_MEMORY, &gf100_dmaobj_ofuncs },
160	{ NV_DMA_TO_MEMORY, &gf100_dmaobj_ofuncs },
161	{ NV_DMA_IN_MEMORY, &gf100_dmaobj_ofuncs },
162	{}
163};
164
165struct nvkm_oclass *
166gf100_dmaeng_oclass = &(struct nvkm_dmaeng_impl) {
167	.base.handle = NV_ENGINE(DMAOBJ, 0xc0),
168	.base.ofuncs = &(struct nvkm_ofuncs) {
169		.ctor = _nvkm_dmaeng_ctor,
170		.dtor = _nvkm_dmaeng_dtor,
171		.init = _nvkm_dmaeng_init,
172		.fini = _nvkm_dmaeng_fini,
173	},
174	.sclass = gf100_dmaeng_sclass,
175	.bind = gf100_dmaobj_bind,
176}.base;
177