1/*
2 * Copyright 2013 Ilia Mirkin
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22#include <engine/xtensa.h>
23#include <core/device.h>
24
25#include <core/engctx.h>
26
27u32
28_nvkm_xtensa_rd32(struct nvkm_object *object, u64 addr)
29{
30	struct nvkm_xtensa *xtensa = (void *)object;
31	return nv_rd32(xtensa, xtensa->addr + addr);
32}
33
34void
35_nvkm_xtensa_wr32(struct nvkm_object *object, u64 addr, u32 data)
36{
37	struct nvkm_xtensa *xtensa = (void *)object;
38	nv_wr32(xtensa, xtensa->addr + addr, data);
39}
40
41int
42_nvkm_xtensa_engctx_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
43			 struct nvkm_oclass *oclass, void *data, u32 size,
44			 struct nvkm_object **pobject)
45{
46	struct nvkm_engctx *engctx;
47	int ret;
48
49	ret = nvkm_engctx_create(parent, engine, oclass, NULL, 0x10000, 0x1000,
50				 NVOBJ_FLAG_ZERO_ALLOC, &engctx);
51	*pobject = nv_object(engctx);
52	return ret;
53}
54
55void
56_nvkm_xtensa_intr(struct nvkm_subdev *subdev)
57{
58	struct nvkm_xtensa *xtensa = (void *)subdev;
59	u32 unk104 = nv_ro32(xtensa, 0xd04);
60	u32 intr = nv_ro32(xtensa, 0xc20);
61	u32 chan = nv_ro32(xtensa, 0xc28);
62	u32 unk10c = nv_ro32(xtensa, 0xd0c);
63
64	if (intr & 0x10)
65		nv_warn(xtensa, "Watchdog interrupt, engine hung.\n");
66	nv_wo32(xtensa, 0xc20, intr);
67	intr = nv_ro32(xtensa, 0xc20);
68	if (unk104 == 0x10001 && unk10c == 0x200 && chan && !intr) {
69		nv_debug(xtensa, "Enabling FIFO_CTRL\n");
70		nv_mask(xtensa, xtensa->addr + 0xd94, 0, xtensa->fifo_val);
71	}
72}
73
74int
75nvkm_xtensa_create_(struct nvkm_object *parent, struct nvkm_object *engine,
76		    struct nvkm_oclass *oclass, u32 addr, bool enable,
77		    const char *iname, const char *fname,
78		    int length, void **pobject)
79{
80	struct nvkm_xtensa *xtensa;
81	int ret;
82
83	ret = nvkm_engine_create_(parent, engine, oclass, enable, iname,
84				  fname, length, pobject);
85	xtensa = *pobject;
86	if (ret)
87		return ret;
88
89	nv_subdev(xtensa)->intr = _nvkm_xtensa_intr;
90	xtensa->addr = addr;
91	return 0;
92}
93
94int
95_nvkm_xtensa_init(struct nvkm_object *object)
96{
97	struct nvkm_device *device = nv_device(object);
98	struct nvkm_xtensa *xtensa = (void *)object;
99	const struct firmware *fw;
100	char name[32];
101	int i, ret;
102	u32 tmp;
103
104	ret = nvkm_engine_init(&xtensa->base);
105	if (ret)
106		return ret;
107
108	if (!xtensa->gpu_fw) {
109		snprintf(name, sizeof(name), "nouveau/nv84_xuc%03x",
110			 xtensa->addr >> 12);
111
112		ret = request_firmware(&fw, name, nv_device_base(device));
113		if (ret) {
114			nv_warn(xtensa, "unable to load firmware %s\n", name);
115			return ret;
116		}
117
118		if (fw->size > 0x40000) {
119			nv_warn(xtensa, "firmware %s too large\n", name);
120			release_firmware(fw);
121			return -EINVAL;
122		}
123
124		ret = nvkm_gpuobj_new(object, NULL, 0x40000, 0x1000, 0,
125				      &xtensa->gpu_fw);
126		if (ret) {
127			release_firmware(fw);
128			return ret;
129		}
130
131		nv_debug(xtensa, "Loading firmware to address: 0x%llx\n",
132			 xtensa->gpu_fw->addr);
133
134		for (i = 0; i < fw->size / 4; i++)
135			nv_wo32(xtensa->gpu_fw, i * 4, *((u32 *)fw->data + i));
136		release_firmware(fw);
137	}
138
139	nv_wo32(xtensa, 0xd10, 0x1fffffff); /* ?? */
140	nv_wo32(xtensa, 0xd08, 0x0fffffff); /* ?? */
141
142	nv_wo32(xtensa, 0xd28, xtensa->unkd28); /* ?? */
143	nv_wo32(xtensa, 0xc20, 0x3f); /* INTR */
144	nv_wo32(xtensa, 0xd84, 0x3f); /* INTR_EN */
145
146	nv_wo32(xtensa, 0xcc0, xtensa->gpu_fw->addr >> 8); /* XT_REGION_BASE */
147	nv_wo32(xtensa, 0xcc4, 0x1c); /* XT_REGION_SETUP */
148	nv_wo32(xtensa, 0xcc8, xtensa->gpu_fw->size >> 8); /* XT_REGION_LIMIT */
149
150	tmp = nv_rd32(xtensa, 0x0);
151	nv_wo32(xtensa, 0xde0, tmp); /* SCRATCH_H2X */
152
153	nv_wo32(xtensa, 0xce8, 0xf); /* XT_REGION_SETUP */
154
155	nv_wo32(xtensa, 0xc20, 0x3f); /* INTR */
156	nv_wo32(xtensa, 0xd84, 0x3f); /* INTR_EN */
157	return 0;
158}
159
160int
161_nvkm_xtensa_fini(struct nvkm_object *object, bool suspend)
162{
163	struct nvkm_xtensa *xtensa = (void *)object;
164
165	nv_wo32(xtensa, 0xd84, 0); /* INTR_EN */
166	nv_wo32(xtensa, 0xd94, 0); /* FIFO_CTRL */
167
168	if (!suspend)
169		nvkm_gpuobj_ref(NULL, &xtensa->gpu_fw);
170
171	return nvkm_engine_fini(&xtensa->base, suspend);
172}
173