1/* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24#include "nv04.h" 25 26#include <core/client.h> 27#include <core/engctx.h> 28#include <core/ramht.h> 29#include <subdev/instmem/nv04.h> 30 31#include <nvif/class.h> 32#include <nvif/unpack.h> 33 34static struct ramfc_desc 35nv17_ramfc[] = { 36 { 32, 0, 0x00, 0, NV04_PFIFO_CACHE1_DMA_PUT }, 37 { 32, 0, 0x04, 0, NV04_PFIFO_CACHE1_DMA_GET }, 38 { 32, 0, 0x08, 0, NV10_PFIFO_CACHE1_REF_CNT }, 39 { 16, 0, 0x0c, 0, NV04_PFIFO_CACHE1_DMA_INSTANCE }, 40 { 16, 16, 0x0c, 0, NV04_PFIFO_CACHE1_DMA_DCOUNT }, 41 { 32, 0, 0x10, 0, NV04_PFIFO_CACHE1_DMA_STATE }, 42 { 32, 0, 0x14, 0, NV04_PFIFO_CACHE1_DMA_FETCH }, 43 { 32, 0, 0x18, 0, NV04_PFIFO_CACHE1_ENGINE }, 44 { 32, 0, 0x1c, 0, NV04_PFIFO_CACHE1_PULL1 }, 45 { 32, 0, 0x20, 0, NV10_PFIFO_CACHE1_ACQUIRE_VALUE }, 46 { 32, 0, 0x24, 0, NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP }, 47 { 32, 0, 0x28, 0, NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT }, 48 { 32, 0, 0x2c, 0, NV10_PFIFO_CACHE1_SEMAPHORE }, 49 { 32, 0, 0x30, 0, NV10_PFIFO_CACHE1_DMA_SUBROUTINE }, 50 {} 51}; 52 53/******************************************************************************* 54 * FIFO channel objects 55 ******************************************************************************/ 56 57static int 58nv17_fifo_chan_ctor(struct nvkm_object *parent, 59 struct nvkm_object *engine, 60 struct nvkm_oclass *oclass, void *data, u32 size, 61 struct nvkm_object **pobject) 62{ 63 union { 64 struct nv03_channel_dma_v0 v0; 65 } *args = data; 66 struct nv04_fifo_priv *priv = (void *)engine; 67 struct nv04_fifo_chan *chan; 68 int ret; 69 70 nv_ioctl(parent, "create channel dma size %d\n", size); 71 if (nvif_unpack(args->v0, 0, 0, false)) { 72 nv_ioctl(parent, "create channel dma vers %d pushbuf %08x " 73 "offset %016llx\n", args->v0.version, 74 args->v0.pushbuf, args->v0.offset); 75 } else 76 return ret; 77 78 ret = nvkm_fifo_channel_create(parent, engine, oclass, 0, 0x800000, 79 0x10000, args->v0.pushbuf, 80 (1ULL << NVDEV_ENGINE_DMAOBJ) | 81 (1ULL << NVDEV_ENGINE_SW) | 82 (1ULL << NVDEV_ENGINE_GR) | 83 (1ULL << NVDEV_ENGINE_MPEG), /* NV31- */ 84 &chan); 85 *pobject = nv_object(chan); 86 if (ret) 87 return ret; 88 89 args->v0.chid = chan->base.chid; 90 91 nv_parent(chan)->object_attach = nv04_fifo_object_attach; 92 nv_parent(chan)->object_detach = nv04_fifo_object_detach; 93 nv_parent(chan)->context_attach = nv04_fifo_context_attach; 94 chan->ramfc = chan->base.chid * 64; 95 96 nv_wo32(priv->ramfc, chan->ramfc + 0x00, args->v0.offset); 97 nv_wo32(priv->ramfc, chan->ramfc + 0x04, args->v0.offset); 98 nv_wo32(priv->ramfc, chan->ramfc + 0x0c, chan->base.pushgpu->addr >> 4); 99 nv_wo32(priv->ramfc, chan->ramfc + 0x14, 100 NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES | 101 NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES | 102#ifdef __BIG_ENDIAN 103 NV_PFIFO_CACHE1_BIG_ENDIAN | 104#endif 105 NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8); 106 return 0; 107} 108 109static struct nvkm_ofuncs 110nv17_fifo_ofuncs = { 111 .ctor = nv17_fifo_chan_ctor, 112 .dtor = nv04_fifo_chan_dtor, 113 .init = nv04_fifo_chan_init, 114 .fini = nv04_fifo_chan_fini, 115 .map = _nvkm_fifo_channel_map, 116 .rd32 = _nvkm_fifo_channel_rd32, 117 .wr32 = _nvkm_fifo_channel_wr32, 118 .ntfy = _nvkm_fifo_channel_ntfy 119}; 120 121static struct nvkm_oclass 122nv17_fifo_sclass[] = { 123 { NV17_CHANNEL_DMA, &nv17_fifo_ofuncs }, 124 {} 125}; 126 127/******************************************************************************* 128 * FIFO context - basically just the instmem reserved for the channel 129 ******************************************************************************/ 130 131static struct nvkm_oclass 132nv17_fifo_cclass = { 133 .handle = NV_ENGCTX(FIFO, 0x17), 134 .ofuncs = &(struct nvkm_ofuncs) { 135 .ctor = nv04_fifo_context_ctor, 136 .dtor = _nvkm_fifo_context_dtor, 137 .init = _nvkm_fifo_context_init, 138 .fini = _nvkm_fifo_context_fini, 139 .rd32 = _nvkm_fifo_context_rd32, 140 .wr32 = _nvkm_fifo_context_wr32, 141 }, 142}; 143 144/******************************************************************************* 145 * PFIFO engine 146 ******************************************************************************/ 147 148static int 149nv17_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 150 struct nvkm_oclass *oclass, void *data, u32 size, 151 struct nvkm_object **pobject) 152{ 153 struct nv04_instmem_priv *imem = nv04_instmem(parent); 154 struct nv04_fifo_priv *priv; 155 int ret; 156 157 ret = nvkm_fifo_create(parent, engine, oclass, 0, 31, &priv); 158 *pobject = nv_object(priv); 159 if (ret) 160 return ret; 161 162 nvkm_ramht_ref(imem->ramht, &priv->ramht); 163 nvkm_gpuobj_ref(imem->ramro, &priv->ramro); 164 nvkm_gpuobj_ref(imem->ramfc, &priv->ramfc); 165 166 nv_subdev(priv)->unit = 0x00000100; 167 nv_subdev(priv)->intr = nv04_fifo_intr; 168 nv_engine(priv)->cclass = &nv17_fifo_cclass; 169 nv_engine(priv)->sclass = nv17_fifo_sclass; 170 priv->base.pause = nv04_fifo_pause; 171 priv->base.start = nv04_fifo_start; 172 priv->ramfc_desc = nv17_ramfc; 173 return 0; 174} 175 176static int 177nv17_fifo_init(struct nvkm_object *object) 178{ 179 struct nv04_fifo_priv *priv = (void *)object; 180 int ret; 181 182 ret = nvkm_fifo_init(&priv->base); 183 if (ret) 184 return ret; 185 186 nv_wr32(priv, NV04_PFIFO_DELAY_0, 0x000000ff); 187 nv_wr32(priv, NV04_PFIFO_DMA_TIMESLICE, 0x0101ffff); 188 189 nv_wr32(priv, NV03_PFIFO_RAMHT, (0x03 << 24) /* search 128 */ | 190 ((priv->ramht->bits - 9) << 16) | 191 (priv->ramht->gpuobj.addr >> 8)); 192 nv_wr32(priv, NV03_PFIFO_RAMRO, priv->ramro->addr >> 8); 193 nv_wr32(priv, NV03_PFIFO_RAMFC, priv->ramfc->addr >> 8 | 0x00010000); 194 195 nv_wr32(priv, NV03_PFIFO_CACHE1_PUSH1, priv->base.max); 196 197 nv_wr32(priv, NV03_PFIFO_INTR_0, 0xffffffff); 198 nv_wr32(priv, NV03_PFIFO_INTR_EN_0, 0xffffffff); 199 200 nv_wr32(priv, NV03_PFIFO_CACHE1_PUSH0, 1); 201 nv_wr32(priv, NV04_PFIFO_CACHE1_PULL0, 1); 202 nv_wr32(priv, NV03_PFIFO_CACHES, 1); 203 return 0; 204} 205 206struct nvkm_oclass * 207nv17_fifo_oclass = &(struct nvkm_oclass) { 208 .handle = NV_ENGINE(FIFO, 0x17), 209 .ofuncs = &(struct nvkm_ofuncs) { 210 .ctor = nv17_fifo_ctor, 211 .dtor = nv04_fifo_dtor, 212 .init = nv17_fifo_init, 213 .fini = _nvkm_fifo_fini, 214 }, 215}; 216