1#include "nv20.h" 2#include "regs.h" 3 4#include <core/device.h> 5#include <engine/fifo.h> 6#include <subdev/fb.h> 7 8/******************************************************************************* 9 * Graphics object classes 10 ******************************************************************************/ 11 12static struct nvkm_oclass 13nv30_gr_sclass[] = { 14 { 0x0012, &nv04_gr_ofuncs, NULL }, /* beta1 */ 15 { 0x0019, &nv04_gr_ofuncs, NULL }, /* clip */ 16 { 0x0030, &nv04_gr_ofuncs, NULL }, /* null */ 17 { 0x0039, &nv04_gr_ofuncs, NULL }, /* m2mf */ 18 { 0x0043, &nv04_gr_ofuncs, NULL }, /* rop */ 19 { 0x0044, &nv04_gr_ofuncs, NULL }, /* patt */ 20 { 0x004a, &nv04_gr_ofuncs, NULL }, /* gdi */ 21 { 0x0062, &nv04_gr_ofuncs, NULL }, /* surf2d */ 22 { 0x0072, &nv04_gr_ofuncs, NULL }, /* beta4 */ 23 { 0x0089, &nv04_gr_ofuncs, NULL }, /* sifm */ 24 { 0x008a, &nv04_gr_ofuncs, NULL }, /* ifc */ 25 { 0x009f, &nv04_gr_ofuncs, NULL }, /* imageblit */ 26 { 0x0362, &nv04_gr_ofuncs, NULL }, /* surf2d (nv30) */ 27 { 0x0389, &nv04_gr_ofuncs, NULL }, /* sifm (nv30) */ 28 { 0x038a, &nv04_gr_ofuncs, NULL }, /* ifc (nv30) */ 29 { 0x039e, &nv04_gr_ofuncs, NULL }, /* swzsurf (nv30) */ 30 { 0x0397, &nv04_gr_ofuncs, NULL }, /* rankine */ 31 {}, 32}; 33 34/******************************************************************************* 35 * PGRAPH context 36 ******************************************************************************/ 37 38static int 39nv30_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 40 struct nvkm_oclass *oclass, void *data, u32 size, 41 struct nvkm_object **pobject) 42{ 43 struct nv20_gr_chan *chan; 44 int ret, i; 45 46 ret = nvkm_gr_context_create(parent, engine, oclass, NULL, 0x5f48, 47 16, NVOBJ_FLAG_ZERO_ALLOC, &chan); 48 *pobject = nv_object(chan); 49 if (ret) 50 return ret; 51 52 chan->chid = nvkm_fifo_chan(parent)->chid; 53 54 nv_wo32(chan, 0x0028, 0x00000001 | (chan->chid << 24)); 55 nv_wo32(chan, 0x0410, 0x00000101); 56 nv_wo32(chan, 0x0424, 0x00000111); 57 nv_wo32(chan, 0x0428, 0x00000060); 58 nv_wo32(chan, 0x0444, 0x00000080); 59 nv_wo32(chan, 0x0448, 0xffff0000); 60 nv_wo32(chan, 0x044c, 0x00000001); 61 nv_wo32(chan, 0x0460, 0x44400000); 62 nv_wo32(chan, 0x048c, 0xffff0000); 63 for (i = 0x04e0; i < 0x04e8; i += 4) 64 nv_wo32(chan, i, 0x0fff0000); 65 nv_wo32(chan, 0x04ec, 0x00011100); 66 for (i = 0x0508; i < 0x0548; i += 4) 67 nv_wo32(chan, i, 0x07ff0000); 68 nv_wo32(chan, 0x0550, 0x4b7fffff); 69 nv_wo32(chan, 0x058c, 0x00000080); 70 nv_wo32(chan, 0x0590, 0x30201000); 71 nv_wo32(chan, 0x0594, 0x70605040); 72 nv_wo32(chan, 0x0598, 0xb8a89888); 73 nv_wo32(chan, 0x059c, 0xf8e8d8c8); 74 nv_wo32(chan, 0x05b0, 0xb0000000); 75 for (i = 0x0600; i < 0x0640; i += 4) 76 nv_wo32(chan, i, 0x00010588); 77 for (i = 0x0640; i < 0x0680; i += 4) 78 nv_wo32(chan, i, 0x00030303); 79 for (i = 0x06c0; i < 0x0700; i += 4) 80 nv_wo32(chan, i, 0x0008aae4); 81 for (i = 0x0700; i < 0x0740; i += 4) 82 nv_wo32(chan, i, 0x01012000); 83 for (i = 0x0740; i < 0x0780; i += 4) 84 nv_wo32(chan, i, 0x00080008); 85 nv_wo32(chan, 0x085c, 0x00040000); 86 nv_wo32(chan, 0x0860, 0x00010000); 87 for (i = 0x0864; i < 0x0874; i += 4) 88 nv_wo32(chan, i, 0x00040004); 89 for (i = 0x1f18; i <= 0x3088 ; i += 16) { 90 nv_wo32(chan, i + 0, 0x10700ff9); 91 nv_wo32(chan, i + 1, 0x0436086c); 92 nv_wo32(chan, i + 2, 0x000c001b); 93 } 94 for (i = 0x30b8; i < 0x30c8; i += 4) 95 nv_wo32(chan, i, 0x0000ffff); 96 nv_wo32(chan, 0x344c, 0x3f800000); 97 nv_wo32(chan, 0x3808, 0x3f800000); 98 nv_wo32(chan, 0x381c, 0x3f800000); 99 nv_wo32(chan, 0x3848, 0x40000000); 100 nv_wo32(chan, 0x384c, 0x3f800000); 101 nv_wo32(chan, 0x3850, 0x3f000000); 102 nv_wo32(chan, 0x3858, 0x40000000); 103 nv_wo32(chan, 0x385c, 0x3f800000); 104 nv_wo32(chan, 0x3864, 0xbf800000); 105 nv_wo32(chan, 0x386c, 0xbf800000); 106 return 0; 107} 108 109static struct nvkm_oclass 110nv30_gr_cclass = { 111 .handle = NV_ENGCTX(GR, 0x30), 112 .ofuncs = &(struct nvkm_ofuncs) { 113 .ctor = nv30_gr_context_ctor, 114 .dtor = _nvkm_gr_context_dtor, 115 .init = nv20_gr_context_init, 116 .fini = nv20_gr_context_fini, 117 .rd32 = _nvkm_gr_context_rd32, 118 .wr32 = _nvkm_gr_context_wr32, 119 }, 120}; 121 122/******************************************************************************* 123 * PGRAPH engine/subdev functions 124 ******************************************************************************/ 125 126static int 127nv30_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 128 struct nvkm_oclass *oclass, void *data, u32 size, 129 struct nvkm_object **pobject) 130{ 131 struct nv20_gr_priv *priv; 132 int ret; 133 134 ret = nvkm_gr_create(parent, engine, oclass, true, &priv); 135 *pobject = nv_object(priv); 136 if (ret) 137 return ret; 138 139 ret = nvkm_gpuobj_new(nv_object(priv), NULL, 32 * 4, 16, 140 NVOBJ_FLAG_ZERO_ALLOC, &priv->ctxtab); 141 if (ret) 142 return ret; 143 144 nv_subdev(priv)->unit = 0x00001000; 145 nv_subdev(priv)->intr = nv20_gr_intr; 146 nv_engine(priv)->cclass = &nv30_gr_cclass; 147 nv_engine(priv)->sclass = nv30_gr_sclass; 148 nv_engine(priv)->tile_prog = nv20_gr_tile_prog; 149 return 0; 150} 151 152int 153nv30_gr_init(struct nvkm_object *object) 154{ 155 struct nvkm_engine *engine = nv_engine(object); 156 struct nv20_gr_priv *priv = (void *)engine; 157 struct nvkm_fb *pfb = nvkm_fb(object); 158 int ret, i; 159 160 ret = nvkm_gr_init(&priv->base); 161 if (ret) 162 return ret; 163 164 nv_wr32(priv, NV20_PGRAPH_CHANNEL_CTX_TABLE, priv->ctxtab->addr >> 4); 165 166 nv_wr32(priv, NV03_PGRAPH_INTR , 0xFFFFFFFF); 167 nv_wr32(priv, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF); 168 169 nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF); 170 nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0x00000000); 171 nv_wr32(priv, NV04_PGRAPH_DEBUG_1, 0x401287c0); 172 nv_wr32(priv, 0x400890, 0x01b463ff); 173 nv_wr32(priv, NV04_PGRAPH_DEBUG_3, 0xf2de0475); 174 nv_wr32(priv, NV10_PGRAPH_DEBUG_4, 0x00008000); 175 nv_wr32(priv, NV04_PGRAPH_LIMIT_VIOL_PIX, 0xf04bdff6); 176 nv_wr32(priv, 0x400B80, 0x1003d888); 177 nv_wr32(priv, 0x400B84, 0x0c000000); 178 nv_wr32(priv, 0x400098, 0x00000000); 179 nv_wr32(priv, 0x40009C, 0x0005ad00); 180 nv_wr32(priv, 0x400B88, 0x62ff00ff); /* suspiciously like PGRAPH_DEBUG_2 */ 181 nv_wr32(priv, 0x4000a0, 0x00000000); 182 nv_wr32(priv, 0x4000a4, 0x00000008); 183 nv_wr32(priv, 0x4008a8, 0xb784a400); 184 nv_wr32(priv, 0x400ba0, 0x002f8685); 185 nv_wr32(priv, 0x400ba4, 0x00231f3f); 186 nv_wr32(priv, 0x4008a4, 0x40000020); 187 188 if (nv_device(priv)->chipset == 0x34) { 189 nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0004); 190 nv_wr32(priv, NV10_PGRAPH_RDI_DATA , 0x00200201); 191 nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0008); 192 nv_wr32(priv, NV10_PGRAPH_RDI_DATA , 0x00000008); 193 nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0000); 194 nv_wr32(priv, NV10_PGRAPH_RDI_DATA , 0x00000032); 195 nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00E00004); 196 nv_wr32(priv, NV10_PGRAPH_RDI_DATA , 0x00000002); 197 } 198 199 nv_wr32(priv, 0x4000c0, 0x00000016); 200 201 /* Turn all the tiling regions off. */ 202 for (i = 0; i < pfb->tile.regions; i++) 203 engine->tile_prog(engine, i); 204 205 nv_wr32(priv, NV10_PGRAPH_CTX_CONTROL, 0x10000100); 206 nv_wr32(priv, NV10_PGRAPH_STATE , 0xFFFFFFFF); 207 nv_wr32(priv, 0x0040075c , 0x00000001); 208 209 /* begin RAM config */ 210 /* vramsz = pci_resource_len(priv->dev->pdev, 0) - 1; */ 211 nv_wr32(priv, 0x4009A4, nv_rd32(priv, 0x100200)); 212 nv_wr32(priv, 0x4009A8, nv_rd32(priv, 0x100204)); 213 if (nv_device(priv)->chipset != 0x34) { 214 nv_wr32(priv, 0x400750, 0x00EA0000); 215 nv_wr32(priv, 0x400754, nv_rd32(priv, 0x100200)); 216 nv_wr32(priv, 0x400750, 0x00EA0004); 217 nv_wr32(priv, 0x400754, nv_rd32(priv, 0x100204)); 218 } 219 return 0; 220} 221 222struct nvkm_oclass 223nv30_gr_oclass = { 224 .handle = NV_ENGINE(GR, 0x30), 225 .ofuncs = &(struct nvkm_ofuncs) { 226 .ctor = nv30_gr_ctor, 227 .dtor = nv20_gr_dtor, 228 .init = nv30_gr_init, 229 .fini = _nvkm_gr_fini, 230 }, 231}; 232