1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24#include "priv.h"
25
26#include <subdev/bios.h>
27#include <subdev/bus.h>
28#include <subdev/mmu.h>
29#include <subdev/gpio.h>
30#include <subdev/i2c.h>
31#include <subdev/clk.h>
32#include <subdev/therm.h>
33#include <subdev/devinit.h>
34#include <subdev/mc.h>
35#include <subdev/timer.h>
36#include <subdev/fb.h>
37#include <subdev/instmem.h>
38#include <subdev/mmu.h>
39#include <subdev/volt.h>
40
41#include <engine/dmaobj.h>
42#include <engine/fifo.h>
43#include <engine/sw.h>
44#include <engine/gr.h>
45#include <engine/mpeg.h>
46#include <engine/disp.h>
47#include <engine/pm.h>
48
49int
50nv40_identify(struct nvkm_device *device)
51{
52	switch (device->chipset) {
53	case 0x40:
54		device->cname = "NV40";
55		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nvkm_bios_oclass;
56		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv10_gpio_oclass;
57		device->oclass[NVDEV_SUBDEV_I2C    ] =  nv04_i2c_oclass;
58		device->oclass[NVDEV_SUBDEV_CLK    ] = &nv40_clk_oclass;
59		device->oclass[NVDEV_SUBDEV_THERM  ] = &nv40_therm_oclass;
60		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv1a_devinit_oclass;
61		device->oclass[NVDEV_SUBDEV_MC     ] =  nv40_mc_oclass;
62		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv31_bus_oclass;
63		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
64		device->oclass[NVDEV_SUBDEV_FB     ] =  nv40_fb_oclass;
65		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv40_instmem_oclass;
66		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv04_mmu_oclass;
67		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
68		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
69		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
70		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
71		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
72		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv40_mpeg_oclass;
73		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
74		device->oclass[NVDEV_ENGINE_PM     ] =  nv40_pm_oclass;
75		break;
76	case 0x41:
77		device->cname = "NV41";
78		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nvkm_bios_oclass;
79		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv10_gpio_oclass;
80		device->oclass[NVDEV_SUBDEV_I2C    ] =  nv04_i2c_oclass;
81		device->oclass[NVDEV_SUBDEV_CLK    ] = &nv40_clk_oclass;
82		device->oclass[NVDEV_SUBDEV_THERM  ] = &nv40_therm_oclass;
83		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv1a_devinit_oclass;
84		device->oclass[NVDEV_SUBDEV_MC     ] =  nv40_mc_oclass;
85		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv31_bus_oclass;
86		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
87		device->oclass[NVDEV_SUBDEV_FB     ] =  nv41_fb_oclass;
88		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv40_instmem_oclass;
89		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv41_mmu_oclass;
90		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
91		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
92		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
93		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
94		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
95		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv40_mpeg_oclass;
96		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
97		device->oclass[NVDEV_ENGINE_PM     ] =  nv40_pm_oclass;
98		break;
99	case 0x42:
100		device->cname = "NV42";
101		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nvkm_bios_oclass;
102		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv10_gpio_oclass;
103		device->oclass[NVDEV_SUBDEV_I2C    ] =  nv04_i2c_oclass;
104		device->oclass[NVDEV_SUBDEV_CLK    ] = &nv40_clk_oclass;
105		device->oclass[NVDEV_SUBDEV_THERM  ] = &nv40_therm_oclass;
106		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv1a_devinit_oclass;
107		device->oclass[NVDEV_SUBDEV_MC     ] =  nv40_mc_oclass;
108		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv31_bus_oclass;
109		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
110		device->oclass[NVDEV_SUBDEV_FB     ] =  nv41_fb_oclass;
111		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv40_instmem_oclass;
112		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv41_mmu_oclass;
113		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
114		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
115		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
116		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
117		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
118		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv40_mpeg_oclass;
119		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
120		device->oclass[NVDEV_ENGINE_PM     ] =  nv40_pm_oclass;
121		break;
122	case 0x43:
123		device->cname = "NV43";
124		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nvkm_bios_oclass;
125		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv10_gpio_oclass;
126		device->oclass[NVDEV_SUBDEV_I2C    ] =  nv04_i2c_oclass;
127		device->oclass[NVDEV_SUBDEV_CLK    ] = &nv40_clk_oclass;
128		device->oclass[NVDEV_SUBDEV_THERM  ] = &nv40_therm_oclass;
129		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv1a_devinit_oclass;
130		device->oclass[NVDEV_SUBDEV_MC     ] =  nv40_mc_oclass;
131		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv31_bus_oclass;
132		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
133		device->oclass[NVDEV_SUBDEV_FB     ] =  nv41_fb_oclass;
134		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv40_instmem_oclass;
135		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv41_mmu_oclass;
136		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
137		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
138		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
139		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
140		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
141		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv40_mpeg_oclass;
142		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
143		device->oclass[NVDEV_ENGINE_PM     ] =  nv40_pm_oclass;
144		break;
145	case 0x45:
146		device->cname = "NV45";
147		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nvkm_bios_oclass;
148		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv10_gpio_oclass;
149		device->oclass[NVDEV_SUBDEV_I2C    ] =  nv04_i2c_oclass;
150		device->oclass[NVDEV_SUBDEV_CLK    ] = &nv40_clk_oclass;
151		device->oclass[NVDEV_SUBDEV_THERM  ] = &nv40_therm_oclass;
152		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv1a_devinit_oclass;
153		device->oclass[NVDEV_SUBDEV_MC     ] =  nv40_mc_oclass;
154		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv31_bus_oclass;
155		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
156		device->oclass[NVDEV_SUBDEV_FB     ] =  nv40_fb_oclass;
157		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv40_instmem_oclass;
158		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv04_mmu_oclass;
159		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
160		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
161		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
162		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
163		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
164		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
165		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
166		device->oclass[NVDEV_ENGINE_PM     ] =  nv40_pm_oclass;
167		break;
168	case 0x47:
169		device->cname = "G70";
170		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nvkm_bios_oclass;
171		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv10_gpio_oclass;
172		device->oclass[NVDEV_SUBDEV_I2C    ] =  nv04_i2c_oclass;
173		device->oclass[NVDEV_SUBDEV_CLK    ] = &nv40_clk_oclass;
174		device->oclass[NVDEV_SUBDEV_THERM  ] = &nv40_therm_oclass;
175		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv1a_devinit_oclass;
176		device->oclass[NVDEV_SUBDEV_MC     ] =  nv40_mc_oclass;
177		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv31_bus_oclass;
178		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
179		device->oclass[NVDEV_SUBDEV_FB     ] =  nv47_fb_oclass;
180		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv40_instmem_oclass;
181		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv41_mmu_oclass;
182		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
183		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
184		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
185		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
186		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
187		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
188		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
189		device->oclass[NVDEV_ENGINE_PM     ] =  nv40_pm_oclass;
190		break;
191	case 0x49:
192		device->cname = "G71";
193		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nvkm_bios_oclass;
194		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv10_gpio_oclass;
195		device->oclass[NVDEV_SUBDEV_I2C    ] =  nv04_i2c_oclass;
196		device->oclass[NVDEV_SUBDEV_CLK    ] = &nv40_clk_oclass;
197		device->oclass[NVDEV_SUBDEV_THERM  ] = &nv40_therm_oclass;
198		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv1a_devinit_oclass;
199		device->oclass[NVDEV_SUBDEV_MC     ] =  nv40_mc_oclass;
200		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv31_bus_oclass;
201		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
202		device->oclass[NVDEV_SUBDEV_FB     ] =  nv49_fb_oclass;
203		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv40_instmem_oclass;
204		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv41_mmu_oclass;
205		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
206		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
207		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
208		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
209		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
210		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
211		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
212		device->oclass[NVDEV_ENGINE_PM     ] =  nv40_pm_oclass;
213		break;
214	case 0x4b:
215		device->cname = "G73";
216		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nvkm_bios_oclass;
217		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv10_gpio_oclass;
218		device->oclass[NVDEV_SUBDEV_I2C    ] =  nv04_i2c_oclass;
219		device->oclass[NVDEV_SUBDEV_CLK    ] = &nv40_clk_oclass;
220		device->oclass[NVDEV_SUBDEV_THERM  ] = &nv40_therm_oclass;
221		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv1a_devinit_oclass;
222		device->oclass[NVDEV_SUBDEV_MC     ] =  nv40_mc_oclass;
223		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv31_bus_oclass;
224		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
225		device->oclass[NVDEV_SUBDEV_FB     ] =  nv49_fb_oclass;
226		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv40_instmem_oclass;
227		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv41_mmu_oclass;
228		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
229		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
230		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
231		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
232		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
233		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
234		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
235		device->oclass[NVDEV_ENGINE_PM     ] =  nv40_pm_oclass;
236		break;
237	case 0x44:
238		device->cname = "NV44";
239		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nvkm_bios_oclass;
240		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv10_gpio_oclass;
241		device->oclass[NVDEV_SUBDEV_I2C    ] =  nv04_i2c_oclass;
242		device->oclass[NVDEV_SUBDEV_CLK    ] = &nv40_clk_oclass;
243		device->oclass[NVDEV_SUBDEV_THERM  ] = &nv40_therm_oclass;
244		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv1a_devinit_oclass;
245		device->oclass[NVDEV_SUBDEV_MC     ] =  nv44_mc_oclass;
246		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv31_bus_oclass;
247		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
248		device->oclass[NVDEV_SUBDEV_FB     ] =  nv44_fb_oclass;
249		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv40_instmem_oclass;
250		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv44_mmu_oclass;
251		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
252		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
253		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
254		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
255		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
256		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
257		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
258		device->oclass[NVDEV_ENGINE_PM     ] =  nv40_pm_oclass;
259		break;
260	case 0x46:
261		device->cname = "G72";
262		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nvkm_bios_oclass;
263		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv10_gpio_oclass;
264		device->oclass[NVDEV_SUBDEV_I2C    ] =  nv04_i2c_oclass;
265		device->oclass[NVDEV_SUBDEV_CLK    ] = &nv40_clk_oclass;
266		device->oclass[NVDEV_SUBDEV_THERM  ] = &nv40_therm_oclass;
267		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv1a_devinit_oclass;
268		device->oclass[NVDEV_SUBDEV_MC     ] =  nv44_mc_oclass;
269		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv31_bus_oclass;
270		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
271		device->oclass[NVDEV_SUBDEV_FB     ] =  nv46_fb_oclass;
272		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv40_instmem_oclass;
273		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv44_mmu_oclass;
274		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
275		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
276		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
277		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
278		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
279		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
280		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
281		device->oclass[NVDEV_ENGINE_PM     ] =  nv40_pm_oclass;
282		break;
283	case 0x4a:
284		device->cname = "NV44A";
285		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nvkm_bios_oclass;
286		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv10_gpio_oclass;
287		device->oclass[NVDEV_SUBDEV_I2C    ] =  nv04_i2c_oclass;
288		device->oclass[NVDEV_SUBDEV_CLK    ] = &nv40_clk_oclass;
289		device->oclass[NVDEV_SUBDEV_THERM  ] = &nv40_therm_oclass;
290		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv1a_devinit_oclass;
291		device->oclass[NVDEV_SUBDEV_MC     ] =  nv44_mc_oclass;
292		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv31_bus_oclass;
293		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
294		device->oclass[NVDEV_SUBDEV_FB     ] =  nv44_fb_oclass;
295		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv40_instmem_oclass;
296		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv44_mmu_oclass;
297		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
298		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
299		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
300		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
301		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
302		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
303		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
304		device->oclass[NVDEV_ENGINE_PM     ] =  nv40_pm_oclass;
305		break;
306	case 0x4c:
307		device->cname = "C61";
308		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nvkm_bios_oclass;
309		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv10_gpio_oclass;
310		device->oclass[NVDEV_SUBDEV_I2C    ] =  nv04_i2c_oclass;
311		device->oclass[NVDEV_SUBDEV_CLK    ] = &nv40_clk_oclass;
312		device->oclass[NVDEV_SUBDEV_THERM  ] = &nv40_therm_oclass;
313		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv1a_devinit_oclass;
314		device->oclass[NVDEV_SUBDEV_MC     ] =  nv4c_mc_oclass;
315		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv31_bus_oclass;
316		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
317		device->oclass[NVDEV_SUBDEV_FB     ] =  nv46_fb_oclass;
318		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv40_instmem_oclass;
319		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv44_mmu_oclass;
320		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
321		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
322		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
323		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
324		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
325		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
326		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
327		device->oclass[NVDEV_ENGINE_PM     ] =  nv40_pm_oclass;
328		break;
329	case 0x4e:
330		device->cname = "C51";
331		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nvkm_bios_oclass;
332		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv10_gpio_oclass;
333		device->oclass[NVDEV_SUBDEV_I2C    ] =  nv4e_i2c_oclass;
334		device->oclass[NVDEV_SUBDEV_CLK    ] = &nv40_clk_oclass;
335		device->oclass[NVDEV_SUBDEV_THERM  ] = &nv40_therm_oclass;
336		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv1a_devinit_oclass;
337		device->oclass[NVDEV_SUBDEV_MC     ] =  nv4c_mc_oclass;
338		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv31_bus_oclass;
339		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
340		device->oclass[NVDEV_SUBDEV_FB     ] =  nv4e_fb_oclass;
341		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv40_instmem_oclass;
342		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv44_mmu_oclass;
343		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
344		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
345		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
346		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
347		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
348		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
349		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
350		device->oclass[NVDEV_ENGINE_PM     ] =  nv40_pm_oclass;
351		break;
352	case 0x63:
353		device->cname = "C73";
354		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nvkm_bios_oclass;
355		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv10_gpio_oclass;
356		device->oclass[NVDEV_SUBDEV_I2C    ] =  nv04_i2c_oclass;
357		device->oclass[NVDEV_SUBDEV_CLK    ] = &nv40_clk_oclass;
358		device->oclass[NVDEV_SUBDEV_THERM  ] = &nv40_therm_oclass;
359		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv1a_devinit_oclass;
360		device->oclass[NVDEV_SUBDEV_MC     ] =  nv4c_mc_oclass;
361		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv31_bus_oclass;
362		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
363		device->oclass[NVDEV_SUBDEV_FB     ] =  nv46_fb_oclass;
364		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv40_instmem_oclass;
365		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv44_mmu_oclass;
366		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
367		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
368		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
369		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
370		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
371		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
372		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
373		device->oclass[NVDEV_ENGINE_PM     ] =  nv40_pm_oclass;
374		break;
375	case 0x67:
376		device->cname = "C67";
377		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nvkm_bios_oclass;
378		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv10_gpio_oclass;
379		device->oclass[NVDEV_SUBDEV_I2C    ] =  nv04_i2c_oclass;
380		device->oclass[NVDEV_SUBDEV_CLK    ] = &nv40_clk_oclass;
381		device->oclass[NVDEV_SUBDEV_THERM  ] = &nv40_therm_oclass;
382		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv1a_devinit_oclass;
383		device->oclass[NVDEV_SUBDEV_MC     ] =  nv4c_mc_oclass;
384		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv31_bus_oclass;
385		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
386		device->oclass[NVDEV_SUBDEV_FB     ] =  nv46_fb_oclass;
387		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv40_instmem_oclass;
388		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv44_mmu_oclass;
389		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
390		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
391		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
392		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
393		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
394		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
395		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
396		device->oclass[NVDEV_ENGINE_PM     ] =  nv40_pm_oclass;
397		break;
398	case 0x68:
399		device->cname = "C68";
400		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nvkm_bios_oclass;
401		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv10_gpio_oclass;
402		device->oclass[NVDEV_SUBDEV_I2C    ] =  nv04_i2c_oclass;
403		device->oclass[NVDEV_SUBDEV_CLK    ] = &nv40_clk_oclass;
404		device->oclass[NVDEV_SUBDEV_THERM  ] = &nv40_therm_oclass;
405		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv1a_devinit_oclass;
406		device->oclass[NVDEV_SUBDEV_MC     ] =  nv4c_mc_oclass;
407		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv31_bus_oclass;
408		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
409		device->oclass[NVDEV_SUBDEV_FB     ] =  nv46_fb_oclass;
410		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv40_instmem_oclass;
411		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv44_mmu_oclass;
412		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
413		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
414		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
415		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
416		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
417		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
418		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
419		device->oclass[NVDEV_ENGINE_PM     ] =  nv40_pm_oclass;
420		break;
421	default:
422		nv_fatal(device, "unknown Curie chipset\n");
423		return -EINVAL;
424	}
425
426	return 0;
427}
428