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Searched refs:readl (Results 1 – 200 of 1392) sorted by relevance

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/linux-4.1.27/drivers/net/ethernet/stmicro/stmmac/
Dmmc_core.c137 u32 value = readl(ioaddr + MMC_CNTRL); in dwmac_mmc_ctrl()
162 mmc->mmc_tx_octetcount_gb += readl(ioaddr + MMC_TX_OCTETCOUNT_GB); in dwmac_mmc_read()
163 mmc->mmc_tx_framecount_gb += readl(ioaddr + MMC_TX_FRAMECOUNT_GB); in dwmac_mmc_read()
164 mmc->mmc_tx_broadcastframe_g += readl(ioaddr + MMC_TX_BROADCASTFRAME_G); in dwmac_mmc_read()
165 mmc->mmc_tx_multicastframe_g += readl(ioaddr + MMC_TX_MULTICASTFRAME_G); in dwmac_mmc_read()
166 mmc->mmc_tx_64_octets_gb += readl(ioaddr + MMC_TX_64_OCTETS_GB); in dwmac_mmc_read()
168 readl(ioaddr + MMC_TX_65_TO_127_OCTETS_GB); in dwmac_mmc_read()
170 readl(ioaddr + MMC_TX_128_TO_255_OCTETS_GB); in dwmac_mmc_read()
172 readl(ioaddr + MMC_TX_256_TO_511_OCTETS_GB); in dwmac_mmc_read()
174 readl(ioaddr + MMC_TX_512_TO_1023_OCTETS_GB); in dwmac_mmc_read()
[all …]
Dstmmac_hwtstamp.c38 u32 value = readl(ioaddr + PTP_TCR); in stmmac_config_sub_second_increment()
62 value = readl(ioaddr + PTP_TCR); in stmmac_init_systime()
69 if (!(readl(ioaddr + PTP_TCR) & PTP_TCR_TSINIT)) in stmmac_init_systime()
86 value = readl(ioaddr + PTP_TCR); in stmmac_config_addend()
93 if (!(readl(ioaddr + PTP_TCR) & PTP_TCR_TSADDREG)) in stmmac_config_addend()
113 value = readl(ioaddr + PTP_TCR); in stmmac_adjust_systime()
120 if (!(readl(ioaddr + PTP_TCR) & PTP_TCR_TSUPDT)) in stmmac_adjust_systime()
134 ns = readl(ioaddr + PTP_STNSR); in stmmac_get_systime()
136 ns += readl(ioaddr + PTP_STSR) * 1000000000ULL; in stmmac_get_systime()
Ddwmac_lib.c47 u32 value = readl(ioaddr + DMA_CONTROL); in dwmac_dma_start_tx()
54 u32 value = readl(ioaddr + DMA_CONTROL); in dwmac_dma_stop_tx()
61 u32 value = readl(ioaddr + DMA_CONTROL); in dwmac_dma_start_rx()
68 u32 value = readl(ioaddr + DMA_CONTROL); in dwmac_dma_stop_rx()
148 u32 intr_status = readl(ioaddr + DMA_STATUS); in dwmac_dma_interrupt()
189 u32 value = readl(ioaddr + DMA_INTR_ENA); in dwmac_dma_interrupt()
216 u32 csr6 = readl(ioaddr + DMA_CONTROL); in dwmac_dma_flush_tx_fifo()
219 do {} while ((readl(ioaddr + DMA_CONTROL) & DMA_CONTROL_FTF)); in dwmac_dma_flush_tx_fifo()
240 u32 value = readl(ioaddr + MAC_CTRL_REG); in stmmac_set_mac()
256 hi_addr = readl(ioaddr + high); in stmmac_get_mac_addr()
[all …]
Ddwmac100_core.c38 u32 value = readl(ioaddr + MAC_CONTROL); in dwmac100_core_init()
54 readl(ioaddr + MAC_CONTROL)); in dwmac100_dump_mac_regs()
56 readl(ioaddr + MAC_ADDR_HIGH)); in dwmac100_dump_mac_regs()
58 readl(ioaddr + MAC_ADDR_LOW)); in dwmac100_dump_mac_regs()
60 MAC_HASH_HIGH, readl(ioaddr + MAC_HASH_HIGH)); in dwmac100_dump_mac_regs()
62 MAC_HASH_LOW, readl(ioaddr + MAC_HASH_LOW)); in dwmac100_dump_mac_regs()
64 MAC_FLOW_CTRL, readl(ioaddr + MAC_FLOW_CTRL)); in dwmac100_dump_mac_regs()
66 readl(ioaddr + MAC_VLAN1)); in dwmac100_dump_mac_regs()
68 readl(ioaddr + MAC_VLAN2)); in dwmac100_dump_mac_regs()
102 u32 value = readl(ioaddr + MAC_CONTROL); in dwmac100_set_filter()
Ddwmac100_dma.c38 u32 value = readl(ioaddr + DMA_BUS_MODE); in dwmac100_dma_init()
46 if (!(readl(ioaddr + DMA_BUS_MODE) & DMA_BUS_MODE_SFT_RESET)) in dwmac100_dma_init()
77 u32 csr6 = readl(ioaddr + DMA_CONTROL); in dwmac100_dma_operation_mode()
97 readl(ioaddr + DMA_BUS_MODE + i * 4)); in dwmac100_dump_dma_regs()
100 DMA_CUR_TX_BUF_ADDR, readl(ioaddr + DMA_CUR_TX_BUF_ADDR), in dwmac100_dump_dma_regs()
101 DMA_CUR_RX_BUF_ADDR, readl(ioaddr + DMA_CUR_RX_BUF_ADDR)); in dwmac100_dump_dma_regs()
109 u32 csr8 = readl(ioaddr + DMA_MISSED_FRAME_CTR); in dwmac100_dma_diagnostic_fr()
Ddwmac1000_core.c38 u32 value = readl(ioaddr + GMAC_CONTROL); in dwmac1000_core_init()
59 u32 value = readl(ioaddr + GMAC_CONTROL); in dwmac1000_rx_ipc_enable()
68 value = readl(ioaddr + GMAC_CONTROL); in dwmac1000_rx_ipc_enable()
82 offset, readl(ioaddr + offset)); in dwmac1000_dump_regs()
248 u32 intr_status = readl(ioaddr + GMAC_INT_STATUS); in dwmac1000_irq_status()
260 readl(ioaddr + GMAC_PMT); in dwmac1000_irq_status()
266 ret = readl(ioaddr + LPI_CTRL_STATUS); in dwmac1000_irq_status()
279 readl(ioaddr + GMAC_AN_STATUS); in dwmac1000_irq_status()
283 u32 status = readl(ioaddr + GMAC_S_R_GMII); in dwmac1000_irq_status()
321 value = readl(ioaddr + LPI_CTRL_STATUS); in dwmac1000_set_eee_mode()
[all …]
Ddwmac1000_dma.c36 u32 value = readl(ioaddr + DMA_BUS_MODE); in dwmac1000_dma_init()
44 if (!(readl(ioaddr + DMA_BUS_MODE) & DMA_BUS_MODE_SFT_RESET)) in dwmac1000_dma_init()
133 u32 csr6 = readl(ioaddr + DMA_CONTROL); in dwmac1000_dma_operation_mode()
192 readl(ioaddr + DMA_BUS_MODE + offset)); in dwmac1000_dump_dma_regs()
199 return readl(ioaddr + DMA_HW_FEATURE); in dwmac1000_get_hw_feature()
/linux-4.1.27/drivers/video/fbdev/mbx/
Dmbxdebugfs.c35 s += sprintf(s, "SYSCFG = %08x\n", readl(SYSCFG)); in sysconf_read_file()
36 s += sprintf(s, "PFBASE = %08x\n", readl(PFBASE)); in sysconf_read_file()
37 s += sprintf(s, "PFCEIL = %08x\n", readl(PFCEIL)); in sysconf_read_file()
38 s += sprintf(s, "POLLFLAG = %08x\n", readl(POLLFLAG)); in sysconf_read_file()
39 s += sprintf(s, "SYSRST = %08x\n", readl(SYSRST)); in sysconf_read_file()
51 s += sprintf(s, "GSCTRL = %08x\n", readl(GSCTRL)); in gsctl_read_file()
52 s += sprintf(s, "VSCTRL = %08x\n", readl(VSCTRL)); in gsctl_read_file()
53 s += sprintf(s, "GBBASE = %08x\n", readl(GBBASE)); in gsctl_read_file()
54 s += sprintf(s, "VBBASE = %08x\n", readl(VBBASE)); in gsctl_read_file()
55 s += sprintf(s, "GDRCTRL = %08x\n", readl(GDRCTRL)); in gsctl_read_file()
[all …]
Dmbxfb.c239 u32 gsctrl = readl(GSCTRL); in mbxfb_set_par()
240 u32 gsadr = readl(GSADR); in mbxfb_set_par()
308 write_reg_dly((readl(DSCTRL) | DSCTRL_SYNCGEN_EN), DSCTRL); in mbxfb_set_par()
322 write_reg_dly((readl(DSCTRL) & ~DSCTRL_SYNCGEN_EN), DSCTRL); in mbxfb_blank()
323 write_reg_dly((readl(PIXCLK) & ~PIXCLK_EN), PIXCLK); in mbxfb_blank()
324 write_reg_dly((readl(VOVRCLK) & ~VOVRCLK_EN), VOVRCLK); in mbxfb_blank()
327 write_reg_dly((readl(DSCTRL) | DSCTRL_SYNCGEN_EN), DSCTRL); in mbxfb_blank()
328 write_reg_dly((readl(PIXCLK) | PIXCLK_EN), PIXCLK); in mbxfb_blank()
346 vovrclk = readl(VOVRCLK); in mbxfb_setupOverlay()
347 vsctrl = readl(VSCTRL); in mbxfb_setupOverlay()
[all …]
/linux-4.1.27/drivers/media/platform/s5p-jpeg/
Djpeg-hw-s5p.c25 reg = readl(regs + S5P_JPG_SW_RESET); in s5p_jpeg_reset()
29 reg = readl(regs + S5P_JPG_SW_RESET); in s5p_jpeg_reset()
48 reg = readl(regs + S5P_JPGCMOD); in s5p_jpeg_input_raw_mode()
63 reg = readl(regs + S5P_JPGMOD); in s5p_jpeg_proc_mode()
78 reg = readl(regs + S5P_JPGMOD); in s5p_jpeg_subsampling_mode()
86 return readl(regs + S5P_JPGMOD) & S5P_SUBSAMPLING_MODE_MASK; in s5p_jpeg_get_subsampling_mode()
93 reg = readl(regs + S5P_JPGDRI_U); in s5p_jpeg_dri()
98 reg = readl(regs + S5P_JPGDRI_L); in s5p_jpeg_dri()
108 reg = readl(regs + S5P_JPG_QTBL); in s5p_jpeg_qtbl()
118 reg = readl(regs + S5P_JPG_HTBL); in s5p_jpeg_htbl_ac()
[all …]
Djpeg-hw-exynos4.c23 reg = readl(base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_sw_reset()
35 reg = readl(base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_set_enc_dec_mode()
52 reg = readl(base + EXYNOS4_IMG_FMT_REG) & in exynos4_jpeg_set_img_fmt()
125 reg = readl(base + EXYNOS4_IMG_FMT_REG) & in exynos4_jpeg_set_enc_out_fmt()
161 int_status = readl(base + EXYNOS4_INT_STATUS_REG); in exynos4_jpeg_get_int_status()
170 fifo_status = readl(base + EXYNOS4_FIFO_STATUS_REG); in exynos4_jpeg_get_fifo_status()
179 reg = readl(base + EXYNOS4_JPEG_CNTL_REG) & ~EXYNOS4_HUF_TBL_EN; in exynos4_jpeg_set_huf_table_enable()
193 reg = readl(base + EXYNOS4_JPEG_CNTL_REG) & ~(EXYNOS4_SYS_INT_EN); in exynos4_jpeg_set_sys_int_enable()
249 size = readl(base + EXYNOS4_BITSTREAM_SIZE_REG); in exynos4_jpeg_get_stream_size()
261 *width = (readl(base + EXYNOS4_DECODE_XY_SIZE_REG) & in exynos4_jpeg_get_frame_size()
[all …]
Djpeg-hw-exynos3250.c31 reg = readl(regs + EXYNOS3250_SW_RESET); in exynos3250_jpeg_reset()
41 reg = readl(regs + EXYNOS3250_JPGDRI); in exynos3250_jpeg_reset()
67 reg = readl(base + EXYNOS3250_JPGCMOD) & ~EXYNOS3250_HALF_EN_MASK; in exynos3250_jpeg_clk_set()
76 reg = readl(regs + EXYNOS3250_JPGCMOD) & in exynos3250_jpeg_input_raw_fmt()
127 reg = readl(regs + EXYNOS3250_JPGCMOD); in exynos3250_jpeg_set_y16()
143 reg = readl(regs + EXYNOS3250_JPGMOD); in exynos3250_jpeg_proc_mode()
165 reg = readl(regs + EXYNOS3250_JPGMOD); in exynos3250_jpeg_subsampling_mode()
173 return readl(regs + EXYNOS3250_JPGMOD) & in exynos3250_jpeg_get_subsampling_mode()
189 reg = readl(regs + EXYNOS3250_QHTBL); in exynos3250_jpeg_qtbl()
200 reg = readl(regs + EXYNOS3250_QHTBL); in exynos3250_jpeg_htbl_ac()
[all …]
/linux-4.1.27/drivers/video/fbdev/exynos/
Dexynos_mipi_dsi_lowlevel.c36 reg = readl(dsim->reg_base + EXYNOS_DSIM_SWRST); in exynos_mipi_dsi_func_reset()
47 reg = readl(dsim->reg_base + EXYNOS_DSIM_SWRST); in exynos_mipi_dsi_sw_reset()
58 reg = readl(dsim->reg_base + EXYNOS_DSIM_INTSRC); in exynos_mipi_dsi_sw_reset_release()
67 return (readl(dsim->reg_base + EXYNOS_DSIM_INTSRC)) & in exynos_mipi_dsi_get_sw_reset_release()
75 reg = readl(dsim->reg_base + EXYNOS_DSIM_INTMSK); in exynos_mipi_dsi_read_interrupt_mask()
98 reg = readl(dsim->reg_base + EXYNOS_DSIM_FIFOCTRL); in exynos_mipi_dsi_init_fifo_pointer()
121 reg = readl(dsim->reg_base + EXYNOS_DSIM_MDRESOL); in exynos_mipi_dsi_set_main_stand_by()
137 reg = (readl(dsim->reg_base + EXYNOS_DSIM_MDRESOL)) & in exynos_mipi_dsi_set_main_disp_resol()
153 reg = (readl(dsim->reg_base + EXYNOS_DSIM_MVPORCH)) & in exynos_mipi_dsi_set_main_disp_vporch()
169 reg = (readl(dsim->reg_base + EXYNOS_DSIM_MHPORCH)) & in exynos_mipi_dsi_set_main_disp_hporch()
[all …]
/linux-4.1.27/arch/unicore32/kernel/
Dtime.c29 writel(readl(OST_OIER) & ~OST_OIER_E0, OST_OIER); in puv3_ost0_interrupt()
30 writel(readl(OST_OSSR) & ~OST_OSSR_M0, OST_OSSR); in puv3_ost0_interrupt()
41 writel(readl(OST_OIER) | OST_OIER_E0, OST_OIER); in puv3_osmr0_set_next_event()
42 next = readl(OST_OSCR) + delta; in puv3_osmr0_set_next_event()
44 oscr = readl(OST_OSCR); in puv3_osmr0_set_next_event()
56 writel(readl(OST_OIER) & ~OST_OIER_E0, OST_OIER); in puv3_osmr0_set_mode()
57 writel(readl(OST_OSSR) & ~OST_OSSR_M0, OST_OSSR); in puv3_osmr0_set_mode()
76 return readl(OST_OSCR); in puv3_read_oscr()
118 osmr[0] = readl(OST_OSMR0); in puv3_timer_suspend()
119 osmr[1] = readl(OST_OSMR1); in puv3_timer_suspend()
[all …]
Dirq.c84 writel(readl(INTC_ICMR) & ~(1 << d->irq), INTC_ICMR); in puv3_low_gpio_mask()
89 writel(readl(INTC_ICMR) | (1 << d->irq), INTC_ICMR); in puv3_low_gpio_unmask()
95 writel(readl(PM_PWER) | (1 << d->irq), PM_PWER); in puv3_low_gpio_wake()
97 writel(readl(PM_PWER) & ~(1 << d->irq), PM_PWER); in puv3_low_gpio_wake()
120 mask = readl(GPIO_GEDR); in puv3_gpio_handler()
135 mask = readl(GPIO_GEDR); in puv3_gpio_handler()
157 writel(readl(GPIO_GRER) & ~mask, GPIO_GRER); in puv3_high_gpio_mask()
158 writel(readl(GPIO_GFER) & ~mask, GPIO_GFER); in puv3_high_gpio_mask()
174 writel(readl(PM_PWER) | PM_PWER_GPIOHIGH, PM_PWER); in puv3_high_gpio_wake()
176 writel(readl(PM_PWER) & ~PM_PWER_GPIOHIGH, PM_PWER); in puv3_high_gpio_wake()
[all …]
Dclock.c156 if (readl(PM_PLLVGACFG) == pll_vgacfg) in clk_set_rate()
163 while ((readl(PM_PLLDFCDONE) & PM_PLLDFCDONE_VGADFC) in clk_set_rate()
168 writel(readl(PM_PCGR) | PM_PCGR_VGACLK, PM_PCGR); in clk_set_rate()
170 writel((readl(PM_DIVCFG) & ~PM_DIVCFG_VGACLK_MASK) in clk_set_rate()
173 writel(readl(PM_SWRESET) | PM_SWRESET_VGADIV, PM_SWRESET); in clk_set_rate()
174 while ((readl(PM_SWRESET) & PM_SWRESET_VGADIV) in clk_set_rate()
178 writel(readl(PM_PCGR) & ~PM_PCGR_VGACLK, PM_PCGR); in clk_set_rate()
182 u32 pll_rate, divstatus = readl(PM_DIVSTATUS); in clk_set_rate()
207 while ((readl(PM_PLLDFCDONE) & PM_PLLDFCDONE_SYSDFC) in clk_set_rate()
328 u32 pllrate, divstatus = readl(PM_DIVSTATUS); in clk_init()
[all …]
/linux-4.1.27/drivers/net/ethernet/samsung/sxgbe/
Dsxgbe_core.c29 regval = readl(ioaddr + SXGBE_CORE_TX_CONFIG_REG); in sxgbe_core_init()
37 regval = readl(ioaddr + SXGBE_CORE_RX_CONFIG_REG); in sxgbe_core_init()
57 lpi_status = readl(ioaddr + SXGBE_CORE_LPI_CTRL_STATUS); in sxgbe_get_lpi_status()
77 irq_status = readl(ioaddr + SXGBE_CORE_INT_STATUS_REG); in sxgbe_core_host_irq_status()
108 high_word = readl(ioaddr + SXGBE_CORE_ADD_HIGHOFFSET(reg_n)); in sxgbe_core_get_umac_addr()
109 low_word = readl(ioaddr + SXGBE_CORE_ADD_LOWOFFSET(reg_n)); in sxgbe_core_get_umac_addr()
124 tx_config = readl(ioaddr + SXGBE_CORE_TX_CONFIG_REG); in sxgbe_enable_tx()
136 rx_config = readl(ioaddr + SXGBE_CORE_RX_CONFIG_REG); in sxgbe_enable_rx()
146 return readl(ioaddr + SXGBE_CORE_VERSION_REG); in sxgbe_get_controller_version()
153 return readl(ioaddr + (SXGBE_CORE_HW_FEA_REG(feature_index))); in sxgbe_get_hw_feature()
[all …]
Dsxgbe_mtl.c28 reg_val = readl(ioaddr + SXGBE_MTL_OP_MODE_REG); in sxgbe_mtl_init()
71 reg_val = readl(ioaddr + SXGBE_MTL_TXQ_OPMODE_REG(queue_num)); in sxgbe_mtl_set_txfifosize()
83 reg_val = readl(ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num)); in sxgbe_mtl_set_rxfifosize()
92 reg_val = readl(ioaddr + SXGBE_MTL_TXQ_OPMODE_REG(queue_num)); in sxgbe_mtl_enable_txqueue()
101 reg_val = readl(ioaddr + SXGBE_MTL_TXQ_OPMODE_REG(queue_num)); in sxgbe_mtl_disable_txqueue()
111 reg_val = readl(ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num)); in sxgbe_mtl_fc_active()
122 reg_val = readl(ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num)); in sxgbe_mtl_fc_enable()
132 reg_val = readl(ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num)); in sxgbe_mtl_fc_deactive()
143 reg_val = readl(ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num)); in sxgbe_mtl_fep_enable()
153 reg_val = readl(ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num)); in sxgbe_mtl_fep_disable()
[all …]
Dsxgbe_dma.c28 reg_val = readl(ioaddr + SXGBE_DMA_SYSBUS_MODE_REG); in sxgbe_dma_init()
53 reg_val = readl(ioaddr + SXGBE_DMA_CHA_CTL_REG(cha_num)); in sxgbe_dma_channel_init()
59 reg_val = readl(ioaddr + SXGBE_DMA_CHA_TXCTL_REG(cha_num)); in sxgbe_dma_channel_init()
63 reg_val = readl(ioaddr + SXGBE_DMA_CHA_RXCTL_REG(cha_num)); in sxgbe_dma_channel_init()
103 tx_config = readl(ioaddr + SXGBE_DMA_CHA_TXCTL_REG(cha_num)); in sxgbe_enable_dma_transmission()
127 tx_ctl_reg = readl(ioaddr + SXGBE_DMA_CHA_TXCTL_REG(cnum)); in sxgbe_dma_start_tx()
138 tx_ctl_reg = readl(ioaddr + SXGBE_DMA_CHA_TXCTL_REG(dma_cnum)); in sxgbe_dma_start_tx_queue()
147 tx_ctl_reg = readl(ioaddr + SXGBE_DMA_CHA_TXCTL_REG(dma_cnum)); in sxgbe_dma_stop_tx_queue()
158 tx_ctl_reg = readl(ioaddr + SXGBE_DMA_CHA_TXCTL_REG(cnum)); in sxgbe_dma_stop_tx()
170 rx_ctl_reg = readl(ioaddr + SXGBE_DMA_CHA_RXCTL_REG(cnum)); in sxgbe_dma_start_rx()
[all …]
/linux-4.1.27/drivers/ata/
Dahci_xgene.c102 readl(ctx->csr_diag + CFG_MEM_RAM_SHUTDOWN); /* Force a barrier */ in xgene_ahci_init_memram()
104 if (readl(ctx->csr_diag + BLOCK_MEM_RDY) != 0xFFFFFFFF) { in xgene_ahci_init_memram()
170 fbs = readl(port_mmio + PORT_FBS); in xgene_ahci_restart_engine()
172 fbs = readl(port_mmio + PORT_FBS); in xgene_ahci_restart_engine()
210 port_fbs = readl(port_mmio + PORT_FBS); in xgene_ahci_qc_issue()
233 return (readl(diagcsr + CFG_MEM_RAM_SHUTDOWN) == 0 && in xgene_ahci_is_memram_inited()
234 readl(diagcsr + BLOCK_MEM_RDY) == 0xFFFFFFFF); in xgene_ahci_is_memram_inited()
281 val = readl(mmio + PORTCFG); in xgene_ahci_set_phy_cfg()
284 readl(mmio + PORTCFG); /* Force a barrier */ in xgene_ahci_set_phy_cfg()
287 readl(mmio + PORTPHY1CFG); /* Force a barrier */ in xgene_ahci_set_phy_cfg()
[all …]
Dsata_sx4.c509 readl(dimm_mmio); /* MMIO PCI posting flush */ in pdc20621_dma_prep()
544 readl(dimm_mmio); /* MMIO PCI posting flush */ in pdc20621_nodata_prep()
575 readl(mmio + PDC_20621_SEQCTL + (seq * 4)); /* flush */ in __pdc20621_push_hdma()
578 readl(mmio + PDC_HDMA_PKT_SUBMIT); /* flush */ in __pdc20621_push_hdma()
628 printk(KERN_ERR "HDMA[0] == 0x%08X\n", readl(dimm_mmio)); in pdc20621_dump_hdma()
629 printk(KERN_ERR "HDMA[1] == 0x%08X\n", readl(dimm_mmio + 4)); in pdc20621_dump_hdma()
630 printk(KERN_ERR "HDMA[2] == 0x%08X\n", readl(dimm_mmio + 8)); in pdc20621_dump_hdma()
631 printk(KERN_ERR "HDMA[3] == 0x%08X\n", readl(dimm_mmio + 12)); in pdc20621_dump_hdma()
668 readl(mmio + PDC_20621_SEQCTL + (seq * 4)); /* flush */ in pdc20621_packet_start()
672 readl(ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); in pdc20621_packet_start()
[all …]
Dlibahci.c207 tmp = readl(mmio + HOST_CTL); in ahci_enable_ahci()
217 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */ in ahci_enable_ahci()
254 return sprintf(buf, "%x\n", readl(mmio + HOST_VERSION)); in ahci_show_host_version()
264 return sprintf(buf, "%x\n", readl(port_mmio + PORT_CMD)); in ahci_show_port_cmd()
282 em_ctl = readl(mmio + HOST_EM_CTL); in ahci_read_em_buffer()
310 msg = readl(em_mmio + i); in ahci_read_em_buffer()
344 em_ctl = readl(mmio + HOST_EM_CTL); in ahci_store_em_buffer()
372 em_ctl = readl(mmio + HOST_EM_CTL); in ahci_show_em_supported()
411 hpriv->saved_cap = cap = readl(mmio + HOST_CAP); in ahci_save_initial_config()
412 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL); in ahci_save_initial_config()
[all …]
Dpata_arasan_cf.c231 dev_dbg(dev, ": CFI_STS: %x", readl(acdev->vbase + CFI_STS)); in cf_dumpregs()
232 dev_dbg(dev, ": IRQ_STS: %x", readl(acdev->vbase + IRQ_STS)); in cf_dumpregs()
233 dev_dbg(dev, ": IRQ_EN: %x", readl(acdev->vbase + IRQ_EN)); in cf_dumpregs()
234 dev_dbg(dev, ": OP_MODE: %x", readl(acdev->vbase + OP_MODE)); in cf_dumpregs()
235 dev_dbg(dev, ": CLK_CFG: %x", readl(acdev->vbase + CLK_CFG)); in cf_dumpregs()
236 dev_dbg(dev, ": TM_CFG: %x", readl(acdev->vbase + TM_CFG)); in cf_dumpregs()
237 dev_dbg(dev, ": XFER_CTR: %x", readl(acdev->vbase + XFER_CTR)); in cf_dumpregs()
238 dev_dbg(dev, ": GIRQ_STS: %x", readl(acdev->vbase + GIRQ_STS)); in cf_dumpregs()
239 dev_dbg(dev, ": GIRQ_STS_EN: %x", readl(acdev->vbase + GIRQ_STS_EN)); in cf_dumpregs()
240 dev_dbg(dev, ": GIRQ_SGN_EN: %x", readl(acdev->vbase + GIRQ_SGN_EN)); in cf_dumpregs()
[all …]
Dsata_promise.c368 tmp = readl(sata_mmio + PDC_PHYMODE4); in pdc_sata_port_start()
381 tmp = readl(sata_mmio + PDC_FPDMA_CTLSTAT); in pdc_fpdma_clear_interrupt_flag()
396 tmp = (u8)readl(sata_mmio + PDC_FPDMA_CTLSTAT); in pdc_fpdma_reset()
400 readl(sata_mmio + PDC_FPDMA_CTLSTAT); /* flush */ in pdc_fpdma_reset()
404 readl(sata_mmio + PDC_FPDMA_CTLSTAT); /* flush */ in pdc_fpdma_reset()
418 tmp = readl(sata_mmio + PDC_INTERNAL_DEBUG_2); in pdc_not_at_command_packet_phase()
442 tmp = readl(ata_ctlstat_mmio); in pdc_reset_port()
447 tmp = readl(ata_ctlstat_mmio); in pdc_reset_port()
459 readl(ata_ctlstat_mmio); /* flush */ in pdc_reset_port()
488 *val = readl(link->ap->ioaddr.scr_addr + (sc_reg * 4)); in pdc_sata_scr_read()
[all …]
Dsata_mv.c872 (void) readl(addr); /* flush to avoid PCI posted write */ in writelfl()
960 pp->cached.fiscfg = readl(port_mmio + FISCFG); in mv_save_cached_regs()
961 pp->cached.ltmode = readl(port_mmio + LTMODE); in mv_save_cached_regs()
962 pp->cached.haltcond = readl(port_mmio + EDMA_HALTCOND); in mv_save_cached_regs()
963 pp->cached.unknown_rsvd = readl(port_mmio + EDMA_UNKNOWN_RSVD); in mv_save_cached_regs()
1211 u32 edma_stat = readl(port_mmio + EDMA_STATUS); in mv_wait_for_edma_empty_idle()
1235 u32 reg = readl(port_mmio + EDMA_CMD); in mv_stop_edma_engine()
1268 printk("%08x ", readl(start + b)); in mv_dump_mem()
1363 *val = readl(mv_ap_base(link->ap) + ofs); in mv_scr_read()
1390 if ((val & 0xf) == 1 || (readl(addr) & 0xf) == 1) in mv_scr_write()
[all …]
/linux-4.1.27/drivers/gpu/drm/exynos/
Dexynos_dp_reg.c32 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1); in exynos_dp_enable_video_mute()
36 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1); in exynos_dp_enable_video_mute()
46 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1); in exynos_dp_stop_video()
182 reg = readl(dp->reg_base + EXYNOS_DP_DEBUG_CTL); in exynos_dp_get_pll_lock_status()
194 reg = readl(dp->reg_base + EXYNOS_DP_PLL_CTL); in exynos_dp_set_pll_power_down()
198 reg = readl(dp->reg_base + EXYNOS_DP_PLL_CTL); in exynos_dp_set_pll_power_down()
213 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD); in exynos_dp_set_analog_power_down()
217 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD); in exynos_dp_set_analog_power_down()
224 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD); in exynos_dp_set_analog_power_down()
228 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD); in exynos_dp_set_analog_power_down()
[all …]
/linux-4.1.27/drivers/scsi/bfa/
Dbfa_ioc_ct.c67 usecnt = readl(ioc->ioc_regs.ioc_usage_reg); in bfa_ioc_ct_firmware_lock()
74 readl(ioc->ioc_regs.ioc_usage_sem_reg); in bfa_ioc_ct_firmware_lock()
81 ioc_fwstate = readl(ioc->ioc_regs.ioc_fwstate); in bfa_ioc_ct_firmware_lock()
94 readl(ioc->ioc_regs.ioc_usage_sem_reg); in bfa_ioc_ct_firmware_lock()
105 readl(ioc->ioc_regs.ioc_usage_sem_reg); in bfa_ioc_ct_firmware_lock()
120 usecnt = readl(ioc->ioc_regs.ioc_usage_reg); in bfa_ioc_ct_firmware_unlock()
127 readl(ioc->ioc_regs.ioc_usage_sem_reg); in bfa_ioc_ct_firmware_unlock()
141 readl(ioc->ioc_regs.ll_halt); in bfa_ioc_ct_notify_fail()
142 readl(ioc->ioc_regs.alt_ll_halt); in bfa_ioc_ct_notify_fail()
145 readl(ioc->ioc_regs.err_set); in bfa_ioc_ct_notify_fail()
[all …]
Dbfa_ioc_cb.c122 readl(ioc->ioc_regs.err_set); in bfa_ioc_cb_notify_fail()
225 u32 ioc_fwstate = readl(ioc->ioc_regs.ioc_fwstate); in bfa_ioc_cb_sync_start()
254 readl(ioc->ioc_regs.ioc_sem_reg); in bfa_ioc_cb_ownership_reset()
264 u32 r32 = readl(ioc->ioc_regs.ioc_fwstate); in bfa_ioc_cb_sync_join()
273 u32 r32 = readl(ioc->ioc_regs.ioc_fwstate); in bfa_ioc_cb_sync_leave()
283 u32 r32 = readl(ioc->ioc_regs.ioc_fwstate); in bfa_ioc_cb_set_cur_ioc_fwstate()
292 return (enum bfi_ioc_state)(readl(ioc->ioc_regs.ioc_fwstate) & in bfa_ioc_cb_get_cur_ioc_fwstate()
300 u32 r32 = readl(ioc->ioc_regs.alt_ioc_fwstate); in bfa_ioc_cb_set_alt_ioc_fwstate()
309 return (enum bfi_ioc_state)(readl(ioc->ioc_regs.alt_ioc_fwstate) & in bfa_ioc_cb_get_alt_ioc_fwstate()
376 join_bits = readl(rb + BFA_IOC0_STATE_REG) & in bfa_ioc_cb_pll_init()
[all …]
/linux-4.1.27/drivers/i2c/busses/
Di2c-pxa.c248 readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c))); in i2c_pxa_show_state()
260 readl(_ICR(i2c)), readl(_ISR(i2c))); in i2c_pxa_scream_blue_murder()
283 return !(readl(_ICR(i2c)) & ICR_SCLE); in i2c_pxa_is_slavemode()
295 while ((i > 0) && (readl(_IBMR(i2c)) & 0x1) == 0) { in i2c_pxa_abort()
296 unsigned long icr = readl(_ICR(i2c)); in i2c_pxa_abort()
309 writel(readl(_ICR(i2c)) & ~(ICR_MA | ICR_START | ICR_STOP), in i2c_pxa_abort()
317 while (timeout-- && readl(_ISR(i2c)) & (ISR_IBB | ISR_UB)) { in i2c_pxa_wait_bus_not_busy()
318 if ((readl(_ISR(i2c)) & ISR_SAD) != 0) in i2c_pxa_wait_bus_not_busy()
338 __func__, (long)jiffies, readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c))); in i2c_pxa_wait_master()
340 if (readl(_ISR(i2c)) & ISR_SAD) { in i2c_pxa_wait_master()
[all …]
Di2c-axxia.c111 int_en = readl(idev->base + MST_INT_ENABLE); in i2c_int_disable()
119 int_en = readl(idev->base + MST_INT_ENABLE); in i2c_int_enable()
147 while (readl(idev->base + SOFT_RESET) & 1) { in axxia_i2c_init()
228 size_t rx_fifo_avail = readl(idev->base + MST_RX_FIFO); in axxia_i2c_empty_rx_fifo()
232 int c = readl(idev->base + MST_DATA); in axxia_i2c_empty_rx_fifo()
260 size_t tx_fifo_avail = FIFO_SIZE - readl(idev->base + MST_TX_FIFO); in axxia_i2c_fill_tx_fifo()
275 if (!(readl(idev->base + INTERRUPT_STATUS) & INT_MST)) in axxia_i2c_isr()
279 status = readl(idev->base + MST_INT_STATUS); in axxia_i2c_isr()
318 readl(idev->base + MST_RX_BYTES_XFRD), in axxia_i2c_isr()
319 readl(idev->base + MST_RX_XFER), in axxia_i2c_isr()
[all …]
Di2c-ismt.c237 readl(priv->smba + ISMT_GR_GCTRL)); in ismt_gen_reg_dump()
243 readl(priv->smba + ISMT_GR_ERRINTMSK)); in ismt_gen_reg_dump()
246 readl(priv->smba + ISMT_GR_ERRAERMSK)); in ismt_gen_reg_dump()
249 readl(priv->smba + ISMT_GR_ERRSTS)); in ismt_gen_reg_dump()
252 readl(priv->smba + ISMT_GR_ERRINFO)); in ismt_gen_reg_dump()
269 readl(priv->smba + ISMT_MSTR_MCTRL)); in ismt_mstr_reg_dump()
272 readl(priv->smba + ISMT_MSTR_MSTS)); in ismt_mstr_reg_dump()
275 readl(priv->smba + ISMT_MSTR_MDS)); in ismt_mstr_reg_dump()
278 readl(priv->smba + ISMT_MSTR_RPOLICY)); in ismt_mstr_reg_dump()
281 readl(priv->smba + ISMT_SPGT)); in ismt_mstr_reg_dump()
[all …]
Di2c-s3c2410.c207 tmp = readl(i2c->regs + S3C2410_IICCON); in s3c24xx_i2c_disable_ack()
215 tmp = readl(i2c->regs + S3C2410_IICCON); in s3c24xx_i2c_enable_ack()
225 tmp = readl(i2c->regs + S3C2410_IICCON); in s3c24xx_i2c_disable_irq()
233 tmp = readl(i2c->regs + S3C2410_IICCON); in s3c24xx_i2c_enable_irq()
242 if (readl(i2c->regs + S3C2410_IICCON) in is_ack()
244 if (!(readl(i2c->regs + S3C2410_IICSTAT) in is_ack()
281 iiccon = readl(i2c->regs + S3C2410_IICCON); in s3c24xx_i2c_message_start()
301 stat = readl(i2c->regs + S3C2410_IICSTAT); in s3c24xx_i2c_message_start()
311 unsigned long iicstat = readl(i2c->regs + S3C2410_IICSTAT); in s3c24xx_i2c_stop()
564 tmp = readl(i2c->regs + S3C2410_IICCON); in i2c_s3c_irq_nextbyte()
[all …]
Di2c-bcm-iproc.c107 u32 status = readl(iproc_i2c->base + IS_OFFSET); in bcm_iproc_i2c_isr()
126 val = readl(iproc_i2c->base + M_CMD_OFFSET); in bcm_iproc_i2c_check_status()
164 if (!!(readl(iproc_i2c->base + M_CMD_OFFSET) & in bcm_iproc_i2c_xfer_single_msg()
216 readl(iproc_i2c->base + IE_OFFSET); in bcm_iproc_i2c_xfer_single_msg()
246 msg->buf[i] = (readl(iproc_i2c->base + M_RX_OFFSET) >> in bcm_iproc_i2c_xfer_single_msg()
312 val = readl(iproc_i2c->base + TIM_CFG_OFFSET); in bcm_iproc_i2c_cfg_speed()
327 val = readl(iproc_i2c->base + CFG_OFFSET); in bcm_iproc_i2c_init()
357 val = readl(iproc_i2c->base + CFG_OFFSET); in bcm_iproc_i2c_enable_disable()
433 readl(iproc_i2c->base + IE_OFFSET); in bcm_iproc_i2c_remove()
Di2c-sirf.c96 data = readl(siic->base + SIRFSOC_I2C_DATA_BUF + i); in i2c_sirfsoc_read_data()
143 u32 i2c_stat = readl(siic->base + SIRFSOC_I2C_STATUS); in i2c_sirfsoc_irq()
160 writel(readl(siic->base + SIRFSOC_I2C_CTRL) | SIRFSOC_I2C_RESET, in i2c_sirfsoc_irq()
162 while (readl(siic->base + SIRFSOC_I2C_CTRL) & SIRFSOC_I2C_RESET) in i2c_sirfsoc_irq()
206 u32 regval = readl(siic->base + SIRFSOC_I2C_CTRL); in i2c_sirfsoc_xfer_msg()
227 writel(readl(siic->base + SIRFSOC_I2C_CTRL) | SIRFSOC_I2C_RESET, in i2c_sirfsoc_xfer_msg()
229 while (readl(siic->base + SIRFSOC_I2C_CTRL) & SIRFSOC_I2C_RESET) in i2c_sirfsoc_xfer_msg()
349 while (readl(siic->base + SIRFSOC_I2C_CTRL) & SIRFSOC_I2C_RESET) in i2c_sirfsoc_probe()
415 siic->sda_delay = readl(siic->base + SIRFSOC_I2C_SDA_DELAY); in i2c_sirfsoc_suspend()
416 siic->clk_div = readl(siic->base + SIRFSOC_I2C_CLK_CTRL); in i2c_sirfsoc_suspend()
[all …]
Di2c-puv3.c36 } while (!(readl(I2C_STATUS) & bit) && (--loop_cntr > 0)); in poll_status()
40 if (readl(I2C_TAR) == I2C_TAR_EEPROM) in poll_status()
44 } while (!(readl(I2C_RXFLR) & 0xf) && (--loop_cntr > 0)); in poll_status()
77 *buf = (readl(I2C_DATACMD) & I2C_DATACMD_DAT_MASK); in xfer_read()
254 if (readl(I2C_ENSTATUS) & I2C_ENSTATUS_ENABLE) in puv3_i2c_suspend()
/linux-4.1.27/drivers/net/ethernet/brocade/bna/
Dbfa_ioc_ct.c134 usecnt = readl(ioc->ioc_regs.ioc_usage_reg); in bfa_ioc_ct_firmware_lock()
146 ioc_fwstate = readl(ioc->ioc_regs.ioc_fwstate); in bfa_ioc_ct_firmware_lock()
187 usecnt = readl(ioc->ioc_regs.ioc_usage_reg); in bfa_ioc_ct_firmware_unlock()
203 readl(ioc->ioc_regs.ll_halt); in bfa_ioc_ct_notify_fail()
204 readl(ioc->ioc_regs.alt_ll_halt); in bfa_ioc_ct_notify_fail()
386 r32 = readl(rb + FNC_PERS_REG); in bfa_ioc_ct_map_port()
398 r32 = readl(rb + CT2_HOSTFN_PERSONALITY0); in bfa_ioc_ct2_map_port()
409 r32 = readl(rb + FNC_PERS_REG); in bfa_ioc_ct_isr_mode_set()
436 r32 = readl(ioc->ioc_regs.lpu_read_stat); in bfa_ioc_ct2_lpu_read_stat()
459 r32 = readl(rb + HOSTFN_MSIX_VT_OFST_NUMVT); in bfa_nw_ioc_ct2_poweron()
[all …]
Dbna_hw_defs.h165 init_halt = readl((_bna)->ioceth.ioc.ioc_regs.ll_halt); \
168 init_halt = readl((_bna)->ioceth.ioc.ioc_regs.ll_halt); \
173 (_cur_mask) = readl((_bna)->regs.fn_int_mask); \
182 mask = readl((bna)->regs.fn_int_mask); \
185 mask = readl((bna)->regs.fn_int_mask); \
191 mask = readl((bna)->regs.fn_int_mask); \
194 mask = readl((bna)->regs.fn_int_mask); \
199 (_status) = readl((_bna)->regs.fn_int_status); \
/linux-4.1.27/drivers/media/platform/exynos4-is/
Dfimc-lite-reg.c28 cfg = readl(dev->regs + FLITE_REG_CIGCTRL); in flite_hw_reset()
33 cfg = readl(dev->regs + FLITE_REG_CIGCTRL); in flite_hw_reset()
45 u32 cfg = readl(dev->regs + FLITE_REG_CISTATUS); in flite_hw_clear_pending_irq()
52 u32 intsrc = readl(dev->regs + FLITE_REG_CISTATUS); in flite_hw_get_interrupt_source()
59 u32 cfg = readl(dev->regs + FLITE_REG_CISTATUS2); in flite_hw_clear_last_capture_end()
80 cfg = readl(dev->regs + FLITE_REG_CIGCTRL); in flite_hw_set_interrupt_mask()
88 u32 cfg = readl(dev->regs + FLITE_REG_CIIMGCPT); in flite_hw_capture_start()
95 u32 cfg = readl(dev->regs + FLITE_REG_CIIMGCPT); in flite_hw_capture_stop()
106 u32 cfg = readl(dev->regs + FLITE_REG_CIGCTRL); in flite_hw_set_test_pattern()
147 cfg = readl(dev->regs + FLITE_REG_CIGCTRL); in flite_hw_set_source_format()
[all …]
Dfimc-reg.c26 cfg = readl(dev->regs + FIMC_REG_CISRCFMT); in fimc_hw_reset()
31 cfg = readl(dev->regs + FIMC_REG_CIGCTRL); in fimc_hw_reset()
36 cfg = readl(dev->regs + FIMC_REG_CIGCTRL); in fimc_hw_reset()
79 cfg = readl(dev->regs + FIMC_REG_CITRGFMT); in fimc_hw_set_rotation()
100 flip = readl(dev->regs + FIMC_REG_MSCTRL); in fimc_hw_set_rotation()
116 cfg = readl(dev->regs + FIMC_REG_CITRGFMT); in fimc_hw_set_target_format()
144 cfg = readl(dev->regs + FIMC_REG_CITAREA); in fimc_hw_set_target_format()
160 cfg = readl(dev->regs + FIMC_REG_CIGCTRL); in fimc_hw_set_out_dma_size()
190 cfg = readl(dev->regs + FIMC_REG_CIOCTRL); in fimc_hw_set_out_dma()
216 u32 cfg = readl(dev->regs + FIMC_REG_ORGISIZE); in fimc_hw_en_autoload()
[all …]
/linux-4.1.27/drivers/usb/dwc2/
Dcore_intr.c83 u32 hprt0 = readl(hsotg->regs + HPRT0); in dwc2_handle_usb_port_intr()
120 gotgint = readl(hsotg->regs + GOTGINT); in dwc2_handle_otg_intr()
121 gotgctl = readl(hsotg->regs + GOTGCTL); in dwc2_handle_otg_intr()
129 gotgctl = readl(hsotg->regs + GOTGCTL); in dwc2_handle_otg_intr()
155 gotgctl = readl(hsotg->regs + GOTGCTL); in dwc2_handle_otg_intr()
163 gotgctl = readl(hsotg->regs + GOTGCTL); in dwc2_handle_otg_intr()
171 gotgctl = readl(hsotg->regs + GOTGCTL); in dwc2_handle_otg_intr()
183 gotgctl = readl(hsotg->regs + GOTGCTL); in dwc2_handle_otg_intr()
203 gintmsk = readl(hsotg->regs + GINTMSK); in dwc2_handle_otg_intr()
219 gotgctl = readl(hsotg->regs + GOTGCTL); in dwc2_handle_otg_intr()
[all …]
Dcore.c107 hcfg = readl(hsotg->regs + HCFG); in dwc2_init_fs_ls_pclk_sel()
128 greset = readl(hsotg->regs + GRSTCTL); in dwc2_core_reset()
143 greset = readl(hsotg->regs + GRSTCTL); in dwc2_core_reset()
153 gusbcfg = readl(hsotg->regs + GUSBCFG); in dwc2_core_reset()
158 gusbcfg = readl(hsotg->regs + GUSBCFG); in dwc2_core_reset()
163 gusbcfg = readl(hsotg->regs + GUSBCFG); in dwc2_core_reset()
189 usbcfg = readl(hsotg->regs + GUSBCFG); in dwc2_fs_phy_init()
214 usbcfg = readl(hsotg->regs + GUSBCFG); in dwc2_fs_phy_init()
219 i2cctl = readl(hsotg->regs + GI2CCTL); in dwc2_fs_phy_init()
239 usbcfg = readl(hsotg->regs + GUSBCFG); in dwc2_hs_phy_init()
[all …]
Dgadget.c61 writel(readl(ptr) | val, ptr); in __orr32()
66 writel(readl(ptr) & ~val, ptr); in __bic32()
112 u32 gsintmsk = readl(hsotg->regs + GINTMSK); in s3c_hsotg_en_gsint()
130 u32 gsintmsk = readl(hsotg->regs + GINTMSK); in s3c_hsotg_disable_gsint()
161 daint = readl(hsotg->regs + DAINTMSK); in s3c_hsotg_ctrl_epint()
229 val = readl(hsotg->regs + GRSTCTL); in s3c_hsotg_init_fifo()
322 u32 gnptxsts = readl(hsotg->regs + GNPTXSTS); in s3c_hsotg_write_fifo()
337 u32 epsize = readl(hsotg->regs + DIEPTSIZ(hs_ep->index)); in s3c_hsotg_write_fifo()
378 can_write = readl(hsotg->regs + DTXFSTS(hs_ep->index)); in s3c_hsotg_write_fifo()
555 __func__, readl(hsotg->regs + epctrl_reg), index, in s3c_hsotg_start_req()
[all …]
/linux-4.1.27/drivers/usb/phy/
Dphy-tegra-usb.c212 val = readl(base + TEGRA_USB_HOSTPC1_DEVLC); in set_pts()
217 val = readl(base + TEGRA_USB_PORTSC1) & ~TEGRA_PORTSC1_RWC_BITS; in set_pts()
230 val = readl(base + TEGRA_USB_HOSTPC1_DEVLC); in set_phcd()
237 val = readl(base + TEGRA_USB_PORTSC1) & ~PORT_RWC_BITS; in set_phcd()
268 val = readl(base + UTMIP_BIAS_CFG0); in utmip_pad_power_on()
303 val = readl(base + UTMIP_BIAS_CFG0); in utmip_pad_power_off()
319 if ((readl(reg) & mask) == result) in utmi_wait_register()
333 val = readl(base + USB_SUSP_CTRL); in utmi_phy_clk_disable()
339 val = readl(base + USB_SUSP_CTRL); in utmi_phy_clk_disable()
355 val = readl(base + USB_SUSP_CTRL); in utmi_phy_clk_enable()
[all …]
/linux-4.1.27/arch/arm/mach-dove/
Dmpp.c63 readl(DOVE_MPP_CTRL4_VIRT_BASE)); in dove_mpp_dump_regs()
66 readl(DOVE_PMU_MPP_GENERAL_CTRL)); in dove_mpp_dump_regs()
68 pr_debug("MPP_GENERAL: %08x\n", readl(DOVE_MPP_GENERAL_VIRT_BASE)); in dove_mpp_dump_regs()
73 u32 mpp_gen_cfg = readl(DOVE_MPP_GENERAL_VIRT_BASE); in dove_mpp_cfg_nfc()
84 u32 mpp_ctrl4 = readl(DOVE_MPP_CTRL4_VIRT_BASE); in dove_mpp_cfg_au1()
85 u32 ssp_ctrl1 = readl(DOVE_SSP_CTRL_STATUS_1); in dove_mpp_cfg_au1()
86 u32 mpp_gen_ctrl = readl(DOVE_MPP_GENERAL_VIRT_BASE); in dove_mpp_cfg_au1()
87 u32 global_cfg_2 = readl(DOVE_GLOBAL_CONFIG_2); in dove_mpp_cfg_au1()
124 u32 mpp_ctrl4 = readl(DOVE_MPP_CTRL4_VIRT_BASE); in dove_mpp_conf_grp()
Dirq.c29 u = readl(PMU_INTERRUPT_MASK); in pmu_irq_mask()
39 u = readl(PMU_INTERRUPT_MASK); in pmu_irq_unmask()
74 unsigned long cause = readl(PMU_INTERRUPT_CAUSE); in pmu_irq_handler()
76 cause &= readl(PMU_INTERRUPT_MASK); in pmu_irq_handler()
/linux-4.1.27/drivers/usb/early/
Dehci-dbgp.c81 dbgp_printk(" Debug control: %08x", readl(&ehci_debug->control)); in dbgp_ehci_status()
82 dbgp_printk(" ehci cmd : %08x", readl(&ehci_regs->command)); in dbgp_ehci_status()
84 readl(&ehci_regs->configured_flag)); in dbgp_ehci_status()
85 dbgp_printk(" ehci status : %08x", readl(&ehci_regs->status)); in dbgp_ehci_status()
87 readl(&ehci_regs->port_status[dbgp_phys_port - 1])); in dbgp_ehci_status()
167 ctrl = readl(&ehci_debug->control); in dbgp_wait_until_complete()
208 pids = readl(&ehci_debug->pids); in dbgp_wait_until_done()
262 lo = readl(&ehci_debug->data03); in dbgp_get_data()
263 hi = readl(&ehci_debug->data47); in dbgp_get_data()
282 pids = readl(&ehci_debug->pids); in dbgp_bulk_write()
[all …]
/linux-4.1.27/drivers/staging/unisys/uislib/
Duisqueue.c65 head = readl(&pqhdr->head); in spar_signal_insert()
66 tail = readl(&pqhdr->tail); in spar_signal_insert()
69 if (((head + 1) % readl(&pqhdr->max_slots)) == tail) { in spar_signal_insert()
76 head = (head + 1) % readl(&pqhdr->max_slots); in spar_signal_insert()
82 (head * readl(&pqhdr->signal_size)); in spar_signal_insert()
83 memcpy_toio(psignal, sig, readl(&pqhdr->signal_size)); in spar_signal_insert()
121 head = readl(&pqhdr->head); in spar_signal_remove()
122 tail = readl(&pqhdr->tail); in spar_signal_remove()
131 tail = (tail + 1) % readl(&pqhdr->max_slots); in spar_signal_remove()
135 (tail * readl(&pqhdr->signal_size)); in spar_signal_remove()
[all …]
/linux-4.1.27/sound/soc/samsung/
Ds3c24xx-i2s.c64 iisfcon = readl(s3c24xx_i2s.regs + S3C2410_IISFCON); in s3c24xx_snd_txctrl()
65 iiscon = readl(s3c24xx_i2s.regs + S3C2410_IISCON); in s3c24xx_snd_txctrl()
66 iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD); in s3c24xx_snd_txctrl()
109 iisfcon = readl(s3c24xx_i2s.regs + S3C2410_IISFCON); in s3c24xx_snd_rxctrl()
110 iiscon = readl(s3c24xx_i2s.regs + S3C2410_IISCON); in s3c24xx_snd_rxctrl()
111 iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD); in s3c24xx_snd_rxctrl()
158 iiscon = readl(s3c24xx_i2s.regs + S3C2410_IISCON); in s3c24xx_snd_lrsync()
177 return (readl(s3c24xx_i2s.regs + S3C2410_IISMOD) & S3C2410_IISMOD_SLAVE) ? 0:1; in s3c24xx_snd_is_clkmaster()
190 iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD); in s3c24xx_i2s_set_fmt()
232 iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD); in s3c24xx_i2s_hw_params()
[all …]
Ds3c-i2s-v2.c85 fic = readl(regs + S3C2412_IISFIC); in s3c2412_snd_txctrl()
86 con = readl(regs + S3C2412_IISCON); in s3c2412_snd_txctrl()
87 mod = readl(regs + S3C2412_IISMOD); in s3c2412_snd_txctrl()
146 fic = readl(regs + S3C2412_IISFIC); in s3c2412_snd_txctrl()
158 fic = readl(regs + S3C2412_IISFIC); in s3c2412_snd_rxctrl()
159 con = readl(regs + S3C2412_IISCON); in s3c2412_snd_rxctrl()
160 mod = readl(regs + S3C2412_IISMOD); in s3c2412_snd_rxctrl()
214 fic = readl(regs + S3C2412_IISFIC); in s3c2412_snd_rxctrl()
232 iiscon = readl(i2s->regs + S3C2412_IISCON); in s3c2412_snd_lrsync()
258 iismod = readl(i2s->regs + S3C2412_IISMOD); in s3c2412_i2s_set_fmt()
[all …]
Dac97.c57 stat = readl(s3c_ac97.regs + S3C_AC97_GLBSTAT) & 0x7; in s3c_ac97_activate()
63 ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL); in s3c_ac97_activate()
72 ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL); in s3c_ac97_activate()
92 ac_codec_cmd = readl(s3c_ac97.regs + S3C_AC97_CODEC_CMD); in s3c_ac97_read()
98 ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL); in s3c_ac97_read()
105 stat = readl(s3c_ac97.regs + S3C_AC97_STAT); in s3c_ac97_read()
129 ac_codec_cmd = readl(s3c_ac97.regs + S3C_AC97_CODEC_CMD); in s3c_ac97_write()
135 ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL); in s3c_ac97_write()
142 ac_codec_cmd = readl(s3c_ac97.regs + S3C_AC97_CODEC_CMD); in s3c_ac97_write()
164 stat = readl(s3c_ac97.regs + S3C_AC97_GLBSTAT) & 0x7; in s3c_ac97_warm_reset()
[all …]
Dspdif.c111 clkcon = readl(regs + CLKCON) & CLKCTL_MASK; in spdif_snd_txctrl()
126 clkcon = readl(spdif->regs + CLKCON); in spdif_set_sysclk()
200 con = readl(regs + CON) & CON_MASK; in spdif_hw_params()
201 cstas = readl(regs + CSTAS) & CSTAS_MASK; in spdif_hw_params()
202 clkcon = readl(regs + CLKCON) & CLKCTL_MASK; in spdif_hw_params()
288 con = readl(regs + CON) & CON_MASK; in spdif_shutdown()
289 clkcon = readl(regs + CLKCON) & CLKCTL_MASK; in spdif_shutdown()
305 spdif->saved_clkcon = readl(spdif->regs + CLKCON) & CLKCTL_MASK; in spdif_suspend()
306 spdif->saved_con = readl(spdif->regs + CON) & CON_MASK; in spdif_suspend()
307 spdif->saved_cstas = readl(spdif->regs + CSTAS) & CSTAS_MASK; in spdif_suspend()
/linux-4.1.27/drivers/staging/unisys/common-spar/include/channels/
Dchannel.h97 (readl(&(ch)->srv_state) == CHANNELSRV_READY)
134 readl(&(((struct channel_header __iomem *)\
140 readl(&((struct channel_header __iomem *)\
142 readl(&((struct channel_header __iomem *)\
327 unsigned long ver = readl(&((struct channel_header __iomem *) in spar_check_channel_client()
407 if (readl(&hdr->cli_state_os) == CHANNELCLI_DISABLED) { in spar_channel_client_acquire_os()
421 if ((readl(&hdr->cli_state_os) != CHANNELCLI_OWNED) && in spar_channel_client_acquire_os()
422 (readl(&hdr->cli_state_boot) == CHANNELCLI_DISABLED)) { in spar_channel_client_acquire_os()
426 ULTRA_CHANNELCLI_STRING(readl(&hdr->cli_state_os)), in spar_channel_client_acquire_os()
427 readl(&hdr->cli_state_os), in spar_channel_client_acquire_os()
[all …]
/linux-4.1.27/arch/mips/ar7/
Dgpio.c37 return readl(gpio_in) & (1 << gpio); in ar7_gpio_get_value()
47 return readl(gpio >> 5 ? gpio_in1 : gpio_in0) & (1 << (gpio & 0x1f)); in titan_gpio_get_value()
58 tmp = readl(gpio_out) & ~(1 << gpio); in ar7_gpio_set_value()
73 tmp = readl(gpio >> 5 ? gpio_out1 : gpio_out0) & ~(1 << (gpio & 0x1f)); in titan_gpio_set_value()
85 writel(readl(gpio_dir) | (1 << gpio), gpio_dir); in ar7_gpio_direction_input()
100 writel(readl(gpio >> 5 ? gpio_dir1 : gpio_dir0) | (1 << (gpio & 0x1f)), in titan_gpio_direction_input()
113 writel(readl(gpio_dir) & ~(1 << gpio), gpio_dir); in ar7_gpio_direction_output()
130 writel(readl(gpio >> 5 ? gpio_dir1 : gpio_dir0) & ~(1 << in titan_gpio_direction_output()
164 writel(readl(gpio_en) | (1 << gpio), gpio_en); in ar7_gpio_enable_ar7()
174 writel(readl(gpio >> 5 ? gpio_en1 : gpio_en0) | (1 << (gpio & 0x1f)), in ar7_gpio_enable_titan()
[all …]
Dclock.c160 didr1 = readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x18)); in tnetd7300_dsp_clock()
161 didr2 = readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x1c)); in tnetd7300_dsp_clock()
177 u32 ctrl = readl(&clock->ctrl); in tnetd7300_get_clock()
178 u32 pll = readl(&clock->pll); in tnetd7300_get_clock()
244 while (readl(&clock->pll) & PLL_STATUS) in tnetd7300_set_clock()
286 while (readl(&clock->status) & 0x1) in tnetd7200_set_clock()
291 writel(readl(&clock->cmden) | 1, &clock->cmden); in tnetd7200_set_clock()
292 writel(readl(&clock->cmd) | 1, &clock->cmd); in tnetd7200_set_clock()
294 while (readl(&clock->status) & 0x1) in tnetd7200_set_clock()
299 writel(readl(&clock->cmden) | 1, &clock->cmden); in tnetd7200_set_clock()
[all …]
/linux-4.1.27/drivers/block/
Dcciss.h227 readl(h->vaddr + SA5_SCRATCHPAD_OFFSET); in SA5_submit_command()
244 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); in SA5_intr_mask()
250 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); in SA5_intr_mask()
264 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); in SA5B_intr_mask()
270 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); in SA5B_intr_mask()
280 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); in SA5_performant_intr_mask()
285 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); in SA5_performant_intr_mask()
308 = readl(h->vaddr + SA5_REPLY_PORT_OFFSET); in SA5_completed()
334 register_value = readl(h->vaddr + SA5_OUTDB_STATUS); in SA5_performant_completed()
341 register_value = readl(h->vaddr + SA5_OUTDB_STATUS); in SA5_performant_completed()
[all …]
Dsmart1,2.h72 return (!readl(h->vaddr + S42XX_REQUEST_PORT_OFFSET)); in smart4_fifo_full()
82 = readl(h->vaddr + S42XX_REPLY_PORT_OFFSET); in smart4_completed()
103 readl(h->vaddr + S42XX_INTR_STATUS); in smart4_intr_pending()
133 return readl(h->vaddr + COMMAND_FIFO); in smart2_fifo_full()
138 return readl(h->vaddr + COMMAND_COMPLETE_FIFO); in smart2_completed()
143 return readl(h->vaddr + INTR_PENDING); in smart2_intr_pending()
/linux-4.1.27/arch/arm/plat-orion/
Dtime.c66 return ~readl(timer_base + TIMER0_VAL_OFF); in orion_read_sched_clock()
88 u = readl(bridge_base + BRIDGE_MASK_OFF); in orion_clkevt_next_event()
100 u = readl(timer_base + TIMER_CTRL_OFF); in orion_clkevt_next_event()
126 u = readl(bridge_base + BRIDGE_MASK_OFF); in orion_clkevt_mode()
132 u = readl(timer_base + TIMER_CTRL_OFF); in orion_clkevt_mode()
139 u = readl(timer_base + TIMER_CTRL_OFF); in orion_clkevt_mode()
145 u = readl(bridge_base + BRIDGE_MASK_OFF); in orion_clkevt_mode()
213 u = readl(bridge_base + BRIDGE_MASK_OFF); in orion_time_init()
215 u = readl(timer_base + TIMER_CTRL_OFF); in orion_time_init()
Dpcie.c57 return readl(base + PCIE_DEV_ID_OFF) >> 16; in orion_pcie_dev_id()
62 return readl(base + PCIE_DEV_REV_OFF) & 0xff; in orion_pcie_rev()
67 return !(readl(base + PCIE_STAT_OFF) & PCIE_STAT_LINK_DOWN); in orion_pcie_link_up()
72 return !(readl(base + PCIE_CTRL_OFF) & PCIE_CTRL_X1_MODE); in orion_pcie_x4_mode()
77 u32 stat = readl(base + PCIE_STAT_OFF); in orion_pcie_get_local_bus_nr()
86 stat = readl(base + PCIE_STAT_OFF); in orion_pcie_set_local_bus_nr()
103 reg = readl(base + PCIE_DEBUG_CTRL); in orion_pcie_reset()
203 mask = readl(base + PCIE_MASK_OFF); in orion_pcie_setup()
217 *val = readl(base + PCIE_CONF_DATA_OFF); in orion_pcie_rd_conf()
236 *val = readl(base + PCIE_CONF_DATA_OFF); in orion_pcie_rd_conf_tlp()
[all …]
Dgpio.c100 u = readl(GPIO_IO_CONF(ochip)); in __set_direction()
112 u = readl(GPIO_OUT(ochip)); in __set_level()
125 u = readl(GPIO_BLINK_EN(ochip)); in __set_blinking()
189 if (readl(GPIO_IO_CONF(ochip)) & (1 << pin)) { in orion_gpio_get()
190 val = readl(GPIO_DATA_IN(ochip)) ^ readl(GPIO_IN_POL(ochip)); in orion_gpio_get()
192 val = readl(GPIO_OUT(ochip)); in orion_gpio_get()
367 u = readl(GPIO_IO_CONF(ochip)) & (1 << pin); in gpio_irq_set_type()
385 u = readl(GPIO_IN_POL(ochip)); in gpio_irq_set_type()
389 u = readl(GPIO_IN_POL(ochip)); in gpio_irq_set_type()
395 v = readl(GPIO_IN_POL(ochip)) ^ readl(GPIO_DATA_IN(ochip)); in gpio_irq_set_type()
[all …]
/linux-4.1.27/drivers/tty/serial/
Dnetx-serial.c121 val = readl(port->membase + UART_CR); in netx_stop_tx()
128 val = readl(port->membase + UART_CR); in netx_stop_rx()
135 val = readl(port->membase + UART_CR); in netx_enable_ms()
164 } while (!(readl(port->membase + UART_FR) & FR_TXFF)); in netx_transmit_buffer()
173 readl(port->membase + UART_CR) | CR_TIE, port->membase + UART_CR); in netx_start_tx()
175 if (!(readl(port->membase + UART_FR) & FR_TXFF)) in netx_start_tx()
181 return readl(port->membase + UART_FR) & FR_BUSY ? 0 : TIOCSER_TEMT; in netx_tx_empty()
203 while (!(readl(port->membase + UART_FR) & FR_RXFE)) { in netx_rxint()
204 rx = readl(port->membase + UART_DR); in netx_rxint()
207 status = readl(port->membase + UART_SR); in netx_rxint()
[all …]
Dimx.c293 ucr->ucr1 = readl(port->membase + UCR1); in imx_port_ucrs_save()
294 ucr->ucr2 = readl(port->membase + UCR2); in imx_port_ucrs_save()
295 ucr->ucr3 = readl(port->membase + UCR3); in imx_port_ucrs_save()
368 temp = readl(port->membase + UCR1); in imx_stop_tx()
373 readl(port->membase + USR2) & USR2_TXDC) { in imx_stop_tx()
374 temp = readl(port->membase + UCR2); in imx_stop_tx()
381 temp = readl(port->membase + UCR4); in imx_stop_tx()
404 temp = readl(sport->port.membase + UCR2); in imx_stop_rx()
408 temp = readl(sport->port.membase + UCR1); in imx_stop_rx()
446 temp = readl(sport->port.membase + UCR1); in imx_transmit_buffer()
[all …]
Dxilinx_uartps.c195 isrstatus = readl(port->membase + CDNS_UART_ISR_OFFSET); in cdns_uart_isr()
203 while (!(readl(port->membase + CDNS_UART_SR_OFFSET) & in cdns_uart_isr()
205 if (!readl(port->membase + CDNS_UART_FIFO_OFFSET)) { in cdns_uart_isr()
224 while (!(readl(port->membase + CDNS_UART_SR_OFFSET) & in cdns_uart_isr()
226 data = readl(port->membase + CDNS_UART_FIFO_OFFSET); in cdns_uart_isr()
398 mreg = readl(port->membase + CDNS_UART_MR_OFFSET); in cdns_uart_set_baud_rate()
452 ctrl_reg = readl(port->membase + CDNS_UART_CR_OFFSET); in cdns_uart_clk_notifier_cb()
479 ctrl_reg = readl(port->membase + CDNS_UART_CR_OFFSET); in cdns_uart_clk_notifier_cb()
483 while (readl(port->membase + CDNS_UART_CR_OFFSET) & in cdns_uart_clk_notifier_cb()
493 ctrl_reg = readl(port->membase + CDNS_UART_CR_OFFSET); in cdns_uart_clk_notifier_cb()
[all …]
Dmeson_uart.c102 val = readl(port->membase + AML_UART_STATUS); in meson_uart_tx_empty()
110 val = readl(port->membase + AML_UART_CONTROL); in meson_uart_stop_tx()
119 val = readl(port->membase + AML_UART_CONTROL); in meson_uart_stop_rx()
133 val = readl(port->membase + AML_UART_CONTROL); in meson_uart_shutdown()
151 while (!(readl(port->membase + AML_UART_STATUS) & AML_UART_TX_FULL)) { in meson_uart_start_tx()
181 status = readl(port->membase + AML_UART_STATUS); in meson_receive_chars()
191 mode = readl(port->membase + AML_UART_CONTROL); in meson_receive_chars()
206 ch = readl(port->membase + AML_UART_RFIFO); in meson_receive_chars()
215 } while (!(readl(port->membase + AML_UART_STATUS) & AML_UART_RX_EMPTY)); in meson_receive_chars()
228 if (!(readl(port->membase + AML_UART_STATUS) & AML_UART_RX_EMPTY)) in meson_uart_interrupt()
[all …]
Dlpc32xx_hs.c110 if (LPC32XX_HSU_TX_LEV(readl(LPC32XX_HSUART_LEVEL( in wait_for_xmit_empty()
124 if (LPC32XX_HSU_TX_LEV(readl(LPC32XX_HSUART_LEVEL( in wait_for_xmit_ready()
253 while ((readl(LPC32XX_HSUART_LEVEL(port->membase)) > 0) && in __serial_uart_flush()
255 tmp = readl(LPC32XX_HSUART_FIFO(port->membase)); in __serial_uart_flush()
264 tmp = readl(LPC32XX_HSUART_FIFO(port->membase)); in __serial_lpc32xx_rx()
280 tmp = readl(LPC32XX_HSUART_FIFO(port->membase)); in __serial_lpc32xx_rx()
304 while (LPC32XX_HSU_TX_LEV(readl( in __serial_lpc32xx_tx()
319 tmp = readl(LPC32XX_HSUART_CTRL(port->membase)); in __serial_lpc32xx_tx()
334 status = readl(LPC32XX_HSUART_IIR(port->membase)); in serial_lpc32xx_interrupt()
376 if (LPC32XX_HSU_TX_LEV(readl(LPC32XX_HSUART_LEVEL(port->membase))) == 0) in serial_lpc32xx_tx_empty()
[all …]
/linux-4.1.27/arch/mips/include/asm/mach-ar7/
Dar7.h124 return (readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x24)) & 0xffff) == in ar7_is_titan()
130 return ar7_is_titan() ? AR7_CHIP_TITAN : (readl((void *) in ar7_chip_id()
136 unsigned int val = readl((void *)KSEG1ADDR(AR7_REGS_GPIO + in titan_chip_id()
143 return (readl((void *)KSEG1ADDR(AR7_REGS_GPIO + (ar7_is_titan() ? 0x24 : in ar7_chip_rev()
171 writel(readl(reset_reg) | (1 << bit), reset_reg); in ar7_device_enable()
179 writel(readl(reset_reg) & ~(1 << bit), reset_reg); in ar7_device_disable()
192 writel(readl(power_reg) | (1 << bit), power_reg); in ar7_device_on()
199 writel(readl(power_reg) & ~(1 << bit), power_reg); in ar7_device_off()
/linux-4.1.27/drivers/rtc/
Drtc-snvs.c51 read1 = readl(ioaddr + SNVS_LPSRTCMR); in rtc_read_lp_counter()
53 read1 |= readl(ioaddr + SNVS_LPSRTCLR); in rtc_read_lp_counter()
55 read2 = readl(ioaddr + SNVS_LPSRTCMR); in rtc_read_lp_counter()
57 read2 |= readl(ioaddr + SNVS_LPSRTCLR); in rtc_read_lp_counter()
72 count1 = readl(ioaddr + SNVS_LPSRTCLR); in rtc_write_sync_lp()
73 count2 = readl(ioaddr + SNVS_LPSRTCLR); in rtc_write_sync_lp()
79 count2 = readl(ioaddr + SNVS_LPSRTCLR); in rtc_write_sync_lp()
80 count3 = readl(ioaddr + SNVS_LPSRTCLR); in rtc_write_sync_lp()
94 lpcr = readl(data->ioaddr + SNVS_LPCR); in snvs_rtc_enable()
104 lpcr = readl(data->ioaddr + SNVS_LPCR); in snvs_rtc_enable()
[all …]
Drtc-puv3.c41 writel(readl(RTC_RTSR) | RTC_RTSR_AL, RTC_RTSR); in puv3_rtc_alarmirq()
50 writel(readl(RTC_RTSR) | RTC_RTSR_HZ, RTC_RTSR); in puv3_rtc_tickirq()
62 tmp = readl(RTC_RTSR) & ~RTC_RTSR_ALE; in puv3_rtc_setaie()
77 tmp = readl(RTC_RTSR) & ~RTC_RTSR_HZE; in puv3_rtc_setpie()
91 rtc_time_to_tm(readl(RTC_RCNR), rtc_tm); in puv3_rtc_gettime()
118 rtc_time_to_tm(readl(RTC_RTAR), alm_tm); in puv3_rtc_getalarm()
120 alrm->enabled = readl(RTC_RTSR) & RTC_RTSR_ALE; in puv3_rtc_getalarm()
156 (readl(RTC_RTSR) & RTC_RTSR_HZE) ? "yes" : "no"); in puv3_rtc_proc()
213 writel(readl(RTC_RTSR) & ~RTC_RTSR_HZE, RTC_RTSR); in puv3_rtc_enable()
216 if ((readl(RTC_RTSR) & RTC_RTSR_HZE) == 0) { in puv3_rtc_enable()
[all …]
Drtc-ls1x.c92 v = readl(SYS_TOYREAD0); in ls1x_rtc_read_time()
93 t = readl(SYS_TOYREAD1); in ls1x_rtc_read_time()
118 while ((readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_TS) && --c) in ls1x_rtc_set_time()
129 while ((readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_TS) && --c) in ls1x_rtc_set_time()
152 v = readl(SYS_COUNTER_CNTRL); in ls1x_rtc_probe()
160 if (readl(SYS_TOYTRIM) != 32767) { in ls1x_rtc_probe()
162 while ((readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_TTS) && --v) in ls1x_rtc_probe()
172 while (readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_TTS) in ls1x_rtc_probe()
Drtc-pl031.c103 imsc = readl(ldata->base + RTC_IMSC); in pl031_alarm_irq_enable()
173 pl031_stv2_time_to_tm(readl(ldata->base + RTC_DR), in pl031_stv2_read_time()
174 readl(ldata->base + RTC_YDR), tm); in pl031_stv2_read_time()
200 ret = pl031_stv2_time_to_tm(readl(ldata->base + RTC_MR), in pl031_stv2_read_alarm()
201 readl(ldata->base + RTC_YMR), &alarm->time); in pl031_stv2_read_alarm()
203 alarm->pending = readl(ldata->base + RTC_RIS) & RTC_BIT_AI; in pl031_stv2_read_alarm()
204 alarm->enabled = readl(ldata->base + RTC_IMSC) & RTC_BIT_AI; in pl031_stv2_read_alarm()
238 rtcmis = readl(ldata->base + RTC_MIS); in pl031_interrupt()
254 rtc_time_to_tm(readl(ldata->base + RTC_DR), tm); in pl031_read_time()
277 rtc_time_to_tm(readl(ldata->base + RTC_MR), &alarm->time); in pl031_read_alarm()
[all …]
Drtc-tegra.c73 return readl(info->rtc_base + TEGRA_RTC_REG_BUSY) & 1; in tegra_rtc_check_busy()
117 msec = readl(info->rtc_base + TEGRA_RTC_REG_MILLI_SECONDS); in tegra_rtc_read_time()
118 sec = readl(info->rtc_base + TEGRA_RTC_REG_SHADOW_SECONDS); in tegra_rtc_read_time()
166 readl(info->rtc_base + TEGRA_RTC_REG_SECONDS)); in tegra_rtc_set_time()
177 sec = readl(info->rtc_base + TEGRA_RTC_REG_SECONDS_ALARM0); in tegra_rtc_read_alarm()
194 tmp = readl(info->rtc_base + TEGRA_RTC_REG_INTR_STATUS); in tegra_rtc_read_alarm()
210 status = readl(info->rtc_base + TEGRA_RTC_REG_INTR_MASK); in tegra_rtc_alarm_irq_enable()
236 readl(info->rtc_base + TEGRA_RTC_REG_SECONDS_ALARM0)); in tegra_rtc_set_alarm()
277 status = readl(info->rtc_base + TEGRA_RTC_REG_INTR_STATUS); in tegra_rtc_irq_handler()
386 readl(info->rtc_base + TEGRA_RTC_REG_SECONDS_ALARM0)); in tegra_rtc_suspend()
Drtc-armada38x.c70 time = readl(rtc->regs + RTC_TIME); in armada38x_rtc_read_time()
76 time_check = readl(rtc->regs + RTC_TIME); in armada38x_rtc_read_time()
78 time_check = readl(rtc->regs + RTC_TIME); in armada38x_rtc_read_time()
121 time = readl(rtc->regs + RTC_ALARM1); in armada38x_rtc_read_alarm()
122 val = readl(rtc->regs + RTC_IRQ1_CONF) & RTC_IRQ1_AL_EN; in armada38x_rtc_read_alarm()
150 val = readl(rtc->regs_soc + SOC_RTC_INTERRUPT); in armada38x_rtc_set_alarm()
189 val = readl(rtc->regs_soc + SOC_RTC_INTERRUPT); in armada38x_rtc_alarm_irq()
192 val = readl(rtc->regs + RTC_IRQ1_CONF); in armada38x_rtc_alarm_irq()
Drtc-xgene.c61 rtc_time_to_tm(readl(pdata->csr_base + RTC_CCVR), tm); in xgene_rtc_read_time()
74 readl(pdata->csr_base + RTC_CLR); /* Force a barrier */ in xgene_rtc_set_mmss()
84 alrm->enabled = readl(pdata->csr_base + RTC_CCR) & RTC_CCR_IE; in xgene_rtc_read_alarm()
94 ccr = readl(pdata->csr_base + RTC_CCR); in xgene_rtc_alarm_irq_enable()
113 rtc_time = readl(pdata->csr_base + RTC_CCVR); in xgene_rtc_set_alarm()
137 if (!(readl(pdata->csr_base + RTC_STAT) & RTC_STAT_BIT)) in xgene_rtc_interrupt()
141 readl(pdata->csr_base + RTC_EOI); in xgene_rtc_interrupt()
Drtc-sunxi.c164 val = readl(chip->base + SUNXI_ALRM_IRQ_STA); in sunxi_rtc_alarmirq()
184 alrm_val = readl(chip->base + SUNXI_ALRM_EN); in sunxi_rtc_setaie()
187 alrm_irq_val = readl(chip->base + SUNXI_ALRM_IRQ_EN); in sunxi_rtc_setaie()
206 alrm = readl(chip->base + SUNXI_ALRM_DHMS); in sunxi_rtc_getalarm()
207 date = readl(chip->base + SUNXI_RTC_YMD); in sunxi_rtc_getalarm()
226 alrm_en = readl(chip->base + SUNXI_ALRM_IRQ_EN); in sunxi_rtc_getalarm()
242 date = readl(chip->base + SUNXI_RTC_YMD); in sunxi_rtc_gettime()
243 time = readl(chip->base + SUNXI_RTC_HMS); in sunxi_rtc_gettime()
244 } while ((date != readl(chip->base + SUNXI_RTC_YMD)) || in sunxi_rtc_gettime()
245 (time != readl(chip->base + SUNXI_RTC_HMS))); in sunxi_rtc_gettime()
[all …]
Drtc-spear.c94 val = readl(config->ioaddr + STATUS_REG); in spear_rtc_clear_interrupt()
104 val = readl(config->ioaddr + CTRL_REG); in spear_rtc_enable_interrupt()
116 val = readl(config->ioaddr + CTRL_REG); in spear_rtc_disable_interrupt()
129 if ((readl(config->ioaddr + STATUS_REG)) & STATUS_FAIL) in is_write_complete()
144 status = readl(config->ioaddr + STATUS_REG); in rtc_wait_not_busy()
160 irq_data = readl(config->ioaddr + STATUS_REG); in spear_rtc_irq()
214 time = readl(config->ioaddr + TIME_REG); in spear_rtc_read_time()
215 date = readl(config->ioaddr + DATE_REG); in spear_rtc_read_time()
269 time = readl(config->ioaddr + ALARM_TIME_REG); in spear_rtc_read_alarm()
270 date = readl(config->ioaddr + ALARM_DATE_REG); in spear_rtc_read_alarm()
[all …]
Drtc-mv.c75 rtc_time = readl(ioaddr + RTC_TIME_REG_OFFS); in mv_rtc_read_time()
76 rtc_date = readl(ioaddr + RTC_DATE_REG_OFFS); in mv_rtc_read_time()
106 rtc_time = readl(ioaddr + RTC_ALARM_TIME_REG_OFFS); in mv_rtc_read_alarm()
107 rtc_date = readl(ioaddr + RTC_ALARM_DATE_REG_OFFS); in mv_rtc_read_alarm()
132 alm->enabled = !!readl(ioaddr + RTC_ALARM_INTERRUPT_MASK_REG_OFFS); in mv_rtc_read_alarm()
198 if (!readl(ioaddr + RTC_ALARM_INTERRUPT_CASUE_REG_OFFS)) in mv_rtc_interrupt()
243 rtc_time = readl(pdata->ioaddr + RTC_TIME_REG_OFFS); in mv_rtc_probe()
253 rtc_time = readl(pdata->ioaddr + RTC_TIME_REG_OFFS); in mv_rtc_probe()
266 rtc_date = readl(pdata->ioaddr + RTC_DATE_REG_OFFS); in mv_rtc_probe()
Drtc-coh901331.c82 if (readl(rtap->virtbase + COH901331_VALID)) { in coh901331_read_time()
83 rtc_time_to_tm(readl(rtap->virtbase + COH901331_CUR_TIME), tm); in coh901331_read_time()
107 rtc_time_to_tm(readl(rtap->virtbase + COH901331_ALARM), &alarm->time); in coh901331_read_alarm()
108 alarm->pending = readl(rtap->virtbase + COH901331_IRQ_EVENT) & 1U; in coh901331_read_alarm()
109 alarm->enabled = readl(rtap->virtbase + COH901331_IRQ_MASK) & 1U; in coh901331_read_alarm()
227 rtap->irqmaskstore = readl(rtap->virtbase + COH901331_IRQ_MASK); in coh901331_suspend()
Drtc-sun6i.c124 val = readl(chip->base + SUN6I_ALRM_IRQ_STA); in sun6i_rtc_alarmirq()
167 date = readl(chip->base + SUN6I_RTC_YMD); in sun6i_rtc_gettime()
168 time = readl(chip->base + SUN6I_RTC_HMS); in sun6i_rtc_gettime()
169 } while ((date != readl(chip->base + SUN6I_RTC_YMD)) || in sun6i_rtc_gettime()
170 (time != readl(chip->base + SUN6I_RTC_HMS))); in sun6i_rtc_gettime()
197 alrm_en = readl(chip->base + SUN6I_ALRM_IRQ_EN); in sun6i_rtc_getalarm()
198 alrm_st = readl(chip->base + SUN6I_ALRM_IRQ_STA); in sun6i_rtc_getalarm()
255 reg = readl(chip->base + offset); in sun6i_rtc_wait()
/linux-4.1.27/drivers/net/ethernet/agere/
Det131x.c757 csr = readl(&adapter->regs->rxdma.csr); in et131x_rx_dma_enable()
760 csr = readl(&adapter->regs->rxdma.csr); in et131x_rx_dma_enable()
775 csr = readl(&adapter->regs->rxdma.csr); in et131x_rx_dma_disable()
778 csr = readl(&adapter->regs->rxdma.csr); in et131x_rx_dma_disable()
873 ctl = readl(&adapter->regs->txmac.ctl); in et1310_config_mac_regs2()
874 cfg1 = readl(&mac->cfg1); in et1310_config_mac_regs2()
875 cfg2 = readl(&mac->cfg2); in et1310_config_mac_regs2()
876 ifctrl = readl(&mac->if_ctrl); in et1310_config_mac_regs2()
920 cfg1 = readl(&mac->cfg1); in et1310_config_mac_regs2()
940 u32 pmcsr = readl(&adapter->regs->global.pm_csr); in et1310_in_phy_coma()
[all …]
/linux-4.1.27/sound/soc/ux500/
Dux500_msp_i2s.c209 temp_reg = readl(msp->registers + MSP_GCR) & ~TX_CLK_POL_RISING; in configure_protocol()
212 temp_reg = readl(msp->registers + MSP_GCR) & ~RX_CLK_POL_RISING; in configure_protocol()
228 reg_val_GCR = readl(msp->registers + MSP_GCR); in setup_bitclk()
267 reg_val_GCR = readl(msp->registers + MSP_GCR); in setup_bitclk()
297 reg_val_MCR = readl(msp->registers + MSP_MCR); in configure_multichannel()
318 reg_val_MCR = readl(msp->registers + MSP_MCR); in configure_multichannel()
337 reg_val_MCR = readl(msp->registers + MSP_MCR); in configure_multichannel()
383 reg_val_DMACR = readl(msp->registers + MSP_DMACR); in enable_msp()
393 reg_val_GCR = readl(msp->registers + MSP_GCR); in enable_msp()
404 reg_val_GCR = readl(msp->registers + MSP_GCR); in flush_fifo_rx()
[all …]
/linux-4.1.27/drivers/clk/mvebu/
Dorion.c32 u32 opt = (readl(sar) >> SAR_MV88F5182_TCLK_FREQ) & in mv88f5182_get_tclk_freq()
47 u32 opt = (readl(sar) >> SAR_MV88F5182_CPU_FREQ) & in mv88f5182_get_cpu_freq()
62 u32 opt = (readl(sar) >> SAR_MV88F5182_CPU_FREQ) & in mv88f5182_get_clk_ratio()
106 u32 opt = (readl(sar) >> SAR_MV88F5281_CPU_FREQ) & in mv88f5281_get_cpu_freq()
119 u32 opt = (readl(sar) >> SAR_MV88F5281_CPU_FREQ) & in mv88f5281_get_clk_ratio()
157 u32 opt = (readl(sar) >> SAR_MV88F6183_TCLK_FREQ) & in mv88f6183_get_tclk_freq()
172 u32 opt = (readl(sar) >> SAR_MV88F6183_CPU_FREQ) & in mv88f6183_get_cpu_freq()
185 u32 opt = (readl(sar) >> SAR_MV88F6183_CPU_FREQ) & in mv88f6183_get_clk_ratio()
Dclk-cpu.c55 reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_VALUE_OFFSET); in clk_cpu_recalc_rate()
84 reg = (readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_VALUE_OFFSET) in clk_cpu_off_set_rate()
91 reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET) in clk_cpu_off_set_rate()
96 reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET) in clk_cpu_off_set_rate()
125 reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL2_OFFSET); in clk_cpu_on_set_rate()
139 reg = readl(cpuclk->pmu_dfs); in clk_cpu_on_set_rate()
144 reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET); in clk_cpu_on_set_rate()
Ddove.c90 u32 opt = (readl(sar) >> SAR_DOVE_TCLK_FREQ) & in dove_get_tclk_freq()
109 u32 opt = (readl(sar) >> SAR_DOVE_CPU_FREQ) & in dove_get_cpu_freq()
132 u32 opt = (readl(sar) >> SAR_DOVE_L2_RATIO) & in dove_get_clk_ratio()
140 u32 opt = (readl(sar) >> SAR_DOVE_DDR_RATIO) & in dove_get_clk_ratio()
Darmada-370.c51 tclk_freq_select = ((readl(sar) >> SARL_A370_TCLK_FREQ_OPT) & in a370_get_tclk_freq()
71 cpu_freq_select = ((readl(sar) >> SARL_A370_PCLK_FREQ_OPT) & in a370_get_cpu_freq()
118 u32 opt = ((readl(sar) >> SARL_A370_FAB_FREQ_OPT) & in a370_get_clk_ratio()
139 return !(readl(sar) & SARL_A370_SSCG_ENABLE); in a370_is_sscg_enabled()
Dkirkwood.c90 u32 opt = (readl(sar) >> SAR_KIRKWOOD_TCLK_FREQ) & in kirkwood_get_tclk_freq()
112 u32 opt = SAR_KIRKWOOD_CPU_FREQ(readl(sar)); in kirkwood_get_cpu_freq()
134 u32 opt = SAR_KIRKWOOD_L2_RATIO(readl(sar)); in kirkwood_get_clk_ratio()
141 u32 opt = (readl(sar) >> SAR_KIRKWOOD_DDR_RATIO) & in kirkwood_get_clk_ratio()
159 u32 opt = (readl(sar) >> SAR_MV88F6180_CLK) & SAR_MV88F6180_CLK_MASK; in mv88f6180_get_cpu_freq()
181 u32 opt = (readl(sar) >> SAR_MV88F6180_CLK) & in mv88f6180_get_clk_ratio()
Darmada-xp.c75 cpu_freq_select = ((readl(sar + SARL) >> SARL_AXP_PCLK_FREQ_OPT) & in axp_get_cpu_freq()
81 cpu_freq_select |= (((readl(sar + SARH) >> SARH_AXP_PCLK_FREQ_OPT) & in axp_get_cpu_freq()
128 u32 opt = ((readl(sar + SARL) >> SARL_AXP_FAB_FREQ_OPT) & in axp_get_clk_ratio()
134 opt |= (((readl(sar + SARH) >> SARH_AXP_FAB_FREQ_OPT) & in axp_get_clk_ratio()
Dclk-corediv.c83 return !!(readl(corediv->reg) & enable_mask); in clk_corediv_is_enabled()
96 reg = readl(corediv->reg); in clk_corediv_enable()
115 reg = readl(corediv->reg); in clk_corediv_disable()
130 reg = readl(corediv->reg + soc_desc->ratio_offset); in clk_corediv_recalc_rate()
164 reg = readl(corediv->reg + soc_desc->ratio_offset); in clk_corediv_set_rate()
170 reg = readl(corediv->reg) | BIT(desc->fieldbit); in clk_corediv_set_rate()
174 reg = readl(corediv->reg) | soc_desc->ratio_reload; in clk_corediv_set_rate()
/linux-4.1.27/drivers/usb/gadget/udc/
Dnet2280.c129 u32 tmp = readl(&ep->dev->regs->pciirqenb0); in enable_pciirqenb()
268 tmp |= readl(&ep->regs->ep_irqenb); in net2280_enable()
272 tmp |= readl(&dev->regs->pciirqenb1); in net2280_enable()
307 result = readl(ptr); in handshake()
340 tmp = readl(&regs->pciirqenb0); in ep_reset_228x()
344 tmp = readl(&regs->pciirqenb1); in ep_reset_228x()
418 dmastat = readl(&ep->dma->dmastat); in ep_reset_338x()
425 tmp = readl(&regs->pciirqenb0); in ep_reset_338x()
430 tmp = readl(&regs->pciirqenb1); in ep_reset_338x()
470 (void)readl(&ep->cfg->ep_cfg); in net2280_disable()
[all …]
Damd5536udc.c181 DBG(dev, "dev config = %08x\n", readl(&dev->regs->cfg)); in print_regs()
182 DBG(dev, "dev control = %08x\n", readl(&dev->regs->ctl)); in print_regs()
183 DBG(dev, "dev status = %08x\n", readl(&dev->regs->sts)); in print_regs()
185 DBG(dev, "dev int's = %08x\n", readl(&dev->regs->irqsts)); in print_regs()
186 DBG(dev, "dev intmask = %08x\n", readl(&dev->regs->irqmsk)); in print_regs()
188 DBG(dev, "dev ep int's = %08x\n", readl(&dev->regs->ep_irqsts)); in print_regs()
189 DBG(dev, "dev ep intmask = %08x\n", readl(&dev->regs->ep_irqmsk)); in print_regs()
240 tmp = readl(&dev->regs->ep_irqmsk); in udc_enable_ep0_interrupts()
257 tmp = readl(&dev->regs->irqmsk); in udc_enable_dev_setup_interrupts()
287 tmp = readl(&dev->ep[i].regs->bufin_framenum); in udc_set_txfifo_addr()
[all …]
Dgoku_udc.c122 if ((readl(ep->reg_status) & EPxSTATUS_EP_MASK) in goku_ep_enable()
166 tmp |= readl(&regs->EPxSingle); in goku_ep_enable()
170 tmp |= readl(&regs->EPxBCS); in goku_ep_enable()
204 readl(&regs->int_enable); in ep_reset()
209 tmp = readl(&r->EPxSingle); in ep_reset()
213 tmp = readl(&r->EPxBCS); in ep_reset()
221 master = readl(&regs->dma_master) & MST_RW_BITS; in ep_reset()
353 tmp = readl(&dev->regs->DataSet); in write_fifo()
425 set = readl(&regs->DataSet) & DATASET_AB(ep->num); in read_fifo()
426 size = readl(&regs->EPxSizeLA[ep->num]); in read_fifo()
[all …]
Dmv_udc_core.c96 epctrlx = readl(&udc->op_regs->epctrlx[0]); in ep0_reset()
118 epctrlx = readl(&udc->op_regs->epctrlx[0]); in ep0_stall()
196 while (readl(&udc->op_regs->epstatus) & bit_pos) in process_ep_req()
281 if (readl(&udc->op_regs->epprime) & bit_pos) in queue_dtd()
287 usbcmd = readl(&udc->op_regs->usbcmd); in queue_dtd()
292 epstatus = readl(&udc->op_regs->epstatus) & bit_pos; in queue_dtd()
301 if (readl(&udc->op_regs->usbcmd) in queue_dtd()
316 usbcmd = readl(&udc->op_regs->usbcmd); in queue_dtd()
477 if ((readl(&udc->op_regs->epprime) & bit_pos) in mv_ep_enable()
478 || (readl(&udc->op_regs->epstatus) & bit_pos)) { in mv_ep_enable()
[all …]
Ds3c-hsudc.c189 writel(readl(ptr) | val, ptr); in __orr32()
196 cfg = readl(S3C2443_PWRCFG) | S3C2443_PWRCFG_USBPHY; in s3c_hsudc_init_phy()
199 cfg = readl(S3C2443_URSTCON); in s3c_hsudc_init_phy()
204 cfg = readl(S3C2443_URSTCON); in s3c_hsudc_init_phy()
208 cfg = readl(S3C2443_PHYCTRL); in s3c_hsudc_init_phy()
213 cfg = readl(S3C2443_PHYPWR); in s3c_hsudc_init_phy()
220 cfg = readl(S3C2443_UCLKCON); in s3c_hsudc_init_phy()
230 cfg = readl(S3C2443_PWRCFG) & ~S3C2443_PWRCFG_USBPHY; in s3c_hsudc_uninit_phy()
235 cfg = readl(S3C2443_UCLKCON) & ~S3C2443_UCLKCON_FUNC_CLKEN; in s3c_hsudc_uninit_phy()
316 count = readl(hsudc->regs + S3C_BRCR); in s3c_hsudc_read_setup_pkt()
[all …]
Dnet2280.h32 return readl(&regs->idxdata); in get_idx_reg()
270 u32 val = readl(&dev->regs->gpioctl); in net2280_led_speed()
293 u32 val = readl(&dev->regs->gpioctl); in net2280_led_active()
306 writel(readl(&dev->regs->gpioctl) & ~0x0f, in net2280_led_shutdown()
342 u32 tmp = readl(&ep->cfg->ep_cfg) & in set_fifo_bytecount()
353 readl(&ep->regs->ep_rsp); in start_out_naking()
360 tmp = readl(&ep->regs->ep_stat); in stop_out_naking()
/linux-4.1.27/arch/arm/mach-s3c64xx/
Dsetup-usb-phy.c29 writel(readl(S3C64XX_OTHERS) | S3C64XX_OTHERS_USBMASK, S3C64XX_OTHERS); in s3c_usb_otgphy_init()
32 phyclk = readl(S3C_PHYCLK) & ~S3C_PHYCLK_CLKSEL_MASK; in s3c_usb_otgphy_init()
55 writel((readl(S3C_PHYPWR) & ~S3C_PHYPWR_NORMAL_MASK), S3C_PHYPWR); in s3c_usb_otgphy_init()
69 writel((readl(S3C_PHYPWR) | S3C_PHYPWR_ANALOG_POWERDOWN | in s3c_usb_otgphy_exit()
72 writel(readl(S3C64XX_OTHERS) & ~S3C64XX_OTHERS_USBMASK, S3C64XX_OTHERS); in s3c_usb_otgphy_exit()
/linux-4.1.27/drivers/clk/
Dclk-highbank.c60 reg = readl(hbclk->reg); in clk_pll_prepare()
64 while ((readl(hbclk->reg) & HB_PLL_LOCK) == 0) in clk_pll_prepare()
66 while ((readl(hbclk->reg) & HB_PLL_LOCK_500) == 0) in clk_pll_prepare()
77 reg = readl(hbclk->reg); in clk_pll_unprepare()
87 reg = readl(hbclk->reg); in clk_pll_enable()
99 reg = readl(hbclk->reg); in clk_pll_disable()
110 reg = readl(hbclk->reg); in clk_pll_recalc_rate()
165 reg = readl(hbclk->reg); in clk_pll_set_rate()
177 while ((readl(hbclk->reg) & HB_PLL_LOCK) == 0) in clk_pll_set_rate()
179 while ((readl(hbclk->reg) & HB_PLL_LOCK_500) == 0) in clk_pll_set_rate()
[all …]
Dclk-nomadik.c72 val = readl(src_base + SRC_XTALCR); in nomadik_clk_reboot_handler()
107 val = readl(src_base + SRC_CR); in nomadik_src_init()
118 val = readl(src_base + SRC_XTALCR); in nomadik_src_init()
171 val = readl(src_base + SRC_PLLCR); in pll_clk_enable()
191 val = readl(src_base + SRC_PLLCR); in pll_clk_disable()
209 val = readl(src_base + SRC_PLLCR); in pll_clk_is_enabled()
225 val = readl(src_base + SRC_PLLFR); in pll_clk_recalc_rate()
309 while (!(readl(src_base + sreg) & sclk->clkbit)) in src_clk_enable()
322 while (readl(src_base + sreg) & sclk->clkbit) in src_clk_disable()
330 u32 val = readl(src_base + sreg); in src_clk_is_enabled()
[all …]
/linux-4.1.27/drivers/misc/ibmasm/
Dlowlevel.h57 return SP_INTR_MASK & readl(base_address + INTR_STATUS_REGISTER); in sp_interrupt_pending()
62 return UART_INTR_MASK & readl(base_address + INTR_STATUS_REGISTER); in uart_interrupt_pending()
68 writel( readl(ctrl_reg) & ~mask, ctrl_reg); in ibmasm_enable_interrupts()
74 writel( readl(ctrl_reg) | mask, ctrl_reg); in ibmasm_disable_interrupts()
105 mfa = readl(base_address + OUTBOUND_QUEUE_PORT); in get_mfa_outbound()
119 u32 mfa = readl(base_address + INBOUND_QUEUE_PORT); in get_mfa_inbound()
/linux-4.1.27/drivers/net/hippi/
Drrunner.c189 writel(readl(&rrpriv->regs->HostCtrl) | NO_SWAP, in rr_init_one()
228 if (!(readl(&rr->regs->HostCtrl) & NIC_HALTED)) { in rr_remove_one()
262 if (readl(&regs->HostCtrl) & NIC_HALTED){ in rr_issue_cmd()
264 "HostCtrl %08x\n", cmd->code, readl(&regs->HostCtrl)); in rr_issue_cmd()
265 if (readl(&regs->Mode) & FATAL_ERR) in rr_issue_cmd()
267 readl(&regs->Fail1), readl(&regs->Fail2)); in rr_issue_cmd()
279 if (readl(&regs->Mode) & FATAL_ERR) in rr_issue_cmd()
280 printk("error code %02x\n", readl(&regs->Fail1)); in rr_issue_cmd()
408 io = readl(&regs->ExtIo); in rr_read_eeprom()
410 misc = readl(&regs->LocalCtrl); in rr_read_eeprom()
[all …]
/linux-4.1.27/drivers/phy/
Dphy-exynos5250-sata.c65 if ((readl(base + reg) & checkbit) == status) in wait_for_reg_status()
104 val = readl(sata_phy->regs + EXYNOS5_SATA_RESET); in exynos_sata_phy_init()
110 val = readl(sata_phy->regs + EXYNOS5_SATA_RESET); in exynos_sata_phy_init()
114 val = readl(sata_phy->regs + EXYNOS5_SATA_RESET); in exynos_sata_phy_init()
118 val = readl(sata_phy->regs + EXYNOS5_SATA_PHSATA_CTRLM); in exynos_sata_phy_init()
123 val = readl(sata_phy->regs + EXYNOS5_SATA_PHSATA_CTRLM); in exynos_sata_phy_init()
127 val = readl(sata_phy->regs + EXYNOS5_SATA_CTRL0); in exynos_sata_phy_init()
131 val = readl(sata_phy->regs + EXYNOS5_SATA_MODE0); in exynos_sata_phy_init()
140 val = readl(sata_phy->regs + EXYNOS5_SATA_RESET); in exynos_sata_phy_init()
144 val = readl(sata_phy->regs + EXYNOS5_SATA_RESET); in exynos_sata_phy_init()
Dphy-mvebu-sata.c40 reg = readl(priv->base + SATA_PHY_MODE_2); in phy_mvebu_sata_power_on()
46 reg = readl(priv->base + SATA_IF_CTRL); in phy_mvebu_sata_power_on()
63 reg = readl(priv->base + SATA_PHY_MODE_2); in phy_mvebu_sata_power_off()
69 reg = readl(priv->base + SATA_IF_CTRL); in phy_mvebu_sata_power_off()
Dphy-exynos5250-usb2.c217 otg = readl(drv->reg_phy + EXYNOS_5250_USBOTGSYS); in exynos5250_power_on()
247 ctrl0 = readl(drv->reg_phy + EXYNOS_5250_HOSTPHYCTRL0); in exynos5250_power_on()
269 otg = readl(drv->reg_phy + EXYNOS_5250_USBOTGSYS); in exynos5250_power_on()
306 ehci = readl(drv->reg_phy + EXYNOS_5250_HOSTEHCICTRL); in exynos5250_power_on()
314 ohci = readl(drv->reg_phy + EXYNOS_5250_HOSTOHCICTRL); in exynos5250_power_on()
337 otg = readl(drv->reg_phy + EXYNOS_5250_USBOTGSYS); in exynos5250_power_off()
344 ctrl0 = readl(drv->reg_phy + EXYNOS_5250_HOSTPHYCTRL0); in exynos5250_power_off()
/linux-4.1.27/arch/arm/mach-mvebu/
Dpmsu.c216 reg = readl(pmsu_mp_base + L2C_NFABRIC_PM_CTL); in mvebu_v7_pmsu_enable_l2_powerdown_onidle()
241 reg = readl(pmsu_mp_base + PMSU_STATUS_AND_MASK(hw_cpu)); in mvebu_v7_pmsu_idle_prepare()
250 reg = readl(pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu)); in mvebu_v7_pmsu_idle_prepare()
261 reg = readl(pmsu_mp_base + PMSU_CPU_POWER_DOWN_CONTROL(hw_cpu)); in mvebu_v7_pmsu_idle_prepare()
350 reg = readl(pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu)); in mvebu_v7_pmsu_idle_exit()
355 reg = readl(pmsu_mp_base + PMSU_STATUS_AND_MASK(hw_cpu)); in mvebu_v7_pmsu_idle_exit()
436 reg = readl(mpsoc_base + MPCORE_RESET_CTL); in armada_38x_cpuidle_init()
443 reg = readl(pmsu_mp_base + PMSU_POWERDOWN_DELAY); in armada_38x_cpuidle_init()
524 reg = readl(pmsu_mp_base + PMSU_STATUS_AND_MASK(cpu)); in mvebu_pmsu_dfs_request_local()
531 reg = readl(pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(cpu)); in mvebu_pmsu_dfs_request_local()
[all …]
/linux-4.1.27/drivers/usb/chipidea/
Dusbmisc_imx.c101 val = readl(usbmisc->base); in usbmisc_imx25_init()
108 val = readl(usbmisc->base); in usbmisc_imx25_init()
136 val = readl(reg); in usbmisc_imx25_post()
167 val = readl(usbmisc->base) | val; in usbmisc_imx27_init()
169 val = readl(usbmisc->base) & ~val; in usbmisc_imx27_init()
187 val = readl(usbmisc->base + MX53_USB_OTG_PHY_CTRL_1_OFFSET); in usbmisc_imx53_init()
197 val = readl(reg) | MX53_BM_OVER_CUR_DIS_OTG; in usbmisc_imx53_init()
201 val = readl(reg) | MX53_BM_OVER_CUR_DIS_H1; in usbmisc_imx53_init()
205 val = readl(reg) | MX53_BM_OVER_CUR_DIS_UHx; in usbmisc_imx53_init()
209 val = readl(reg) | MX53_BM_OVER_CUR_DIS_UHx; in usbmisc_imx53_init()
[all …]
/linux-4.1.27/drivers/usb/host/
Dxhci-hub.c98 portsc = readl(xhci->usb2_ports[i]); in xhci_usb2_hub_descriptor()
152 portsc = readl(xhci->usb3_ports[i]); in xhci_usb3_hub_descriptor()
350 port_status = readl(addr); in xhci_disable_port()
400 port_status = readl(addr); in xhci_clear_port_change_bit()
426 temp = readl(port_array[port_id]); in xhci_set_link_state()
438 temp = readl(port_array[port_id]); in xhci_set_remote_wake_mask()
465 temp = readl(port_array[port_id]); in xhci_test_and_clear_bit()
648 int port_status = readl(port_array[wIndex]); in xhci_get_port_status()
758 temp = readl(&xhci->cap_regs->hcs_params3); in xhci_hub_control()
764 temp = readl(&xhci->cap_regs->hcc_params); in xhci_hub_control()
[all …]
Dxhci-rcar.c65 temp = readl(hcd->regs + RCAR_USB3_INT_ENA); in xhci_rcar_start()
93 temp = readl(regs + RCAR_USB3_DL_CTRL); in xhci_rcar_download_firmware()
104 temp = readl(regs + RCAR_USB3_DL_CTRL); in xhci_rcar_download_firmware()
109 val = readl(regs + RCAR_USB3_DL_CTRL); in xhci_rcar_download_firmware()
120 temp = readl(regs + RCAR_USB3_DL_CTRL); in xhci_rcar_download_firmware()
125 val = readl(regs + RCAR_USB3_DL_CTRL); in xhci_rcar_download_firmware()
Dxhci-dbg.c35 temp = readl(&xhci->cap_regs->hc_capbase); in xhci_dbg_regs()
47 temp = readl(&xhci->cap_regs->run_regs_off); in xhci_dbg_regs()
53 temp = readl(&xhci->cap_regs->db_off); in xhci_dbg_regs()
64 temp = readl(&xhci->cap_regs->hc_capbase); in xhci_print_cap_regs()
72 temp = readl(&xhci->cap_regs->hcs_params1); in xhci_print_cap_regs()
82 temp = readl(&xhci->cap_regs->hcs_params2); in xhci_print_cap_regs()
90 temp = readl(&xhci->cap_regs->hcs_params3); in xhci_print_cap_regs()
98 temp = readl(&xhci->cap_regs->hcc_params); in xhci_print_cap_regs()
105 temp = readl(&xhci->cap_regs->run_regs_off); in xhci_print_cap_regs()
113 temp = readl(&xhci->op_regs->command); in xhci_print_command_reg()
[all …]
Dpci-quirks.c588 control = readl(base + OHCI_CONTROL); in quirk_usb_handoff_ohci()
601 readl(base + OHCI_CONTROL) & OHCI_CTRL_IR) { in quirk_usb_handoff_ohci()
608 readl(base + OHCI_CONTROL)); in quirk_usb_handoff_ohci()
619 readl(base + OHCI_CONTROL); in quirk_usb_handoff_ohci()
627 fminterval = readl(base + OHCI_FMINTERVAL); in quirk_usb_handoff_ohci()
633 if ((readl(base + OHCI_CMDSTATUS) & OHCI_HCR) == 0) in quirk_usb_handoff_ohci()
773 hcc_params = readl(base + EHCI_HCC_PARAMS); in quirk_usb_disable_ehci()
797 val = readl(op_reg_base + EHCI_USBSTS); in quirk_usb_disable_ehci()
799 val = readl(op_reg_base + EHCI_USBCMD); in quirk_usb_disable_ehci()
808 val = readl(op_reg_base + EHCI_USBSTS); in quirk_usb_disable_ehci()
[all …]
/linux-4.1.27/arch/arm/mach-netx/include/mach/
Dpfifo.h32 return readl(NETX_PFIFO_BASE(no)); in pfifo_pop()
38 return readl(NETX_PFIFO_FILL_LEVEL(no)); in pfifo_fill_level()
43 return readl(NETX_PFIFO_FULL) & (1<<no) ? 1 : 0; in pfifo_full()
48 return readl(NETX_PFIFO_EMPTY) & (1<<no) ? 1 : 0; in pfifo_empty()
/linux-4.1.27/drivers/net/ethernet/allwinner/
Dsun4i-emac.c94 reg_val = readl(db->membase + EMAC_MAC_SUPP_REG); in emac_update_speed()
107 reg_val = readl(db->membase + EMAC_MAC_CTL1_REG); in emac_update_duplex()
266 reg_val = readl(db->membase + EMAC_TX_MODE_REG); in emac_setup()
273 reg_val = readl(db->membase + EMAC_MAC_CTL0_REG); in emac_setup()
279 reg_val = readl(db->membase + EMAC_MAC_CTL1_REG); in emac_setup()
309 reg_val = readl(db->membase + EMAC_RX_CTL_REG); in emac_set_rx_mode()
330 reg_val = readl(db->membase + EMAC_RX_CTL_REG); in emac_powerup()
337 reg_val = readl(db->membase + EMAC_MAC_CTL0_REG); in emac_powerup()
342 reg_val = readl(db->membase + EMAC_MAC_MCFG_REG); in emac_powerup()
352 reg_val = readl(db->membase + EMAC_INT_STA_REG); in emac_powerup()
[all …]
/linux-4.1.27/arch/arm/mach-ux500/
Dpm.c49 u32 val = readl(PRCM_A9_MASK_REQ); in prcmu_gic_decouple()
56 readl(PRCM_A9_MASK_REQ); in prcmu_gic_decouple()
67 u32 val = readl(PRCM_A9_MASK_REQ); in prcmu_gic_recouple()
118 it = readl(PRCM_ARMITVAL31TO0 + i * 4); in prcmu_pending_irq()
119 im = readl(PRCM_ARMITMSK31TO0 + i * 4); in prcmu_pending_irq()
135 return readl(PRCM_ARM_WFI_STANDBY) & cpu ? PRCM_ARM_WFI_STANDBY_WFI1 : in prcmu_is_cpu_in_wfi()
Dcpu-db8500.c133 readl((u32 *)uid+0), in db8500_read_soc_id()
134 readl((u32 *)uid+1), readl((u32 *)uid+2), in db8500_read_soc_id()
135 readl((u32 *)uid+3), readl((u32 *)uid+4)); in db8500_read_soc_id()
/linux-4.1.27/sound/soc/kirkwood/
Dkirkwood-i2s.c65 value = readl(priv->io+KIRKWOOD_I2S_PLAYCTL); in kirkwood_i2s_set_fmt()
70 value = readl(priv->io+KIRKWOOD_I2S_RECCTL); in kirkwood_i2s_set_fmt()
100 value = readl(io + KIRKWOOD_DCO_SPCR_STATUS); in kirkwood_set_dco()
156 i2s_value = readl(priv->io+i2s_reg); in kirkwood_i2s_hw_params()
241 ctl = readl(priv->io + KIRKWOOD_PLAYCTL); in kirkwood_i2s_play_trigger()
251 ctl = readl(priv->io + KIRKWOOD_PLAYCTL); in kirkwood_i2s_play_trigger()
276 value = readl(priv->io + KIRKWOOD_INT_MASK); in kirkwood_i2s_play_trigger()
291 value = readl(priv->io + KIRKWOOD_INT_MASK); in kirkwood_i2s_play_trigger()
328 value = readl(priv->io + KIRKWOOD_RECCTL); in kirkwood_i2s_rec_trigger()
343 value = readl(priv->io + KIRKWOOD_INT_MASK); in kirkwood_i2s_rec_trigger()
[all …]
/linux-4.1.27/drivers/net/ethernet/sun/
Dsungem.c131 cmd = readl(gp->regs + MIF_FRAME); in __sungem_phy_read()
169 cmd = readl(gp->regs + MIF_FRAME); in __sungem_phy_write()
198 (void)readl(gp->regs + GREG_IMASK); /* write posting */ in gem_disable_ints()
259 u32 pcs_istat = readl(gp->regs + PCS_ISTAT); in gem_pcs_interrupt()
275 pcs_miistat = readl(gp->regs + PCS_MIISTAT); in gem_pcs_interrupt()
278 (readl(gp->regs + PCS_MIISTAT) & in gem_pcs_interrupt()
309 u32 txmac_stat = readl(gp->regs + MAC_TXSTAT); in gem_txmac_interrupt()
370 if (!(readl(gp->regs + MAC_RXRST) & MAC_RXRST_CMD)) in gem_rxmac_reset()
382 if (!(readl(gp->regs + MAC_RXCFG) & MAC_RXCFG_ENAB)) in gem_rxmac_reset()
394 if (!(readl(gp->regs + RXDMA_CFG) & RXDMA_CFG_ENABLE)) in gem_rxmac_reset()
[all …]
Dcassini.c378 batch_entropy_store(readl(cp->regs + REG_ENTROPY_IV), in cas_entropy_gather()
379 readl(cp->regs + REG_ENTROPY_IV), in cas_entropy_gather()
418 cmd = readl(cp->regs + REG_MIF_FRAME); in cas_phy_read()
440 cmd = readl(cp->regs + REG_MIF_FRAME); in cas_phy_write()
676 cfg = readl(cp->regs + REG_MIF_CFG); in cas_mif_poll()
757 u32 val = readl(cp->regs + REG_PCS_MII_CTRL); in cas_begin_auto_negotiation()
966 val = readl(cp->regs + REG_PCS_MII_CTRL); in cas_phy_init()
973 if ((readl(cp->regs + REG_PCS_MII_CTRL) & in cas_phy_init()
979 readl(cp->regs + REG_PCS_STATE_MACHINE)); in cas_phy_init()
987 val = readl(cp->regs + REG_PCS_MII_ADVERT); in cas_phy_init()
[all …]
/linux-4.1.27/drivers/memstick/host/
Dtifm_ms.c102 while (!(TIFM_MS_STAT_EMP & readl(sock->addr + SOCK_MS_STATUS))) { in tifm_ms_read_data()
112 && !(TIFM_MS_STAT_EMP & readl(sock->addr + SOCK_MS_STATUS))) { in tifm_ms_read_data()
113 host->io_word = readl(sock->addr + SOCK_MS_DATA); in tifm_ms_read_data()
141 && !(TIFM_MS_STAT_FUL & readl(sock->addr + SOCK_MS_STATUS))) { in tifm_ms_write_data()
142 writel(TIFM_MS_SYS_FDIR | readl(sock->addr + SOCK_MS_SYSTEM), in tifm_ms_write_data()
154 while (!(TIFM_MS_STAT_FUL & readl(sock->addr + SOCK_MS_STATUS))) { in tifm_ms_write_data()
157 writel(TIFM_MS_SYS_FDIR | readl(sock->addr + SOCK_MS_SYSTEM), in tifm_ms_write_data()
239 | readl(sock->addr + SOCK_MS_SYSTEM), in tifm_ms_transfer_data()
244 | readl(sock->addr + SOCK_MS_SYSTEM), in tifm_ms_transfer_data()
248 readl(sock->addr + SOCK_MS_DATA); in tifm_ms_transfer_data()
[all …]
Djmb38x_ms.c172 while (!(STATUS_FIFO_EMPTY & readl(host->addr + STATUS))) { in jmb38x_ms_read_data()
181 && !(STATUS_FIFO_EMPTY & readl(host->addr + STATUS))) { in jmb38x_ms_read_data()
182 host->io_word[0] = readl(host->addr + DATA); in jmb38x_ms_read_data()
236 && !(STATUS_FIFO_FULL & readl(host->addr + STATUS))) { in jmb38x_ms_write_data()
247 while (!(STATUS_FIFO_FULL & readl(host->addr + STATUS))) { in jmb38x_ms_write_data()
373 if (!(STATUS_HAS_MEDIA & readl(host->addr + STATUS))) { in jmb38x_ms_issue_cmd()
379 dev_dbg(&msh->dev, "control %08x\n", readl(host->addr + HOST_CONTROL)); in jmb38x_ms_issue_cmd()
380 dev_dbg(&msh->dev, "status %08x\n", readl(host->addr + INT_STATUS)); in jmb38x_ms_issue_cmd()
381 dev_dbg(&msh->dev, "hstatus %08x\n", readl(host->addr + STATUS)); in jmb38x_ms_issue_cmd()
440 t_val = readl(host->addr + INT_STATUS_ENABLE); in jmb38x_ms_issue_cmd()
[all …]
/linux-4.1.27/Documentation/zh_CN/
Dio_ordering.txt36 CPU A: val = readl(my_status);
42 CPU B: val = readl(my_status);
53 CPU A: val = readl(my_status);
56 CPU A: (void)readl(safe_register); /* 配置寄存器？*/
60 CPU B: val = readl(my_status);
63 CPU B: (void)readl(safe_register); /* 配置寄存器？*/
/linux-4.1.27/arch/sparc/kernel/
Debus.c61 val = readl(p->regs + EBDMA_CSR); in __ebus_dma_reset()
76 csr = readl(p->regs + EBDMA_CSR); in ebus_dma_irq()
135 csr = readl(p->regs + EBDMA_CSR); in ebus_dma_irq_enable()
141 csr = readl(p->regs + EBDMA_CSR); in ebus_dma_irq_enable()
162 csr = readl(p->regs + EBDMA_CSR); in ebus_dma_unregister()
185 csr = readl(p->regs + EBDMA_CSR); in ebus_dma_request()
230 return readl(p->regs + EBDMA_COUNT); in ebus_dma_residue()
236 return readl(p->regs + EBDMA_ADDR); in ebus_dma_addr()
246 orig_csr = csr = readl(p->regs + EBDMA_CSR); in ebus_dma_enable()
/linux-4.1.27/arch/arm/mach-cns3xxx/
Dcore.c104 clkctrl = readl(pm_base + PM_SYS_CLK_CTRL_OFFSET); in cns3xxx_power_off()
119 unsigned long ctrl = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); in cns3xxx_timer_set_mode()
145 unsigned long ctrl = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); in cns3xxx_timer_set_next_event()
180 val = readl(stat); in cns3xxx_timer_interrupt()
219 irq_mask = readl(cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET); in __cns3xxx_timer_init()
225 val = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); in __cns3xxx_timer_init()
234 irq_mask = readl(cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET); in __cns3xxx_timer_init()
239 val = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); in __cns3xxx_timer_init()
275 val = readl(base + L310_TAG_LATENCY_CTRL); in cns3xxx_l2x0_init()
288 val = readl(base + L310_DATA_LATENCY_CTRL); in cns3xxx_l2x0_init()
/linux-4.1.27/drivers/hsi/controllers/
Domap_ssi_port.c70 readl(base + SSI_WAKE_REG(port->num))); in ssi_debug_port_show()
72 readl(base + SSI_MPU_ENABLE_REG(port->num, 0))); in ssi_debug_port_show()
74 readl(base + SSI_MPU_STATUS_REG(port->num, 0))); in ssi_debug_port_show()
79 readl(base + SSI_SST_ID_REG)); in ssi_debug_port_show()
81 readl(base + SSI_SST_MODE_REG)); in ssi_debug_port_show()
83 readl(base + SSI_SST_FRAMESIZE_REG)); in ssi_debug_port_show()
85 readl(base + SSI_SST_DIVISOR_REG)); in ssi_debug_port_show()
87 readl(base + SSI_SST_CHANNELS_REG)); in ssi_debug_port_show()
89 readl(base + SSI_SST_ARBMODE_REG)); in ssi_debug_port_show()
91 readl(base + SSI_SST_TXSTATE_REG)); in ssi_debug_port_show()
[all …]
Domap_ssi.c58 seq_printf(m, "REVISION\t: 0x%08x\n", readl(sys + SSI_REVISION_REG)); in ssi_debug_show()
59 seq_printf(m, "SYSCONFIG\t: 0x%08x\n", readl(sys + SSI_SYSCONFIG_REG)); in ssi_debug_show()
60 seq_printf(m, "SYSSTATUS\t: 0x%08x\n", readl(sys + SSI_SYSSTATUS_REG)); in ssi_debug_show()
77 readl(sys + SSI_GDD_MPU_IRQ_STATUS_REG)); in ssi_debug_gdd_show()
79 readl(sys + SSI_GDD_MPU_IRQ_ENABLE_REG)); in ssi_debug_gdd_show()
81 readl(gdd + SSI_GDD_HW_ID_REG)); in ssi_debug_gdd_show()
83 readl(gdd + SSI_GDD_PPORT_ID_REG)); in ssi_debug_gdd_show()
85 readl(gdd + SSI_GDD_MPORT_ID_REG)); in ssi_debug_gdd_show()
87 readl(gdd + SSI_GDD_TEST_REG)); in ssi_debug_gdd_show()
89 readl(gdd + SSI_GDD_GCR_REG)); in ssi_debug_gdd_show()
[all …]
/linux-4.1.27/arch/arm/mach-clps711x/
Ddevices.c111 id[0] = readl(base + UNIQID); in clps711x_soc_init()
112 id[1] = readl(base + RANDID0); in clps711x_soc_init()
113 id[2] = readl(base + RANDID1); in clps711x_soc_init()
114 id[3] = readl(base + RANDID2); in clps711x_soc_init()
115 id[4] = readl(base + RANDID3); in clps711x_soc_init()
116 system_rev = SYSFLG1_VERID(readl(base + SYSFLG1)); in clps711x_soc_init()
/linux-4.1.27/drivers/gpio/
Dgpio-altera.c56 intmask = readl(mm_gc->regs + ALTERA_GPIO_IRQ_MASK); in altera_gpio_irq_unmask()
74 intmask = readl(mm_gc->regs + ALTERA_GPIO_IRQ_MASK); in altera_gpio_irq_mask()
131 return !!(readl(mm_gc->regs + ALTERA_GPIO_DATA) & BIT(offset)); in altera_gpio_get()
145 data_reg = readl(mm_gc->regs + ALTERA_GPIO_DATA); in altera_gpio_set()
166 gpio_ddr = readl(mm_gc->regs + ALTERA_GPIO_DIR); in altera_gpio_direction_input()
187 data_reg = readl(mm_gc->regs + ALTERA_GPIO_DATA); in altera_gpio_direction_output()
195 gpio_ddr = readl(mm_gc->regs + ALTERA_GPIO_DIR); in altera_gpio_direction_output()
221 (readl(mm_gc->regs + ALTERA_GPIO_EDGE_CAP) & in altera_gpio_irq_edge_handler()
222 readl(mm_gc->regs + ALTERA_GPIO_IRQ_MASK)))) { in altera_gpio_irq_edge_handler()
250 status = readl(mm_gc->regs + ALTERA_GPIO_DATA); in altera_gpio_irq_leveL_high_handler()
[all …]
Dgpio-bcm-kona.c102 val = readl(kona_gpio->reg_base + GPIO_PWD_STATUS(bank_id)); in bcm_kona_gpio_lock_gpio()
118 val = readl(kona_gpio->reg_base + GPIO_PWD_STATUS(bank_id)); in bcm_kona_gpio_unlock_gpio()
139 val = readl(reg_base + GPIO_CONTROL(gpio)); in bcm_kona_gpio_set()
148 val = readl(reg_base + reg_offset); in bcm_kona_gpio_set()
170 val = readl(reg_base + GPIO_CONTROL(gpio)); in bcm_kona_gpio_get()
176 val = readl(reg_base + reg_offset); in bcm_kona_gpio_get()
210 val = readl(reg_base + GPIO_CONTROL(gpio)); in bcm_kona_gpio_direction_input()
234 val = readl(reg_base + GPIO_CONTROL(gpio)); in bcm_kona_gpio_direction_output()
240 val = readl(reg_base + reg_offset); in bcm_kona_gpio_direction_output()
290 val = readl(reg_base + GPIO_CONTROL(gpio)); in bcm_kona_gpio_set_debounce()
[all …]
Dgpio-intel-mid.c109 u32 value = readl(gafr); in intel_gpio_request()
123 return readl(gplr) & BIT(offset % 32); in intel_gpio_get()
150 value = readl(gpdr); in intel_gpio_direction_input()
174 value = readl(gpdr); in intel_gpio_direction_output()
203 value = readl(grer) | BIT(gpio % 32); in intel_mid_irq_type()
205 value = readl(grer) & (~BIT(gpio % 32)); in intel_mid_irq_type()
209 value = readl(gfer) | BIT(gpio % 32); in intel_mid_irq_type()
211 value = readl(gfer) & (~BIT(gpio % 32)); in intel_mid_irq_type()
317 while ((pending = readl(gedr))) { in intel_mid_irq_handler()
381 irq_base = readl(base); in intel_gpio_probe()
[all …]
Dgpio-mb86s7x.c60 val = readl(gchip->base + PFR(gpio)); in mb86s70_gpio_request()
82 val = readl(gchip->base + PFR(gpio)); in mb86s70_gpio_free()
97 val = readl(gchip->base + DDR(gpio)); in mb86s70_gpio_direction_input()
115 val = readl(gchip->base + PDR(gpio)); in mb86s70_gpio_direction_output()
122 val = readl(gchip->base + DDR(gpio)); in mb86s70_gpio_direction_output()
135 return !!(readl(gchip->base + PDR(gpio)) & OFFSET(gpio)); in mb86s70_gpio_get()
146 val = readl(gchip->base + PDR(gpio)); in mb86s70_gpio_set()
Dgpio-sta2x11.c93 return readl(&regs->dat) & bit; in gsta_gpio_get()
181 val = readl(&regs->afsela); in gsta_set_config()
204 val = readl(&regs->pdis) | bit; in gsta_set_config()
209 val = readl(&regs->pdis) & ~bit; in gsta_set_config()
215 val = readl(&regs->pdis) & ~bit; in gsta_set_config()
244 val = readl(&regs->rimsc) & ~bit; in gsta_irq_disable()
248 val = readl(&regs->fimsc) & ~bit; in gsta_irq_disable()
269 val = readl(&regs->rimsc); in gsta_irq_enable()
274 val = readl(&regs->rimsc); in gsta_irq_enable()
312 while ((is = readl(&regs->is))) { in gsta_gpio_handler()
Dgpio-msm-v2.c131 writel(readl(reg) | n, reg); in set_gpio_bits()
136 writel(readl(reg) & ~n, reg); in clear_gpio_bits()
141 return readl(GPIO_IN_OUT(offset)) & BIT(GPIO_IN); in msm_gpio_get()
224 val = readl(GPIO_IN_OUT(gpio)) & BIT(GPIO_IN); in msm_gpio_update_dual_edge_pos()
229 val2 = readl(GPIO_IN_OUT(gpio)) & BIT(GPIO_IN); in msm_gpio_update_dual_edge_pos()
230 intstat = readl(GPIO_INTR_STATUS(gpio)) & BIT(INTR_STATUS); in msm_gpio_update_dual_edge_pos()
280 bits = readl(GPIO_INTR_CFG(gpio)); in msm_gpio_irq_set_type()
324 if (readl(GPIO_INTR_STATUS(i)) & BIT(INTR_STATUS)) in msm_summary_irq_handler()
/linux-4.1.27/drivers/net/ethernet/natsemi/
Dns83820.c620 cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY; in phy_intr()
624 tbisr = readl(dev->base + TBISR); in phy_intr()
625 tanar = readl(dev->base + TANAR); in phy_intr()
626 tanlpar = readl(dev->base + TANLPAR); in phy_intr()
634 writel(readl(dev->base + TXCFG) in phy_intr()
637 writel(readl(dev->base + RXCFG) | RXCFG_RX_FD, in phy_intr()
640 writel(readl(dev->base + GPIOR) | GPIOR_GP1_OUT, in phy_intr()
651 writel((readl(dev->base + TXCFG) in phy_intr()
654 writel(readl(dev->base + RXCFG) & ~RXCFG_RX_FD, in phy_intr()
657 writel(readl(dev->base + GPIOR) & ~GPIOR_GP1_OUT, in phy_intr()
[all …]
Dnatsemi.c711 readl(ns_ioaddr(dev) + IntrEnable); in natsemi_irq_enable()
717 readl(ns_ioaddr(dev) + IntrEnable); in natsemi_irq_disable()
894 if (np->ignore_phy || readl(ioaddr + ChipConfig) & CfgExtPhy) in natsemi_probe1()
938 np->srr = readl(ioaddr + SiliconRev); in natsemi_probe1()
990 #define eeprom_delay(ee_addr) readl(ee_addr)
1023 retval |= (readl(ee_addr) & EE_DataOut) ? 1 << i : 0; in eeprom_read()
1043 #define mii_delay(ioaddr) readl(ioaddr + EECtrl)
1051 data = readl(ioaddr + EECtrl); in mii_getbit()
1175 readl(ioaddr + ChipConfig); in init_phy_fixup()
1197 cfg = readl(ioaddr + ChipConfig); in init_phy_fixup()
[all …]
/linux-4.1.27/drivers/mmc/host/
Dtifm_sd.c128 val = readl(sock->addr + SOCK_MMCSD_DATA); in tifm_sd_read_fifo()
393 cmd->resp[0] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x1c) << 16) in tifm_sd_fetch_resp()
394 | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x18); in tifm_sd_fetch_resp()
395 cmd->resp[1] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x14) << 16) in tifm_sd_fetch_resp()
396 | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x10); in tifm_sd_fetch_resp()
397 cmd->resp[2] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x0c) << 16) in tifm_sd_fetch_resp()
398 | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x08); in tifm_sd_fetch_resp()
399 cmd->resp[3] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x04) << 16) in tifm_sd_fetch_resp()
400 | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x00); in tifm_sd_fetch_resp()
434 | readl(sock->addr in tifm_sd_check_status()
[all …]
Ds3cmci.c156 con = readl(host->base + S3C2410_SDICON); in dbg_dumpregs()
157 pre = readl(host->base + S3C2410_SDIPRE); in dbg_dumpregs()
158 cmdarg = readl(host->base + S3C2410_SDICMDARG); in dbg_dumpregs()
159 cmdcon = readl(host->base + S3C2410_SDICMDCON); in dbg_dumpregs()
160 cmdsta = readl(host->base + S3C2410_SDICMDSTAT); in dbg_dumpregs()
161 r0 = readl(host->base + S3C2410_SDIRSP0); in dbg_dumpregs()
162 r1 = readl(host->base + S3C2410_SDIRSP1); in dbg_dumpregs()
163 r2 = readl(host->base + S3C2410_SDIRSP2); in dbg_dumpregs()
164 r3 = readl(host->base + S3C2410_SDIRSP3); in dbg_dumpregs()
165 timer = readl(host->base + S3C2410_SDITIMER); in dbg_dumpregs()
[all …]
Dsdhci-esdhc-imx.c216 writel(((readl(base) & ~(mask << shift)) | (val << shift)), base); in esdhc_clrset_le()
223 u32 val = readl(host->ioaddr + reg); in esdhc_readl_le()
256 val = readl(host->ioaddr + SDHCI_CAPABILITIES) & 0xFFFF; in esdhc_readl_le()
310 data = readl(host->ioaddr + SDHCI_HOST_CONTROL); in esdhc_writel_le()
322 v = readl(host->ioaddr + ESDHC_VENDOR_SPEC); in esdhc_writel_le()
365 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); in esdhc_readw_le()
371 val = readl(host->ioaddr + ESDHC_MIX_CTRL); in esdhc_readw_le()
374 val = readl(host->ioaddr + SDHCI_ACMD12_ERR); in esdhc_readw_le()
389 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); in esdhc_readw_le()
414 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); in esdhc_writew_le()
[all …]
Ddavinci_mmc.c271 *((u32 *)p) = readl(host->base + DAVINCI_MMCDRR); in davinci_fifo_data_trans()
638 mmcst1 = readl(host->base + DAVINCI_MMCST1); in mmc_davinci_request()
701 temp = readl(host->base + DAVINCI_MMCCLK) & ~MMCCLK_CLKRT_MASK; in calculate_clk_divider()
714 temp = readl(host->base + DAVINCI_MMCCLK) & ~MMCCLK_CLKEN; in calculate_clk_divider()
719 temp = readl(host->base + DAVINCI_MMCCLK) & ~MMCCLK_CLKRT_MASK; in calculate_clk_divider()
754 writel((readl(host->base + DAVINCI_MMCCTL) & in mmc_davinci_set_ios()
761 writel((readl(host->base + DAVINCI_MMCCTL) & in mmc_davinci_set_ios()
765 writel(readl(host->base + DAVINCI_MMCCTL) | in mmc_davinci_set_ios()
772 writel(readl(host->base + DAVINCI_MMCCTL) & in mmc_davinci_set_ios()
776 writel(readl(host->base + DAVINCI_MMCCTL) & in mmc_davinci_set_ios()
[all …]
Dvia-sdmmc.c339 readl(addrbase + VIA_CRDR_SDCTRL), in via_print_sdchc()
340 readl(addrbase + VIA_CRDR_SDCARG), in via_print_sdchc()
341 readl(addrbase + VIA_CRDR_SDBUSMODE)); in via_print_sdchc()
343 readl(addrbase + VIA_CRDR_SDBLKLEN), in via_print_sdchc()
344 readl(addrbase + VIA_CRDR_SDCURBLKCNT), in via_print_sdchc()
345 readl(addrbase + VIA_CRDR_SDINTMASK)); in via_print_sdchc()
347 readl(addrbase + VIA_CRDR_SDSTATUS), in via_print_sdchc()
348 readl(addrbase + VIA_CRDR_SDCLKSEL), in via_print_sdchc()
349 readl(addrbase + VIA_CRDR_SDEXTCTRL)); in via_print_sdchc()
410 pm_sdhc_reg->sdcontrol_reg = readl(addrbase + VIA_CRDR_SDCTRL); in via_save_sdcreg()
[all …]
Dmoxart-mmc.c187 *status = readl(host->base + REG_STATUS); in moxart_wait_for_status()
240 cmd->resp[3] = readl(host->base + REG_RESPONSE0); in moxart_send_command()
241 cmd->resp[2] = readl(host->base + REG_RESPONSE1); in moxart_send_command()
242 cmd->resp[1] = readl(host->base + REG_RESPONSE2); in moxart_send_command()
243 cmd->resp[0] = readl(host->base + REG_RESPONSE3); in moxart_send_command()
245 cmd->resp[0] = readl(host->base + REG_RESPONSE0); in moxart_send_command()
410 if (readl(host->base + REG_STATUS) & CARD_DETECT) { in moxart_request()
473 status = readl(host->base + REG_STATUS); in moxart_irq()
515 writel(readl(host->base + REG_POWER_CONTROL) & ~SD_POWER_ON, in moxart_set_ios()
547 return !!(readl(host->base + REG_STATUS) & WRITE_PROT); in moxart_get_ro()
[all …]
/linux-4.1.27/drivers/net/ethernet/alteon/
Dacenic.c562 if ((readl(&ap->regs->HostCtrl) >> 28) == 4) { in acenic_probe_one()
614 writel(readl(&regs->CpuCtrl) | CPU_HALT, &regs->CpuCtrl); in acenic_remove_one()
616 writel(readl(&regs->CpuBCtrl) | CPU_HALT, &regs->CpuBCtrl); in acenic_remove_one()
622 readl(&regs->CpuCtrl); /* flush */ in acenic_remove_one()
851 idx = readl(&regs->CmdPrd); in ace_issue_cmd()
884 readl(&regs->HostCtrl); /* PCI write posting */ in ace_init()
901 readl(&regs->HostCtrl); /* PCI write posting */ in ace_init()
906 writel(readl(&regs->CpuCtrl) | CPU_HALT, &regs->CpuCtrl); in ace_init()
907 readl(&regs->CpuCtrl); /* PCI write posting */ in ace_init()
910 tig_ver = readl(&regs->HostCtrl) >> 28; in ace_init()
[all …]
/linux-4.1.27/drivers/platform/goldfish/
Dpdev_bus.c84 base = readl(pdev_bus_base + PDEV_BUS_IO_BASE); in goldfish_pdev_remove()
113 base = readl(pdev_bus_base + PDEV_BUS_IO_BASE); in goldfish_new_pdev()
115 irq_count = readl(pdev_bus_base + PDEV_BUS_IRQ_COUNT); in goldfish_new_pdev()
116 name_len = readl(pdev_bus_base + PDEV_BUS_NAME_LEN); in goldfish_new_pdev()
138 dev->pdev.id = readl(pdev_bus_base + PDEV_BUS_ID); in goldfish_new_pdev()
141 readl(pdev_bus_base + PDEV_BUS_IO_SIZE) - 1; in goldfish_new_pdev()
144 irq = readl(pdev_bus_base + PDEV_BUS_IRQ); in goldfish_new_pdev()
161 u32 op = readl(pdev_bus_base + PDEV_BUS_OP); in goldfish_pdev_bus_interrupt()
/linux-4.1.27/arch/arm/mach-netx/
Dgeneric.c78 stat = ((readl(NETX_DPMAS_INT_EN) & in netx_hif_demux_handler()
79 readl(NETX_DPMAS_INT_STAT)) >> 24) & 0x1f; in netx_hif_demux_handler()
96 val = readl(NETX_DPMAS_IF_CONF1); in netx_hif_irq_type()
130 val = readl(NETX_DPMAS_INT_EN); in netx_hif_ack_irq()
143 val = readl(NETX_DPMAS_INT_EN); in netx_hif_mask_irq()
155 val = readl(NETX_DPMAS_INT_EN); in netx_hif_unmask_irq()
/linux-4.1.27/drivers/pinctrl/
Dpinctrl-coh901.c242 return readl(U300_PIN_REG(offset, dir)) & U300_PIN_BIT(offset); in u300_gpio_get()
253 val = readl(U300_PIN_REG(offset, dor)); in u300_gpio_set()
269 val = readl(U300_PIN_REG(offset, pcr)); in u300_gpio_direction_input()
286 val = readl(U300_PIN_REG(offset, pcr)); in u300_gpio_direction_output()
317 biasmode = !!(readl(U300_PIN_REG(offset, per)) & U300_PIN_BIT(offset)); in u300_gpio_config_get()
320 drmode = readl(U300_PIN_REG(offset, pcr)); in u300_gpio_config_get()
377 val = readl(U300_PIN_REG(offset, per)); in u300_gpio_config_set()
381 val = readl(U300_PIN_REG(offset, per)); in u300_gpio_config_set()
385 val = readl(U300_PIN_REG(offset, pcr)); in u300_gpio_config_set()
393 val = readl(U300_PIN_REG(offset, pcr)); in u300_gpio_config_set()
[all …]
Dpinctrl-amd.c50 pin_reg = readl(gpio_dev->base + offset * 4); in amd_gpio_direction_input()
77 pin_reg = readl(gpio_dev->base + offset * 4); in amd_gpio_direction_output()
96 pin_reg = readl(gpio_dev->base + offset * 4); in amd_gpio_get_value()
109 pin_reg = readl(gpio_dev->base + offset * 4); in amd_gpio_set_value()
128 pin_reg = readl(gpio_dev->base + offset * 4); in amd_gpio_set_debounce()
226 pin_reg = readl(gpio_dev->base + i * 4); in amd_gpio_dbg_show()
333 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); in amd_gpio_irq_enable()
357 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); in amd_gpio_irq_disable()
372 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); in amd_gpio_irq_mask()
386 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); in amd_gpio_irq_unmask()
[all …]
/linux-4.1.27/sound/soc/intel/haswell/
Dsst-haswell-dsp.c256 reg = readl(sst->addr.pci_cfg + SST_VDRTCTL2); in hsw_set_dsp_D3()
261 val = readl(sst->addr.pci_cfg + SST_VDRTCTL0); in hsw_set_dsp_D3()
268 val = readl(sst->addr.pci_cfg + SST_VDRTCTL2); in hsw_set_dsp_D3()
277 val = readl(sst->addr.pci_cfg + SST_PMCS); in hsw_set_dsp_D3()
283 reg = readl(sst->addr.pci_cfg + SST_VDRTCTL2); in hsw_set_dsp_D3()
312 reg = readl(sst->addr.pci_cfg + SST_VDRTCTL2); in hsw_set_dsp_D0()
317 reg = readl(sst->addr.pci_cfg + SST_VDRTCTL0); in hsw_set_dsp_D0()
322 reg = readl(sst->addr.pci_cfg + SST_PMCS); in hsw_set_dsp_D0()
328 reg = readl(sst->addr.pci_cfg + SST_PMCS) & SST_PMCS_PS_MASK; in hsw_set_dsp_D0()
356 reg = readl(sst->addr.pci_cfg + SST_VDRTCTL2); in hsw_set_dsp_D0()
[all …]
/linux-4.1.27/drivers/ide/
Dsgiioc4.c112 if (readl((void __iomem *)intr_addr) & 0x03) in sgiioc4_checkirq()
128 intr_reg = readl((void __iomem *)other_ir); in sgiioc4_clearirq()
153 readl((void __iomem *)io_ports->irq_addr); in sgiioc4_clearirq()
155 readl((void __iomem *)(io_ports->irq_addr + 4)); in sgiioc4_clearirq()
171 intr_reg = readl((void __iomem *)other_ir); in sgiioc4_clearirq()
181 unsigned int reg = readl((void __iomem *)ioc4_dma_addr); in sgiioc4_dma_start()
194 ioc4_dma = readl((void __iomem *)ioc4_dma_addr); in sgiioc4_ide_dma_stop()
197 ioc4_dma = readl((void __iomem *)ioc4_dma_addr); in sgiioc4_ide_dma_stop()
243 bc_dev = readl((void __iomem *)(dma_base + IOC4_BC_DEV * 4)); in sgiioc4_dma_end()
244 bc_mem = readl((void __iomem *)(dma_base + IOC4_BC_MEM * 4)); in sgiioc4_dma_end()
[all …]
Dpalm_bk3710.c92 val32 = readl(base + BK3710_UDMASTB) & (0xFF << (dev ? 0 : 8)); in palm_bk3710_setudmamode()
97 val32 = readl(base + BK3710_UDMATRP) & (0xFF << (dev ? 0 : 8)); in palm_bk3710_setudmamode()
102 val32 = readl(base + BK3710_UDMAENV) & (0xFF << (dev ? 0 : 8)); in palm_bk3710_setudmamode()
130 val32 = readl(base + BK3710_DMASTB) & (0xFF << (dev ? 0 : 8)); in palm_bk3710_setdmamode()
134 val32 = readl(base + BK3710_DMARCVR) & (0xFF << (dev ? 0 : 8)); in palm_bk3710_setdmamode()
160 val32 = readl(base + BK3710_DATSTB) & (0xFF << (dev ? 0 : 8)); in palm_bk3710_setpiomode()
164 val32 = readl(base + BK3710_DATRCVR) & (0xFF << (dev ? 0 : 8)); in palm_bk3710_setpiomode()
182 val32 = readl(base + BK3710_REGSTB) & (0xFF << (dev ? 0 : 8)); in palm_bk3710_setpiomode()
186 val32 = readl(base + BK3710_REGRCVR) & (0xFF << (dev ? 0 : 8)); in palm_bk3710_setpiomode()
/linux-4.1.27/drivers/scsi/
Dhpsa.h360 (void) readl(h->vaddr + SA5_SCRATCHPAD_OFFSET); in SA5_submit_command()
385 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); in SA5_intr_mask()
390 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); in SA5_intr_mask()
399 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); in SA5_performant_intr_mask()
404 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); in SA5_performant_intr_mask()
418 (void) readl(h->vaddr + SA5_OUTDB_STATUS); in SA5_performant_completed()
423 (void) readl(h->vaddr + SA5_OUTDB_STATUS); in SA5_performant_completed()
449 = readl(h->vaddr + SA5_REPLY_PORT_OFFSET); in SA5_completed()
470 readl(h->vaddr + SA5_INTR_STATUS); in SA5_intr_pending()
476 unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS); in SA5_performant_intr_pending()
[all …]
Dhptiop.c60 req = readl(&hba->u.itl.iop->inbound_queue); in iop_wait_ready_itl()
68 readl(&hba->u.itl.iop->outbound_intstatus); in iop_wait_ready_itl()
98 while ((req = readl(&hba->u.itl.iop->outbound_queue)) != in hptiop_drain_outbound_queue_itl()
109 if (readl(&p->flags) & IOP_REQUEST_FLAG_SYNC_REQUEST) { in hptiop_drain_outbound_queue_itl()
110 if (readl(&p->context)) in hptiop_drain_outbound_queue_itl()
128 if (plx && readl(plx + 0x11C5C) & 0xf) in iop_intr_itl()
131 status = readl(&iop->outbound_intstatus); in iop_intr_itl()
134 u32 msg = readl(&iop->outbound_msgaddr0); in iop_intr_itl()
152 u32 outbound_tail = readl(&mu->outbound_tail); in mv_outbound_read()
153 u32 outbound_head = readl(&mu->outbound_head); in mv_outbound_read()
[all …]
/linux-4.1.27/drivers/pinctrl/intel/
Dpinctrl-baytrail.c178 value = readl(reg); in byt_gpio_clear_triggering()
217 value = readl(reg) & BYT_PIN_MUX; in byt_gpio_request()
220 value = readl(reg) & ~BYT_PIN_MUX; in byt_gpio_request()
255 value = readl(reg); in byt_irq_type()
286 val = readl(reg); in byt_gpio_get()
301 old_val = readl(reg); in byt_gpio_set()
320 value = readl(reg) | BYT_DIR_MASK; in byt_gpio_direction_input()
346 WARN(readl(conf_reg) & BYT_DIRECT_IRQ_EN, in byt_gpio_direction_output()
349 reg_val = readl(reg) | BYT_DIR_MASK; in byt_gpio_direction_output()
376 conf0 = readl(vg->reg_base + offs + BYT_CONF0_REG); in byt_gpio_dbg_show()
[all …]
Dpinctrl-intel.c159 return !(readl(padown) & PADOWN_MASK(padno)); in intel_pad_owned_by_host()
180 return !(readl(hostown) & BIT(padno % NPADS_IN_GPP)); in intel_pad_reserved_for_acpi()
204 value = readl(community->regs + offset); in intel_pad_locked()
209 value = readl(community->regs + offset); in intel_pad_locked()
260 cfg0 = readl(intel_get_padcfg(pctrl, pin, PADCFG0)); in intel_pin_dbg_show()
261 cfg1 = readl(intel_get_padcfg(pctrl, pin, PADCFG1)); in intel_pin_dbg_show()
348 value = readl(padcfg0); in intel_pinmux_set_mux()
379 value = readl(padcfg0) & ~PADCFG0_PMODE_MASK; in intel_gpio_request_enable()
406 value = readl(padcfg0); in intel_gpio_set_direction()
438 value = readl(intel_get_padcfg(pctrl, pin, PADCFG1)); in intel_config_get()
[all …]
Dpinctrl-cherryview.c678 readl(reg); in chv_writel()
687 return readl(reg) & CHV_PADCTRL1_CFGLOCK; in chv_pad_locked()
725 ctrl0 = readl(chv_padreg(pctrl, offset, CHV_PADCTRL0)); in chv_pin_dbg_show()
726 ctrl1 = readl(chv_padreg(pctrl, offset, CHV_PADCTRL1)); in chv_pin_dbg_show()
823 value = readl(reg); in chv_pinmux_set_mux()
833 value = readl(reg) & ~CHV_PADCTRL1_INVRXTX_MASK; in chv_pinmux_set_mux()
859 value = readl(chv_padreg(pctrl, offset, CHV_PADCTRL0)); in chv_gpio_request_enable()
878 value = readl(reg); in chv_gpio_request_enable()
884 value = readl(reg); in chv_gpio_request_enable()
919 value = readl(reg) & ~CHV_PADCTRL0_GPIOEN; in chv_gpio_disable_free()
[all …]
/linux-4.1.27/drivers/net/ethernet/chelsio/cxgb/
Despi.c74 busy = readl(adapter->regs + A_ESPI_GOSTAT) & F_ESPI_CMD_BUSY; in tricn_write()
87 if (!(readl(adapter->regs + A_ESPI_RX_RESET) & F_RX_CLK_STATUS)) { in tricn_init()
119 u32 enable, pl_intr = readl(espi->adapter->regs + A_PL_ENABLE); in t1_espi_intr_enable()
135 readl(espi->adapter->regs + A_ESPI_DIP2_ERR_COUNT); in t1_espi_intr_clear()
142 u32 pl_intr = readl(espi->adapter->regs + A_PL_ENABLE); in t1_espi_intr_disable()
150 u32 status = readl(espi->adapter->regs + A_ESPI_INTR_STATUS); in t1_espi_intr_handler()
169 readl(espi->adapter->regs + A_ESPI_DIP2_ERR_COUNT); in t1_espi_intr_handler()
273 espi->misc_ctrl = readl(adapter->regs + A_ESPI_MISC_CONTROL); in t1_espi_init()
332 sel = readl(adapter->regs + A_ESPI_SCH_TOKEN3); in t1_espi_get_mon()
335 sel = readl(adapter->regs + A_ESPI_SCH_TOKEN3); in t1_espi_get_mon()
[all …]
/linux-4.1.27/arch/arm/mach-mv78xx0/
Dcommon.c54 switch ((readl(SAMPLE_AT_RESET_LOW) >> 5) & 7) { in get_hclk()
72 readl(SAMPLE_AT_RESET_LOW)); in get_hclk()
87 cfg = (readl(SAMPLE_AT_RESET_LOW) >> 8) & 0x3f; in get_pclk_l2clk()
89 cfg = (readl(SAMPLE_AT_RESET_LOW) >> 14) & 0x3f; in get_pclk_l2clk()
112 switch ((readl(SAMPLE_AT_RESET_HIGH) >> 6) & 7) { in get_tclk()
121 readl(SAMPLE_AT_RESET_HIGH)); in get_tclk()
387 return !!(readl(CPU_CONTROL) & L2_WRITETHROUGH); in is_l2_writethrough()
/linux-4.1.27/drivers/edac/
Dsynopsys_edac.c158 regval = readl(base + STAT_OFST); in synps_edac_geterror_info()
165 regval = readl(base + CE_LOG_OFST); in synps_edac_geterror_info()
170 regval = readl(base + CE_ADDR_OFST); in synps_edac_geterror_info()
174 p->ceinfo.data = readl(base + CE_DATA_31_0_OFST); in synps_edac_geterror_info()
180 regval = readl(base + UE_LOG_OFST); in synps_edac_geterror_info()
184 regval = readl(base + UE_ADDR_OFST); in synps_edac_geterror_info()
188 p->ueinfo.data = readl(base + UE_DATA_31_0_OFST); in synps_edac_geterror_info()
271 width = readl(base + CTRL_OFST); in synps_edac_get_dtype()
306 ecctype = readl(base + SCRUB_OFST) & SCRUB_MODE_MASK; in synps_edac_get_eccstate()
341 memtype = readl(base + T_ZQ_OFST); in synps_edac_get_mtype()
Dhighbank_mc_edac.c72 status = readl(drvdata->mc_int_base + HB_DDR_ECC_INT_STATUS); in highbank_mc_err_handler()
75 err_addr = readl(drvdata->mc_err_base + HB_DDR_ECC_U_ERR_ADDR); in highbank_mc_err_handler()
83 u32 syndrome = readl(drvdata->mc_err_base + HB_DDR_ECC_C_ERR_STAT); in highbank_mc_err_handler()
85 err_addr = readl(drvdata->mc_err_base + HB_DDR_ECC_C_ERR_ADDR); in highbank_mc_err_handler()
103 reg = readl(pdata->mc_err_base + HB_DDR_ECC_OPT); in highbank_mc_err_inject()
217 control = readl(drvdata->mc_err_base + HB_DDR_ECC_OPT) & 0x3; in highbank_mc_probe()
/linux-4.1.27/drivers/media/platform/s5p-mfc/
Ds5p_mfc_opr_v6.c549 *y_addr = readl(mfc_regs->e_encoded_source_first_plane_addr); in s5p_mfc_get_enc_frame_buffer_v6()
550 *c_addr = readl(mfc_regs->e_encoded_source_second_plane_addr); in s5p_mfc_get_enc_frame_buffer_v6()
552 enc_recon_y_addr = readl(mfc_regs->e_recon_luma_dpb_addr); in s5p_mfc_get_enc_frame_buffer_v6()
553 enc_recon_c_addr = readl(mfc_regs->e_recon_chroma_dpb_addr); in s5p_mfc_get_enc_frame_buffer_v6()
680 reg = readl(mfc_regs->e_enc_options); in s5p_mfc_set_enc_params()
688 reg = readl(mfc_regs->e_enc_options); in s5p_mfc_set_enc_params()
695 reg = readl(mfc_regs->e_enc_options); in s5p_mfc_set_enc_params()
702 reg = readl(mfc_regs->e_enc_options); in s5p_mfc_set_enc_params()
709 reg = readl(mfc_regs->e_enc_options); in s5p_mfc_set_enc_params()
718 reg = readl(mfc_regs->e_enc_options); in s5p_mfc_set_enc_params()
[all …]
/linux-4.1.27/drivers/clocksource/
Dsun4i_timer.c53 u32 old = readl(timer_base + TIMER_CNTVAL_REG(1)); in sun4i_clkevt_sync()
55 while ((old - readl(timer_base + TIMER_CNTVAL_REG(1))) < TIMER_SYNC_TICKS) in sun4i_clkevt_sync()
61 u32 val = readl(timer_base + TIMER_CTL_REG(timer)); in sun4i_clkevt_time_stop()
73 u32 val = readl(timer_base + TIMER_CTL_REG(timer)); in sun4i_clkevt_time_start()
143 return ~readl(timer_base + TIMER_CNTVAL_REG(1)); in sun4i_timer_sched_read()
204 val = readl(timer_base + TIMER_IRQ_EN_REG); in sun4i_timer_init()
Dbcm_kona_timer.c59 reg = readl(base + KONA_GPTIMER_STCS_OFFSET); in kona_timer_disable_and_clear()
88 *msw = readl(timer_base + KONA_GPTIMER_STCHI_OFFSET); in kona_timer_get_counter()
89 *lsw = readl(timer_base + KONA_GPTIMER_STCLO_OFFSET); in kona_timer_get_counter()
90 if (*msw == readl(timer_base + KONA_GPTIMER_STCHI_OFFSET)) in kona_timer_get_counter()
123 reg = readl(timers.tmr_regs + KONA_GPTIMER_STCS_OFFSET); in kona_timer_set_next_event()
Dvt8500_timer.c61 while ((readl((regbase + TIMER_AS_VAL)) & TIMER_COUNT_R_ACTIVE) in vt8500_timer_read()
64 return readl(regbase + TIMER_COUNT_VAL); in vt8500_timer_read()
80 while ((readl(regbase + TIMER_AS_VAL) & TIMER_MATCH_W_ACTIVE) in vt8500_timer_set_next_event()
103 writel(readl(regbase + TIMER_CTRL_VAL) | 1, in vt8500_timer_set_mode()
/linux-4.1.27/arch/x86/kernel/
Dpci-calgary_64.c552 aer = readl(target); in calgary_tce_cache_blast()
557 val = readl(target); in calgary_tce_cache_blast()
575 (void)readl(target); /* flush */ in calgary_tce_cache_blast()
594 val = be32_to_cpu(readl(target)); in calioc2_tce_cache_blast()
612 val = be32_to_cpu(readl(target)); in calioc2_tce_cache_blast()
628 val = be32_to_cpu(readl(target)); in calioc2_tce_cache_blast()
631 val = be32_to_cpu(readl(target)); in calioc2_tce_cache_blast()
642 val = be32_to_cpu(readl(target)); in calioc2_tce_cache_blast()
651 val = be32_to_cpu(readl(target)); in calioc2_tce_cache_blast()
678 low = be32_to_cpu(readl(target)); in calgary_reserve_peripheral_mem_1()
[all …]
/linux-4.1.27/drivers/net/ethernet/ti/
Dnetcp_xgbepcsr.c29 writel(((readl(addr) & (~(mask))) | \
219 val_0 = (readl(sw_regs + XGBE_SGMII_1_OFFSET) & BIT(4)); in netcp_xgbe_wait_pll_locked()
220 val_1 = (readl(sw_regs + XGBE_SGMII_2_OFFSET) & BIT(4)); in netcp_xgbe_wait_pll_locked()
247 tmp = (readl(serdes_regs + 0x0ec) >> 24) & 0x0ff; in netcp_xgbe_serdes_read_tbus_val()
248 tmp |= ((readl(serdes_regs + 0x0fc) >> 16) & 0x00f00); in netcp_xgbe_serdes_read_tbus_val()
250 tmp = (readl(serdes_regs + 0x0f8) >> 16) & 0x0fff; in netcp_xgbe_serdes_read_tbus_val()
325 loss = readl(serdes_regs + 0x1fc0 + 0x20 + (i * 0x04)) & 0x1; in netcp_xgbe_check_link_status()
328 pcsr_rx_stat = readl(pcsr_base + 0x0c + (i * 0x80)); in netcp_xgbe_check_link_status()
495 val = readl(serdes_regs + 0xa00); in netcp_xgbe_serdes_init()
/linux-4.1.27/drivers/vlynq/
Dvlynq.c114 if (readl(&dev->local->status) & VLYNQ_STATUS_LINK) in vlynq_linked()
124 writel(readl(&dev->local->control) | VLYNQ_CTRL_RESET, in vlynq_reset()
131 writel(readl(&dev->local->control) & ~VLYNQ_CTRL_RESET, in vlynq_reset()
146 val = readl(&dev->remote->int_device[virq >> 2]); in vlynq_irq_unmask()
159 val = readl(&dev->remote->int_device[virq >> 2]); in vlynq_irq_mask()
172 val = readl(&dev->remote->int_device[virq >> 2]); in vlynq_irq_type()
198 u32 status = readl(&dev->local->status); in vlynq_local_ack()
208 u32 status = readl(&dev->remote->status); in vlynq_remote_ack()
221 status = readl(&dev->local->int_status); in vlynq_irq()
271 writel(readl(&dev->local->status), &dev->local->status); in vlynq_setup_irq()
[all …]
/linux-4.1.27/drivers/media/platform/exynos-gsc/
Dgsc-regs.c29 cfg = readl(dev->regs + GSC_SW_RESET); in gsc_wait_reset()
42 cfg = readl(dev->regs + GSC_IRQ); in gsc_hw_set_frm_done_irq_mask()
54 cfg = readl(dev->regs + GSC_IRQ); in gsc_hw_set_gsc_irq_enable()
65 u32 cfg = readl(dev->regs + GSC_IN_BASE_ADDR_Y_MASK); in gsc_hw_set_input_buf_masking()
79 u32 cfg = readl(dev->regs + GSC_OUT_BASE_ADDR_Y_MASK); in gsc_hw_set_output_buf_masking()
115 u32 cfg = readl(dev->regs + GSC_IN_CON); in gsc_hw_set_input_path()
152 cfg = readl(dev->regs + GSC_IN_CON); in gsc_hw_set_in_image_rgb()
173 cfg = readl(dev->regs + GSC_IN_CON); in gsc_hw_set_in_image_format()
226 u32 cfg = readl(dev->regs + GSC_OUT_CON); in gsc_hw_set_output_path()
272 cfg = readl(dev->regs + GSC_OUT_CON); in gsc_hw_set_out_image_rgb()
[all …]
/linux-4.1.27/drivers/irqchip/
Dirq-sun4i.c58 val = readl(sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(reg)); in sun4i_irq_mask()
70 val = readl(sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(reg)); in sun4i_irq_unmask()
151 hwirq = readl(sun4i_irq_base + SUN4I_IRQ_VECTOR_REG) >> 2; in sun4i_handle_irq()
153 !(readl(sun4i_irq_base + SUN4I_IRQ_PENDING_REG(0)) & BIT(0))) in sun4i_handle_irq()
158 hwirq = readl(sun4i_irq_base + SUN4I_IRQ_VECTOR_REG) >> 2; in sun4i_handle_irq()
Dirq-zevio.c50 readl(gc->reg_base + regs->ack); in zevio_irq_ack()
57 while (readl(zevio_irq_io + IO_STATUS)) { in zevio_handle_irq()
58 irqnr = readl(zevio_irq_io + IO_CURRENT); in zevio_handle_irq()
72 readl(base + IO_RESET); in zevio_init_irq_base()
/linux-4.1.27/drivers/scsi/isci/
Dphy.c108 tl_control = readl(&iphy->transport_layer_registers->control); in sci_phy_transport_layer_initialization()
158 phy_configuration = readl(&llr->phy_configuration); in sci_phy_link_layer_initialization()
203 reg = readl(&xcvr->afe_xcvr_control0); in sci_phy_link_layer_initialization()
207 reg = readl(&xcvr->afe_tx_ssc_control); in sci_phy_link_layer_initialization()
215 reg = readl(&xcvr->afe_tx_ssc_control); in sci_phy_link_layer_initialization()
219 reg = readl(&llr->stp_control); in sci_phy_link_layer_initialization()
284 sp_timeouts = readl(&llr->sas_phy_timeouts); in sci_phy_link_layer_initialization()
419 tl_control = readl(&iphy->transport_layer_registers->control); in sci_phy_setup_transport()
429 readl(&iphy->link_layer_registers->phy_configuration); in sci_phy_suspend()
442 readl(&iphy->link_layer_registers->phy_configuration); in sci_phy_resume()
[all …]
/linux-4.1.27/Documentation/
Dio_ordering.txt15 CPU A: val = readl(my_status);
21 CPU B: val = readl(my_status);
32 CPU A: val = readl(my_status);
35 CPU A: (void)readl(safe_register); /* maybe a config register? */
39 CPU B: val = readl(my_status);
42 CPU B: (void)readl(safe_register); /* maybe a config register? */
/linux-4.1.27/drivers/pinctrl/qcom/
Dpinctrl-msm.c160 val = readl(pctrl->regs + g->ctl_reg); in msm_pinmux_set_mux()
236 val = readl(pctrl->regs + g->ctl_reg); in msm_config_group_get()
261 val = readl(pctrl->regs + g->io_reg); in msm_config_group_get()
329 val = readl(pctrl->regs + g->io_reg); in msm_config_group_set()
357 val = readl(pctrl->regs + g->ctl_reg); in msm_config_group_set()
391 val = readl(pctrl->regs + g->ctl_reg); in msm_gpio_direction_input()
411 val = readl(pctrl->regs + g->io_reg); in msm_gpio_direction_output()
418 val = readl(pctrl->regs + g->ctl_reg); in msm_gpio_direction_output()
435 val = readl(pctrl->regs + g->io_reg); in msm_gpio_get()
450 val = readl(pctrl->regs + g->io_reg); in msm_gpio_set()
[all …]
/linux-4.1.27/arch/m68k/coldfire/
Dm53xx.c366 if (!(readl(MCF_SDRAMC_SDCR) & MCF_SDRAMC_SDCR_REF)) { in sdramc_init()
423 writel(readl(MCF_SDRAMC_SDCR) | MCF_SDRAMC_SDCR_IPALL, MCF_SDRAMC_SDCR); in sdramc_init()
428 writel(readl(MCF_SDRAMC_SDCR) | MCF_SDRAMC_SDCR_IREF, MCF_SDRAMC_SDCR); in sdramc_init()
429 writel(readl(MCF_SDRAMC_SDCR) | MCF_SDRAMC_SDCR_IREF, MCF_SDRAMC_SDCR); in sdramc_init()
442 writel(readl(MCF_SDRAMC_SDCR) & ~MCF_SDRAMC_SDCR_MODE_EN, in sdramc_init()
499 if (readl(MCF_SDRAMC_SDCR) & MCF_SDRAMC_SDCR_REF) in clock_pll()
501 writel(readl(MCF_SDRAMC_SDCR) & ~MCF_SDRAMC_SDCR_CKE, in clock_pll()
524 if (readl(MCF_SDRAMC_SDCR) & MCF_SDRAMC_SDCR_REF) in clock_pll()
526 writel(readl(MCF_SDRAMC_SDCR) | MCF_SDRAMC_SDCR_CKE, in clock_pll()
/linux-4.1.27/drivers/input/serio/
Dolpc_apsp.c94 u32 sts = readl(priv->base + COMMAND_FIFO_STATUS); in olpc_apsp_write()
105 readl(priv->base + COMMAND_FIFO_STATUS)); in olpc_apsp_write()
120 tmp = readl(priv->base + PJ_RST_INTERRUPT); in olpc_apsp_rx()
126 w = readl(priv->base + COMMAND_RETURN_STATUS); in olpc_apsp_rx()
151 tmp = readl(priv->base + PJ_INTERRUPT_MASK); in olpc_apsp_open()
165 tmp = readl(priv->base + PJ_INTERRUPT_MASK); in olpc_apsp_close()
195 l = readl(priv->base + COMMAND_FIFO_STATUS); in olpc_apsp_probe()
/linux-4.1.27/drivers/clk/socfpga/
Dclk-gate.c50 l4_src = readl(clk_mgr_base_addr + CLKMGR_L4SRC); in socfpga_clk_get_parent()
54 l4_src = readl(clk_mgr_base_addr + CLKMGR_L4SRC); in socfpga_clk_get_parent()
58 perpll_src = readl(clk_mgr_base_addr + CLKMGR_PERPLL_SRC); in socfpga_clk_get_parent()
75 src_reg = readl(clk_mgr_base_addr + CLKMGR_L4SRC); in socfpga_clk_set_parent()
80 src_reg = readl(clk_mgr_base_addr + CLKMGR_L4SRC); in socfpga_clk_set_parent()
85 src_reg = readl(clk_mgr_base_addr + CLKMGR_PERPLL_SRC); in socfpga_clk_set_parent()
112 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; in socfpga_clk_recalc_rate()
/linux-4.1.27/drivers/pci/host/
Dpci-imx6.c87 val = readl(dbi_base + PCIE_PHY_STAT); in pcie_phy_poll_ack()
143 val = readl(dbi_base + PCIE_PHY_STAT); in pcie_phy_read()
238 val = readl(pp->dbi_base + PCIE_PL_PFLR); in imx6_pcie_assert_core_reset()
347 readl(pp->dbi_base + PCIE_PHY_DEBUG_R0), in imx6_pcie_wait_for_link()
348 readl(pp->dbi_base + PCIE_PHY_DEBUG_R1)); in imx6_pcie_wait_for_link()
373 tmp = readl(pp->dbi_base + PCIE_RC_LCR); in imx6_pcie_start_link()
387 tmp = readl(pp->dbi_base + PCIE_RC_LCR); in imx6_pcie_start_link()
396 tmp = readl(pp->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL); in imx6_pcie_start_link()
402 tmp = readl(pp->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL); in imx6_pcie_start_link()
418 tmp = readl(pp->dbi_base + 0x80); in imx6_pcie_start_link()
[all …]
Dpci-keystone-dw.c86 pending = readl(ks_pcie->va_app_base + MSI0_IRQ_STATUS + (offset << 4)); in ks_dw_pcie_handle_msi_irq()
242 pending = readl(ks_pcie->va_app_base + IRQ_STATUS + (offset << 4)); in ks_dw_pcie_handle_legacy_irq()
301 writel(DBI_CS2_EN_VAL | readl(reg_virt + CMD_STATUS), in ks_dw_pcie_set_dbi_mode()
305 val = readl(reg_virt + CMD_STATUS); in ks_dw_pcie_set_dbi_mode()
319 writel(~DBI_CS2_EN_VAL & readl(reg_virt + CMD_STATUS), in ks_dw_pcie_clear_dbi_mode()
323 val = readl(reg_virt + CMD_STATUS); in ks_dw_pcie_clear_dbi_mode()
352 writel(OB_XLAT_EN_VAL | readl(ks_pcie->va_app_base + CMD_STATUS), in ks_dw_pcie_setup_rc_app_regs()
451 u32 val = readl(pp->dbi_base + DEBUG0); in ks_dw_pcie_link_up()
461 val = readl(ks_pcie->va_app_base + CMD_STATUS); in ks_dw_pcie_initiate_link_train()
466 val = readl(ks_pcie->va_app_base + CMD_STATUS); in ks_dw_pcie_initiate_link_train()
/linux-4.1.27/drivers/virtio/
Dvirtio_mmio.c121 features = readl(vm_dev->base + VIRTIO_MMIO_DEVICE_FEATURES); in vm_get_features()
125 features |= readl(vm_dev->base + VIRTIO_MMIO_DEVICE_FEATURES); in vm_get_features()
183 l = cpu_to_le32(readl(base + offset)); in vm_get()
187 l = cpu_to_le32(readl(base + offset)); in vm_get()
247 return readl(vm_dev->base + VIRTIO_MMIO_CONFIG_GENERATION); in vm_generation()
254 return readl(vm_dev->base + VIRTIO_MMIO_STATUS) & 0xff; in vm_get_status()
300 status = readl(vm_dev->base + VIRTIO_MMIO_INTERRUPT_STATUS); in vm_interrupt()
339 WARN_ON(readl(vm_dev->base + VIRTIO_MMIO_QUEUE_READY)); in vm_del_vq()
377 if (readl(vm_dev->base + (vm_dev->version == 1 ? in vm_setup_vq()
395 info->num = readl(vm_dev->base + VIRTIO_MMIO_QUEUE_NUM_MAX); in vm_setup_vq()
[all …]
/linux-4.1.27/arch/arm/mach-sunxi/
Dplatsmp.c90 reg = readl(cpucfg_membase + CPUCFG_GEN_CTRL_REG); in sun6i_smp_boot_secondary()
94 reg = readl(cpucfg_membase + CPUCFG_DBG_CTL1_REG); in sun6i_smp_boot_secondary()
103 reg = readl(prcm_membase + PRCM_CPU_PWROFF_REG); in sun6i_smp_boot_secondary()
111 reg = readl(cpucfg_membase + CPUCFG_DBG_CTL1_REG); in sun6i_smp_boot_secondary()
/linux-4.1.27/drivers/scsi/qla4xxx/
Dql4_inline.h44 readl(&ha->reg->u1.isp4022.intr_mask); in __qla4xxx_enable_intrs()
47 readl(&ha->reg->ctrl_status); in __qla4xxx_enable_intrs()
58 readl(&ha->reg->u1.isp4022.intr_mask); in __qla4xxx_disable_intrs()
61 readl(&ha->reg->ctrl_status); in __qla4xxx_disable_intrs()
Dql4_isr.c685 ha->mbox_status[i] = readl(&mailbox_out[i]); in qla4xxx_isr_decode_mailbox()
694 mbox_sts[i] = readl(&mailbox_out[i]); in qla4xxx_isr_decode_mailbox()
1033 readl(&ha->qla4_83xx_reg->mailbox_out[0])); in qla4_83xx_interrupt_service_routine()
1062 readl(&ha->qla4_82xx_reg->mailbox_out[0])); in qla4_82xx_interrupt_service_routine()
1066 readl(&ha->qla4_82xx_reg->host_int); in qla4_82xx_interrupt_service_routine()
1086 readl(&ha->reg->mailbox[0])); in qla4xxx_interrupt_service_routine()
1091 readl(&ha->reg->ctrl_status); in qla4xxx_interrupt_service_routine()
1151 intr_status = readl(&ha->reg->ctrl_status); in qla4xxx_intr_handler()
1163 readl(isp_port_error_status (ha)))); in qla4xxx_intr_handler()
1172 if ((readl(&ha->reg->ctrl_status) & in qla4xxx_intr_handler()
[all …]
/linux-4.1.27/drivers/pinctrl/samsung/
Dpinctrl-exynos5440.c360 data = readl(base + GPIO_MUX); in exynos5440_pinmux_setup()
419 data = readl(base + GPIO_PE); in exynos5440_pinconf_set()
426 data = readl(base + GPIO_PS); in exynos5440_pinconf_set()
435 data = readl(base + GPIO_DS0); in exynos5440_pinconf_set()
442 data = readl(base + GPIO_DS1); in exynos5440_pinconf_set()
448 data = readl(base + GPIO_SR); in exynos5440_pinconf_set()
454 data = readl(base + GPIO_TYPE); in exynos5440_pinconf_set()
482 data = readl(base + GPIO_PE); in exynos5440_pinconf_get()
487 *config = ((readl(base + GPIO_PS) >> pin) & 1) + 1; in exynos5440_pinconf_get()
490 data = readl(base + GPIO_DS0); in exynos5440_pinconf_get()
[all …]
/linux-4.1.27/sound/arm/
Daaci.c47 v = readl(aaci->base + AACI_SLFR); in aaci_ac97_select_codec()
49 readl(aaci->base + AACI_SL2RX); in aaci_ac97_select_codec()
51 readl(aaci->base + AACI_SL1RX); in aaci_ac97_select_codec()
53 if (maincr != readl(aaci->base + AACI_MAINCR)) { in aaci_ac97_select_codec()
55 readl(aaci->base + AACI_MAINCR); in aaci_ac97_select_codec()
97 v = readl(aaci->base + AACI_SLFR); in aaci_ac97_write()
135 v = readl(aaci->base + AACI_SLFR); in aaci_ac97_read()
152 v = readl(aaci->base + AACI_SLFR) & (SLFR_1RXV|SLFR_2RXV); in aaci_ac97_read()
162 v = readl(aaci->base + AACI_SL1RX) >> 12; in aaci_ac97_read()
164 v = readl(aaci->base + AACI_SL2RX) >> 4; in aaci_ac97_read()
[all …]
/linux-4.1.27/drivers/mfd/
Ddb8500-prcmu.c599 if ((readl(PRCM_PLLDSI_LOCKP) & PRCMU_PLLDSI_LOCKP_LOCKED) in db8500_prcmu_enable_dsipll()
625 while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0) in db8500_prcmu_set_display_clocks()
642 return readl(prcmu_base + reg); in db8500_prcmu_read()
660 val = readl(prcmu_base + reg); in db8500_prcmu_write_masked()
761 val = readl(PRCM_CLKOCR); in prcmu_config_clkout()
792 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0)) in db8500_prcmu_set_power_state()
835 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0)) in config_wakeups()
905 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) in db8500_prcmu_set_arm_opp()
976 while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0) in request_even_slower_clocks()
983 val = readl(prcmu_base + clock_reg[i]); in request_even_slower_clocks()
[all …]
/linux-4.1.27/drivers/pinctrl/sirf/
Dpinctrl-sirf.c150 muxval = readl(spmx->gpio_virtbase + in sirfsoc_pinmux_endisable()
164 readl(spmx->rsc_virtbase + mux->ctrlreg); in sirfsoc_pinmux_endisable()
215 muxval = readl(spmx->gpio_virtbase + in sirfsoc_pinmux_request_gpio()
338 spmx->gpio_regs[i][j] = readl(spmx->gpio_virtbase + in sirfsoc_pinmux_suspend_noirq()
341 spmx->ints_regs[i] = readl(spmx->gpio_virtbase + in sirfsoc_pinmux_suspend_noirq()
343 spmx->paden_regs[i] = readl(spmx->gpio_virtbase + in sirfsoc_pinmux_suspend_noirq()
346 spmx->dspen_regs = readl(spmx->gpio_virtbase + SIRFSOC_GPIO_DSP_EN0); in sirfsoc_pinmux_suspend_noirq()
349 spmx->rsc_regs[i] = readl(spmx->rsc_virtbase + 4 * i); in sirfsoc_pinmux_suspend_noirq()
431 val = readl(sgpio->chip.regs + offset); in sirfsoc_gpio_irq_ack()
449 val = readl(sgpio->chip.regs + offset); in __sirfsoc_gpio_irq_mask()
[all …]
/linux-4.1.27/drivers/mcb/
Dmcb-parse.c24 dtype = readl(p); in get_next_dtype()
52 reg1 = readl(&gdd->reg1); in chameleon_parse_gdd()
53 reg2 = readl(&gdd->reg2); in chameleon_parse_gdd()
54 offset = readl(&gdd->offset); in chameleon_parse_gdd()
55 size = readl(&gdd->size); in chameleon_parse_gdd()
/linux-4.1.27/drivers/watchdog/
Dsirfsoc_wdt.c49 counter = readl(wdt_base + SIRFSOC_TIMER_COUNTER_LO); in sirfsoc_wdt_gettimeleft()
50 match = readl(wdt_base + in sirfsoc_wdt_gettimeleft()
70 counter = readl(wdt_base + SIRFSOC_TIMER_LATCHED_LO); in sirfsoc_wdt_updatetimeout()
89 writel(readl(wdt_base + SIRFSOC_TIMER_INT_EN) in sirfsoc_wdt_enable()
102 writel(readl(wdt_base + SIRFSOC_TIMER_INT_EN) in sirfsoc_wdt_disable()
/linux-4.1.27/drivers/net/wireless/prism54/
Disl_38xx.c130 readl(device_base + ISL38XX_CTRL_STAT_REG)); in isl38xx_trigger_device()
133 reg = readl(device_base + ISL38XX_INT_IDENT_REG); in isl38xx_trigger_device()
142 while (reg = readl(device_base + ISL38XX_CTRL_STAT_REG), in isl38xx_trigger_device()
154 readl(device_base + ISL38XX_CTRL_STAT_REG)); in isl38xx_trigger_device()
170 reg = readl(device_base + ISL38XX_CTRL_STAT_REG); in isl38xx_trigger_device()
/linux-4.1.27/drivers/net/ethernet/calxeda/
Dxgmac.c518 u32 reg = readl(ioaddr + XGMAC_OMR); in xgmac_dma_flush_tx_fifo()
521 while ((timeout-- > 0) && readl(ioaddr + XGMAC_OMR) & XGMAC_OMR_FTF) in xgmac_dma_flush_tx_fifo()
600 u32 value = readl(ioaddr + XGMAC_CONTROL); in xgmac_mac_enable()
604 value = readl(ioaddr + XGMAC_DMA_CONTROL); in xgmac_mac_enable()
611 u32 value = readl(ioaddr + XGMAC_DMA_CONTROL); in xgmac_mac_disable()
615 value = readl(ioaddr + XGMAC_CONTROL); in xgmac_mac_disable()
642 hi_addr = readl(ioaddr + XGMAC_ADDR_HIGH(num)); in xgmac_get_mac_addr()
643 lo_addr = readl(ioaddr + XGMAC_ADDR_LOW(num)); in xgmac_get_mac_addr()
673 reg = readl(priv->base + XGMAC_OMR); in xgmac_set_flow_ctrl()
679 reg = readl(priv->base + XGMAC_OMR); in xgmac_set_flow_ctrl()
[all …]
/linux-4.1.27/drivers/net/ethernet/freescale/
Dfec_ptp.c143 val = readl(fep->hwp + FEC_TCSR(fep->pps_channel)); in fec_ptp_enable_pps()
147 val = readl(fep->hwp + FEC_TCSR(fep->pps_channel)); in fec_ptp_enable_pps()
159 tempval = readl(fep->hwp + FEC_ATIME_CTRL); in fec_ptp_enable_pps()
163 tempval = readl(fep->hwp + FEC_ATIME); in fec_ptp_enable_pps()
200 val = readl(fep->hwp + FEC_ATIME_CTRL); in fec_ptp_enable_pps()
205 val = readl(fep->hwp + FEC_TCSR(fep->pps_channel)); in fec_ptp_enable_pps()
243 tempval = readl(fep->hwp + FEC_ATIME_CTRL); in fec_ptp_read()
250 return readl(fep->hwp + FEC_ATIME); in fec_ptp_read()
353 tmp = readl(fep->hwp + FEC_ATIME_INC) & FEC_T_INC_MASK; in fec_ptp_adjfreq()
618 val = readl(fep->hwp + FEC_TCSR(channel)); in fec_ptp_check_pps_event()
[all …]
/linux-4.1.27/drivers/scsi/arcmsr/
Darcmsr_hba.c249 if (readl(&acb->pmuC->outbound_doorbell) & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) { in arcmsr_remap_pciregion()
344 if (readl(&reg->outbound_intstatus) & in arcmsr_hbaA_wait_msgint_ready()
362 if (readl(reg->iop2drv_doorbell) in arcmsr_hbaB_wait_msgint_ready()
382 if (readl(&phbcmu->outbound_doorbell) in arcmsr_hbaC_wait_msgint_ready()
400 if (readl(reg->outbound_doorbell) in arcmsr_hbaD_wait_msgint_ready()
603 if (readl(signature) != ARCMSR_SIGNATURE_GET_CONFIG) in arcmsr_message_isr_bh_fn()
1005 orig_mask = readl(&reg->outbound_intmask); in arcmsr_disable_outbound_ints()
1012 orig_mask = readl(reg->iop2drv_doorbell_mask); in arcmsr_disable_outbound_ints()
1019 orig_mask = readl(&reg->host_int_mask); /* disable outbound message0 int */ in arcmsr_disable_outbound_ints()
1128 outbound_intstatus = readl(&reg->outbound_intstatus) & in arcmsr_done4abort_postqueue()
[all …]
/linux-4.1.27/drivers/clk/keystone/
Dgate.c82 mdctl = readl(control_base + MDCTL); in psc_config()
90 pdstat = readl(domain_base + PDSTAT); in psc_config()
92 pdctl = readl(domain_base + PDCTL); in psc_config()
100 ptstat = readl(domain_transition_base + PTSTAT); in psc_config()
105 mdstat = readl(control_base + MDSTAT); in psc_config()
113 u32 mdstat = readl(data->control_base + MDSTAT); in keystone_clk_is_enabled()
/linux-4.1.27/arch/arm/mach-integrator/
Dintegrator_ap.c118 ic_irq_enable = readl(VA_IC_BASE + IRQ_ENABLE); in irq_suspend()
160 tmp = readl(ebi_base + INTEGRATOR_EBI_CSR1_OFFSET) | in ap_flash_init()
164 if (!(readl(ebi_base + INTEGRATOR_EBI_CSR1_OFFSET) in ap_flash_init()
180 tmp = readl(ebi_base + INTEGRATOR_EBI_CSR1_OFFSET) & in ap_flash_exit()
184 if (readl(ebi_base + INTEGRATOR_EBI_CSR1_OFFSET) & in ap_flash_exit()
309 sc_dec = readl(ap_syscon_base + INTEGRATOR_SC_DEC_OFFSET); in ap_init_of()
Dintegrator_cp.c117 val = readl(intcp_con_base + INTCP_FLASHPROG); in intcp_flash_init()
128 val = readl(intcp_con_base + INTCP_FLASHPROG); in intcp_flash_exit()
137 val = readl(intcp_con_base + INTCP_FLASHPROG); in intcp_flash_set_vpp()
160 unsigned int status = readl(__io_address(0xca000000 + 4)); in mmc_status()
228 return readl(REFCOUNTER); in intcp_read_sched_clock()
/linux-4.1.27/arch/mips/mti-sead3/
Dsead3-time.c32 orig = readl(status_reg) & 0x2; /* get original sample */ in estimate_cpu_frequency()
34 while ((readl(status_reg) & 0x2) == orig) in estimate_cpu_frequency()
43 while ((readl(status_reg) & 0x2) == orig) in estimate_cpu_frequency()
/linux-4.1.27/drivers/net/ethernet/amd/
Damd8111e.c119 reg_val = readl(mmio + PHY_ACCESS); in amd8111e_read_phy()
121 reg_val = readl( mmio + PHY_ACCESS ); in amd8111e_read_phy()
126 reg_val = readl(mmio + PHY_ACCESS); in amd8111e_read_phy()
148 reg_val = readl(mmio + PHY_ACCESS); in amd8111e_write_phy()
150 reg_val = readl( mmio + PHY_ACCESS ); in amd8111e_write_phy()
156 reg_val = readl(mmio + PHY_ACCESS); in amd8111e_write_phy()
450 reg_val = readl(mmio + CTRL1); in amd8111e_restart()
503 readl(mmio+CMD0); in amd8111e_restart()
547 reg_val = readl(mmio + INT0); in amd8111e_init_hw_default()
581 reg_val = readl(mmio + SRAM_SIZE); in amd8111e_init_hw_default()
[all …]
/linux-4.1.27/drivers/net/ethernet/
Dnetx-eth.c181 status = readl(NETX_PFIFO_XPEC_ISR(priv->id)); in netx_eth_interrupt()
191 readl(NETX_PFIFO_FILL_LEVEL(IND_FIFO_PORT_LO(priv->id))); in netx_eth_interrupt()
201 status = readl(NETX_PFIFO_XPEC_ISR(priv->id)); in netx_eth_interrupt()
282 while (readl(NETX_MIIMU) & MIIMU_SNRDY); in netx_eth_phy_read()
284 return readl(NETX_MIIMU) >> 16; in netx_eth_phy_read()
298 while (readl(NETX_MIIMU) & MIIMU_SNRDY); in netx_eth_phy_write()
339 mac4321 = readl(priv->xpec_base + in netx_eth_enable()
341 mac65 = readl(priv->xpec_base + in netx_eth_enable()
478 val = readl(NETX_SYSTEM_IOC_ACCESS_KEY); in netx_eth_init()
484 val = readl(NETX_SYSTEM_IOC_ACCESS_KEY); in netx_eth_init()
Dkorina.c151 if (readl(&ch->dmac) & DMA_CHAN_RUN_BIT) { in korina_abort_dma()
154 while (!(readl(&ch->dmas) & DMA_STAT_HALT)) in korina_abort_dma()
236 if (readl(&(lp->tx_dma_regs->dmandptr)) == 0) { in korina_send_packet()
304 ret = (int)(readl(&lp->eth_regs->miimrdd)); in mdio_read()
329 dmas = readl(&lp->rx_dma_regs->dmas); in korina_rx_dma_interrupt()
331 dmasm = readl(&lp->rx_dma_regs->dmasm); in korina_rx_dma_interrupt()
441 dmas = readl(&lp->rx_dma_regs->dmas); in korina_rx()
469 writel(readl(&lp->rx_dma_regs->dmasm) & in korina_poll()
592 dmas = readl(&lp->tx_dma_regs->dmas); in korina_tx()
595 writel(readl(&lp->tx_dma_regs->dmasm) & in korina_tx()
[all …]
/linux-4.1.27/drivers/clk/at91/
Dclk-slow.c79 u32 tmp = readl(sckcr); in clk_slow_osc_prepare()
95 u32 tmp = readl(sckcr); in clk_slow_osc_unprepare()
107 u32 tmp = readl(sckcr); in clk_slow_osc_is_prepared()
150 writel((readl(sckcr) & ~AT91_SCKC_OSC32EN) | AT91_SCKC_OSC32BYP, in at91_clk_register_slow_osc()
203 writel(readl(sckcr) | AT91_SCKC_RCEN, sckcr); in clk_slow_rc_osc_prepare()
215 writel(readl(sckcr) & ~AT91_SCKC_RCEN, sckcr); in clk_slow_rc_osc_unprepare()
222 return !!(readl(osc->sckcr) & AT91_SCKC_RCEN); in clk_slow_rc_osc_is_prepared()
301 tmp = readl(sckcr); in clk_sam9x5_slow_set_parent()
323 return !!(readl(slowck->sckcr) & AT91_SCKC_OSCSEL); in clk_sam9x5_slow_get_parent()
356 slowck->parent = !!(readl(sckcr) & AT91_SCKC_OSCSEL); in at91_clk_register_sam9x5_slow()
/linux-4.1.27/arch/cris/arch-v32/drivers/mach-a3/
Dgpio.c240 data = readl(data_in[priv->minor]); in gpio_poll()
312 unsigned long shadow = readl(port) & ~clk_mask; in gpio_write_bit()
488 dir_shadow = readl(dir_oe[priv->minor]) & in setget_input()
515 dir_shadow = readl(dir_oe[priv->minor]) | in setget_output()
551 return readl(data_in[priv->minor]); in gpio_ioctl_unlocked()
555 shadow = readl(data_out[priv->minor]) | in gpio_ioctl_unlocked()
563 shadow = readl(data_out[priv->minor]) & in gpio_ioctl_unlocked()
586 return readl(dir_oe[priv->minor]); in gpio_ioctl_unlocked()
613 dir_shadow = readl(dir_oe[priv->minor]); in gpio_ioctl_unlocked()
629 val = readl(data_in[priv->minor]); in gpio_ioctl_unlocked()
[all …]
/linux-4.1.27/drivers/bus/
Dmvebu-mbus.c180 u32 basereg = readl(addr + WIN_BASE_OFF); in mvebu_mbus_read_window()
181 u32 ctrlreg = readl(addr + WIN_CTRL_OFF); in mvebu_mbus_read_window()
204 remap_low = readl(addr_rmp + WIN_REMAP_LO_OFF); in mvebu_mbus_read_window()
205 remap_hi = readl(addr_rmp + WIN_REMAP_HI_OFF); in mvebu_mbus_read_window()
235 u32 ctrl = readl(addr + WIN_CTRL_OFF); in mvebu_mbus_window_is_free()
390 u32 basereg = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i)); in mvebu_sdram_debug_show_orion()
391 u32 sizereg = readl(mbus->sdramwins_base + DDR_SIZE_CS_OFF(i)); in mvebu_sdram_debug_show_orion()
420 u32 map = readl(mbus->sdramwins_base + DOVE_DDR_BASE_CS_OFF(i)); in mvebu_sdram_debug_show_dove()
588 u32 base = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i)); in mvebu_mbus_default_setup_cpu_target()
589 u32 size = readl(mbus->sdramwins_base + DDR_SIZE_CS_OFF(i)); in mvebu_mbus_default_setup_cpu_target()
[all …]
/linux-4.1.27/drivers/video/fbdev/
Dcobalt_lcdfb.c74 return readl(info->screen_base) >> 24; in lcd_read_control()
84 return readl(info->screen_base + LCD_DATA_REG_OFFSET) >> 24; in lcd_read_data()
96 } while (readl(info->screen_base + CPLD_STATUS) & 1); in cpld_wait()
108 readl(info->screen_base + LCD_CTL); in lcd_read_control()
110 return readl(info->screen_base + CPLD_DATA) & 0xff; in lcd_read_control()
122 readl(info->screen_base + LCD_DATA); in lcd_read_data()
124 return readl(info->screen_base + CPLD_DATA) & 0xff; in lcd_read_data()
/linux-4.1.27/drivers/thermal/samsung/
Dexynos_tmu.c393 sanitize_temp_error(data, readl(data->base + EXYNOS_TMU_REG_TRIMINFO)); in exynos4210_tmu_initialize()
434 ctrl = readl(data->base + EXYNOS_TMU_TRIMINFO_CON1); in exynos4412_tmu_initialize()
438 ctrl = readl(data->base + EXYNOS_TMU_TRIMINFO_CON2); in exynos4412_tmu_initialize()
445 trim_info = readl(data->base_second + EXYNOS_TMU_REG_TRIMINFO); in exynos4412_tmu_initialize()
447 trim_info = readl(data->base + EXYNOS_TMU_REG_TRIMINFO); in exynos4412_tmu_initialize()
452 rising_threshold = readl(data->base + EXYNOS_THD_TEMP_RISE); in exynos4412_tmu_initialize()
479 con = readl(data->base + EXYNOS_TMU_REG_CONTROL); in exynos4412_tmu_initialize()
500 trim_info = readl(data->base + EXYNOS5440_EFUSE_SWAP_OFFSET + in exynos5440_tmu_initialize()
504 trim_info = readl(data->base + EXYNOS5440_TMU_S0_7_TRIM); in exynos5440_tmu_initialize()
507 trim_info = readl(data->base - EXYNOS5440_EFUSE_SWAP_OFFSET + in exynos5440_tmu_initialize()
[all …]
/linux-4.1.27/drivers/misc/
Dspear13xx_pcie_gadget.c72 writel(readl(&app_reg->slv_armisc) | (1 << AXI_OP_DBI_ACCESS_ID), in enable_dbi_access()
74 writel(readl(&app_reg->slv_awmisc) | (1 << AXI_OP_DBI_ACCESS_ID), in enable_dbi_access()
82 writel(readl(&app_reg->slv_armisc) & ~(1 << AXI_OP_DBI_ACCESS_ID), in disable_dbi_access()
84 writel(readl(&app_reg->slv_awmisc) & ~(1 << AXI_OP_DBI_ACCESS_ID), in disable_dbi_access()
100 *val = readl(va_address); in spear_dbi_read_reg()
229 if (readl(&app_reg->app_status_1) & ((u32)1 << XMLH_LINK_UP_ID)) in pcie_gadget_show_link()
242 writel(readl(&app_reg->app_ctrl_0) | (1 << APP_LTSSM_ENABLE_ID), in pcie_gadget_store_link()
245 writel(readl(&app_reg->app_ctrl_0) in pcie_gadget_store_link()
299 if ((readl(&app_reg->msg_status) & (1 << CFG_MSI_EN_ID)) in pcie_gadget_show_no_of_msi()
345 writel(readl(&app_reg->app_ctrl_0) | (1 << SYS_INT_ID), in pcie_gadget_store_inta()
[all …]
Dtifm_7xx1.c47 irq_status = readl(fm->addr + FM_INTERRUPT_STATUS); in tifm_7xx1_isr()
91 & readl(sock_addr + SOCK_PRESENT_STATE))) in tifm_7xx1_toggle_sock_power()
97 s_state = readl(sock_addr + SOCK_PRESENT_STATE); in tifm_7xx1_toggle_sock_power()
101 writel(readl(sock_addr + SOCK_CONTROL) | TIFM_CTRL_LED, in tifm_7xx1_toggle_sock_power()
105 if (((readl(sock_addr + SOCK_PRESENT_STATE) >> 4) & 7) in tifm_7xx1_toggle_sock_power()
115 & readl(sock_addr + SOCK_PRESENT_STATE))) in tifm_7xx1_toggle_sock_power()
121 writel(readl(sock_addr + SOCK_CONTROL) & (~TIFM_CTRL_LED), in tifm_7xx1_toggle_sock_power()
124 return (readl(sock_addr + SOCK_PRESENT_STATE) >> 4) & 7; in tifm_7xx1_toggle_sock_power()
129 writel((~TIFM_CTRL_POWER_MASK) & readl(sock_addr + SOCK_CONTROL), in tifm_7xx1_sock_power_off()
/linux-4.1.27/arch/arm/mach-gemini/
Dtime.c45 cr = readl(TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE))); in gemini_timer_set_next_event()
75 cr = readl(TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE))); in gemini_timer_set_mode()
88 cr = readl(TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE))); in gemini_timer_set_mode()
131 reg_v = readl(IO_ADDRESS(GEMINI_GLOBAL_BASE + GLOBAL_STATUS)); in gemini_timer_init()
/linux-4.1.27/drivers/video/fbdev/savage/
Dsavagefb-i2c.c50 r = readl(chan->ioaddr + chan->reg); in savage4_gpio_setscl()
56 readl(chan->ioaddr + chan->reg); /* flush posted write */ in savage4_gpio_setscl()
64 r = readl(chan->ioaddr + chan->reg); in savage4_gpio_setsda()
70 readl(chan->ioaddr + chan->reg); /* flush posted write */ in savage4_gpio_setsda()
77 return (0 != (readl(chan->ioaddr + chan->reg) & SAVAGE4_I2C_SCL_IN)); in savage4_gpio_getscl()
84 return (0 != (readl(chan->ioaddr + chan->reg) & SAVAGE4_I2C_SDA_IN)); in savage4_gpio_getsda()

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