872 	(void) readl(addr);	/* flush to avoid PCI posted write */  in writelfl()
960 	pp->cached.fiscfg = readl(port_mmio + FISCFG);  in mv_save_cached_regs()
961 	pp->cached.ltmode = readl(port_mmio + LTMODE);  in mv_save_cached_regs()
962 	pp->cached.haltcond = readl(port_mmio + EDMA_HALTCOND);  in mv_save_cached_regs()
963 	pp->cached.unknown_rsvd = readl(port_mmio + EDMA_UNKNOWN_RSVD);  in mv_save_cached_regs()
1211 		u32 edma_stat = readl(port_mmio + EDMA_STATUS);  in mv_wait_for_edma_empty_idle()
1235 		u32 reg = readl(port_mmio + EDMA_CMD);  in mv_stop_edma_engine()
1268 			printk("%08x ", readl(start + b));  in mv_dump_mem()
1363 		*val = readl(mv_ap_base(link->ap) + ofs);  in mv_scr_read()
1390 			if ((val & 0xf) == 1 || (readl(addr) & 0xf) == 1)  in mv_scr_write()
1526 	old = readl(hpriv->base + GPIO_PORT_CTL);  in mv_60x1_errata_sata25()
1584 	led_ctrl = readl(hc_mmio + SOC_LED_CTRL);  in mv_soc_led_blink_enable()
1610 	led_ctrl = readl(hc_mmio + SOC_LED_CTRL);  in mv_soc_led_blink_disable()
1950 	cmd = readl(port_mmio + BMDMA_CMD);  in mv_bmdma_stop_ap()
1983 	reg = readl(port_mmio + BMDMA_STATUS);  in mv_bmdma_status()
2247 	old_ifctl = readl(port_mmio + SATA_IFCTL);  in mv_send_fis()
2264 		ifstat = readl(port_mmio + SATA_IFSTAT);  in mv_send_fis()
2478 	return readl(port_mmio + SATA_TESTCTL) >> 16;  in mv_get_err_pmp_map()
2511 	in_ptr  = (readl(port_mmio + EDMA_REQ_Q_IN_PTR)  in mv_req_q_empty()
2513 	out_ptr = (readl(port_mmio + EDMA_REQ_Q_OUT_PTR)  in mv_req_q_empty()
2671 	edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE);  in mv_err_intr()
2673 		fis_cause = readl(port_mmio + FIS_IRQ_CAUSE);  in mv_err_intr()
2824 	in_index = (readl(port_mmio + EDMA_RSP_Q_IN_PTR)  in mv_process_crpb_entries()
2972 	err_cause = readl(mmio + hpriv->irq_cause_offset);  in mv_pci_error()
3031 	main_irq_cause = readl(hpriv->main_irq_cause_addr);  in mv_interrupt()
3078 		*val = readl(addr + ofs);  in mv5_scr_read()
3106 		u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);  in mv5_reset_bus()
3125 	tmp = readl(phy_mmio + MV5_PHY_MODE);  in mv5_read_preamp()
3139 	tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);  in mv5_enable_leds()
3153 		tmp = readl(phy_mmio + MV5_LTMODE);  in mv5_phy_errata()
3157 		tmp = readl(phy_mmio + MV5_PHY_CTL);  in mv5_phy_errata()
3163 	tmp = readl(phy_mmio + MV5_PHY_MODE);  in mv5_phy_errata()
3208 	tmp = readl(hc_mmio + 0x20);  in mv5_reset_one_hc()
3238 	tmp = readl(mmio + MV_PCI_MODE);  in mv_reset_pci_bus()
3261 	tmp = readl(mmio + GPIO_PORT_CTL);  in mv6_reset_flash()
3286 	t = readl(reg);  in mv6_reset_hc()
3291 		t = readl(reg);  in mv6_reset_hc()
3305 		t = readl(reg);  in mv6_reset_hc()
3319 		t = readl(reg);  in mv6_reset_hc()
3337 	tmp = readl(mmio + RESET_CFG);  in mv6_read_preamp()
3345 	tmp = readl(port_mmio + PHY_MODE2);  in mv6_read_preamp()
3369 		m2 = readl(port_mmio + PHY_MODE2);  in mv6_phy_errata()
3376 		m2 = readl(port_mmio + PHY_MODE2);  in mv6_phy_errata()
3387 	m3 = readl(port_mmio + PHY_MODE3);  in mv6_phy_errata()
3395 		u32 m4 = readl(port_mmio + PHY_MODE4);  in mv6_phy_errata()
3416 	m2 = readl(port_mmio + PHY_MODE2);  in mv6_phy_errata()
3447 	tmp = readl(port_mmio + PHY_MODE2);  in mv_soc_read_preamp()
3523 	reg = readl(port_mmio + PHY_MODE3);  in mv_soc_65n_phy_errata()
3530 	reg = readl(port_mmio + PHY_MODE4);  in mv_soc_65n_phy_errata()
3535 	reg = readl(port_mmio + PHY_MODE9_GEN2);  in mv_soc_65n_phy_errata()
3541 	reg = readl(port_mmio + PHY_MODE9_GEN1);  in mv_soc_65n_phy_errata()
3559 	if (readl(port0_mmio + PHYCFG_OFS))  in soc_is_65n()
3566 	u32 ifcfg = readl(port_mmio + SATA_IFCFG);  in mv_setup_ifcfg()
3610 		u32 reg = readl(port_mmio + SATA_IFCTL);  in mv_pmp_select()
3732 	writelfl(readl(serr), serr);  in mv_port_init()
3739 		readl(port_mmio + EDMA_CFG),  in mv_port_init()
3740 		readl(port_mmio + EDMA_ERR_IRQ_CAUSE),  in mv_port_init()
3741 		readl(port_mmio + EDMA_ERR_IRQ_MASK));  in mv_port_init()
3752 	reg = readl(mmio + MV_PCI_MODE);  in mv_in_pcix_mode()
3765 		reg = readl(mmio + MV_PCI_COMMAND);  in mv_pci_cut_through_okay()
3779 		u32 reg = readl(mmio + MV_PCI_COMMAND);  in mv_60x1b2_errata_pci7()
3957 	hpriv->main_irq_mask = readl(hpriv->main_irq_mask_addr);  in mv_init_host()
3988 			readl(hc_mmio + HC_CFG),  in mv_init_host()
3989 			readl(hc_mmio + HC_IRQ_CAUSE));  in mv_init_host()