1/* 2 * Copyright 2011-2012 Calxeda, Inc. 3 * Copyright (C) 2012-2013 Altera Corporation <www.altera.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * Based from clk-highbank.c 16 * 17 */ 18#include <linux/clk.h> 19#include <linux/clkdev.h> 20#include <linux/clk-provider.h> 21#include <linux/io.h> 22#include <linux/mfd/syscon.h> 23#include <linux/of.h> 24#include <linux/regmap.h> 25 26#include "clk.h" 27 28#define SOCFPGA_L4_MP_CLK "l4_mp_clk" 29#define SOCFPGA_L4_SP_CLK "l4_sp_clk" 30#define SOCFPGA_NAND_CLK "nand_clk" 31#define SOCFPGA_NAND_X_CLK "nand_x_clk" 32#define SOCFPGA_MMC_CLK "sdmmc_clk" 33#define SOCFPGA_GPIO_DB_CLK_OFFSET 0xA8 34 35#define streq(a, b) (strcmp((a), (b)) == 0) 36 37#define to_socfpga_gate_clk(p) container_of(p, struct socfpga_gate_clk, hw.hw) 38 39/* SDMMC Group for System Manager defines */ 40#define SYSMGR_SDMMCGRP_CTRL_OFFSET 0x108 41#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \ 42 ((((smplsel) & 0x7) << 3) | (((drvsel) & 0x7) << 0)) 43 44static u8 socfpga_clk_get_parent(struct clk_hw *hwclk) 45{ 46 u32 l4_src; 47 u32 perpll_src; 48 49 if (streq(hwclk->init->name, SOCFPGA_L4_MP_CLK)) { 50 l4_src = readl(clk_mgr_base_addr + CLKMGR_L4SRC); 51 return l4_src &= 0x1; 52 } 53 if (streq(hwclk->init->name, SOCFPGA_L4_SP_CLK)) { 54 l4_src = readl(clk_mgr_base_addr + CLKMGR_L4SRC); 55 return !!(l4_src & 2); 56 } 57 58 perpll_src = readl(clk_mgr_base_addr + CLKMGR_PERPLL_SRC); 59 if (streq(hwclk->init->name, SOCFPGA_MMC_CLK)) 60 return perpll_src &= 0x3; 61 if (streq(hwclk->init->name, SOCFPGA_NAND_CLK) || 62 streq(hwclk->init->name, SOCFPGA_NAND_X_CLK)) 63 return (perpll_src >> 2) & 3; 64 65 /* QSPI clock */ 66 return (perpll_src >> 4) & 3; 67 68} 69 70static int socfpga_clk_set_parent(struct clk_hw *hwclk, u8 parent) 71{ 72 u32 src_reg; 73 74 if (streq(hwclk->init->name, SOCFPGA_L4_MP_CLK)) { 75 src_reg = readl(clk_mgr_base_addr + CLKMGR_L4SRC); 76 src_reg &= ~0x1; 77 src_reg |= parent; 78 writel(src_reg, clk_mgr_base_addr + CLKMGR_L4SRC); 79 } else if (streq(hwclk->init->name, SOCFPGA_L4_SP_CLK)) { 80 src_reg = readl(clk_mgr_base_addr + CLKMGR_L4SRC); 81 src_reg &= ~0x2; 82 src_reg |= (parent << 1); 83 writel(src_reg, clk_mgr_base_addr + CLKMGR_L4SRC); 84 } else { 85 src_reg = readl(clk_mgr_base_addr + CLKMGR_PERPLL_SRC); 86 if (streq(hwclk->init->name, SOCFPGA_MMC_CLK)) { 87 src_reg &= ~0x3; 88 src_reg |= parent; 89 } else if (streq(hwclk->init->name, SOCFPGA_NAND_CLK) || 90 streq(hwclk->init->name, SOCFPGA_NAND_X_CLK)) { 91 src_reg &= ~0xC; 92 src_reg |= (parent << 2); 93 } else {/* QSPI clock */ 94 src_reg &= ~0x30; 95 src_reg |= (parent << 4); 96 } 97 writel(src_reg, clk_mgr_base_addr + CLKMGR_PERPLL_SRC); 98 } 99 100 return 0; 101} 102 103static unsigned long socfpga_clk_recalc_rate(struct clk_hw *hwclk, 104 unsigned long parent_rate) 105{ 106 struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk); 107 u32 div = 1, val; 108 109 if (socfpgaclk->fixed_div) 110 div = socfpgaclk->fixed_div; 111 else if (socfpgaclk->div_reg) { 112 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; 113 val &= div_mask(socfpgaclk->width); 114 /* Check for GPIO_DB_CLK by its offset */ 115 if ((int) socfpgaclk->div_reg & SOCFPGA_GPIO_DB_CLK_OFFSET) 116 div = val + 1; 117 else 118 div = (1 << val); 119 } 120 121 return parent_rate / div; 122} 123 124static int socfpga_clk_prepare(struct clk_hw *hwclk) 125{ 126 struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk); 127 struct regmap *sys_mgr_base_addr; 128 int i; 129 u32 hs_timing; 130 u32 clk_phase[2]; 131 132 if (socfpgaclk->clk_phase[0] || socfpgaclk->clk_phase[1]) { 133 sys_mgr_base_addr = syscon_regmap_lookup_by_compatible("altr,sys-mgr"); 134 if (IS_ERR(sys_mgr_base_addr)) { 135 pr_err("%s: failed to find altr,sys-mgr regmap!\n", __func__); 136 return -EINVAL; 137 } 138 139 for (i = 0; i < 2; i++) { 140 switch (socfpgaclk->clk_phase[i]) { 141 case 0: 142 clk_phase[i] = 0; 143 break; 144 case 45: 145 clk_phase[i] = 1; 146 break; 147 case 90: 148 clk_phase[i] = 2; 149 break; 150 case 135: 151 clk_phase[i] = 3; 152 break; 153 case 180: 154 clk_phase[i] = 4; 155 break; 156 case 225: 157 clk_phase[i] = 5; 158 break; 159 case 270: 160 clk_phase[i] = 6; 161 break; 162 case 315: 163 clk_phase[i] = 7; 164 break; 165 default: 166 clk_phase[i] = 0; 167 break; 168 } 169 } 170 hs_timing = SYSMGR_SDMMC_CTRL_SET(clk_phase[0], clk_phase[1]); 171 regmap_write(sys_mgr_base_addr, SYSMGR_SDMMCGRP_CTRL_OFFSET, 172 hs_timing); 173 } 174 return 0; 175} 176 177static struct clk_ops gateclk_ops = { 178 .prepare = socfpga_clk_prepare, 179 .recalc_rate = socfpga_clk_recalc_rate, 180 .get_parent = socfpga_clk_get_parent, 181 .set_parent = socfpga_clk_set_parent, 182}; 183 184static void __init __socfpga_gate_init(struct device_node *node, 185 const struct clk_ops *ops) 186{ 187 u32 clk_gate[2]; 188 u32 div_reg[3]; 189 u32 clk_phase[2]; 190 u32 fixed_div; 191 struct clk *clk; 192 struct socfpga_gate_clk *socfpga_clk; 193 const char *clk_name = node->name; 194 const char *parent_name[SOCFPGA_MAX_PARENTS]; 195 struct clk_init_data init; 196 int rc; 197 int i = 0; 198 199 socfpga_clk = kzalloc(sizeof(*socfpga_clk), GFP_KERNEL); 200 if (WARN_ON(!socfpga_clk)) 201 return; 202 203 rc = of_property_read_u32_array(node, "clk-gate", clk_gate, 2); 204 if (rc) 205 clk_gate[0] = 0; 206 207 if (clk_gate[0]) { 208 socfpga_clk->hw.reg = clk_mgr_base_addr + clk_gate[0]; 209 socfpga_clk->hw.bit_idx = clk_gate[1]; 210 211 gateclk_ops.enable = clk_gate_ops.enable; 212 gateclk_ops.disable = clk_gate_ops.disable; 213 } 214 215 rc = of_property_read_u32(node, "fixed-divider", &fixed_div); 216 if (rc) 217 socfpga_clk->fixed_div = 0; 218 else 219 socfpga_clk->fixed_div = fixed_div; 220 221 rc = of_property_read_u32_array(node, "div-reg", div_reg, 3); 222 if (!rc) { 223 socfpga_clk->div_reg = clk_mgr_base_addr + div_reg[0]; 224 socfpga_clk->shift = div_reg[1]; 225 socfpga_clk->width = div_reg[2]; 226 } else { 227 socfpga_clk->div_reg = 0; 228 } 229 230 rc = of_property_read_u32_array(node, "clk-phase", clk_phase, 2); 231 if (!rc) { 232 socfpga_clk->clk_phase[0] = clk_phase[0]; 233 socfpga_clk->clk_phase[1] = clk_phase[1]; 234 } 235 236 of_property_read_string(node, "clock-output-names", &clk_name); 237 238 init.name = clk_name; 239 init.ops = ops; 240 init.flags = 0; 241 while (i < SOCFPGA_MAX_PARENTS && (parent_name[i] = 242 of_clk_get_parent_name(node, i)) != NULL) 243 i++; 244 245 init.parent_names = parent_name; 246 init.num_parents = i; 247 socfpga_clk->hw.hw.init = &init; 248 249 clk = clk_register(NULL, &socfpga_clk->hw.hw); 250 if (WARN_ON(IS_ERR(clk))) { 251 kfree(socfpga_clk); 252 return; 253 } 254 rc = of_clk_add_provider(node, of_clk_src_simple_get, clk); 255 if (WARN_ON(rc)) 256 return; 257} 258 259void __init socfpga_gate_init(struct device_node *node) 260{ 261 __socfpga_gate_init(node, &gateclk_ops); 262} 263