212 		val = readl(base + TEGRA_USB_HOSTPC1_DEVLC);  in set_pts()
217 		val = readl(base + TEGRA_USB_PORTSC1) & ~TEGRA_PORTSC1_RWC_BITS;  in set_pts()
230 		val = readl(base + TEGRA_USB_HOSTPC1_DEVLC);  in set_phcd()
237 		val = readl(base + TEGRA_USB_PORTSC1) & ~PORT_RWC_BITS;  in set_phcd()
268 		val = readl(base + UTMIP_BIAS_CFG0);  in utmip_pad_power_on()
303 		val = readl(base + UTMIP_BIAS_CFG0);  in utmip_pad_power_off()
319 		if ((readl(reg) & mask) == result)  in utmi_wait_register()
333 		val = readl(base + USB_SUSP_CTRL);  in utmi_phy_clk_disable()
339 		val = readl(base + USB_SUSP_CTRL);  in utmi_phy_clk_disable()
355 		val = readl(base + USB_SUSP_CTRL);  in utmi_phy_clk_enable()
361 		val = readl(base + USB_SUSP_CTRL);  in utmi_phy_clk_enable()
378 	val = readl(base + USB_SUSP_CTRL);  in utmi_phy_power_on()
383 		val = readl(base + USB1_LEGACY_CTRL);  in utmi_phy_power_on()
388 	val = readl(base + UTMIP_TX_CFG0);  in utmi_phy_power_on()
392 	val = readl(base + UTMIP_HSRX_CFG0);  in utmi_phy_power_on()
398 	val = readl(base + UTMIP_HSRX_CFG1);  in utmi_phy_power_on()
403 	val = readl(base + UTMIP_DEBOUNCE_CFG0);  in utmi_phy_power_on()
408 	val = readl(base + UTMIP_MISC_CFG0);  in utmi_phy_power_on()
413 		val = readl(base + UTMIP_MISC_CFG1);  in utmi_phy_power_on()
420 		val = readl(base + UTMIP_PLL_CFG1);  in utmi_phy_power_on()
429 		val = readl(base + USB_SUSP_CTRL);  in utmi_phy_power_on()
433 		val = readl(base + UTMIP_BAT_CHRG_CFG0);  in utmi_phy_power_on()
437 		val = readl(base + UTMIP_BAT_CHRG_CFG0);  in utmi_phy_power_on()
444 	val = readl(base + UTMIP_XCVR_CFG0);  in utmi_phy_power_on()
464 	val = readl(base + UTMIP_XCVR_CFG1);  in utmi_phy_power_on()
470 	val = readl(base + UTMIP_BIAS_CFG1);  in utmi_phy_power_on()
475 	val = readl(base + UTMIP_SPARE_CFG0);  in utmi_phy_power_on()
483 		val = readl(base + USB_SUSP_CTRL);  in utmi_phy_power_on()
488 	val = readl(base + USB_SUSP_CTRL);  in utmi_phy_power_on()
493 		val = readl(base + USB1_LEGACY_CTRL);  in utmi_phy_power_on()
498 		val = readl(base + USB_SUSP_CTRL);  in utmi_phy_power_on()
506 		val = readl(base + USB_USBMODE);  in utmi_phy_power_on()
529 		val = readl(base + USB_SUSP_CTRL);  in utmi_phy_power_off()
535 	val = readl(base + USB_SUSP_CTRL);  in utmi_phy_power_off()
539 	val = readl(base + UTMIP_BAT_CHRG_CFG0);  in utmi_phy_power_off()
543 	val = readl(base + UTMIP_XCVR_CFG0);  in utmi_phy_power_off()
548 	val = readl(base + UTMIP_XCVR_CFG1);  in utmi_phy_power_off()
561 	val = readl(base + UTMIP_TX_CFG0);  in utmi_phy_preresume()
571 	val = readl(base + UTMIP_TX_CFG0);  in utmi_phy_postresume()
582 	val = readl(base + UTMIP_MISC_CFG0);  in utmi_phy_restore_start()
591 	val = readl(base + UTMIP_MISC_CFG0);  in utmi_phy_restore_start()
602 	val = readl(base + UTMIP_MISC_CFG0);  in utmi_phy_restore_end()
631 	val = readl(base + USB_SUSP_CTRL);  in ulpi_phy_power_on()
635 	val = readl(base + ULPI_TIMING_CTRL_0);  in ulpi_phy_power_on()
639 	val = readl(base + USB_SUSP_CTRL);  in ulpi_phy_power_on()
670 	val = readl(base + USB_SUSP_CTRL);  in ulpi_phy_power_on()
675 	val = readl(base + USB_SUSP_CTRL);  in ulpi_phy_power_on()