160 	val = readl(pctrl->regs + g->ctl_reg);  in msm_pinmux_set_mux()
236 	val = readl(pctrl->regs + g->ctl_reg);  in msm_config_group_get()
261 		val = readl(pctrl->regs + g->io_reg);  in msm_config_group_get()
329 			val = readl(pctrl->regs + g->io_reg);  in msm_config_group_set()
357 		val = readl(pctrl->regs + g->ctl_reg);  in msm_config_group_set()
391 	val = readl(pctrl->regs + g->ctl_reg);  in msm_gpio_direction_input()
411 	val = readl(pctrl->regs + g->io_reg);  in msm_gpio_direction_output()
418 	val = readl(pctrl->regs + g->ctl_reg);  in msm_gpio_direction_output()
435 	val = readl(pctrl->regs + g->io_reg);  in msm_gpio_get()
450 	val = readl(pctrl->regs + g->io_reg);  in msm_gpio_set()
497 	ctl_reg = readl(pctrl->regs + g->ctl_reg);  in msm_gpio_dbg_show_one()
563 		val = readl(pctrl->regs + g->io_reg) & BIT(g->in_bit);  in msm_gpio_update_dual_edge_pos()
565 		pol = readl(pctrl->regs + g->intr_cfg_reg);  in msm_gpio_update_dual_edge_pos()
569 		val2 = readl(pctrl->regs + g->io_reg) & BIT(g->in_bit);  in msm_gpio_update_dual_edge_pos()
570 		intstat = readl(pctrl->regs + g->intr_status_reg);  in msm_gpio_update_dual_edge_pos()
590 	val = readl(pctrl->regs + g->intr_cfg_reg);  in msm_gpio_irq_mask()
611 	val = readl(pctrl->regs + g->intr_status_reg);  in msm_gpio_irq_unmask()
615 	val = readl(pctrl->regs + g->intr_cfg_reg);  in msm_gpio_irq_unmask()
636 	val = readl(pctrl->regs + g->intr_status_reg);  in msm_gpio_irq_ack()
670 	val = readl(pctrl->regs + g->intr_target_reg);  in msm_gpio_irq_set_type()
680 	val = readl(pctrl->regs + g->intr_cfg_reg);  in msm_gpio_irq_set_type()
786 		val = readl(pctrl->regs + g->intr_status_reg);  in msm_gpio_irq_handler()