Lines Matching refs:readl
72 writel(readl(&app_reg->slv_armisc) | (1 << AXI_OP_DBI_ACCESS_ID), in enable_dbi_access()
74 writel(readl(&app_reg->slv_awmisc) | (1 << AXI_OP_DBI_ACCESS_ID), in enable_dbi_access()
82 writel(readl(&app_reg->slv_armisc) & ~(1 << AXI_OP_DBI_ACCESS_ID), in disable_dbi_access()
84 writel(readl(&app_reg->slv_awmisc) & ~(1 << AXI_OP_DBI_ACCESS_ID), in disable_dbi_access()
100 *val = readl(va_address); in spear_dbi_read_reg()
229 if (readl(&app_reg->app_status_1) & ((u32)1 << XMLH_LINK_UP_ID)) in pcie_gadget_show_link()
242 writel(readl(&app_reg->app_ctrl_0) | (1 << APP_LTSSM_ENABLE_ID), in pcie_gadget_store_link()
245 writel(readl(&app_reg->app_ctrl_0) in pcie_gadget_store_link()
299 if ((readl(&app_reg->msg_status) & (1 << CFG_MSI_EN_ID)) in pcie_gadget_show_no_of_msi()
345 writel(readl(&app_reg->app_ctrl_0) | (1 << SYS_INT_ID), in pcie_gadget_store_inta()
348 writel(readl(&app_reg->app_ctrl_0) & ~(1 << SYS_INT_ID), in pcie_gadget_store_inta()
373 ven_msi = readl(&app_reg->ven_msi_1); in pcie_gadget_store_send_msi()
498 u32 address = readl(&app_reg->pim0_mem_addr_start); in pcie_gadget_show_bar0_address()
562 data = readl((ulong)config->va_bar0_address + config->bar0_rw_offset); in pcie_gadget_show_bar0_data()