102 	readl(ctx->csr_diag + CFG_MEM_RAM_SHUTDOWN); /* Force a barrier */  in xgene_ahci_init_memram()
104 	if (readl(ctx->csr_diag + BLOCK_MEM_RDY) != 0xFFFFFFFF) {  in xgene_ahci_init_memram()
170 		fbs = readl(port_mmio + PORT_FBS);  in xgene_ahci_restart_engine()
172 		fbs = readl(port_mmio + PORT_FBS);  in xgene_ahci_restart_engine()
210 		port_fbs = readl(port_mmio + PORT_FBS);  in xgene_ahci_qc_issue()
233 	return (readl(diagcsr + CFG_MEM_RAM_SHUTDOWN) == 0 &&  in xgene_ahci_is_memram_inited()
234 	        readl(diagcsr + BLOCK_MEM_RDY) == 0xFFFFFFFF);  in xgene_ahci_is_memram_inited()
281 	val = readl(mmio + PORTCFG);  in xgene_ahci_set_phy_cfg()
284 	readl(mmio + PORTCFG);  /* Force a barrier */  in xgene_ahci_set_phy_cfg()
287 	readl(mmio + PORTPHY1CFG); /* Force a barrier */  in xgene_ahci_set_phy_cfg()
289 	readl(mmio + PORTPHY2CFG); /* Force a barrier */  in xgene_ahci_set_phy_cfg()
291 	readl(mmio + PORTPHY3CFG); /* Force a barrier */  in xgene_ahci_set_phy_cfg()
293 	readl(mmio + PORTPHY4CFG); /* Force a barrier */  in xgene_ahci_set_phy_cfg()
295 	val = readl(mmio + PORTPHY5CFG);  in xgene_ahci_set_phy_cfg()
298 	readl(mmio + PORTPHY5CFG); /* Force a barrier */  in xgene_ahci_set_phy_cfg()
299 	val = readl(mmio + PORTAXICFG);  in xgene_ahci_set_phy_cfg()
303 	readl(mmio + PORTAXICFG); /* Force a barrier */  in xgene_ahci_set_phy_cfg()
305 	val = readl(mmio + PORTRANSCFG);  in xgene_ahci_set_phy_cfg()
380 			val = readl(port_mmio + PORT_SCR_ERR);  in xgene_ahci_do_hardreset()
391 	val = readl(port_mmio + PORT_SCR_ERR);  in xgene_ahci_do_hardreset()
412 	portcmd_saved = readl(port_mmio + PORT_CMD);  in xgene_ahci_hardreset()
413 	portclb_saved = readl(port_mmio + PORT_LST_ADDR);  in xgene_ahci_hardreset()
414 	portclbhi_saved = readl(port_mmio + PORT_LST_ADDR_HI);  in xgene_ahci_hardreset()
415 	portrxfis_saved = readl(port_mmio + PORT_FIS_ADDR);  in xgene_ahci_hardreset()
416 	portrxfishi_saved = readl(port_mmio + PORT_FIS_ADDR_HI);  in xgene_ahci_hardreset()
471 	port_fbs = readl(port_mmio + PORT_FBS);  in xgene_ahci_pmp_softreset()
515 	port_fbs_save = readl(port_mmio + PORT_FBS);  in xgene_ahci_softreset()
521 	port_fbs = readl(port_mmio + PORT_FBS);  in xgene_ahci_softreset()
579 	readl(hpriv->mmio + HOST_IRQ_STAT); /* Force a barrier */  in xgene_ahci_hw_init()
581 	val = readl(ctx->csr_core + INTSTATUSMASK); /* Force a barrier */  in xgene_ahci_hw_init()
586 	readl(ctx->csr_core + ERRINTSTATUSMASK); /* Force a barrier */  in xgene_ahci_hw_init()
588 	readl(ctx->csr_axi + INT_SLV_TMOMASK);  in xgene_ahci_hw_init()
597 	val = readl(ctx->csr_core + BUSCTLREG);  in xgene_ahci_hw_init()
602 	val = readl(ctx->csr_core + IOFMSTRWAUX);  in xgene_ahci_hw_init()
606 	val = readl(ctx->csr_core + IOFMSTRWAUX);  in xgene_ahci_hw_init()
621 	val = readl(ctx->csr_mux + SATA_ENET_CONFIG_REG);  in xgene_ahci_mux_select()
624 	val = readl(ctx->csr_mux + SATA_ENET_CONFIG_REG);  in xgene_ahci_mux_select()