711 	readl(ns_ioaddr(dev) + IntrEnable);  in natsemi_irq_enable()
717 	readl(ns_ioaddr(dev) + IntrEnable);  in natsemi_irq_disable()
894 	if (np->ignore_phy || readl(ioaddr + ChipConfig) & CfgExtPhy)  in natsemi_probe1()
938 	np->srr = readl(ioaddr + SiliconRev);  in natsemi_probe1()
990 #define eeprom_delay(ee_addr)	readl(ee_addr)
1023 		retval |= (readl(ee_addr) & EE_DataOut) ? 1 << i : 0;  in eeprom_read()
1043 #define mii_delay(ioaddr)  readl(ioaddr + EECtrl)
1051 	data = readl(ioaddr + EECtrl);  in mii_getbit()
1175 	readl(ioaddr + ChipConfig);  in init_phy_fixup()
1197 	cfg = readl(ioaddr + ChipConfig);  in init_phy_fixup()
1223 		readl(ioaddr + ChipConfig);  in init_phy_fixup()
1259 	cfg = readl(ioaddr + ChipConfig);  in switch_port_external()
1270 	readl(ioaddr + ChipConfig);  in switch_port_external()
1294 	cfg = readl(ioaddr + ChipConfig);  in switch_port_internal()
1305 	readl(ioaddr + ChipConfig);  in switch_port_internal()
1311 	readl(ioaddr + ChipConfig);  in switch_port_internal()
1401 	cfg = readl(ioaddr + ChipConfig) & CFG_RESET_SAVE;  in natsemi_reset()
1403 	wcsr = readl(ioaddr + WOLCmd) & WCSR_RESET_SAVE;  in natsemi_reset()
1405 	rfcr = readl(ioaddr + RxFilterAddr) & RFCR_RESET_SAVE;  in natsemi_reset()
1420 		if (!(readl(ioaddr + ChipCmd) & ChipReset))  in natsemi_reset()
1433 	cfg |= readl(ioaddr + ChipConfig) & ~CFG_RESET_SAVE;  in natsemi_reset()
1441 	wcsr |= readl(ioaddr + WOLCmd) & ~WCSR_RESET_SAVE;  in natsemi_reset()
1444 	rfcr |= readl(ioaddr + RxFilterAddr) & ~RFCR_RESET_SAVE;  in natsemi_reset()
1469 		np->intr_status |= readl(ioaddr + IntrStatus);  in reset_rx()
1492 		if (!(readl(ioaddr + PCIBusCfg) & EepromReload))  in natsemi_reload_eeprom()
1512 		if ((readl(ioaddr + ChipCmd) & (TxOn|RxOn)) == 0)  in natsemi_stop_rxtx()
1565 			dev->name, (int)readl(ioaddr + ChipCmd));  in netdev_open()
1594 	if (readl(ioaddr + ChipConfig) & CfgSpeed100) {  in do_cable_magic()
1715 	readl(ioaddr + IntrStatus);  in init_registers()
1755 	np->SavedClkRun = readl(ioaddr + ClkRun);  in init_registers()
1759 			dev->name, readl(ioaddr + WOLCmd));  in init_registers()
1893 				dev->name, readl(ioaddr + IntrStatus));  in ns_tx_timeout()
2181 	if (np->hands_off || !readl(ioaddr + IntrEnable))  in intr_handler()
2184 	np->intr_status = readl(ioaddr + IntrStatus);  in intr_handler()
2193 		       readl(ioaddr + IntrMask));  in intr_handler()
2205 		       readl(ioaddr + IntrMask));  in intr_handler()
2225 			       readl(ioaddr + IntrMask));  in natsemi_poll()
2249 		np->intr_status = readl(ioaddr + IntrStatus);  in natsemi_poll()
2421 		int wol_status = readl(ioaddr + WOLCmd);  in netdev_error()
2450 	dev->stats.rx_crc_errors += readl(ioaddr + RxCRCErrs);  in __get_stats()
2451 	dev->stats.rx_missed_errors += readl(ioaddr + RxMissed);  in __get_stats()
2695 	u32 data = readl(ioaddr + WOLCmd) & ~WakeOptsSummary;  in netdev_set_wol()
2725 	u32 regval = readl(ioaddr + WOLCmd);  in netdev_get_wol()
2769 	addr = readl(ioaddr + RxFilterAddr) & ~RFCRAddressMask;  in netdev_set_sopass()
2802 	addr = readl(ioaddr + RxFilterAddr) & ~RFCRAddressMask;  in netdev_get_sopass()
2990 		rbuf[i] = readl(ioaddr + i*4);  in netdev_get_regs()
3006 	rfcr = readl(ioaddr + RxFilterAddr);  in netdev_get_regs()
3118 	readl(ioaddr + WOLCmd);  in enable_wol_mode()
3144 			dev->name, (int)readl(ioaddr + ChipCmd));  in netdev_close()
3176 	readl(ioaddr + IntrMask);  in netdev_close()
3197 		u32 wol = readl(ioaddr + WOLCmd) & WakeOptsSummary;  in netdev_close()
3283 			u32 wol = readl(ioaddr + WOLCmd) & WakeOptsSummary;  in natsemi_suspend()