1/* natsemi.c: A Linux PCI Ethernet driver for the NatSemi DP8381x series. */ 2/* 3 Written/copyright 1999-2001 by Donald Becker. 4 Portions copyright (c) 2001,2002 Sun Microsystems (thockin@sun.com) 5 Portions copyright 2001,2002 Manfred Spraul (manfred@colorfullife.com) 6 Portions copyright 2004 Harald Welte <laforge@gnumonks.org> 7 8 This software may be used and distributed according to the terms of 9 the GNU General Public License (GPL), incorporated herein by reference. 10 Drivers based on or derived from this code fall under the GPL and must 11 retain the authorship, copyright and license notice. This file is not 12 a complete program and may only be used when the entire operating 13 system is licensed under the GPL. License for under other terms may be 14 available. Contact the original author for details. 15 16 The original author may be reached as becker@scyld.com, or at 17 Scyld Computing Corporation 18 410 Severn Ave., Suite 210 19 Annapolis MD 21403 20 21 Support information and updates available at 22 http://www.scyld.com/network/netsemi.html 23 [link no longer provides useful info -jgarzik] 24 25 26 TODO: 27 * big endian support with CFG:BEM instead of cpu_to_le32 28*/ 29 30#include <linux/module.h> 31#include <linux/kernel.h> 32#include <linux/string.h> 33#include <linux/timer.h> 34#include <linux/errno.h> 35#include <linux/ioport.h> 36#include <linux/slab.h> 37#include <linux/interrupt.h> 38#include <linux/pci.h> 39#include <linux/netdevice.h> 40#include <linux/etherdevice.h> 41#include <linux/skbuff.h> 42#include <linux/init.h> 43#include <linux/spinlock.h> 44#include <linux/ethtool.h> 45#include <linux/delay.h> 46#include <linux/rtnetlink.h> 47#include <linux/mii.h> 48#include <linux/crc32.h> 49#include <linux/bitops.h> 50#include <linux/prefetch.h> 51#include <asm/processor.h> /* Processor type for cache alignment. */ 52#include <asm/io.h> 53#include <asm/irq.h> 54#include <asm/uaccess.h> 55 56#define DRV_NAME "natsemi" 57#define DRV_VERSION "2.1" 58#define DRV_RELDATE "Sept 11, 2006" 59 60#define RX_OFFSET 2 61 62/* Updated to recommendations in pci-skeleton v2.03. */ 63 64/* The user-configurable values. 65 These may be modified when a driver module is loaded.*/ 66 67#define NATSEMI_DEF_MSG (NETIF_MSG_DRV | \ 68 NETIF_MSG_LINK | \ 69 NETIF_MSG_WOL | \ 70 NETIF_MSG_RX_ERR | \ 71 NETIF_MSG_TX_ERR) 72static int debug = -1; 73 74static int mtu; 75 76/* Maximum number of multicast addresses to filter (vs. rx-all-multicast). 77 This chip uses a 512 element hash table based on the Ethernet CRC. */ 78static const int multicast_filter_limit = 100; 79 80/* Set the copy breakpoint for the copy-only-tiny-frames scheme. 81 Setting to > 1518 effectively disables this feature. */ 82static int rx_copybreak; 83 84static int dspcfg_workaround = 1; 85 86/* Used to pass the media type, etc. 87 Both 'options[]' and 'full_duplex[]' should exist for driver 88 interoperability. 89 The media type is usually passed in 'options[]'. 90*/ 91#define MAX_UNITS 8 /* More are supported, limit only on options */ 92static int options[MAX_UNITS]; 93static int full_duplex[MAX_UNITS]; 94 95/* Operational parameters that are set at compile time. */ 96 97/* Keep the ring sizes a power of two for compile efficiency. 98 The compiler will convert <unsigned>'%'<2^N> into a bit mask. 99 Making the Tx ring too large decreases the effectiveness of channel 100 bonding and packet priority. 101 There are no ill effects from too-large receive rings. */ 102#define TX_RING_SIZE 16 103#define TX_QUEUE_LEN 10 /* Limit ring entries actually used, min 4. */ 104#define RX_RING_SIZE 32 105 106/* Operational parameters that usually are not changed. */ 107/* Time in jiffies before concluding the transmitter is hung. */ 108#define TX_TIMEOUT (2*HZ) 109 110#define NATSEMI_HW_TIMEOUT 400 111#define NATSEMI_TIMER_FREQ 5*HZ 112#define NATSEMI_PG0_NREGS 64 113#define NATSEMI_RFDR_NREGS 8 114#define NATSEMI_PG1_NREGS 4 115#define NATSEMI_NREGS (NATSEMI_PG0_NREGS + NATSEMI_RFDR_NREGS + \ 116 NATSEMI_PG1_NREGS) 117#define NATSEMI_REGS_VER 1 /* v1 added RFDR registers */ 118#define NATSEMI_REGS_SIZE (NATSEMI_NREGS * sizeof(u32)) 119 120/* Buffer sizes: 121 * The nic writes 32-bit values, even if the upper bytes of 122 * a 32-bit value are beyond the end of the buffer. 123 */ 124#define NATSEMI_HEADERS 22 /* 2*mac,type,vlan,crc */ 125#define NATSEMI_PADDING 16 /* 2 bytes should be sufficient */ 126#define NATSEMI_LONGPKT 1518 /* limit for normal packets */ 127#define NATSEMI_RX_LIMIT 2046 /* maximum supported by hardware */ 128 129/* These identify the driver base version and may not be removed. */ 130static const char version[] = 131 KERN_INFO DRV_NAME " dp8381x driver, version " 132 DRV_VERSION ", " DRV_RELDATE "\n" 133 " originally by Donald Becker <becker@scyld.com>\n" 134 " 2.4.x kernel port by Jeff Garzik, Tjeerd Mulder\n"; 135 136MODULE_AUTHOR("Donald Becker <becker@scyld.com>"); 137MODULE_DESCRIPTION("National Semiconductor DP8381x series PCI Ethernet driver"); 138MODULE_LICENSE("GPL"); 139 140module_param(mtu, int, 0); 141module_param(debug, int, 0); 142module_param(rx_copybreak, int, 0); 143module_param(dspcfg_workaround, int, 0); 144module_param_array(options, int, NULL, 0); 145module_param_array(full_duplex, int, NULL, 0); 146MODULE_PARM_DESC(mtu, "DP8381x MTU (all boards)"); 147MODULE_PARM_DESC(debug, "DP8381x default debug level"); 148MODULE_PARM_DESC(rx_copybreak, 149 "DP8381x copy breakpoint for copy-only-tiny-frames"); 150MODULE_PARM_DESC(dspcfg_workaround, "DP8381x: control DspCfg workaround"); 151MODULE_PARM_DESC(options, 152 "DP8381x: Bits 0-3: media type, bit 17: full duplex"); 153MODULE_PARM_DESC(full_duplex, "DP8381x full duplex setting(s) (1)"); 154 155/* 156 Theory of Operation 157 158I. Board Compatibility 159 160This driver is designed for National Semiconductor DP83815 PCI Ethernet NIC. 161It also works with other chips in in the DP83810 series. 162 163II. Board-specific settings 164 165This driver requires the PCI interrupt line to be valid. 166It honors the EEPROM-set values. 167 168III. Driver operation 169 170IIIa. Ring buffers 171 172This driver uses two statically allocated fixed-size descriptor lists 173formed into rings by a branch from the final descriptor to the beginning of 174the list. The ring sizes are set at compile time by RX/TX_RING_SIZE. 175The NatSemi design uses a 'next descriptor' pointer that the driver forms 176into a list. 177 178IIIb/c. Transmit/Receive Structure 179 180This driver uses a zero-copy receive and transmit scheme. 181The driver allocates full frame size skbuffs for the Rx ring buffers at 182open() time and passes the skb->data field to the chip as receive data 183buffers. When an incoming frame is less than RX_COPYBREAK bytes long, 184a fresh skbuff is allocated and the frame is copied to the new skbuff. 185When the incoming frame is larger, the skbuff is passed directly up the 186protocol stack. Buffers consumed this way are replaced by newly allocated 187skbuffs in a later phase of receives. 188 189The RX_COPYBREAK value is chosen to trade-off the memory wasted by 190using a full-sized skbuff for small frames vs. the copying costs of larger 191frames. New boards are typically used in generously configured machines 192and the underfilled buffers have negligible impact compared to the benefit of 193a single allocation size, so the default value of zero results in never 194copying packets. When copying is done, the cost is usually mitigated by using 195a combined copy/checksum routine. Copying also preloads the cache, which is 196most useful with small frames. 197 198A subtle aspect of the operation is that unaligned buffers are not permitted 199by the hardware. Thus the IP header at offset 14 in an ethernet frame isn't 200longword aligned for further processing. On copies frames are put into the 201skbuff at an offset of "+2", 16-byte aligning the IP header. 202 203IIId. Synchronization 204 205Most operations are synchronized on the np->lock irq spinlock, except the 206receive and transmit paths which are synchronised using a combination of 207hardware descriptor ownership, disabling interrupts and NAPI poll scheduling. 208 209IVb. References 210 211http://www.scyld.com/expert/100mbps.html 212http://www.scyld.com/expert/NWay.html 213Datasheet is available from: 214http://www.national.com/pf/DP/DP83815.html 215 216IVc. Errata 217 218None characterised. 219*/ 220 221 222 223/* 224 * Support for fibre connections on Am79C874: 225 * This phy needs a special setup when connected to a fibre cable. 226 * http://www.amd.com/files/connectivitysolutions/networking/archivednetworking/22235.pdf 227 */ 228#define PHYID_AM79C874 0x0022561b 229 230enum { 231 MII_MCTRL = 0x15, /* mode control register */ 232 MII_FX_SEL = 0x0001, /* 100BASE-FX (fiber) */ 233 MII_EN_SCRM = 0x0004, /* enable scrambler (tp) */ 234}; 235 236enum { 237 NATSEMI_FLAG_IGNORE_PHY = 0x1, 238}; 239 240/* array of board data directly indexed by pci_tbl[x].driver_data */ 241static struct { 242 const char *name; 243 unsigned long flags; 244 unsigned int eeprom_size; 245} natsemi_pci_info[] = { 246 { "Aculab E1/T1 PMXc cPCI carrier card", NATSEMI_FLAG_IGNORE_PHY, 128 }, 247 { "NatSemi DP8381[56]", 0, 24 }, 248}; 249 250static const struct pci_device_id natsemi_pci_tbl[] = { 251 { PCI_VENDOR_ID_NS, 0x0020, 0x12d9, 0x000c, 0, 0, 0 }, 252 { PCI_VENDOR_ID_NS, 0x0020, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 }, 253 { } /* terminate list */ 254}; 255MODULE_DEVICE_TABLE(pci, natsemi_pci_tbl); 256 257/* Offsets to the device registers. 258 Unlike software-only systems, device drivers interact with complex hardware. 259 It's not useful to define symbolic names for every register bit in the 260 device. 261*/ 262enum register_offsets { 263 ChipCmd = 0x00, 264 ChipConfig = 0x04, 265 EECtrl = 0x08, 266 PCIBusCfg = 0x0C, 267 IntrStatus = 0x10, 268 IntrMask = 0x14, 269 IntrEnable = 0x18, 270 IntrHoldoff = 0x1C, /* DP83816 only */ 271 TxRingPtr = 0x20, 272 TxConfig = 0x24, 273 RxRingPtr = 0x30, 274 RxConfig = 0x34, 275 ClkRun = 0x3C, 276 WOLCmd = 0x40, 277 PauseCmd = 0x44, 278 RxFilterAddr = 0x48, 279 RxFilterData = 0x4C, 280 BootRomAddr = 0x50, 281 BootRomData = 0x54, 282 SiliconRev = 0x58, 283 StatsCtrl = 0x5C, 284 StatsData = 0x60, 285 RxPktErrs = 0x60, 286 RxMissed = 0x68, 287 RxCRCErrs = 0x64, 288 BasicControl = 0x80, 289 BasicStatus = 0x84, 290 AnegAdv = 0x90, 291 AnegPeer = 0x94, 292 PhyStatus = 0xC0, 293 MIntrCtrl = 0xC4, 294 MIntrStatus = 0xC8, 295 PhyCtrl = 0xE4, 296 297 /* These are from the spec, around page 78... on a separate table. 298 * The meaning of these registers depend on the value of PGSEL. */ 299 PGSEL = 0xCC, 300 PMDCSR = 0xE4, 301 TSTDAT = 0xFC, 302 DSPCFG = 0xF4, 303 SDCFG = 0xF8 304}; 305/* the values for the 'magic' registers above (PGSEL=1) */ 306#define PMDCSR_VAL 0x189c /* enable preferred adaptation circuitry */ 307#define TSTDAT_VAL 0x0 308#define DSPCFG_VAL 0x5040 309#define SDCFG_VAL 0x008c /* set voltage thresholds for Signal Detect */ 310#define DSPCFG_LOCK 0x20 /* coefficient lock bit in DSPCFG */ 311#define DSPCFG_COEF 0x1000 /* see coefficient (in TSTDAT) bit in DSPCFG */ 312#define TSTDAT_FIXED 0xe8 /* magic number for bad coefficients */ 313 314/* misc PCI space registers */ 315enum pci_register_offsets { 316 PCIPM = 0x44, 317}; 318 319enum ChipCmd_bits { 320 ChipReset = 0x100, 321 RxReset = 0x20, 322 TxReset = 0x10, 323 RxOff = 0x08, 324 RxOn = 0x04, 325 TxOff = 0x02, 326 TxOn = 0x01, 327}; 328 329enum ChipConfig_bits { 330 CfgPhyDis = 0x200, 331 CfgPhyRst = 0x400, 332 CfgExtPhy = 0x1000, 333 CfgAnegEnable = 0x2000, 334 CfgAneg100 = 0x4000, 335 CfgAnegFull = 0x8000, 336 CfgAnegDone = 0x8000000, 337 CfgFullDuplex = 0x20000000, 338 CfgSpeed100 = 0x40000000, 339 CfgLink = 0x80000000, 340}; 341 342enum EECtrl_bits { 343 EE_ShiftClk = 0x04, 344 EE_DataIn = 0x01, 345 EE_ChipSelect = 0x08, 346 EE_DataOut = 0x02, 347 MII_Data = 0x10, 348 MII_Write = 0x20, 349 MII_ShiftClk = 0x40, 350}; 351 352enum PCIBusCfg_bits { 353 EepromReload = 0x4, 354}; 355 356/* Bits in the interrupt status/mask registers. */ 357enum IntrStatus_bits { 358 IntrRxDone = 0x0001, 359 IntrRxIntr = 0x0002, 360 IntrRxErr = 0x0004, 361 IntrRxEarly = 0x0008, 362 IntrRxIdle = 0x0010, 363 IntrRxOverrun = 0x0020, 364 IntrTxDone = 0x0040, 365 IntrTxIntr = 0x0080, 366 IntrTxErr = 0x0100, 367 IntrTxIdle = 0x0200, 368 IntrTxUnderrun = 0x0400, 369 StatsMax = 0x0800, 370 SWInt = 0x1000, 371 WOLPkt = 0x2000, 372 LinkChange = 0x4000, 373 IntrHighBits = 0x8000, 374 RxStatusFIFOOver = 0x10000, 375 IntrPCIErr = 0xf00000, 376 RxResetDone = 0x1000000, 377 TxResetDone = 0x2000000, 378 IntrAbnormalSummary = 0xCD20, 379}; 380 381/* 382 * Default Interrupts: 383 * Rx OK, Rx Packet Error, Rx Overrun, 384 * Tx OK, Tx Packet Error, Tx Underrun, 385 * MIB Service, Phy Interrupt, High Bits, 386 * Rx Status FIFO overrun, 387 * Received Target Abort, Received Master Abort, 388 * Signalled System Error, Received Parity Error 389 */ 390#define DEFAULT_INTR 0x00f1cd65 391 392enum TxConfig_bits { 393 TxDrthMask = 0x3f, 394 TxFlthMask = 0x3f00, 395 TxMxdmaMask = 0x700000, 396 TxMxdma_512 = 0x0, 397 TxMxdma_4 = 0x100000, 398 TxMxdma_8 = 0x200000, 399 TxMxdma_16 = 0x300000, 400 TxMxdma_32 = 0x400000, 401 TxMxdma_64 = 0x500000, 402 TxMxdma_128 = 0x600000, 403 TxMxdma_256 = 0x700000, 404 TxCollRetry = 0x800000, 405 TxAutoPad = 0x10000000, 406 TxMacLoop = 0x20000000, 407 TxHeartIgn = 0x40000000, 408 TxCarrierIgn = 0x80000000 409}; 410 411/* 412 * Tx Configuration: 413 * - 256 byte DMA burst length 414 * - fill threshold 512 bytes (i.e. restart DMA when 512 bytes are free) 415 * - 64 bytes initial drain threshold (i.e. begin actual transmission 416 * when 64 byte are in the fifo) 417 * - on tx underruns, increase drain threshold by 64. 418 * - at most use a drain threshold of 1472 bytes: The sum of the fill 419 * threshold and the drain threshold must be less than 2016 bytes. 420 * 421 */ 422#define TX_FLTH_VAL ((512/32) << 8) 423#define TX_DRTH_VAL_START (64/32) 424#define TX_DRTH_VAL_INC 2 425#define TX_DRTH_VAL_LIMIT (1472/32) 426 427enum RxConfig_bits { 428 RxDrthMask = 0x3e, 429 RxMxdmaMask = 0x700000, 430 RxMxdma_512 = 0x0, 431 RxMxdma_4 = 0x100000, 432 RxMxdma_8 = 0x200000, 433 RxMxdma_16 = 0x300000, 434 RxMxdma_32 = 0x400000, 435 RxMxdma_64 = 0x500000, 436 RxMxdma_128 = 0x600000, 437 RxMxdma_256 = 0x700000, 438 RxAcceptLong = 0x8000000, 439 RxAcceptTx = 0x10000000, 440 RxAcceptRunt = 0x40000000, 441 RxAcceptErr = 0x80000000 442}; 443#define RX_DRTH_VAL (128/8) 444 445enum ClkRun_bits { 446 PMEEnable = 0x100, 447 PMEStatus = 0x8000, 448}; 449 450enum WolCmd_bits { 451 WakePhy = 0x1, 452 WakeUnicast = 0x2, 453 WakeMulticast = 0x4, 454 WakeBroadcast = 0x8, 455 WakeArp = 0x10, 456 WakePMatch0 = 0x20, 457 WakePMatch1 = 0x40, 458 WakePMatch2 = 0x80, 459 WakePMatch3 = 0x100, 460 WakeMagic = 0x200, 461 WakeMagicSecure = 0x400, 462 SecureHack = 0x100000, 463 WokePhy = 0x400000, 464 WokeUnicast = 0x800000, 465 WokeMulticast = 0x1000000, 466 WokeBroadcast = 0x2000000, 467 WokeArp = 0x4000000, 468 WokePMatch0 = 0x8000000, 469 WokePMatch1 = 0x10000000, 470 WokePMatch2 = 0x20000000, 471 WokePMatch3 = 0x40000000, 472 WokeMagic = 0x80000000, 473 WakeOptsSummary = 0x7ff 474}; 475 476enum RxFilterAddr_bits { 477 RFCRAddressMask = 0x3ff, 478 AcceptMulticast = 0x00200000, 479 AcceptMyPhys = 0x08000000, 480 AcceptAllPhys = 0x10000000, 481 AcceptAllMulticast = 0x20000000, 482 AcceptBroadcast = 0x40000000, 483 RxFilterEnable = 0x80000000 484}; 485 486enum StatsCtrl_bits { 487 StatsWarn = 0x1, 488 StatsFreeze = 0x2, 489 StatsClear = 0x4, 490 StatsStrobe = 0x8, 491}; 492 493enum MIntrCtrl_bits { 494 MICRIntEn = 0x2, 495}; 496 497enum PhyCtrl_bits { 498 PhyAddrMask = 0x1f, 499}; 500 501#define PHY_ADDR_NONE 32 502#define PHY_ADDR_INTERNAL 1 503 504/* values we might find in the silicon revision register */ 505#define SRR_DP83815_C 0x0302 506#define SRR_DP83815_D 0x0403 507#define SRR_DP83816_A4 0x0504 508#define SRR_DP83816_A5 0x0505 509 510/* The Rx and Tx buffer descriptors. */ 511/* Note that using only 32 bit fields simplifies conversion to big-endian 512 architectures. */ 513struct netdev_desc { 514 __le32 next_desc; 515 __le32 cmd_status; 516 __le32 addr; 517 __le32 software_use; 518}; 519 520/* Bits in network_desc.status */ 521enum desc_status_bits { 522 DescOwn=0x80000000, DescMore=0x40000000, DescIntr=0x20000000, 523 DescNoCRC=0x10000000, DescPktOK=0x08000000, 524 DescSizeMask=0xfff, 525 526 DescTxAbort=0x04000000, DescTxFIFO=0x02000000, 527 DescTxCarrier=0x01000000, DescTxDefer=0x00800000, 528 DescTxExcDefer=0x00400000, DescTxOOWCol=0x00200000, 529 DescTxExcColl=0x00100000, DescTxCollCount=0x000f0000, 530 531 DescRxAbort=0x04000000, DescRxOver=0x02000000, 532 DescRxDest=0x01800000, DescRxLong=0x00400000, 533 DescRxRunt=0x00200000, DescRxInvalid=0x00100000, 534 DescRxCRC=0x00080000, DescRxAlign=0x00040000, 535 DescRxLoop=0x00020000, DesRxColl=0x00010000, 536}; 537 538struct netdev_private { 539 /* Descriptor rings first for alignment */ 540 dma_addr_t ring_dma; 541 struct netdev_desc *rx_ring; 542 struct netdev_desc *tx_ring; 543 /* The addresses of receive-in-place skbuffs */ 544 struct sk_buff *rx_skbuff[RX_RING_SIZE]; 545 dma_addr_t rx_dma[RX_RING_SIZE]; 546 /* address of a sent-in-place packet/buffer, for later free() */ 547 struct sk_buff *tx_skbuff[TX_RING_SIZE]; 548 dma_addr_t tx_dma[TX_RING_SIZE]; 549 struct net_device *dev; 550 void __iomem *ioaddr; 551 struct napi_struct napi; 552 /* Media monitoring timer */ 553 struct timer_list timer; 554 /* Frequently used values: keep some adjacent for cache effect */ 555 struct pci_dev *pci_dev; 556 struct netdev_desc *rx_head_desc; 557 /* Producer/consumer ring indices */ 558 unsigned int cur_rx, dirty_rx; 559 unsigned int cur_tx, dirty_tx; 560 /* Based on MTU+slack. */ 561 unsigned int rx_buf_sz; 562 int oom; 563 /* Interrupt status */ 564 u32 intr_status; 565 /* Do not touch the nic registers */ 566 int hands_off; 567 /* Don't pay attention to the reported link state. */ 568 int ignore_phy; 569 /* external phy that is used: only valid if dev->if_port != PORT_TP */ 570 int mii; 571 int phy_addr_external; 572 unsigned int full_duplex; 573 /* Rx filter */ 574 u32 cur_rx_mode; 575 u32 rx_filter[16]; 576 /* FIFO and PCI burst thresholds */ 577 u32 tx_config, rx_config; 578 /* original contents of ClkRun register */ 579 u32 SavedClkRun; 580 /* silicon revision */ 581 u32 srr; 582 /* expected DSPCFG value */ 583 u16 dspcfg; 584 int dspcfg_workaround; 585 /* parms saved in ethtool format */ 586 u16 speed; /* The forced speed, 10Mb, 100Mb, gigabit */ 587 u8 duplex; /* Duplex, half or full */ 588 u8 autoneg; /* Autonegotiation enabled */ 589 /* MII transceiver section */ 590 u16 advertising; 591 unsigned int iosize; 592 spinlock_t lock; 593 u32 msg_enable; 594 /* EEPROM data */ 595 int eeprom_size; 596}; 597 598static void move_int_phy(struct net_device *dev, int addr); 599static int eeprom_read(void __iomem *ioaddr, int location); 600static int mdio_read(struct net_device *dev, int reg); 601static void mdio_write(struct net_device *dev, int reg, u16 data); 602static void init_phy_fixup(struct net_device *dev); 603static int miiport_read(struct net_device *dev, int phy_id, int reg); 604static void miiport_write(struct net_device *dev, int phy_id, int reg, u16 data); 605static int find_mii(struct net_device *dev); 606static void natsemi_reset(struct net_device *dev); 607static void natsemi_reload_eeprom(struct net_device *dev); 608static void natsemi_stop_rxtx(struct net_device *dev); 609static int netdev_open(struct net_device *dev); 610static void do_cable_magic(struct net_device *dev); 611static void undo_cable_magic(struct net_device *dev); 612static void check_link(struct net_device *dev); 613static void netdev_timer(unsigned long data); 614static void dump_ring(struct net_device *dev); 615static void ns_tx_timeout(struct net_device *dev); 616static int alloc_ring(struct net_device *dev); 617static void refill_rx(struct net_device *dev); 618static void init_ring(struct net_device *dev); 619static void drain_tx(struct net_device *dev); 620static void drain_ring(struct net_device *dev); 621static void free_ring(struct net_device *dev); 622static void reinit_ring(struct net_device *dev); 623static void init_registers(struct net_device *dev); 624static netdev_tx_t start_tx(struct sk_buff *skb, struct net_device *dev); 625static irqreturn_t intr_handler(int irq, void *dev_instance); 626static void netdev_error(struct net_device *dev, int intr_status); 627static int natsemi_poll(struct napi_struct *napi, int budget); 628static void netdev_rx(struct net_device *dev, int *work_done, int work_to_do); 629static void netdev_tx_done(struct net_device *dev); 630static int natsemi_change_mtu(struct net_device *dev, int new_mtu); 631#ifdef CONFIG_NET_POLL_CONTROLLER 632static void natsemi_poll_controller(struct net_device *dev); 633#endif 634static void __set_rx_mode(struct net_device *dev); 635static void set_rx_mode(struct net_device *dev); 636static void __get_stats(struct net_device *dev); 637static struct net_device_stats *get_stats(struct net_device *dev); 638static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); 639static int netdev_set_wol(struct net_device *dev, u32 newval); 640static int netdev_get_wol(struct net_device *dev, u32 *supported, u32 *cur); 641static int netdev_set_sopass(struct net_device *dev, u8 *newval); 642static int netdev_get_sopass(struct net_device *dev, u8 *data); 643static int netdev_get_ecmd(struct net_device *dev, struct ethtool_cmd *ecmd); 644static int netdev_set_ecmd(struct net_device *dev, struct ethtool_cmd *ecmd); 645static void enable_wol_mode(struct net_device *dev, int enable_intr); 646static int netdev_close(struct net_device *dev); 647static int netdev_get_regs(struct net_device *dev, u8 *buf); 648static int netdev_get_eeprom(struct net_device *dev, u8 *buf); 649static const struct ethtool_ops ethtool_ops; 650 651#define NATSEMI_ATTR(_name) \ 652static ssize_t natsemi_show_##_name(struct device *dev, \ 653 struct device_attribute *attr, char *buf); \ 654 static ssize_t natsemi_set_##_name(struct device *dev, \ 655 struct device_attribute *attr, \ 656 const char *buf, size_t count); \ 657 static DEVICE_ATTR(_name, 0644, natsemi_show_##_name, natsemi_set_##_name) 658 659#define NATSEMI_CREATE_FILE(_dev, _name) \ 660 device_create_file(&_dev->dev, &dev_attr_##_name) 661#define NATSEMI_REMOVE_FILE(_dev, _name) \ 662 device_remove_file(&_dev->dev, &dev_attr_##_name) 663 664NATSEMI_ATTR(dspcfg_workaround); 665 666static ssize_t natsemi_show_dspcfg_workaround(struct device *dev, 667 struct device_attribute *attr, 668 char *buf) 669{ 670 struct netdev_private *np = netdev_priv(to_net_dev(dev)); 671 672 return sprintf(buf, "%s\n", np->dspcfg_workaround ? "on" : "off"); 673} 674 675static ssize_t natsemi_set_dspcfg_workaround(struct device *dev, 676 struct device_attribute *attr, 677 const char *buf, size_t count) 678{ 679 struct netdev_private *np = netdev_priv(to_net_dev(dev)); 680 int new_setting; 681 unsigned long flags; 682 683 /* Find out the new setting */ 684 if (!strncmp("on", buf, count - 1) || !strncmp("1", buf, count - 1)) 685 new_setting = 1; 686 else if (!strncmp("off", buf, count - 1) || 687 !strncmp("0", buf, count - 1)) 688 new_setting = 0; 689 else 690 return count; 691 692 spin_lock_irqsave(&np->lock, flags); 693 694 np->dspcfg_workaround = new_setting; 695 696 spin_unlock_irqrestore(&np->lock, flags); 697 698 return count; 699} 700 701static inline void __iomem *ns_ioaddr(struct net_device *dev) 702{ 703 struct netdev_private *np = netdev_priv(dev); 704 705 return np->ioaddr; 706} 707 708static inline void natsemi_irq_enable(struct net_device *dev) 709{ 710 writel(1, ns_ioaddr(dev) + IntrEnable); 711 readl(ns_ioaddr(dev) + IntrEnable); 712} 713 714static inline void natsemi_irq_disable(struct net_device *dev) 715{ 716 writel(0, ns_ioaddr(dev) + IntrEnable); 717 readl(ns_ioaddr(dev) + IntrEnable); 718} 719 720static void move_int_phy(struct net_device *dev, int addr) 721{ 722 struct netdev_private *np = netdev_priv(dev); 723 void __iomem *ioaddr = ns_ioaddr(dev); 724 int target = 31; 725 726 /* 727 * The internal phy is visible on the external mii bus. Therefore we must 728 * move it away before we can send commands to an external phy. 729 * There are two addresses we must avoid: 730 * - the address on the external phy that is used for transmission. 731 * - the address that we want to access. User space can access phys 732 * on the mii bus with SIOCGMIIREG/SIOCSMIIREG, independent from the 733 * phy that is used for transmission. 734 */ 735 736 if (target == addr) 737 target--; 738 if (target == np->phy_addr_external) 739 target--; 740 writew(target, ioaddr + PhyCtrl); 741 readw(ioaddr + PhyCtrl); 742 udelay(1); 743} 744 745static void natsemi_init_media(struct net_device *dev) 746{ 747 struct netdev_private *np = netdev_priv(dev); 748 u32 tmp; 749 750 if (np->ignore_phy) 751 netif_carrier_on(dev); 752 else 753 netif_carrier_off(dev); 754 755 /* get the initial settings from hardware */ 756 tmp = mdio_read(dev, MII_BMCR); 757 np->speed = (tmp & BMCR_SPEED100)? SPEED_100 : SPEED_10; 758 np->duplex = (tmp & BMCR_FULLDPLX)? DUPLEX_FULL : DUPLEX_HALF; 759 np->autoneg = (tmp & BMCR_ANENABLE)? AUTONEG_ENABLE: AUTONEG_DISABLE; 760 np->advertising= mdio_read(dev, MII_ADVERTISE); 761 762 if ((np->advertising & ADVERTISE_ALL) != ADVERTISE_ALL && 763 netif_msg_probe(np)) { 764 printk(KERN_INFO "natsemi %s: Transceiver default autonegotiation %s " 765 "10%s %s duplex.\n", 766 pci_name(np->pci_dev), 767 (mdio_read(dev, MII_BMCR) & BMCR_ANENABLE)? 768 "enabled, advertise" : "disabled, force", 769 (np->advertising & 770 (ADVERTISE_100FULL|ADVERTISE_100HALF))? 771 "0" : "", 772 (np->advertising & 773 (ADVERTISE_100FULL|ADVERTISE_10FULL))? 774 "full" : "half"); 775 } 776 if (netif_msg_probe(np)) 777 printk(KERN_INFO 778 "natsemi %s: Transceiver status %#04x advertising %#04x.\n", 779 pci_name(np->pci_dev), mdio_read(dev, MII_BMSR), 780 np->advertising); 781 782} 783 784static const struct net_device_ops natsemi_netdev_ops = { 785 .ndo_open = netdev_open, 786 .ndo_stop = netdev_close, 787 .ndo_start_xmit = start_tx, 788 .ndo_get_stats = get_stats, 789 .ndo_set_rx_mode = set_rx_mode, 790 .ndo_change_mtu = natsemi_change_mtu, 791 .ndo_do_ioctl = netdev_ioctl, 792 .ndo_tx_timeout = ns_tx_timeout, 793 .ndo_set_mac_address = eth_mac_addr, 794 .ndo_validate_addr = eth_validate_addr, 795#ifdef CONFIG_NET_POLL_CONTROLLER 796 .ndo_poll_controller = natsemi_poll_controller, 797#endif 798}; 799 800static int natsemi_probe1(struct pci_dev *pdev, const struct pci_device_id *ent) 801{ 802 struct net_device *dev; 803 struct netdev_private *np; 804 int i, option, irq, chip_idx = ent->driver_data; 805 static int find_cnt = -1; 806 resource_size_t iostart; 807 unsigned long iosize; 808 void __iomem *ioaddr; 809 const int pcibar = 1; /* PCI base address register */ 810 int prev_eedata; 811 u32 tmp; 812 813/* when built into the kernel, we only print version if device is found */ 814#ifndef MODULE 815 static int printed_version; 816 if (!printed_version++) 817 printk(version); 818#endif 819 820 i = pci_enable_device(pdev); 821 if (i) return i; 822 823 /* natsemi has a non-standard PM control register 824 * in PCI config space. Some boards apparently need 825 * to be brought to D0 in this manner. 826 */ 827 pci_read_config_dword(pdev, PCIPM, &tmp); 828 if (tmp & PCI_PM_CTRL_STATE_MASK) { 829 /* D0 state, disable PME assertion */ 830 u32 newtmp = tmp & ~PCI_PM_CTRL_STATE_MASK; 831 pci_write_config_dword(pdev, PCIPM, newtmp); 832 } 833 834 find_cnt++; 835 iostart = pci_resource_start(pdev, pcibar); 836 iosize = pci_resource_len(pdev, pcibar); 837 irq = pdev->irq; 838 839 pci_set_master(pdev); 840 841 dev = alloc_etherdev(sizeof (struct netdev_private)); 842 if (!dev) 843 return -ENOMEM; 844 SET_NETDEV_DEV(dev, &pdev->dev); 845 846 i = pci_request_regions(pdev, DRV_NAME); 847 if (i) 848 goto err_pci_request_regions; 849 850 ioaddr = ioremap(iostart, iosize); 851 if (!ioaddr) { 852 i = -ENOMEM; 853 goto err_ioremap; 854 } 855 856 /* Work around the dropped serial bit. */ 857 prev_eedata = eeprom_read(ioaddr, 6); 858 for (i = 0; i < 3; i++) { 859 int eedata = eeprom_read(ioaddr, i + 7); 860 dev->dev_addr[i*2] = (eedata << 1) + (prev_eedata >> 15); 861 dev->dev_addr[i*2+1] = eedata >> 7; 862 prev_eedata = eedata; 863 } 864 865 np = netdev_priv(dev); 866 np->ioaddr = ioaddr; 867 868 netif_napi_add(dev, &np->napi, natsemi_poll, 64); 869 np->dev = dev; 870 871 np->pci_dev = pdev; 872 pci_set_drvdata(pdev, dev); 873 np->iosize = iosize; 874 spin_lock_init(&np->lock); 875 np->msg_enable = (debug >= 0) ? (1<<debug)-1 : NATSEMI_DEF_MSG; 876 np->hands_off = 0; 877 np->intr_status = 0; 878 np->eeprom_size = natsemi_pci_info[chip_idx].eeprom_size; 879 if (natsemi_pci_info[chip_idx].flags & NATSEMI_FLAG_IGNORE_PHY) 880 np->ignore_phy = 1; 881 else 882 np->ignore_phy = 0; 883 np->dspcfg_workaround = dspcfg_workaround; 884 885 /* Initial port: 886 * - If configured to ignore the PHY set up for external. 887 * - If the nic was configured to use an external phy and if find_mii 888 * finds a phy: use external port, first phy that replies. 889 * - Otherwise: internal port. 890 * Note that the phy address for the internal phy doesn't matter: 891 * The address would be used to access a phy over the mii bus, but 892 * the internal phy is accessed through mapped registers. 893 */ 894 if (np->ignore_phy || readl(ioaddr + ChipConfig) & CfgExtPhy) 895 dev->if_port = PORT_MII; 896 else 897 dev->if_port = PORT_TP; 898 /* Reset the chip to erase previous misconfiguration. */ 899 natsemi_reload_eeprom(dev); 900 natsemi_reset(dev); 901 902 if (dev->if_port != PORT_TP) { 903 np->phy_addr_external = find_mii(dev); 904 /* If we're ignoring the PHY it doesn't matter if we can't 905 * find one. */ 906 if (!np->ignore_phy && np->phy_addr_external == PHY_ADDR_NONE) { 907 dev->if_port = PORT_TP; 908 np->phy_addr_external = PHY_ADDR_INTERNAL; 909 } 910 } else { 911 np->phy_addr_external = PHY_ADDR_INTERNAL; 912 } 913 914 option = find_cnt < MAX_UNITS ? options[find_cnt] : 0; 915 /* The lower four bits are the media type. */ 916 if (option) { 917 if (option & 0x200) 918 np->full_duplex = 1; 919 if (option & 15) 920 printk(KERN_INFO 921 "natsemi %s: ignoring user supplied media type %d", 922 pci_name(np->pci_dev), option & 15); 923 } 924 if (find_cnt < MAX_UNITS && full_duplex[find_cnt]) 925 np->full_duplex = 1; 926 927 dev->netdev_ops = &natsemi_netdev_ops; 928 dev->watchdog_timeo = TX_TIMEOUT; 929 930 dev->ethtool_ops = ðtool_ops; 931 932 if (mtu) 933 dev->mtu = mtu; 934 935 natsemi_init_media(dev); 936 937 /* save the silicon revision for later querying */ 938 np->srr = readl(ioaddr + SiliconRev); 939 if (netif_msg_hw(np)) 940 printk(KERN_INFO "natsemi %s: silicon revision %#04x.\n", 941 pci_name(np->pci_dev), np->srr); 942 943 i = register_netdev(dev); 944 if (i) 945 goto err_register_netdev; 946 i = NATSEMI_CREATE_FILE(pdev, dspcfg_workaround); 947 if (i) 948 goto err_create_file; 949 950 if (netif_msg_drv(np)) { 951 printk(KERN_INFO "natsemi %s: %s at %#08llx " 952 "(%s), %pM, IRQ %d", 953 dev->name, natsemi_pci_info[chip_idx].name, 954 (unsigned long long)iostart, pci_name(np->pci_dev), 955 dev->dev_addr, irq); 956 if (dev->if_port == PORT_TP) 957 printk(", port TP.\n"); 958 else if (np->ignore_phy) 959 printk(", port MII, ignoring PHY\n"); 960 else 961 printk(", port MII, phy ad %d.\n", np->phy_addr_external); 962 } 963 return 0; 964 965 err_create_file: 966 unregister_netdev(dev); 967 968 err_register_netdev: 969 iounmap(ioaddr); 970 971 err_ioremap: 972 pci_release_regions(pdev); 973 974 err_pci_request_regions: 975 free_netdev(dev); 976 return i; 977} 978 979 980/* Read the EEPROM and MII Management Data I/O (MDIO) interfaces. 981 The EEPROM code is for the common 93c06/46 EEPROMs with 6 bit addresses. */ 982 983/* Delay between EEPROM clock transitions. 984 No extra delay is needed with 33Mhz PCI, but future 66Mhz access may need 985 a delay. Note that pre-2.0.34 kernels had a cache-alignment bug that 986 made udelay() unreliable. 987 The old method of using an ISA access as a delay, __SLOW_DOWN_IO__, is 988 deprecated. 989*/ 990#define eeprom_delay(ee_addr) readl(ee_addr) 991 992#define EE_Write0 (EE_ChipSelect) 993#define EE_Write1 (EE_ChipSelect | EE_DataIn) 994 995/* The EEPROM commands include the alway-set leading bit. */ 996enum EEPROM_Cmds { 997 EE_WriteCmd=(5 << 6), EE_ReadCmd=(6 << 6), EE_EraseCmd=(7 << 6), 998}; 999 1000static int eeprom_read(void __iomem *addr, int location) 1001{ 1002 int i; 1003 int retval = 0; 1004 void __iomem *ee_addr = addr + EECtrl; 1005 int read_cmd = location | EE_ReadCmd; 1006 1007 writel(EE_Write0, ee_addr); 1008 1009 /* Shift the read command bits out. */ 1010 for (i = 10; i >= 0; i--) { 1011 short dataval = (read_cmd & (1 << i)) ? EE_Write1 : EE_Write0; 1012 writel(dataval, ee_addr); 1013 eeprom_delay(ee_addr); 1014 writel(dataval | EE_ShiftClk, ee_addr); 1015 eeprom_delay(ee_addr); 1016 } 1017 writel(EE_ChipSelect, ee_addr); 1018 eeprom_delay(ee_addr); 1019 1020 for (i = 0; i < 16; i++) { 1021 writel(EE_ChipSelect | EE_ShiftClk, ee_addr); 1022 eeprom_delay(ee_addr); 1023 retval |= (readl(ee_addr) & EE_DataOut) ? 1 << i : 0; 1024 writel(EE_ChipSelect, ee_addr); 1025 eeprom_delay(ee_addr); 1026 } 1027 1028 /* Terminate the EEPROM access. */ 1029 writel(EE_Write0, ee_addr); 1030 writel(0, ee_addr); 1031 return retval; 1032} 1033 1034/* MII transceiver control section. 1035 * The 83815 series has an internal transceiver, and we present the 1036 * internal management registers as if they were MII connected. 1037 * External Phy registers are referenced through the MII interface. 1038 */ 1039 1040/* clock transitions >= 20ns (25MHz) 1041 * One readl should be good to PCI @ 100MHz 1042 */ 1043#define mii_delay(ioaddr) readl(ioaddr + EECtrl) 1044 1045static int mii_getbit (struct net_device *dev) 1046{ 1047 int data; 1048 void __iomem *ioaddr = ns_ioaddr(dev); 1049 1050 writel(MII_ShiftClk, ioaddr + EECtrl); 1051 data = readl(ioaddr + EECtrl); 1052 writel(0, ioaddr + EECtrl); 1053 mii_delay(ioaddr); 1054 return (data & MII_Data)? 1 : 0; 1055} 1056 1057static void mii_send_bits (struct net_device *dev, u32 data, int len) 1058{ 1059 u32 i; 1060 void __iomem *ioaddr = ns_ioaddr(dev); 1061 1062 for (i = (1 << (len-1)); i; i >>= 1) 1063 { 1064 u32 mdio_val = MII_Write | ((data & i)? MII_Data : 0); 1065 writel(mdio_val, ioaddr + EECtrl); 1066 mii_delay(ioaddr); 1067 writel(mdio_val | MII_ShiftClk, ioaddr + EECtrl); 1068 mii_delay(ioaddr); 1069 } 1070 writel(0, ioaddr + EECtrl); 1071 mii_delay(ioaddr); 1072} 1073 1074static int miiport_read(struct net_device *dev, int phy_id, int reg) 1075{ 1076 u32 cmd; 1077 int i; 1078 u32 retval = 0; 1079 1080 /* Ensure sync */ 1081 mii_send_bits (dev, 0xffffffff, 32); 1082 /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */ 1083 /* ST,OP = 0110'b for read operation */ 1084 cmd = (0x06 << 10) | (phy_id << 5) | reg; 1085 mii_send_bits (dev, cmd, 14); 1086 /* Turnaround */ 1087 if (mii_getbit (dev)) 1088 return 0; 1089 /* Read data */ 1090 for (i = 0; i < 16; i++) { 1091 retval <<= 1; 1092 retval |= mii_getbit (dev); 1093 } 1094 /* End cycle */ 1095 mii_getbit (dev); 1096 return retval; 1097} 1098 1099static void miiport_write(struct net_device *dev, int phy_id, int reg, u16 data) 1100{ 1101 u32 cmd; 1102 1103 /* Ensure sync */ 1104 mii_send_bits (dev, 0xffffffff, 32); 1105 /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */ 1106 /* ST,OP,AAAAA,RRRRR,TA = 0101xxxxxxxxxx10'b = 0x5002 for write */ 1107 cmd = (0x5002 << 16) | (phy_id << 23) | (reg << 18) | data; 1108 mii_send_bits (dev, cmd, 32); 1109 /* End cycle */ 1110 mii_getbit (dev); 1111} 1112 1113static int mdio_read(struct net_device *dev, int reg) 1114{ 1115 struct netdev_private *np = netdev_priv(dev); 1116 void __iomem *ioaddr = ns_ioaddr(dev); 1117 1118 /* The 83815 series has two ports: 1119 * - an internal transceiver 1120 * - an external mii bus 1121 */ 1122 if (dev->if_port == PORT_TP) 1123 return readw(ioaddr+BasicControl+(reg<<2)); 1124 else 1125 return miiport_read(dev, np->phy_addr_external, reg); 1126} 1127 1128static void mdio_write(struct net_device *dev, int reg, u16 data) 1129{ 1130 struct netdev_private *np = netdev_priv(dev); 1131 void __iomem *ioaddr = ns_ioaddr(dev); 1132 1133 /* The 83815 series has an internal transceiver; handle separately */ 1134 if (dev->if_port == PORT_TP) 1135 writew(data, ioaddr+BasicControl+(reg<<2)); 1136 else 1137 miiport_write(dev, np->phy_addr_external, reg, data); 1138} 1139 1140static void init_phy_fixup(struct net_device *dev) 1141{ 1142 struct netdev_private *np = netdev_priv(dev); 1143 void __iomem *ioaddr = ns_ioaddr(dev); 1144 int i; 1145 u32 cfg; 1146 u16 tmp; 1147 1148 /* restore stuff lost when power was out */ 1149 tmp = mdio_read(dev, MII_BMCR); 1150 if (np->autoneg == AUTONEG_ENABLE) { 1151 /* renegotiate if something changed */ 1152 if ((tmp & BMCR_ANENABLE) == 0 || 1153 np->advertising != mdio_read(dev, MII_ADVERTISE)) 1154 { 1155 /* turn on autonegotiation and force negotiation */ 1156 tmp |= (BMCR_ANENABLE | BMCR_ANRESTART); 1157 mdio_write(dev, MII_ADVERTISE, np->advertising); 1158 } 1159 } else { 1160 /* turn off auto negotiation, set speed and duplexity */ 1161 tmp &= ~(BMCR_ANENABLE | BMCR_SPEED100 | BMCR_FULLDPLX); 1162 if (np->speed == SPEED_100) 1163 tmp |= BMCR_SPEED100; 1164 if (np->duplex == DUPLEX_FULL) 1165 tmp |= BMCR_FULLDPLX; 1166 /* 1167 * Note: there is no good way to inform the link partner 1168 * that our capabilities changed. The user has to unplug 1169 * and replug the network cable after some changes, e.g. 1170 * after switching from 10HD, autoneg off to 100 HD, 1171 * autoneg off. 1172 */ 1173 } 1174 mdio_write(dev, MII_BMCR, tmp); 1175 readl(ioaddr + ChipConfig); 1176 udelay(1); 1177 1178 /* find out what phy this is */ 1179 np->mii = (mdio_read(dev, MII_PHYSID1) << 16) 1180 + mdio_read(dev, MII_PHYSID2); 1181 1182 /* handle external phys here */ 1183 switch (np->mii) { 1184 case PHYID_AM79C874: 1185 /* phy specific configuration for fibre/tp operation */ 1186 tmp = mdio_read(dev, MII_MCTRL); 1187 tmp &= ~(MII_FX_SEL | MII_EN_SCRM); 1188 if (dev->if_port == PORT_FIBRE) 1189 tmp |= MII_FX_SEL; 1190 else 1191 tmp |= MII_EN_SCRM; 1192 mdio_write(dev, MII_MCTRL, tmp); 1193 break; 1194 default: 1195 break; 1196 } 1197 cfg = readl(ioaddr + ChipConfig); 1198 if (cfg & CfgExtPhy) 1199 return; 1200 1201 /* On page 78 of the spec, they recommend some settings for "optimum 1202 performance" to be done in sequence. These settings optimize some 1203 of the 100Mbit autodetection circuitry. They say we only want to 1204 do this for rev C of the chip, but engineers at NSC (Bradley 1205 Kennedy) recommends always setting them. If you don't, you get 1206 errors on some autonegotiations that make the device unusable. 1207 1208 It seems that the DSP needs a few usec to reinitialize after 1209 the start of the phy. Just retry writing these values until they 1210 stick. 1211 */ 1212 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) { 1213 1214 int dspcfg; 1215 writew(1, ioaddr + PGSEL); 1216 writew(PMDCSR_VAL, ioaddr + PMDCSR); 1217 writew(TSTDAT_VAL, ioaddr + TSTDAT); 1218 np->dspcfg = (np->srr <= SRR_DP83815_C)? 1219 DSPCFG_VAL : (DSPCFG_COEF | readw(ioaddr + DSPCFG)); 1220 writew(np->dspcfg, ioaddr + DSPCFG); 1221 writew(SDCFG_VAL, ioaddr + SDCFG); 1222 writew(0, ioaddr + PGSEL); 1223 readl(ioaddr + ChipConfig); 1224 udelay(10); 1225 1226 writew(1, ioaddr + PGSEL); 1227 dspcfg = readw(ioaddr + DSPCFG); 1228 writew(0, ioaddr + PGSEL); 1229 if (np->dspcfg == dspcfg) 1230 break; 1231 } 1232 1233 if (netif_msg_link(np)) { 1234 if (i==NATSEMI_HW_TIMEOUT) { 1235 printk(KERN_INFO 1236 "%s: DSPCFG mismatch after retrying for %d usec.\n", 1237 dev->name, i*10); 1238 } else { 1239 printk(KERN_INFO 1240 "%s: DSPCFG accepted after %d usec.\n", 1241 dev->name, i*10); 1242 } 1243 } 1244 /* 1245 * Enable PHY Specific event based interrupts. Link state change 1246 * and Auto-Negotiation Completion are among the affected. 1247 * Read the intr status to clear it (needed for wake events). 1248 */ 1249 readw(ioaddr + MIntrStatus); 1250 writew(MICRIntEn, ioaddr + MIntrCtrl); 1251} 1252 1253static int switch_port_external(struct net_device *dev) 1254{ 1255 struct netdev_private *np = netdev_priv(dev); 1256 void __iomem *ioaddr = ns_ioaddr(dev); 1257 u32 cfg; 1258 1259 cfg = readl(ioaddr + ChipConfig); 1260 if (cfg & CfgExtPhy) 1261 return 0; 1262 1263 if (netif_msg_link(np)) { 1264 printk(KERN_INFO "%s: switching to external transceiver.\n", 1265 dev->name); 1266 } 1267 1268 /* 1) switch back to external phy */ 1269 writel(cfg | (CfgExtPhy | CfgPhyDis), ioaddr + ChipConfig); 1270 readl(ioaddr + ChipConfig); 1271 udelay(1); 1272 1273 /* 2) reset the external phy: */ 1274 /* resetting the external PHY has been known to cause a hub supplying 1275 * power over Ethernet to kill the power. We don't want to kill 1276 * power to this computer, so we avoid resetting the phy. 1277 */ 1278 1279 /* 3) reinit the phy fixup, it got lost during power down. */ 1280 move_int_phy(dev, np->phy_addr_external); 1281 init_phy_fixup(dev); 1282 1283 return 1; 1284} 1285 1286static int switch_port_internal(struct net_device *dev) 1287{ 1288 struct netdev_private *np = netdev_priv(dev); 1289 void __iomem *ioaddr = ns_ioaddr(dev); 1290 int i; 1291 u32 cfg; 1292 u16 bmcr; 1293 1294 cfg = readl(ioaddr + ChipConfig); 1295 if (!(cfg &CfgExtPhy)) 1296 return 0; 1297 1298 if (netif_msg_link(np)) { 1299 printk(KERN_INFO "%s: switching to internal transceiver.\n", 1300 dev->name); 1301 } 1302 /* 1) switch back to internal phy: */ 1303 cfg = cfg & ~(CfgExtPhy | CfgPhyDis); 1304 writel(cfg, ioaddr + ChipConfig); 1305 readl(ioaddr + ChipConfig); 1306 udelay(1); 1307 1308 /* 2) reset the internal phy: */ 1309 bmcr = readw(ioaddr+BasicControl+(MII_BMCR<<2)); 1310 writel(bmcr | BMCR_RESET, ioaddr+BasicControl+(MII_BMCR<<2)); 1311 readl(ioaddr + ChipConfig); 1312 udelay(10); 1313 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) { 1314 bmcr = readw(ioaddr+BasicControl+(MII_BMCR<<2)); 1315 if (!(bmcr & BMCR_RESET)) 1316 break; 1317 udelay(10); 1318 } 1319 if (i==NATSEMI_HW_TIMEOUT && netif_msg_link(np)) { 1320 printk(KERN_INFO 1321 "%s: phy reset did not complete in %d usec.\n", 1322 dev->name, i*10); 1323 } 1324 /* 3) reinit the phy fixup, it got lost during power down. */ 1325 init_phy_fixup(dev); 1326 1327 return 1; 1328} 1329 1330/* Scan for a PHY on the external mii bus. 1331 * There are two tricky points: 1332 * - Do not scan while the internal phy is enabled. The internal phy will 1333 * crash: e.g. reads from the DSPCFG register will return odd values and 1334 * the nasty random phy reset code will reset the nic every few seconds. 1335 * - The internal phy must be moved around, an external phy could 1336 * have the same address as the internal phy. 1337 */ 1338static int find_mii(struct net_device *dev) 1339{ 1340 struct netdev_private *np = netdev_priv(dev); 1341 int tmp; 1342 int i; 1343 int did_switch; 1344 1345 /* Switch to external phy */ 1346 did_switch = switch_port_external(dev); 1347 1348 /* Scan the possible phy addresses: 1349 * 1350 * PHY address 0 means that the phy is in isolate mode. Not yet 1351 * supported due to lack of test hardware. User space should 1352 * handle it through ethtool. 1353 */ 1354 for (i = 1; i <= 31; i++) { 1355 move_int_phy(dev, i); 1356 tmp = miiport_read(dev, i, MII_BMSR); 1357 if (tmp != 0xffff && tmp != 0x0000) { 1358 /* found something! */ 1359 np->mii = (mdio_read(dev, MII_PHYSID1) << 16) 1360 + mdio_read(dev, MII_PHYSID2); 1361 if (netif_msg_probe(np)) { 1362 printk(KERN_INFO "natsemi %s: found external phy %08x at address %d.\n", 1363 pci_name(np->pci_dev), np->mii, i); 1364 } 1365 break; 1366 } 1367 } 1368 /* And switch back to internal phy: */ 1369 if (did_switch) 1370 switch_port_internal(dev); 1371 return i; 1372} 1373 1374/* CFG bits [13:16] [18:23] */ 1375#define CFG_RESET_SAVE 0xfde000 1376/* WCSR bits [0:4] [9:10] */ 1377#define WCSR_RESET_SAVE 0x61f 1378/* RFCR bits [20] [22] [27:31] */ 1379#define RFCR_RESET_SAVE 0xf8500000 1380 1381static void natsemi_reset(struct net_device *dev) 1382{ 1383 int i; 1384 u32 cfg; 1385 u32 wcsr; 1386 u32 rfcr; 1387 u16 pmatch[3]; 1388 u16 sopass[3]; 1389 struct netdev_private *np = netdev_priv(dev); 1390 void __iomem *ioaddr = ns_ioaddr(dev); 1391 1392 /* 1393 * Resetting the chip causes some registers to be lost. 1394 * Natsemi suggests NOT reloading the EEPROM while live, so instead 1395 * we save the state that would have been loaded from EEPROM 1396 * on a normal power-up (see the spec EEPROM map). This assumes 1397 * whoever calls this will follow up with init_registers() eventually. 1398 */ 1399 1400 /* CFG */ 1401 cfg = readl(ioaddr + ChipConfig) & CFG_RESET_SAVE; 1402 /* WCSR */ 1403 wcsr = readl(ioaddr + WOLCmd) & WCSR_RESET_SAVE; 1404 /* RFCR */ 1405 rfcr = readl(ioaddr + RxFilterAddr) & RFCR_RESET_SAVE; 1406 /* PMATCH */ 1407 for (i = 0; i < 3; i++) { 1408 writel(i*2, ioaddr + RxFilterAddr); 1409 pmatch[i] = readw(ioaddr + RxFilterData); 1410 } 1411 /* SOPAS */ 1412 for (i = 0; i < 3; i++) { 1413 writel(0xa+(i*2), ioaddr + RxFilterAddr); 1414 sopass[i] = readw(ioaddr + RxFilterData); 1415 } 1416 1417 /* now whack the chip */ 1418 writel(ChipReset, ioaddr + ChipCmd); 1419 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) { 1420 if (!(readl(ioaddr + ChipCmd) & ChipReset)) 1421 break; 1422 udelay(5); 1423 } 1424 if (i==NATSEMI_HW_TIMEOUT) { 1425 printk(KERN_WARNING "%s: reset did not complete in %d usec.\n", 1426 dev->name, i*5); 1427 } else if (netif_msg_hw(np)) { 1428 printk(KERN_DEBUG "%s: reset completed in %d usec.\n", 1429 dev->name, i*5); 1430 } 1431 1432 /* restore CFG */ 1433 cfg |= readl(ioaddr + ChipConfig) & ~CFG_RESET_SAVE; 1434 /* turn on external phy if it was selected */ 1435 if (dev->if_port == PORT_TP) 1436 cfg &= ~(CfgExtPhy | CfgPhyDis); 1437 else 1438 cfg |= (CfgExtPhy | CfgPhyDis); 1439 writel(cfg, ioaddr + ChipConfig); 1440 /* restore WCSR */ 1441 wcsr |= readl(ioaddr + WOLCmd) & ~WCSR_RESET_SAVE; 1442 writel(wcsr, ioaddr + WOLCmd); 1443 /* read RFCR */ 1444 rfcr |= readl(ioaddr + RxFilterAddr) & ~RFCR_RESET_SAVE; 1445 /* restore PMATCH */ 1446 for (i = 0; i < 3; i++) { 1447 writel(i*2, ioaddr + RxFilterAddr); 1448 writew(pmatch[i], ioaddr + RxFilterData); 1449 } 1450 for (i = 0; i < 3; i++) { 1451 writel(0xa+(i*2), ioaddr + RxFilterAddr); 1452 writew(sopass[i], ioaddr + RxFilterData); 1453 } 1454 /* restore RFCR */ 1455 writel(rfcr, ioaddr + RxFilterAddr); 1456} 1457 1458static void reset_rx(struct net_device *dev) 1459{ 1460 int i; 1461 struct netdev_private *np = netdev_priv(dev); 1462 void __iomem *ioaddr = ns_ioaddr(dev); 1463 1464 np->intr_status &= ~RxResetDone; 1465 1466 writel(RxReset, ioaddr + ChipCmd); 1467 1468 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) { 1469 np->intr_status |= readl(ioaddr + IntrStatus); 1470 if (np->intr_status & RxResetDone) 1471 break; 1472 udelay(15); 1473 } 1474 if (i==NATSEMI_HW_TIMEOUT) { 1475 printk(KERN_WARNING "%s: RX reset did not complete in %d usec.\n", 1476 dev->name, i*15); 1477 } else if (netif_msg_hw(np)) { 1478 printk(KERN_WARNING "%s: RX reset took %d usec.\n", 1479 dev->name, i*15); 1480 } 1481} 1482 1483static void natsemi_reload_eeprom(struct net_device *dev) 1484{ 1485 struct netdev_private *np = netdev_priv(dev); 1486 void __iomem *ioaddr = ns_ioaddr(dev); 1487 int i; 1488 1489 writel(EepromReload, ioaddr + PCIBusCfg); 1490 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) { 1491 udelay(50); 1492 if (!(readl(ioaddr + PCIBusCfg) & EepromReload)) 1493 break; 1494 } 1495 if (i==NATSEMI_HW_TIMEOUT) { 1496 printk(KERN_WARNING "natsemi %s: EEPROM did not reload in %d usec.\n", 1497 pci_name(np->pci_dev), i*50); 1498 } else if (netif_msg_hw(np)) { 1499 printk(KERN_DEBUG "natsemi %s: EEPROM reloaded in %d usec.\n", 1500 pci_name(np->pci_dev), i*50); 1501 } 1502} 1503 1504static void natsemi_stop_rxtx(struct net_device *dev) 1505{ 1506 void __iomem * ioaddr = ns_ioaddr(dev); 1507 struct netdev_private *np = netdev_priv(dev); 1508 int i; 1509 1510 writel(RxOff | TxOff, ioaddr + ChipCmd); 1511 for(i=0;i< NATSEMI_HW_TIMEOUT;i++) { 1512 if ((readl(ioaddr + ChipCmd) & (TxOn|RxOn)) == 0) 1513 break; 1514 udelay(5); 1515 } 1516 if (i==NATSEMI_HW_TIMEOUT) { 1517 printk(KERN_WARNING "%s: Tx/Rx process did not stop in %d usec.\n", 1518 dev->name, i*5); 1519 } else if (netif_msg_hw(np)) { 1520 printk(KERN_DEBUG "%s: Tx/Rx process stopped in %d usec.\n", 1521 dev->name, i*5); 1522 } 1523} 1524 1525static int netdev_open(struct net_device *dev) 1526{ 1527 struct netdev_private *np = netdev_priv(dev); 1528 void __iomem * ioaddr = ns_ioaddr(dev); 1529 const int irq = np->pci_dev->irq; 1530 int i; 1531 1532 /* Reset the chip, just in case. */ 1533 natsemi_reset(dev); 1534 1535 i = request_irq(irq, intr_handler, IRQF_SHARED, dev->name, dev); 1536 if (i) return i; 1537 1538 if (netif_msg_ifup(np)) 1539 printk(KERN_DEBUG "%s: netdev_open() irq %d.\n", 1540 dev->name, irq); 1541 i = alloc_ring(dev); 1542 if (i < 0) { 1543 free_irq(irq, dev); 1544 return i; 1545 } 1546 napi_enable(&np->napi); 1547 1548 init_ring(dev); 1549 spin_lock_irq(&np->lock); 1550 init_registers(dev); 1551 /* now set the MAC address according to dev->dev_addr */ 1552 for (i = 0; i < 3; i++) { 1553 u16 mac = (dev->dev_addr[2*i+1]<<8) + dev->dev_addr[2*i]; 1554 1555 writel(i*2, ioaddr + RxFilterAddr); 1556 writew(mac, ioaddr + RxFilterData); 1557 } 1558 writel(np->cur_rx_mode, ioaddr + RxFilterAddr); 1559 spin_unlock_irq(&np->lock); 1560 1561 netif_start_queue(dev); 1562 1563 if (netif_msg_ifup(np)) 1564 printk(KERN_DEBUG "%s: Done netdev_open(), status: %#08x.\n", 1565 dev->name, (int)readl(ioaddr + ChipCmd)); 1566 1567 /* Set the timer to check for link beat. */ 1568 init_timer(&np->timer); 1569 np->timer.expires = round_jiffies(jiffies + NATSEMI_TIMER_FREQ); 1570 np->timer.data = (unsigned long)dev; 1571 np->timer.function = netdev_timer; /* timer handler */ 1572 add_timer(&np->timer); 1573 1574 return 0; 1575} 1576 1577static void do_cable_magic(struct net_device *dev) 1578{ 1579 struct netdev_private *np = netdev_priv(dev); 1580 void __iomem *ioaddr = ns_ioaddr(dev); 1581 1582 if (dev->if_port != PORT_TP) 1583 return; 1584 1585 if (np->srr >= SRR_DP83816_A5) 1586 return; 1587 1588 /* 1589 * 100 MBit links with short cables can trip an issue with the chip. 1590 * The problem manifests as lots of CRC errors and/or flickering 1591 * activity LED while idle. This process is based on instructions 1592 * from engineers at National. 1593 */ 1594 if (readl(ioaddr + ChipConfig) & CfgSpeed100) { 1595 u16 data; 1596 1597 writew(1, ioaddr + PGSEL); 1598 /* 1599 * coefficient visibility should already be enabled via 1600 * DSPCFG | 0x1000 1601 */ 1602 data = readw(ioaddr + TSTDAT) & 0xff; 1603 /* 1604 * the value must be negative, and within certain values 1605 * (these values all come from National) 1606 */ 1607 if (!(data & 0x80) || ((data >= 0xd8) && (data <= 0xff))) { 1608 np = netdev_priv(dev); 1609 1610 /* the bug has been triggered - fix the coefficient */ 1611 writew(TSTDAT_FIXED, ioaddr + TSTDAT); 1612 /* lock the value */ 1613 data = readw(ioaddr + DSPCFG); 1614 np->dspcfg = data | DSPCFG_LOCK; 1615 writew(np->dspcfg, ioaddr + DSPCFG); 1616 } 1617 writew(0, ioaddr + PGSEL); 1618 } 1619} 1620 1621static void undo_cable_magic(struct net_device *dev) 1622{ 1623 u16 data; 1624 struct netdev_private *np = netdev_priv(dev); 1625 void __iomem * ioaddr = ns_ioaddr(dev); 1626 1627 if (dev->if_port != PORT_TP) 1628 return; 1629 1630 if (np->srr >= SRR_DP83816_A5) 1631 return; 1632 1633 writew(1, ioaddr + PGSEL); 1634 /* make sure the lock bit is clear */ 1635 data = readw(ioaddr + DSPCFG); 1636 np->dspcfg = data & ~DSPCFG_LOCK; 1637 writew(np->dspcfg, ioaddr + DSPCFG); 1638 writew(0, ioaddr + PGSEL); 1639} 1640 1641static void check_link(struct net_device *dev) 1642{ 1643 struct netdev_private *np = netdev_priv(dev); 1644 void __iomem * ioaddr = ns_ioaddr(dev); 1645 int duplex = np->duplex; 1646 u16 bmsr; 1647 1648 /* If we are ignoring the PHY then don't try reading it. */ 1649 if (np->ignore_phy) 1650 goto propagate_state; 1651 1652 /* The link status field is latched: it remains low after a temporary 1653 * link failure until it's read. We need the current link status, 1654 * thus read twice. 1655 */ 1656 mdio_read(dev, MII_BMSR); 1657 bmsr = mdio_read(dev, MII_BMSR); 1658 1659 if (!(bmsr & BMSR_LSTATUS)) { 1660 if (netif_carrier_ok(dev)) { 1661 if (netif_msg_link(np)) 1662 printk(KERN_NOTICE "%s: link down.\n", 1663 dev->name); 1664 netif_carrier_off(dev); 1665 undo_cable_magic(dev); 1666 } 1667 return; 1668 } 1669 if (!netif_carrier_ok(dev)) { 1670 if (netif_msg_link(np)) 1671 printk(KERN_NOTICE "%s: link up.\n", dev->name); 1672 netif_carrier_on(dev); 1673 do_cable_magic(dev); 1674 } 1675 1676 duplex = np->full_duplex; 1677 if (!duplex) { 1678 if (bmsr & BMSR_ANEGCOMPLETE) { 1679 int tmp = mii_nway_result( 1680 np->advertising & mdio_read(dev, MII_LPA)); 1681 if (tmp == LPA_100FULL || tmp == LPA_10FULL) 1682 duplex = 1; 1683 } else if (mdio_read(dev, MII_BMCR) & BMCR_FULLDPLX) 1684 duplex = 1; 1685 } 1686 1687propagate_state: 1688 /* if duplex is set then bit 28 must be set, too */ 1689 if (duplex ^ !!(np->rx_config & RxAcceptTx)) { 1690 if (netif_msg_link(np)) 1691 printk(KERN_INFO 1692 "%s: Setting %s-duplex based on negotiated " 1693 "link capability.\n", dev->name, 1694 duplex ? "full" : "half"); 1695 if (duplex) { 1696 np->rx_config |= RxAcceptTx; 1697 np->tx_config |= TxCarrierIgn | TxHeartIgn; 1698 } else { 1699 np->rx_config &= ~RxAcceptTx; 1700 np->tx_config &= ~(TxCarrierIgn | TxHeartIgn); 1701 } 1702 writel(np->tx_config, ioaddr + TxConfig); 1703 writel(np->rx_config, ioaddr + RxConfig); 1704 } 1705} 1706 1707static void init_registers(struct net_device *dev) 1708{ 1709 struct netdev_private *np = netdev_priv(dev); 1710 void __iomem * ioaddr = ns_ioaddr(dev); 1711 1712 init_phy_fixup(dev); 1713 1714 /* clear any interrupts that are pending, such as wake events */ 1715 readl(ioaddr + IntrStatus); 1716 1717 writel(np->ring_dma, ioaddr + RxRingPtr); 1718 writel(np->ring_dma + RX_RING_SIZE * sizeof(struct netdev_desc), 1719 ioaddr + TxRingPtr); 1720 1721 /* Initialize other registers. 1722 * Configure the PCI bus bursts and FIFO thresholds. 1723 * Configure for standard, in-spec Ethernet. 1724 * Start with half-duplex. check_link will update 1725 * to the correct settings. 1726 */ 1727 1728 /* DRTH: 2: start tx if 64 bytes are in the fifo 1729 * FLTH: 0x10: refill with next packet if 512 bytes are free 1730 * MXDMA: 0: up to 256 byte bursts. 1731 * MXDMA must be <= FLTH 1732 * ECRETRY=1 1733 * ATP=1 1734 */ 1735 np->tx_config = TxAutoPad | TxCollRetry | TxMxdma_256 | 1736 TX_FLTH_VAL | TX_DRTH_VAL_START; 1737 writel(np->tx_config, ioaddr + TxConfig); 1738 1739 /* DRTH 0x10: start copying to memory if 128 bytes are in the fifo 1740 * MXDMA 0: up to 256 byte bursts 1741 */ 1742 np->rx_config = RxMxdma_256 | RX_DRTH_VAL; 1743 /* if receive ring now has bigger buffers than normal, enable jumbo */ 1744 if (np->rx_buf_sz > NATSEMI_LONGPKT) 1745 np->rx_config |= RxAcceptLong; 1746 1747 writel(np->rx_config, ioaddr + RxConfig); 1748 1749 /* Disable PME: 1750 * The PME bit is initialized from the EEPROM contents. 1751 * PCI cards probably have PME disabled, but motherboard 1752 * implementations may have PME set to enable WakeOnLan. 1753 * With PME set the chip will scan incoming packets but 1754 * nothing will be written to memory. */ 1755 np->SavedClkRun = readl(ioaddr + ClkRun); 1756 writel(np->SavedClkRun & ~PMEEnable, ioaddr + ClkRun); 1757 if (np->SavedClkRun & PMEStatus && netif_msg_wol(np)) { 1758 printk(KERN_NOTICE "%s: Wake-up event %#08x\n", 1759 dev->name, readl(ioaddr + WOLCmd)); 1760 } 1761 1762 check_link(dev); 1763 __set_rx_mode(dev); 1764 1765 /* Enable interrupts by setting the interrupt mask. */ 1766 writel(DEFAULT_INTR, ioaddr + IntrMask); 1767 natsemi_irq_enable(dev); 1768 1769 writel(RxOn | TxOn, ioaddr + ChipCmd); 1770 writel(StatsClear, ioaddr + StatsCtrl); /* Clear Stats */ 1771} 1772 1773/* 1774 * netdev_timer: 1775 * Purpose: 1776 * 1) check for link changes. Usually they are handled by the MII interrupt 1777 * but it doesn't hurt to check twice. 1778 * 2) check for sudden death of the NIC: 1779 * It seems that a reference set for this chip went out with incorrect info, 1780 * and there exist boards that aren't quite right. An unexpected voltage 1781 * drop can cause the PHY to get itself in a weird state (basically reset). 1782 * NOTE: this only seems to affect revC chips. The user can disable 1783 * this check via dspcfg_workaround sysfs option. 1784 * 3) check of death of the RX path due to OOM 1785 */ 1786static void netdev_timer(unsigned long data) 1787{ 1788 struct net_device *dev = (struct net_device *)data; 1789 struct netdev_private *np = netdev_priv(dev); 1790 void __iomem * ioaddr = ns_ioaddr(dev); 1791 int next_tick = NATSEMI_TIMER_FREQ; 1792 const int irq = np->pci_dev->irq; 1793 1794 if (netif_msg_timer(np)) { 1795 /* DO NOT read the IntrStatus register, 1796 * a read clears any pending interrupts. 1797 */ 1798 printk(KERN_DEBUG "%s: Media selection timer tick.\n", 1799 dev->name); 1800 } 1801 1802 if (dev->if_port == PORT_TP) { 1803 u16 dspcfg; 1804 1805 spin_lock_irq(&np->lock); 1806 /* check for a nasty random phy-reset - use dspcfg as a flag */ 1807 writew(1, ioaddr+PGSEL); 1808 dspcfg = readw(ioaddr+DSPCFG); 1809 writew(0, ioaddr+PGSEL); 1810 if (np->dspcfg_workaround && dspcfg != np->dspcfg) { 1811 if (!netif_queue_stopped(dev)) { 1812 spin_unlock_irq(&np->lock); 1813 if (netif_msg_drv(np)) 1814 printk(KERN_NOTICE "%s: possible phy reset: " 1815 "re-initializing\n", dev->name); 1816 disable_irq(irq); 1817 spin_lock_irq(&np->lock); 1818 natsemi_stop_rxtx(dev); 1819 dump_ring(dev); 1820 reinit_ring(dev); 1821 init_registers(dev); 1822 spin_unlock_irq(&np->lock); 1823 enable_irq(irq); 1824 } else { 1825 /* hurry back */ 1826 next_tick = HZ; 1827 spin_unlock_irq(&np->lock); 1828 } 1829 } else { 1830 /* init_registers() calls check_link() for the above case */ 1831 check_link(dev); 1832 spin_unlock_irq(&np->lock); 1833 } 1834 } else { 1835 spin_lock_irq(&np->lock); 1836 check_link(dev); 1837 spin_unlock_irq(&np->lock); 1838 } 1839 if (np->oom) { 1840 disable_irq(irq); 1841 np->oom = 0; 1842 refill_rx(dev); 1843 enable_irq(irq); 1844 if (!np->oom) { 1845 writel(RxOn, ioaddr + ChipCmd); 1846 } else { 1847 next_tick = 1; 1848 } 1849 } 1850 1851 if (next_tick > 1) 1852 mod_timer(&np->timer, round_jiffies(jiffies + next_tick)); 1853 else 1854 mod_timer(&np->timer, jiffies + next_tick); 1855} 1856 1857static void dump_ring(struct net_device *dev) 1858{ 1859 struct netdev_private *np = netdev_priv(dev); 1860 1861 if (netif_msg_pktdata(np)) { 1862 int i; 1863 printk(KERN_DEBUG " Tx ring at %p:\n", np->tx_ring); 1864 for (i = 0; i < TX_RING_SIZE; i++) { 1865 printk(KERN_DEBUG " #%d desc. %#08x %#08x %#08x.\n", 1866 i, np->tx_ring[i].next_desc, 1867 np->tx_ring[i].cmd_status, 1868 np->tx_ring[i].addr); 1869 } 1870 printk(KERN_DEBUG " Rx ring %p:\n", np->rx_ring); 1871 for (i = 0; i < RX_RING_SIZE; i++) { 1872 printk(KERN_DEBUG " #%d desc. %#08x %#08x %#08x.\n", 1873 i, np->rx_ring[i].next_desc, 1874 np->rx_ring[i].cmd_status, 1875 np->rx_ring[i].addr); 1876 } 1877 } 1878} 1879 1880static void ns_tx_timeout(struct net_device *dev) 1881{ 1882 struct netdev_private *np = netdev_priv(dev); 1883 void __iomem * ioaddr = ns_ioaddr(dev); 1884 const int irq = np->pci_dev->irq; 1885 1886 disable_irq(irq); 1887 spin_lock_irq(&np->lock); 1888 if (!np->hands_off) { 1889 if (netif_msg_tx_err(np)) 1890 printk(KERN_WARNING 1891 "%s: Transmit timed out, status %#08x," 1892 " resetting...\n", 1893 dev->name, readl(ioaddr + IntrStatus)); 1894 dump_ring(dev); 1895 1896 natsemi_reset(dev); 1897 reinit_ring(dev); 1898 init_registers(dev); 1899 } else { 1900 printk(KERN_WARNING 1901 "%s: tx_timeout while in hands_off state?\n", 1902 dev->name); 1903 } 1904 spin_unlock_irq(&np->lock); 1905 enable_irq(irq); 1906 1907 dev->trans_start = jiffies; /* prevent tx timeout */ 1908 dev->stats.tx_errors++; 1909 netif_wake_queue(dev); 1910} 1911 1912static int alloc_ring(struct net_device *dev) 1913{ 1914 struct netdev_private *np = netdev_priv(dev); 1915 np->rx_ring = pci_alloc_consistent(np->pci_dev, 1916 sizeof(struct netdev_desc) * (RX_RING_SIZE+TX_RING_SIZE), 1917 &np->ring_dma); 1918 if (!np->rx_ring) 1919 return -ENOMEM; 1920 np->tx_ring = &np->rx_ring[RX_RING_SIZE]; 1921 return 0; 1922} 1923 1924static void refill_rx(struct net_device *dev) 1925{ 1926 struct netdev_private *np = netdev_priv(dev); 1927 1928 /* Refill the Rx ring buffers. */ 1929 for (; np->cur_rx - np->dirty_rx > 0; np->dirty_rx++) { 1930 struct sk_buff *skb; 1931 int entry = np->dirty_rx % RX_RING_SIZE; 1932 if (np->rx_skbuff[entry] == NULL) { 1933 unsigned int buflen = np->rx_buf_sz+NATSEMI_PADDING; 1934 skb = netdev_alloc_skb(dev, buflen); 1935 np->rx_skbuff[entry] = skb; 1936 if (skb == NULL) 1937 break; /* Better luck next round. */ 1938 np->rx_dma[entry] = pci_map_single(np->pci_dev, 1939 skb->data, buflen, PCI_DMA_FROMDEVICE); 1940 np->rx_ring[entry].addr = cpu_to_le32(np->rx_dma[entry]); 1941 } 1942 np->rx_ring[entry].cmd_status = cpu_to_le32(np->rx_buf_sz); 1943 } 1944 if (np->cur_rx - np->dirty_rx == RX_RING_SIZE) { 1945 if (netif_msg_rx_err(np)) 1946 printk(KERN_WARNING "%s: going OOM.\n", dev->name); 1947 np->oom = 1; 1948 } 1949} 1950 1951static void set_bufsize(struct net_device *dev) 1952{ 1953 struct netdev_private *np = netdev_priv(dev); 1954 if (dev->mtu <= ETH_DATA_LEN) 1955 np->rx_buf_sz = ETH_DATA_LEN + NATSEMI_HEADERS; 1956 else 1957 np->rx_buf_sz = dev->mtu + NATSEMI_HEADERS; 1958} 1959 1960/* Initialize the Rx and Tx rings, along with various 'dev' bits. */ 1961static void init_ring(struct net_device *dev) 1962{ 1963 struct netdev_private *np = netdev_priv(dev); 1964 int i; 1965 1966 /* 1) TX ring */ 1967 np->dirty_tx = np->cur_tx = 0; 1968 for (i = 0; i < TX_RING_SIZE; i++) { 1969 np->tx_skbuff[i] = NULL; 1970 np->tx_ring[i].next_desc = cpu_to_le32(np->ring_dma 1971 +sizeof(struct netdev_desc) 1972 *((i+1)%TX_RING_SIZE+RX_RING_SIZE)); 1973 np->tx_ring[i].cmd_status = 0; 1974 } 1975 1976 /* 2) RX ring */ 1977 np->dirty_rx = 0; 1978 np->cur_rx = RX_RING_SIZE; 1979 np->oom = 0; 1980 set_bufsize(dev); 1981 1982 np->rx_head_desc = &np->rx_ring[0]; 1983 1984 /* Please be careful before changing this loop - at least gcc-2.95.1 1985 * miscompiles it otherwise. 1986 */ 1987 /* Initialize all Rx descriptors. */ 1988 for (i = 0; i < RX_RING_SIZE; i++) { 1989 np->rx_ring[i].next_desc = cpu_to_le32(np->ring_dma 1990 +sizeof(struct netdev_desc) 1991 *((i+1)%RX_RING_SIZE)); 1992 np->rx_ring[i].cmd_status = cpu_to_le32(DescOwn); 1993 np->rx_skbuff[i] = NULL; 1994 } 1995 refill_rx(dev); 1996 dump_ring(dev); 1997} 1998 1999static void drain_tx(struct net_device *dev) 2000{ 2001 struct netdev_private *np = netdev_priv(dev); 2002 int i; 2003 2004 for (i = 0; i < TX_RING_SIZE; i++) { 2005 if (np->tx_skbuff[i]) { 2006 pci_unmap_single(np->pci_dev, 2007 np->tx_dma[i], np->tx_skbuff[i]->len, 2008 PCI_DMA_TODEVICE); 2009 dev_kfree_skb(np->tx_skbuff[i]); 2010 dev->stats.tx_dropped++; 2011 } 2012 np->tx_skbuff[i] = NULL; 2013 } 2014} 2015 2016static void drain_rx(struct net_device *dev) 2017{ 2018 struct netdev_private *np = netdev_priv(dev); 2019 unsigned int buflen = np->rx_buf_sz; 2020 int i; 2021 2022 /* Free all the skbuffs in the Rx queue. */ 2023 for (i = 0; i < RX_RING_SIZE; i++) { 2024 np->rx_ring[i].cmd_status = 0; 2025 np->rx_ring[i].addr = cpu_to_le32(0xBADF00D0); /* An invalid address. */ 2026 if (np->rx_skbuff[i]) { 2027 pci_unmap_single(np->pci_dev, np->rx_dma[i], 2028 buflen + NATSEMI_PADDING, 2029 PCI_DMA_FROMDEVICE); 2030 dev_kfree_skb(np->rx_skbuff[i]); 2031 } 2032 np->rx_skbuff[i] = NULL; 2033 } 2034} 2035 2036static void drain_ring(struct net_device *dev) 2037{ 2038 drain_rx(dev); 2039 drain_tx(dev); 2040} 2041 2042static void free_ring(struct net_device *dev) 2043{ 2044 struct netdev_private *np = netdev_priv(dev); 2045 pci_free_consistent(np->pci_dev, 2046 sizeof(struct netdev_desc) * (RX_RING_SIZE+TX_RING_SIZE), 2047 np->rx_ring, np->ring_dma); 2048} 2049 2050static void reinit_rx(struct net_device *dev) 2051{ 2052 struct netdev_private *np = netdev_priv(dev); 2053 int i; 2054 2055 /* RX Ring */ 2056 np->dirty_rx = 0; 2057 np->cur_rx = RX_RING_SIZE; 2058 np->rx_head_desc = &np->rx_ring[0]; 2059 /* Initialize all Rx descriptors. */ 2060 for (i = 0; i < RX_RING_SIZE; i++) 2061 np->rx_ring[i].cmd_status = cpu_to_le32(DescOwn); 2062 2063 refill_rx(dev); 2064} 2065 2066static void reinit_ring(struct net_device *dev) 2067{ 2068 struct netdev_private *np = netdev_priv(dev); 2069 int i; 2070 2071 /* drain TX ring */ 2072 drain_tx(dev); 2073 np->dirty_tx = np->cur_tx = 0; 2074 for (i=0;i<TX_RING_SIZE;i++) 2075 np->tx_ring[i].cmd_status = 0; 2076 2077 reinit_rx(dev); 2078} 2079 2080static netdev_tx_t start_tx(struct sk_buff *skb, struct net_device *dev) 2081{ 2082 struct netdev_private *np = netdev_priv(dev); 2083 void __iomem * ioaddr = ns_ioaddr(dev); 2084 unsigned entry; 2085 unsigned long flags; 2086 2087 /* Note: Ordering is important here, set the field with the 2088 "ownership" bit last, and only then increment cur_tx. */ 2089 2090 /* Calculate the next Tx descriptor entry. */ 2091 entry = np->cur_tx % TX_RING_SIZE; 2092 2093 np->tx_skbuff[entry] = skb; 2094 np->tx_dma[entry] = pci_map_single(np->pci_dev, 2095 skb->data,skb->len, PCI_DMA_TODEVICE); 2096 2097 np->tx_ring[entry].addr = cpu_to_le32(np->tx_dma[entry]); 2098 2099 spin_lock_irqsave(&np->lock, flags); 2100 2101 if (!np->hands_off) { 2102 np->tx_ring[entry].cmd_status = cpu_to_le32(DescOwn | skb->len); 2103 /* StrongARM: Explicitly cache flush np->tx_ring and 2104 * skb->data,skb->len. */ 2105 wmb(); 2106 np->cur_tx++; 2107 if (np->cur_tx - np->dirty_tx >= TX_QUEUE_LEN - 1) { 2108 netdev_tx_done(dev); 2109 if (np->cur_tx - np->dirty_tx >= TX_QUEUE_LEN - 1) 2110 netif_stop_queue(dev); 2111 } 2112 /* Wake the potentially-idle transmit channel. */ 2113 writel(TxOn, ioaddr + ChipCmd); 2114 } else { 2115 dev_kfree_skb_irq(skb); 2116 dev->stats.tx_dropped++; 2117 } 2118 spin_unlock_irqrestore(&np->lock, flags); 2119 2120 if (netif_msg_tx_queued(np)) { 2121 printk(KERN_DEBUG "%s: Transmit frame #%d queued in slot %d.\n", 2122 dev->name, np->cur_tx, entry); 2123 } 2124 return NETDEV_TX_OK; 2125} 2126 2127static void netdev_tx_done(struct net_device *dev) 2128{ 2129 struct netdev_private *np = netdev_priv(dev); 2130 2131 for (; np->cur_tx - np->dirty_tx > 0; np->dirty_tx++) { 2132 int entry = np->dirty_tx % TX_RING_SIZE; 2133 if (np->tx_ring[entry].cmd_status & cpu_to_le32(DescOwn)) 2134 break; 2135 if (netif_msg_tx_done(np)) 2136 printk(KERN_DEBUG 2137 "%s: tx frame #%d finished, status %#08x.\n", 2138 dev->name, np->dirty_tx, 2139 le32_to_cpu(np->tx_ring[entry].cmd_status)); 2140 if (np->tx_ring[entry].cmd_status & cpu_to_le32(DescPktOK)) { 2141 dev->stats.tx_packets++; 2142 dev->stats.tx_bytes += np->tx_skbuff[entry]->len; 2143 } else { /* Various Tx errors */ 2144 int tx_status = 2145 le32_to_cpu(np->tx_ring[entry].cmd_status); 2146 if (tx_status & (DescTxAbort|DescTxExcColl)) 2147 dev->stats.tx_aborted_errors++; 2148 if (tx_status & DescTxFIFO) 2149 dev->stats.tx_fifo_errors++; 2150 if (tx_status & DescTxCarrier) 2151 dev->stats.tx_carrier_errors++; 2152 if (tx_status & DescTxOOWCol) 2153 dev->stats.tx_window_errors++; 2154 dev->stats.tx_errors++; 2155 } 2156 pci_unmap_single(np->pci_dev,np->tx_dma[entry], 2157 np->tx_skbuff[entry]->len, 2158 PCI_DMA_TODEVICE); 2159 /* Free the original skb. */ 2160 dev_kfree_skb_irq(np->tx_skbuff[entry]); 2161 np->tx_skbuff[entry] = NULL; 2162 } 2163 if (netif_queue_stopped(dev) && 2164 np->cur_tx - np->dirty_tx < TX_QUEUE_LEN - 4) { 2165 /* The ring is no longer full, wake queue. */ 2166 netif_wake_queue(dev); 2167 } 2168} 2169 2170/* The interrupt handler doesn't actually handle interrupts itself, it 2171 * schedules a NAPI poll if there is anything to do. */ 2172static irqreturn_t intr_handler(int irq, void *dev_instance) 2173{ 2174 struct net_device *dev = dev_instance; 2175 struct netdev_private *np = netdev_priv(dev); 2176 void __iomem * ioaddr = ns_ioaddr(dev); 2177 2178 /* Reading IntrStatus automatically acknowledges so don't do 2179 * that while interrupts are disabled, (for example, while a 2180 * poll is scheduled). */ 2181 if (np->hands_off || !readl(ioaddr + IntrEnable)) 2182 return IRQ_NONE; 2183 2184 np->intr_status = readl(ioaddr + IntrStatus); 2185 2186 if (!np->intr_status) 2187 return IRQ_NONE; 2188 2189 if (netif_msg_intr(np)) 2190 printk(KERN_DEBUG 2191 "%s: Interrupt, status %#08x, mask %#08x.\n", 2192 dev->name, np->intr_status, 2193 readl(ioaddr + IntrMask)); 2194 2195 prefetch(&np->rx_skbuff[np->cur_rx % RX_RING_SIZE]); 2196 2197 if (napi_schedule_prep(&np->napi)) { 2198 /* Disable interrupts and register for poll */ 2199 natsemi_irq_disable(dev); 2200 __napi_schedule(&np->napi); 2201 } else 2202 printk(KERN_WARNING 2203 "%s: Ignoring interrupt, status %#08x, mask %#08x.\n", 2204 dev->name, np->intr_status, 2205 readl(ioaddr + IntrMask)); 2206 2207 return IRQ_HANDLED; 2208} 2209 2210/* This is the NAPI poll routine. As well as the standard RX handling 2211 * it also handles all other interrupts that the chip might raise. 2212 */ 2213static int natsemi_poll(struct napi_struct *napi, int budget) 2214{ 2215 struct netdev_private *np = container_of(napi, struct netdev_private, napi); 2216 struct net_device *dev = np->dev; 2217 void __iomem * ioaddr = ns_ioaddr(dev); 2218 int work_done = 0; 2219 2220 do { 2221 if (netif_msg_intr(np)) 2222 printk(KERN_DEBUG 2223 "%s: Poll, status %#08x, mask %#08x.\n", 2224 dev->name, np->intr_status, 2225 readl(ioaddr + IntrMask)); 2226 2227 /* netdev_rx() may read IntrStatus again if the RX state 2228 * machine falls over so do it first. */ 2229 if (np->intr_status & 2230 (IntrRxDone | IntrRxIntr | RxStatusFIFOOver | 2231 IntrRxErr | IntrRxOverrun)) { 2232 netdev_rx(dev, &work_done, budget); 2233 } 2234 2235 if (np->intr_status & 2236 (IntrTxDone | IntrTxIntr | IntrTxIdle | IntrTxErr)) { 2237 spin_lock(&np->lock); 2238 netdev_tx_done(dev); 2239 spin_unlock(&np->lock); 2240 } 2241 2242 /* Abnormal error summary/uncommon events handlers. */ 2243 if (np->intr_status & IntrAbnormalSummary) 2244 netdev_error(dev, np->intr_status); 2245 2246 if (work_done >= budget) 2247 return work_done; 2248 2249 np->intr_status = readl(ioaddr + IntrStatus); 2250 } while (np->intr_status); 2251 2252 napi_complete(napi); 2253 2254 /* Reenable interrupts providing nothing is trying to shut 2255 * the chip down. */ 2256 spin_lock(&np->lock); 2257 if (!np->hands_off) 2258 natsemi_irq_enable(dev); 2259 spin_unlock(&np->lock); 2260 2261 return work_done; 2262} 2263 2264/* This routine is logically part of the interrupt handler, but separated 2265 for clarity and better register allocation. */ 2266static void netdev_rx(struct net_device *dev, int *work_done, int work_to_do) 2267{ 2268 struct netdev_private *np = netdev_priv(dev); 2269 int entry = np->cur_rx % RX_RING_SIZE; 2270 int boguscnt = np->dirty_rx + RX_RING_SIZE - np->cur_rx; 2271 s32 desc_status = le32_to_cpu(np->rx_head_desc->cmd_status); 2272 unsigned int buflen = np->rx_buf_sz; 2273 void __iomem * ioaddr = ns_ioaddr(dev); 2274 2275 /* If the driver owns the next entry it's a new packet. Send it up. */ 2276 while (desc_status < 0) { /* e.g. & DescOwn */ 2277 int pkt_len; 2278 if (netif_msg_rx_status(np)) 2279 printk(KERN_DEBUG 2280 " netdev_rx() entry %d status was %#08x.\n", 2281 entry, desc_status); 2282 if (--boguscnt < 0) 2283 break; 2284 2285 if (*work_done >= work_to_do) 2286 break; 2287 2288 (*work_done)++; 2289 2290 pkt_len = (desc_status & DescSizeMask) - 4; 2291 if ((desc_status&(DescMore|DescPktOK|DescRxLong)) != DescPktOK){ 2292 if (desc_status & DescMore) { 2293 unsigned long flags; 2294 2295 if (netif_msg_rx_err(np)) 2296 printk(KERN_WARNING 2297 "%s: Oversized(?) Ethernet " 2298 "frame spanned multiple " 2299 "buffers, entry %#08x " 2300 "status %#08x.\n", dev->name, 2301 np->cur_rx, desc_status); 2302 dev->stats.rx_length_errors++; 2303 2304 /* The RX state machine has probably 2305 * locked up beneath us. Follow the 2306 * reset procedure documented in 2307 * AN-1287. */ 2308 2309 spin_lock_irqsave(&np->lock, flags); 2310 reset_rx(dev); 2311 reinit_rx(dev); 2312 writel(np->ring_dma, ioaddr + RxRingPtr); 2313 check_link(dev); 2314 spin_unlock_irqrestore(&np->lock, flags); 2315 2316 /* We'll enable RX on exit from this 2317 * function. */ 2318 break; 2319 2320 } else { 2321 /* There was an error. */ 2322 dev->stats.rx_errors++; 2323 if (desc_status & (DescRxAbort|DescRxOver)) 2324 dev->stats.rx_over_errors++; 2325 if (desc_status & (DescRxLong|DescRxRunt)) 2326 dev->stats.rx_length_errors++; 2327 if (desc_status & (DescRxInvalid|DescRxAlign)) 2328 dev->stats.rx_frame_errors++; 2329 if (desc_status & DescRxCRC) 2330 dev->stats.rx_crc_errors++; 2331 } 2332 } else if (pkt_len > np->rx_buf_sz) { 2333 /* if this is the tail of a double buffer 2334 * packet, we've already counted the error 2335 * on the first part. Ignore the second half. 2336 */ 2337 } else { 2338 struct sk_buff *skb; 2339 /* Omit CRC size. */ 2340 /* Check if the packet is long enough to accept 2341 * without copying to a minimally-sized skbuff. */ 2342 if (pkt_len < rx_copybreak && 2343 (skb = netdev_alloc_skb(dev, pkt_len + RX_OFFSET)) != NULL) { 2344 /* 16 byte align the IP header */ 2345 skb_reserve(skb, RX_OFFSET); 2346 pci_dma_sync_single_for_cpu(np->pci_dev, 2347 np->rx_dma[entry], 2348 buflen, 2349 PCI_DMA_FROMDEVICE); 2350 skb_copy_to_linear_data(skb, 2351 np->rx_skbuff[entry]->data, pkt_len); 2352 skb_put(skb, pkt_len); 2353 pci_dma_sync_single_for_device(np->pci_dev, 2354 np->rx_dma[entry], 2355 buflen, 2356 PCI_DMA_FROMDEVICE); 2357 } else { 2358 pci_unmap_single(np->pci_dev, np->rx_dma[entry], 2359 buflen + NATSEMI_PADDING, 2360 PCI_DMA_FROMDEVICE); 2361 skb_put(skb = np->rx_skbuff[entry], pkt_len); 2362 np->rx_skbuff[entry] = NULL; 2363 } 2364 skb->protocol = eth_type_trans(skb, dev); 2365 netif_receive_skb(skb); 2366 dev->stats.rx_packets++; 2367 dev->stats.rx_bytes += pkt_len; 2368 } 2369 entry = (++np->cur_rx) % RX_RING_SIZE; 2370 np->rx_head_desc = &np->rx_ring[entry]; 2371 desc_status = le32_to_cpu(np->rx_head_desc->cmd_status); 2372 } 2373 refill_rx(dev); 2374 2375 /* Restart Rx engine if stopped. */ 2376 if (np->oom) 2377 mod_timer(&np->timer, jiffies + 1); 2378 else 2379 writel(RxOn, ioaddr + ChipCmd); 2380} 2381 2382static void netdev_error(struct net_device *dev, int intr_status) 2383{ 2384 struct netdev_private *np = netdev_priv(dev); 2385 void __iomem * ioaddr = ns_ioaddr(dev); 2386 2387 spin_lock(&np->lock); 2388 if (intr_status & LinkChange) { 2389 u16 lpa = mdio_read(dev, MII_LPA); 2390 if (mdio_read(dev, MII_BMCR) & BMCR_ANENABLE && 2391 netif_msg_link(np)) { 2392 printk(KERN_INFO 2393 "%s: Autonegotiation advertising" 2394 " %#04x partner %#04x.\n", dev->name, 2395 np->advertising, lpa); 2396 } 2397 2398 /* read MII int status to clear the flag */ 2399 readw(ioaddr + MIntrStatus); 2400 check_link(dev); 2401 } 2402 if (intr_status & StatsMax) { 2403 __get_stats(dev); 2404 } 2405 if (intr_status & IntrTxUnderrun) { 2406 if ((np->tx_config & TxDrthMask) < TX_DRTH_VAL_LIMIT) { 2407 np->tx_config += TX_DRTH_VAL_INC; 2408 if (netif_msg_tx_err(np)) 2409 printk(KERN_NOTICE 2410 "%s: increased tx threshold, txcfg %#08x.\n", 2411 dev->name, np->tx_config); 2412 } else { 2413 if (netif_msg_tx_err(np)) 2414 printk(KERN_NOTICE 2415 "%s: tx underrun with maximum tx threshold, txcfg %#08x.\n", 2416 dev->name, np->tx_config); 2417 } 2418 writel(np->tx_config, ioaddr + TxConfig); 2419 } 2420 if (intr_status & WOLPkt && netif_msg_wol(np)) { 2421 int wol_status = readl(ioaddr + WOLCmd); 2422 printk(KERN_NOTICE "%s: Link wake-up event %#08x\n", 2423 dev->name, wol_status); 2424 } 2425 if (intr_status & RxStatusFIFOOver) { 2426 if (netif_msg_rx_err(np) && netif_msg_intr(np)) { 2427 printk(KERN_NOTICE "%s: Rx status FIFO overrun\n", 2428 dev->name); 2429 } 2430 dev->stats.rx_fifo_errors++; 2431 dev->stats.rx_errors++; 2432 } 2433 /* Hmmmmm, it's not clear how to recover from PCI faults. */ 2434 if (intr_status & IntrPCIErr) { 2435 printk(KERN_NOTICE "%s: PCI error %#08x\n", dev->name, 2436 intr_status & IntrPCIErr); 2437 dev->stats.tx_fifo_errors++; 2438 dev->stats.tx_errors++; 2439 dev->stats.rx_fifo_errors++; 2440 dev->stats.rx_errors++; 2441 } 2442 spin_unlock(&np->lock); 2443} 2444 2445static void __get_stats(struct net_device *dev) 2446{ 2447 void __iomem * ioaddr = ns_ioaddr(dev); 2448 2449 /* The chip only need report frame silently dropped. */ 2450 dev->stats.rx_crc_errors += readl(ioaddr + RxCRCErrs); 2451 dev->stats.rx_missed_errors += readl(ioaddr + RxMissed); 2452} 2453 2454static struct net_device_stats *get_stats(struct net_device *dev) 2455{ 2456 struct netdev_private *np = netdev_priv(dev); 2457 2458 /* The chip only need report frame silently dropped. */ 2459 spin_lock_irq(&np->lock); 2460 if (netif_running(dev) && !np->hands_off) 2461 __get_stats(dev); 2462 spin_unlock_irq(&np->lock); 2463 2464 return &dev->stats; 2465} 2466 2467#ifdef CONFIG_NET_POLL_CONTROLLER 2468static void natsemi_poll_controller(struct net_device *dev) 2469{ 2470 struct netdev_private *np = netdev_priv(dev); 2471 const int irq = np->pci_dev->irq; 2472 2473 disable_irq(irq); 2474 intr_handler(irq, dev); 2475 enable_irq(irq); 2476} 2477#endif 2478 2479#define HASH_TABLE 0x200 2480static void __set_rx_mode(struct net_device *dev) 2481{ 2482 void __iomem * ioaddr = ns_ioaddr(dev); 2483 struct netdev_private *np = netdev_priv(dev); 2484 u8 mc_filter[64]; /* Multicast hash filter */ 2485 u32 rx_mode; 2486 2487 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */ 2488 rx_mode = RxFilterEnable | AcceptBroadcast 2489 | AcceptAllMulticast | AcceptAllPhys | AcceptMyPhys; 2490 } else if ((netdev_mc_count(dev) > multicast_filter_limit) || 2491 (dev->flags & IFF_ALLMULTI)) { 2492 rx_mode = RxFilterEnable | AcceptBroadcast 2493 | AcceptAllMulticast | AcceptMyPhys; 2494 } else { 2495 struct netdev_hw_addr *ha; 2496 int i; 2497 2498 memset(mc_filter, 0, sizeof(mc_filter)); 2499 netdev_for_each_mc_addr(ha, dev) { 2500 int b = (ether_crc(ETH_ALEN, ha->addr) >> 23) & 0x1ff; 2501 mc_filter[b/8] |= (1 << (b & 0x07)); 2502 } 2503 rx_mode = RxFilterEnable | AcceptBroadcast 2504 | AcceptMulticast | AcceptMyPhys; 2505 for (i = 0; i < 64; i += 2) { 2506 writel(HASH_TABLE + i, ioaddr + RxFilterAddr); 2507 writel((mc_filter[i + 1] << 8) + mc_filter[i], 2508 ioaddr + RxFilterData); 2509 } 2510 } 2511 writel(rx_mode, ioaddr + RxFilterAddr); 2512 np->cur_rx_mode = rx_mode; 2513} 2514 2515static int natsemi_change_mtu(struct net_device *dev, int new_mtu) 2516{ 2517 if (new_mtu < 64 || new_mtu > NATSEMI_RX_LIMIT-NATSEMI_HEADERS) 2518 return -EINVAL; 2519 2520 dev->mtu = new_mtu; 2521 2522 /* synchronized against open : rtnl_lock() held by caller */ 2523 if (netif_running(dev)) { 2524 struct netdev_private *np = netdev_priv(dev); 2525 void __iomem * ioaddr = ns_ioaddr(dev); 2526 const int irq = np->pci_dev->irq; 2527 2528 disable_irq(irq); 2529 spin_lock(&np->lock); 2530 /* stop engines */ 2531 natsemi_stop_rxtx(dev); 2532 /* drain rx queue */ 2533 drain_rx(dev); 2534 /* change buffers */ 2535 set_bufsize(dev); 2536 reinit_rx(dev); 2537 writel(np->ring_dma, ioaddr + RxRingPtr); 2538 /* restart engines */ 2539 writel(RxOn | TxOn, ioaddr + ChipCmd); 2540 spin_unlock(&np->lock); 2541 enable_irq(irq); 2542 } 2543 return 0; 2544} 2545 2546static void set_rx_mode(struct net_device *dev) 2547{ 2548 struct netdev_private *np = netdev_priv(dev); 2549 spin_lock_irq(&np->lock); 2550 if (!np->hands_off) 2551 __set_rx_mode(dev); 2552 spin_unlock_irq(&np->lock); 2553} 2554 2555static void get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) 2556{ 2557 struct netdev_private *np = netdev_priv(dev); 2558 strlcpy(info->driver, DRV_NAME, sizeof(info->driver)); 2559 strlcpy(info->version, DRV_VERSION, sizeof(info->version)); 2560 strlcpy(info->bus_info, pci_name(np->pci_dev), sizeof(info->bus_info)); 2561} 2562 2563static int get_regs_len(struct net_device *dev) 2564{ 2565 return NATSEMI_REGS_SIZE; 2566} 2567 2568static int get_eeprom_len(struct net_device *dev) 2569{ 2570 struct netdev_private *np = netdev_priv(dev); 2571 return np->eeprom_size; 2572} 2573 2574static int get_settings(struct net_device *dev, struct ethtool_cmd *ecmd) 2575{ 2576 struct netdev_private *np = netdev_priv(dev); 2577 spin_lock_irq(&np->lock); 2578 netdev_get_ecmd(dev, ecmd); 2579 spin_unlock_irq(&np->lock); 2580 return 0; 2581} 2582 2583static int set_settings(struct net_device *dev, struct ethtool_cmd *ecmd) 2584{ 2585 struct netdev_private *np = netdev_priv(dev); 2586 int res; 2587 spin_lock_irq(&np->lock); 2588 res = netdev_set_ecmd(dev, ecmd); 2589 spin_unlock_irq(&np->lock); 2590 return res; 2591} 2592 2593static void get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 2594{ 2595 struct netdev_private *np = netdev_priv(dev); 2596 spin_lock_irq(&np->lock); 2597 netdev_get_wol(dev, &wol->supported, &wol->wolopts); 2598 netdev_get_sopass(dev, wol->sopass); 2599 spin_unlock_irq(&np->lock); 2600} 2601 2602static int set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 2603{ 2604 struct netdev_private *np = netdev_priv(dev); 2605 int res; 2606 spin_lock_irq(&np->lock); 2607 netdev_set_wol(dev, wol->wolopts); 2608 res = netdev_set_sopass(dev, wol->sopass); 2609 spin_unlock_irq(&np->lock); 2610 return res; 2611} 2612 2613static void get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf) 2614{ 2615 struct netdev_private *np = netdev_priv(dev); 2616 regs->version = NATSEMI_REGS_VER; 2617 spin_lock_irq(&np->lock); 2618 netdev_get_regs(dev, buf); 2619 spin_unlock_irq(&np->lock); 2620} 2621 2622static u32 get_msglevel(struct net_device *dev) 2623{ 2624 struct netdev_private *np = netdev_priv(dev); 2625 return np->msg_enable; 2626} 2627 2628static void set_msglevel(struct net_device *dev, u32 val) 2629{ 2630 struct netdev_private *np = netdev_priv(dev); 2631 np->msg_enable = val; 2632} 2633 2634static int nway_reset(struct net_device *dev) 2635{ 2636 int tmp; 2637 int r = -EINVAL; 2638 /* if autoneg is off, it's an error */ 2639 tmp = mdio_read(dev, MII_BMCR); 2640 if (tmp & BMCR_ANENABLE) { 2641 tmp |= (BMCR_ANRESTART); 2642 mdio_write(dev, MII_BMCR, tmp); 2643 r = 0; 2644 } 2645 return r; 2646} 2647 2648static u32 get_link(struct net_device *dev) 2649{ 2650 /* LSTATUS is latched low until a read - so read twice */ 2651 mdio_read(dev, MII_BMSR); 2652 return (mdio_read(dev, MII_BMSR)&BMSR_LSTATUS) ? 1:0; 2653} 2654 2655static int get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data) 2656{ 2657 struct netdev_private *np = netdev_priv(dev); 2658 u8 *eebuf; 2659 int res; 2660 2661 eebuf = kmalloc(np->eeprom_size, GFP_KERNEL); 2662 if (!eebuf) 2663 return -ENOMEM; 2664 2665 eeprom->magic = PCI_VENDOR_ID_NS | (PCI_DEVICE_ID_NS_83815<<16); 2666 spin_lock_irq(&np->lock); 2667 res = netdev_get_eeprom(dev, eebuf); 2668 spin_unlock_irq(&np->lock); 2669 if (!res) 2670 memcpy(data, eebuf+eeprom->offset, eeprom->len); 2671 kfree(eebuf); 2672 return res; 2673} 2674 2675static const struct ethtool_ops ethtool_ops = { 2676 .get_drvinfo = get_drvinfo, 2677 .get_regs_len = get_regs_len, 2678 .get_eeprom_len = get_eeprom_len, 2679 .get_settings = get_settings, 2680 .set_settings = set_settings, 2681 .get_wol = get_wol, 2682 .set_wol = set_wol, 2683 .get_regs = get_regs, 2684 .get_msglevel = get_msglevel, 2685 .set_msglevel = set_msglevel, 2686 .nway_reset = nway_reset, 2687 .get_link = get_link, 2688 .get_eeprom = get_eeprom, 2689}; 2690 2691static int netdev_set_wol(struct net_device *dev, u32 newval) 2692{ 2693 struct netdev_private *np = netdev_priv(dev); 2694 void __iomem * ioaddr = ns_ioaddr(dev); 2695 u32 data = readl(ioaddr + WOLCmd) & ~WakeOptsSummary; 2696 2697 /* translate to bitmasks this chip understands */ 2698 if (newval & WAKE_PHY) 2699 data |= WakePhy; 2700 if (newval & WAKE_UCAST) 2701 data |= WakeUnicast; 2702 if (newval & WAKE_MCAST) 2703 data |= WakeMulticast; 2704 if (newval & WAKE_BCAST) 2705 data |= WakeBroadcast; 2706 if (newval & WAKE_ARP) 2707 data |= WakeArp; 2708 if (newval & WAKE_MAGIC) 2709 data |= WakeMagic; 2710 if (np->srr >= SRR_DP83815_D) { 2711 if (newval & WAKE_MAGICSECURE) { 2712 data |= WakeMagicSecure; 2713 } 2714 } 2715 2716 writel(data, ioaddr + WOLCmd); 2717 2718 return 0; 2719} 2720 2721static int netdev_get_wol(struct net_device *dev, u32 *supported, u32 *cur) 2722{ 2723 struct netdev_private *np = netdev_priv(dev); 2724 void __iomem * ioaddr = ns_ioaddr(dev); 2725 u32 regval = readl(ioaddr + WOLCmd); 2726 2727 *supported = (WAKE_PHY | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST 2728 | WAKE_ARP | WAKE_MAGIC); 2729 2730 if (np->srr >= SRR_DP83815_D) { 2731 /* SOPASS works on revD and higher */ 2732 *supported |= WAKE_MAGICSECURE; 2733 } 2734 *cur = 0; 2735 2736 /* translate from chip bitmasks */ 2737 if (regval & WakePhy) 2738 *cur |= WAKE_PHY; 2739 if (regval & WakeUnicast) 2740 *cur |= WAKE_UCAST; 2741 if (regval & WakeMulticast) 2742 *cur |= WAKE_MCAST; 2743 if (regval & WakeBroadcast) 2744 *cur |= WAKE_BCAST; 2745 if (regval & WakeArp) 2746 *cur |= WAKE_ARP; 2747 if (regval & WakeMagic) 2748 *cur |= WAKE_MAGIC; 2749 if (regval & WakeMagicSecure) { 2750 /* this can be on in revC, but it's broken */ 2751 *cur |= WAKE_MAGICSECURE; 2752 } 2753 2754 return 0; 2755} 2756 2757static int netdev_set_sopass(struct net_device *dev, u8 *newval) 2758{ 2759 struct netdev_private *np = netdev_priv(dev); 2760 void __iomem * ioaddr = ns_ioaddr(dev); 2761 u16 *sval = (u16 *)newval; 2762 u32 addr; 2763 2764 if (np->srr < SRR_DP83815_D) { 2765 return 0; 2766 } 2767 2768 /* enable writing to these registers by disabling the RX filter */ 2769 addr = readl(ioaddr + RxFilterAddr) & ~RFCRAddressMask; 2770 addr &= ~RxFilterEnable; 2771 writel(addr, ioaddr + RxFilterAddr); 2772 2773 /* write the three words to (undocumented) RFCR vals 0xa, 0xc, 0xe */ 2774 writel(addr | 0xa, ioaddr + RxFilterAddr); 2775 writew(sval[0], ioaddr + RxFilterData); 2776 2777 writel(addr | 0xc, ioaddr + RxFilterAddr); 2778 writew(sval[1], ioaddr + RxFilterData); 2779 2780 writel(addr | 0xe, ioaddr + RxFilterAddr); 2781 writew(sval[2], ioaddr + RxFilterData); 2782 2783 /* re-enable the RX filter */ 2784 writel(addr | RxFilterEnable, ioaddr + RxFilterAddr); 2785 2786 return 0; 2787} 2788 2789static int netdev_get_sopass(struct net_device *dev, u8 *data) 2790{ 2791 struct netdev_private *np = netdev_priv(dev); 2792 void __iomem * ioaddr = ns_ioaddr(dev); 2793 u16 *sval = (u16 *)data; 2794 u32 addr; 2795 2796 if (np->srr < SRR_DP83815_D) { 2797 sval[0] = sval[1] = sval[2] = 0; 2798 return 0; 2799 } 2800 2801 /* read the three words from (undocumented) RFCR vals 0xa, 0xc, 0xe */ 2802 addr = readl(ioaddr + RxFilterAddr) & ~RFCRAddressMask; 2803 2804 writel(addr | 0xa, ioaddr + RxFilterAddr); 2805 sval[0] = readw(ioaddr + RxFilterData); 2806 2807 writel(addr | 0xc, ioaddr + RxFilterAddr); 2808 sval[1] = readw(ioaddr + RxFilterData); 2809 2810 writel(addr | 0xe, ioaddr + RxFilterAddr); 2811 sval[2] = readw(ioaddr + RxFilterData); 2812 2813 writel(addr, ioaddr + RxFilterAddr); 2814 2815 return 0; 2816} 2817 2818static int netdev_get_ecmd(struct net_device *dev, struct ethtool_cmd *ecmd) 2819{ 2820 struct netdev_private *np = netdev_priv(dev); 2821 u32 tmp; 2822 2823 ecmd->port = dev->if_port; 2824 ethtool_cmd_speed_set(ecmd, np->speed); 2825 ecmd->duplex = np->duplex; 2826 ecmd->autoneg = np->autoneg; 2827 ecmd->advertising = 0; 2828 if (np->advertising & ADVERTISE_10HALF) 2829 ecmd->advertising |= ADVERTISED_10baseT_Half; 2830 if (np->advertising & ADVERTISE_10FULL) 2831 ecmd->advertising |= ADVERTISED_10baseT_Full; 2832 if (np->advertising & ADVERTISE_100HALF) 2833 ecmd->advertising |= ADVERTISED_100baseT_Half; 2834 if (np->advertising & ADVERTISE_100FULL) 2835 ecmd->advertising |= ADVERTISED_100baseT_Full; 2836 ecmd->supported = (SUPPORTED_Autoneg | 2837 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | 2838 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full | 2839 SUPPORTED_TP | SUPPORTED_MII | SUPPORTED_FIBRE); 2840 ecmd->phy_address = np->phy_addr_external; 2841 /* 2842 * We intentionally report the phy address of the external 2843 * phy, even if the internal phy is used. This is necessary 2844 * to work around a deficiency of the ethtool interface: 2845 * It's only possible to query the settings of the active 2846 * port. Therefore 2847 * # ethtool -s ethX port mii 2848 * actually sends an ioctl to switch to port mii with the 2849 * settings that are used for the current active port. 2850 * If we would report a different phy address in this 2851 * command, then 2852 * # ethtool -s ethX port tp;ethtool -s ethX port mii 2853 * would unintentionally change the phy address. 2854 * 2855 * Fortunately the phy address doesn't matter with the 2856 * internal phy... 2857 */ 2858 2859 /* set information based on active port type */ 2860 switch (ecmd->port) { 2861 default: 2862 case PORT_TP: 2863 ecmd->advertising |= ADVERTISED_TP; 2864 ecmd->transceiver = XCVR_INTERNAL; 2865 break; 2866 case PORT_MII: 2867 ecmd->advertising |= ADVERTISED_MII; 2868 ecmd->transceiver = XCVR_EXTERNAL; 2869 break; 2870 case PORT_FIBRE: 2871 ecmd->advertising |= ADVERTISED_FIBRE; 2872 ecmd->transceiver = XCVR_EXTERNAL; 2873 break; 2874 } 2875 2876 /* if autonegotiation is on, try to return the active speed/duplex */ 2877 if (ecmd->autoneg == AUTONEG_ENABLE) { 2878 ecmd->advertising |= ADVERTISED_Autoneg; 2879 tmp = mii_nway_result( 2880 np->advertising & mdio_read(dev, MII_LPA)); 2881 if (tmp == LPA_100FULL || tmp == LPA_100HALF) 2882 ethtool_cmd_speed_set(ecmd, SPEED_100); 2883 else 2884 ethtool_cmd_speed_set(ecmd, SPEED_10); 2885 if (tmp == LPA_100FULL || tmp == LPA_10FULL) 2886 ecmd->duplex = DUPLEX_FULL; 2887 else 2888 ecmd->duplex = DUPLEX_HALF; 2889 } 2890 2891 /* ignore maxtxpkt, maxrxpkt for now */ 2892 2893 return 0; 2894} 2895 2896static int netdev_set_ecmd(struct net_device *dev, struct ethtool_cmd *ecmd) 2897{ 2898 struct netdev_private *np = netdev_priv(dev); 2899 2900 if (ecmd->port != PORT_TP && ecmd->port != PORT_MII && ecmd->port != PORT_FIBRE) 2901 return -EINVAL; 2902 if (ecmd->transceiver != XCVR_INTERNAL && ecmd->transceiver != XCVR_EXTERNAL) 2903 return -EINVAL; 2904 if (ecmd->autoneg == AUTONEG_ENABLE) { 2905 if ((ecmd->advertising & (ADVERTISED_10baseT_Half | 2906 ADVERTISED_10baseT_Full | 2907 ADVERTISED_100baseT_Half | 2908 ADVERTISED_100baseT_Full)) == 0) { 2909 return -EINVAL; 2910 } 2911 } else if (ecmd->autoneg == AUTONEG_DISABLE) { 2912 u32 speed = ethtool_cmd_speed(ecmd); 2913 if (speed != SPEED_10 && speed != SPEED_100) 2914 return -EINVAL; 2915 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL) 2916 return -EINVAL; 2917 } else { 2918 return -EINVAL; 2919 } 2920 2921 /* 2922 * If we're ignoring the PHY then autoneg and the internal 2923 * transceiver are really not going to work so don't let the 2924 * user select them. 2925 */ 2926 if (np->ignore_phy && (ecmd->autoneg == AUTONEG_ENABLE || 2927 ecmd->port == PORT_TP)) 2928 return -EINVAL; 2929 2930 /* 2931 * maxtxpkt, maxrxpkt: ignored for now. 2932 * 2933 * transceiver: 2934 * PORT_TP is always XCVR_INTERNAL, PORT_MII and PORT_FIBRE are always 2935 * XCVR_EXTERNAL. The implementation thus ignores ecmd->transceiver and 2936 * selects based on ecmd->port. 2937 * 2938 * Actually PORT_FIBRE is nearly identical to PORT_MII: it's for fibre 2939 * phys that are connected to the mii bus. It's used to apply fibre 2940 * specific updates. 2941 */ 2942 2943 /* WHEW! now lets bang some bits */ 2944 2945 /* save the parms */ 2946 dev->if_port = ecmd->port; 2947 np->autoneg = ecmd->autoneg; 2948 np->phy_addr_external = ecmd->phy_address & PhyAddrMask; 2949 if (np->autoneg == AUTONEG_ENABLE) { 2950 /* advertise only what has been requested */ 2951 np->advertising &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4); 2952 if (ecmd->advertising & ADVERTISED_10baseT_Half) 2953 np->advertising |= ADVERTISE_10HALF; 2954 if (ecmd->advertising & ADVERTISED_10baseT_Full) 2955 np->advertising |= ADVERTISE_10FULL; 2956 if (ecmd->advertising & ADVERTISED_100baseT_Half) 2957 np->advertising |= ADVERTISE_100HALF; 2958 if (ecmd->advertising & ADVERTISED_100baseT_Full) 2959 np->advertising |= ADVERTISE_100FULL; 2960 } else { 2961 np->speed = ethtool_cmd_speed(ecmd); 2962 np->duplex = ecmd->duplex; 2963 /* user overriding the initial full duplex parm? */ 2964 if (np->duplex == DUPLEX_HALF) 2965 np->full_duplex = 0; 2966 } 2967 2968 /* get the right phy enabled */ 2969 if (ecmd->port == PORT_TP) 2970 switch_port_internal(dev); 2971 else 2972 switch_port_external(dev); 2973 2974 /* set parms and see how this affected our link status */ 2975 init_phy_fixup(dev); 2976 check_link(dev); 2977 return 0; 2978} 2979 2980static int netdev_get_regs(struct net_device *dev, u8 *buf) 2981{ 2982 int i; 2983 int j; 2984 u32 rfcr; 2985 u32 *rbuf = (u32 *)buf; 2986 void __iomem * ioaddr = ns_ioaddr(dev); 2987 2988 /* read non-mii page 0 of registers */ 2989 for (i = 0; i < NATSEMI_PG0_NREGS/2; i++) { 2990 rbuf[i] = readl(ioaddr + i*4); 2991 } 2992 2993 /* read current mii registers */ 2994 for (i = NATSEMI_PG0_NREGS/2; i < NATSEMI_PG0_NREGS; i++) 2995 rbuf[i] = mdio_read(dev, i & 0x1f); 2996 2997 /* read only the 'magic' registers from page 1 */ 2998 writew(1, ioaddr + PGSEL); 2999 rbuf[i++] = readw(ioaddr + PMDCSR); 3000 rbuf[i++] = readw(ioaddr + TSTDAT); 3001 rbuf[i++] = readw(ioaddr + DSPCFG); 3002 rbuf[i++] = readw(ioaddr + SDCFG); 3003 writew(0, ioaddr + PGSEL); 3004 3005 /* read RFCR indexed registers */ 3006 rfcr = readl(ioaddr + RxFilterAddr); 3007 for (j = 0; j < NATSEMI_RFDR_NREGS; j++) { 3008 writel(j*2, ioaddr + RxFilterAddr); 3009 rbuf[i++] = readw(ioaddr + RxFilterData); 3010 } 3011 writel(rfcr, ioaddr + RxFilterAddr); 3012 3013 /* the interrupt status is clear-on-read - see if we missed any */ 3014 if (rbuf[4] & rbuf[5]) { 3015 printk(KERN_WARNING 3016 "%s: shoot, we dropped an interrupt (%#08x)\n", 3017 dev->name, rbuf[4] & rbuf[5]); 3018 } 3019 3020 return 0; 3021} 3022 3023#define SWAP_BITS(x) ( (((x) & 0x0001) << 15) | (((x) & 0x0002) << 13) \ 3024 | (((x) & 0x0004) << 11) | (((x) & 0x0008) << 9) \ 3025 | (((x) & 0x0010) << 7) | (((x) & 0x0020) << 5) \ 3026 | (((x) & 0x0040) << 3) | (((x) & 0x0080) << 1) \ 3027 | (((x) & 0x0100) >> 1) | (((x) & 0x0200) >> 3) \ 3028 | (((x) & 0x0400) >> 5) | (((x) & 0x0800) >> 7) \ 3029 | (((x) & 0x1000) >> 9) | (((x) & 0x2000) >> 11) \ 3030 | (((x) & 0x4000) >> 13) | (((x) & 0x8000) >> 15) ) 3031 3032static int netdev_get_eeprom(struct net_device *dev, u8 *buf) 3033{ 3034 int i; 3035 u16 *ebuf = (u16 *)buf; 3036 void __iomem * ioaddr = ns_ioaddr(dev); 3037 struct netdev_private *np = netdev_priv(dev); 3038 3039 /* eeprom_read reads 16 bits, and indexes by 16 bits */ 3040 for (i = 0; i < np->eeprom_size/2; i++) { 3041 ebuf[i] = eeprom_read(ioaddr, i); 3042 /* The EEPROM itself stores data bit-swapped, but eeprom_read 3043 * reads it back "sanely". So we swap it back here in order to 3044 * present it to userland as it is stored. */ 3045 ebuf[i] = SWAP_BITS(ebuf[i]); 3046 } 3047 return 0; 3048} 3049 3050static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 3051{ 3052 struct mii_ioctl_data *data = if_mii(rq); 3053 struct netdev_private *np = netdev_priv(dev); 3054 3055 switch(cmd) { 3056 case SIOCGMIIPHY: /* Get address of MII PHY in use. */ 3057 data->phy_id = np->phy_addr_external; 3058 /* Fall Through */ 3059 3060 case SIOCGMIIREG: /* Read MII PHY register. */ 3061 /* The phy_id is not enough to uniquely identify 3062 * the intended target. Therefore the command is sent to 3063 * the given mii on the current port. 3064 */ 3065 if (dev->if_port == PORT_TP) { 3066 if ((data->phy_id & 0x1f) == np->phy_addr_external) 3067 data->val_out = mdio_read(dev, 3068 data->reg_num & 0x1f); 3069 else 3070 data->val_out = 0; 3071 } else { 3072 move_int_phy(dev, data->phy_id & 0x1f); 3073 data->val_out = miiport_read(dev, data->phy_id & 0x1f, 3074 data->reg_num & 0x1f); 3075 } 3076 return 0; 3077 3078 case SIOCSMIIREG: /* Write MII PHY register. */ 3079 if (dev->if_port == PORT_TP) { 3080 if ((data->phy_id & 0x1f) == np->phy_addr_external) { 3081 if ((data->reg_num & 0x1f) == MII_ADVERTISE) 3082 np->advertising = data->val_in; 3083 mdio_write(dev, data->reg_num & 0x1f, 3084 data->val_in); 3085 } 3086 } else { 3087 if ((data->phy_id & 0x1f) == np->phy_addr_external) { 3088 if ((data->reg_num & 0x1f) == MII_ADVERTISE) 3089 np->advertising = data->val_in; 3090 } 3091 move_int_phy(dev, data->phy_id & 0x1f); 3092 miiport_write(dev, data->phy_id & 0x1f, 3093 data->reg_num & 0x1f, 3094 data->val_in); 3095 } 3096 return 0; 3097 default: 3098 return -EOPNOTSUPP; 3099 } 3100} 3101 3102static void enable_wol_mode(struct net_device *dev, int enable_intr) 3103{ 3104 void __iomem * ioaddr = ns_ioaddr(dev); 3105 struct netdev_private *np = netdev_priv(dev); 3106 3107 if (netif_msg_wol(np)) 3108 printk(KERN_INFO "%s: remaining active for wake-on-lan\n", 3109 dev->name); 3110 3111 /* For WOL we must restart the rx process in silent mode. 3112 * Write NULL to the RxRingPtr. Only possible if 3113 * rx process is stopped 3114 */ 3115 writel(0, ioaddr + RxRingPtr); 3116 3117 /* read WoL status to clear */ 3118 readl(ioaddr + WOLCmd); 3119 3120 /* PME on, clear status */ 3121 writel(np->SavedClkRun | PMEEnable | PMEStatus, ioaddr + ClkRun); 3122 3123 /* and restart the rx process */ 3124 writel(RxOn, ioaddr + ChipCmd); 3125 3126 if (enable_intr) { 3127 /* enable the WOL interrupt. 3128 * Could be used to send a netlink message. 3129 */ 3130 writel(WOLPkt | LinkChange, ioaddr + IntrMask); 3131 natsemi_irq_enable(dev); 3132 } 3133} 3134 3135static int netdev_close(struct net_device *dev) 3136{ 3137 void __iomem * ioaddr = ns_ioaddr(dev); 3138 struct netdev_private *np = netdev_priv(dev); 3139 const int irq = np->pci_dev->irq; 3140 3141 if (netif_msg_ifdown(np)) 3142 printk(KERN_DEBUG 3143 "%s: Shutting down ethercard, status was %#04x.\n", 3144 dev->name, (int)readl(ioaddr + ChipCmd)); 3145 if (netif_msg_pktdata(np)) 3146 printk(KERN_DEBUG 3147 "%s: Queue pointers were Tx %d / %d, Rx %d / %d.\n", 3148 dev->name, np->cur_tx, np->dirty_tx, 3149 np->cur_rx, np->dirty_rx); 3150 3151 napi_disable(&np->napi); 3152 3153 /* 3154 * FIXME: what if someone tries to close a device 3155 * that is suspended? 3156 * Should we reenable the nic to switch to 3157 * the final WOL settings? 3158 */ 3159 3160 del_timer_sync(&np->timer); 3161 disable_irq(irq); 3162 spin_lock_irq(&np->lock); 3163 natsemi_irq_disable(dev); 3164 np->hands_off = 1; 3165 spin_unlock_irq(&np->lock); 3166 enable_irq(irq); 3167 3168 free_irq(irq, dev); 3169 3170 /* Interrupt disabled, interrupt handler released, 3171 * queue stopped, timer deleted, rtnl_lock held 3172 * All async codepaths that access the driver are disabled. 3173 */ 3174 spin_lock_irq(&np->lock); 3175 np->hands_off = 0; 3176 readl(ioaddr + IntrMask); 3177 readw(ioaddr + MIntrStatus); 3178 3179 /* Freeze Stats */ 3180 writel(StatsFreeze, ioaddr + StatsCtrl); 3181 3182 /* Stop the chip's Tx and Rx processes. */ 3183 natsemi_stop_rxtx(dev); 3184 3185 __get_stats(dev); 3186 spin_unlock_irq(&np->lock); 3187 3188 /* clear the carrier last - an interrupt could reenable it otherwise */ 3189 netif_carrier_off(dev); 3190 netif_stop_queue(dev); 3191 3192 dump_ring(dev); 3193 drain_ring(dev); 3194 free_ring(dev); 3195 3196 { 3197 u32 wol = readl(ioaddr + WOLCmd) & WakeOptsSummary; 3198 if (wol) { 3199 /* restart the NIC in WOL mode. 3200 * The nic must be stopped for this. 3201 */ 3202 enable_wol_mode(dev, 0); 3203 } else { 3204 /* Restore PME enable bit unmolested */ 3205 writel(np->SavedClkRun, ioaddr + ClkRun); 3206 } 3207 } 3208 return 0; 3209} 3210 3211 3212static void natsemi_remove1(struct pci_dev *pdev) 3213{ 3214 struct net_device *dev = pci_get_drvdata(pdev); 3215 void __iomem * ioaddr = ns_ioaddr(dev); 3216 3217 NATSEMI_REMOVE_FILE(pdev, dspcfg_workaround); 3218 unregister_netdev (dev); 3219 pci_release_regions (pdev); 3220 iounmap(ioaddr); 3221 free_netdev (dev); 3222} 3223 3224#ifdef CONFIG_PM 3225 3226/* 3227 * The ns83815 chip doesn't have explicit RxStop bits. 3228 * Kicking the Rx or Tx process for a new packet reenables the Rx process 3229 * of the nic, thus this function must be very careful: 3230 * 3231 * suspend/resume synchronization: 3232 * entry points: 3233 * netdev_open, netdev_close, netdev_ioctl, set_rx_mode, intr_handler, 3234 * start_tx, ns_tx_timeout 3235 * 3236 * No function accesses the hardware without checking np->hands_off. 3237 * the check occurs under spin_lock_irq(&np->lock); 3238 * exceptions: 3239 * * netdev_ioctl: noncritical access. 3240 * * netdev_open: cannot happen due to the device_detach 3241 * * netdev_close: doesn't hurt. 3242 * * netdev_timer: timer stopped by natsemi_suspend. 3243 * * intr_handler: doesn't acquire the spinlock. suspend calls 3244 * disable_irq() to enforce synchronization. 3245 * * natsemi_poll: checks before reenabling interrupts. suspend 3246 * sets hands_off, disables interrupts and then waits with 3247 * napi_disable(). 3248 * 3249 * Interrupts must be disabled, otherwise hands_off can cause irq storms. 3250 */ 3251 3252static int natsemi_suspend (struct pci_dev *pdev, pm_message_t state) 3253{ 3254 struct net_device *dev = pci_get_drvdata (pdev); 3255 struct netdev_private *np = netdev_priv(dev); 3256 void __iomem * ioaddr = ns_ioaddr(dev); 3257 3258 rtnl_lock(); 3259 if (netif_running (dev)) { 3260 const int irq = np->pci_dev->irq; 3261 3262 del_timer_sync(&np->timer); 3263 3264 disable_irq(irq); 3265 spin_lock_irq(&np->lock); 3266 3267 natsemi_irq_disable(dev); 3268 np->hands_off = 1; 3269 natsemi_stop_rxtx(dev); 3270 netif_stop_queue(dev); 3271 3272 spin_unlock_irq(&np->lock); 3273 enable_irq(irq); 3274 3275 napi_disable(&np->napi); 3276 3277 /* Update the error counts. */ 3278 __get_stats(dev); 3279 3280 /* pci_power_off(pdev, -1); */ 3281 drain_ring(dev); 3282 { 3283 u32 wol = readl(ioaddr + WOLCmd) & WakeOptsSummary; 3284 /* Restore PME enable bit */ 3285 if (wol) { 3286 /* restart the NIC in WOL mode. 3287 * The nic must be stopped for this. 3288 * FIXME: use the WOL interrupt 3289 */ 3290 enable_wol_mode(dev, 0); 3291 } else { 3292 /* Restore PME enable bit unmolested */ 3293 writel(np->SavedClkRun, ioaddr + ClkRun); 3294 } 3295 } 3296 } 3297 netif_device_detach(dev); 3298 rtnl_unlock(); 3299 return 0; 3300} 3301 3302 3303static int natsemi_resume (struct pci_dev *pdev) 3304{ 3305 struct net_device *dev = pci_get_drvdata (pdev); 3306 struct netdev_private *np = netdev_priv(dev); 3307 int ret = 0; 3308 3309 rtnl_lock(); 3310 if (netif_device_present(dev)) 3311 goto out; 3312 if (netif_running(dev)) { 3313 const int irq = np->pci_dev->irq; 3314 3315 BUG_ON(!np->hands_off); 3316 ret = pci_enable_device(pdev); 3317 if (ret < 0) { 3318 dev_err(&pdev->dev, 3319 "pci_enable_device() failed: %d\n", ret); 3320 goto out; 3321 } 3322 /* pci_power_on(pdev); */ 3323 3324 napi_enable(&np->napi); 3325 3326 natsemi_reset(dev); 3327 init_ring(dev); 3328 disable_irq(irq); 3329 spin_lock_irq(&np->lock); 3330 np->hands_off = 0; 3331 init_registers(dev); 3332 netif_device_attach(dev); 3333 spin_unlock_irq(&np->lock); 3334 enable_irq(irq); 3335 3336 mod_timer(&np->timer, round_jiffies(jiffies + 1*HZ)); 3337 } 3338 netif_device_attach(dev); 3339out: 3340 rtnl_unlock(); 3341 return ret; 3342} 3343 3344#endif /* CONFIG_PM */ 3345 3346static struct pci_driver natsemi_driver = { 3347 .name = DRV_NAME, 3348 .id_table = natsemi_pci_tbl, 3349 .probe = natsemi_probe1, 3350 .remove = natsemi_remove1, 3351#ifdef CONFIG_PM 3352 .suspend = natsemi_suspend, 3353 .resume = natsemi_resume, 3354#endif 3355}; 3356 3357static int __init natsemi_init_mod (void) 3358{ 3359/* when a module, this is printed whether or not devices are found in probe */ 3360#ifdef MODULE 3361 printk(version); 3362#endif 3363 3364 return pci_register_driver(&natsemi_driver); 3365} 3366 3367static void __exit natsemi_exit_mod (void) 3368{ 3369 pci_unregister_driver (&natsemi_driver); 3370} 3371 3372module_init(natsemi_init_mod); 3373module_exit(natsemi_exit_mod); 3374 3375