1/*
2 * Copyright 2011-2012 Calxeda, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program.  If not, see <http://www.gnu.org/licenses/>.
15 */
16#include <linux/types.h>
17#include <linux/kernel.h>
18#include <linux/ctype.h>
19#include <linux/edac.h>
20#include <linux/interrupt.h>
21#include <linux/platform_device.h>
22#include <linux/of_platform.h>
23#include <linux/uaccess.h>
24
25#include "edac_core.h"
26#include "edac_module.h"
27
28/* DDR Ctrlr Error Registers */
29
30#define HB_DDR_ECC_ERR_BASE		0x128
31#define MW_DDR_ECC_ERR_BASE		0x1b4
32
33#define HB_DDR_ECC_OPT			0x00
34#define HB_DDR_ECC_U_ERR_ADDR		0x08
35#define HB_DDR_ECC_U_ERR_STAT		0x0c
36#define HB_DDR_ECC_U_ERR_DATAL		0x10
37#define HB_DDR_ECC_U_ERR_DATAH		0x14
38#define HB_DDR_ECC_C_ERR_ADDR		0x18
39#define HB_DDR_ECC_C_ERR_STAT		0x1c
40#define HB_DDR_ECC_C_ERR_DATAL		0x20
41#define HB_DDR_ECC_C_ERR_DATAH		0x24
42
43#define HB_DDR_ECC_OPT_MODE_MASK	0x3
44#define HB_DDR_ECC_OPT_FWC		0x100
45#define HB_DDR_ECC_OPT_XOR_SHIFT	16
46
47/* DDR Ctrlr Interrupt Registers */
48
49#define HB_DDR_ECC_INT_BASE		0x180
50#define MW_DDR_ECC_INT_BASE		0x218
51
52#define HB_DDR_ECC_INT_STATUS		0x00
53#define HB_DDR_ECC_INT_ACK		0x04
54
55#define HB_DDR_ECC_INT_STAT_CE		0x8
56#define HB_DDR_ECC_INT_STAT_DOUBLE_CE	0x10
57#define HB_DDR_ECC_INT_STAT_UE		0x20
58#define HB_DDR_ECC_INT_STAT_DOUBLE_UE	0x40
59
60struct hb_mc_drvdata {
61	void __iomem *mc_err_base;
62	void __iomem *mc_int_base;
63};
64
65static irqreturn_t highbank_mc_err_handler(int irq, void *dev_id)
66{
67	struct mem_ctl_info *mci = dev_id;
68	struct hb_mc_drvdata *drvdata = mci->pvt_info;
69	u32 status, err_addr;
70
71	/* Read the interrupt status register */
72	status = readl(drvdata->mc_int_base + HB_DDR_ECC_INT_STATUS);
73
74	if (status & HB_DDR_ECC_INT_STAT_UE) {
75		err_addr = readl(drvdata->mc_err_base + HB_DDR_ECC_U_ERR_ADDR);
76		edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
77				     err_addr >> PAGE_SHIFT,
78				     err_addr & ~PAGE_MASK, 0,
79				     0, 0, -1,
80				     mci->ctl_name, "");
81	}
82	if (status & HB_DDR_ECC_INT_STAT_CE) {
83		u32 syndrome = readl(drvdata->mc_err_base + HB_DDR_ECC_C_ERR_STAT);
84		syndrome = (syndrome >> 8) & 0xff;
85		err_addr = readl(drvdata->mc_err_base + HB_DDR_ECC_C_ERR_ADDR);
86		edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
87				     err_addr >> PAGE_SHIFT,
88				     err_addr & ~PAGE_MASK, syndrome,
89				     0, 0, -1,
90				     mci->ctl_name, "");
91	}
92
93	/* clear the error, clears the interrupt */
94	writel(status, drvdata->mc_int_base + HB_DDR_ECC_INT_ACK);
95	return IRQ_HANDLED;
96}
97
98static void highbank_mc_err_inject(struct mem_ctl_info *mci, u8 synd)
99{
100	struct hb_mc_drvdata *pdata = mci->pvt_info;
101	u32 reg;
102
103	reg = readl(pdata->mc_err_base + HB_DDR_ECC_OPT);
104	reg &= HB_DDR_ECC_OPT_MODE_MASK;
105	reg |= (synd << HB_DDR_ECC_OPT_XOR_SHIFT) | HB_DDR_ECC_OPT_FWC;
106	writel(reg, pdata->mc_err_base + HB_DDR_ECC_OPT);
107}
108
109#define to_mci(k) container_of(k, struct mem_ctl_info, dev)
110
111static ssize_t highbank_mc_inject_ctrl(struct device *dev,
112	struct device_attribute *attr, const char *buf, size_t count)
113{
114	struct mem_ctl_info *mci = to_mci(dev);
115	u8 synd;
116
117	if (kstrtou8(buf, 16, &synd))
118		return -EINVAL;
119
120	highbank_mc_err_inject(mci, synd);
121
122	return count;
123}
124
125static DEVICE_ATTR(inject_ctrl, S_IWUSR, NULL, highbank_mc_inject_ctrl);
126
127static struct attribute *highbank_dev_attrs[] = {
128	&dev_attr_inject_ctrl.attr,
129	NULL
130};
131
132ATTRIBUTE_GROUPS(highbank_dev);
133
134struct hb_mc_settings {
135	int	err_offset;
136	int	int_offset;
137};
138
139static struct hb_mc_settings hb_settings = {
140	.err_offset = HB_DDR_ECC_ERR_BASE,
141	.int_offset = HB_DDR_ECC_INT_BASE,
142};
143
144static struct hb_mc_settings mw_settings = {
145	.err_offset = MW_DDR_ECC_ERR_BASE,
146	.int_offset = MW_DDR_ECC_INT_BASE,
147};
148
149static const struct of_device_id hb_ddr_ctrl_of_match[] = {
150	{ .compatible = "calxeda,hb-ddr-ctrl",		.data = &hb_settings },
151	{ .compatible = "calxeda,ecx-2000-ddr-ctrl",	.data = &mw_settings },
152	{},
153};
154MODULE_DEVICE_TABLE(of, hb_ddr_ctrl_of_match);
155
156static int highbank_mc_probe(struct platform_device *pdev)
157{
158	const struct of_device_id *id;
159	const struct hb_mc_settings *settings;
160	struct edac_mc_layer layers[2];
161	struct mem_ctl_info *mci;
162	struct hb_mc_drvdata *drvdata;
163	struct dimm_info *dimm;
164	struct resource *r;
165	void __iomem *base;
166	u32 control;
167	int irq;
168	int res = 0;
169
170	id = of_match_device(hb_ddr_ctrl_of_match, &pdev->dev);
171	if (!id)
172		return -ENODEV;
173
174	layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
175	layers[0].size = 1;
176	layers[0].is_virt_csrow = true;
177	layers[1].type = EDAC_MC_LAYER_CHANNEL;
178	layers[1].size = 1;
179	layers[1].is_virt_csrow = false;
180	mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers,
181			    sizeof(struct hb_mc_drvdata));
182	if (!mci)
183		return -ENOMEM;
184
185	mci->pdev = &pdev->dev;
186	drvdata = mci->pvt_info;
187	platform_set_drvdata(pdev, mci);
188
189	if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL))
190		return -ENOMEM;
191
192	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
193	if (!r) {
194		dev_err(&pdev->dev, "Unable to get mem resource\n");
195		res = -ENODEV;
196		goto err;
197	}
198
199	if (!devm_request_mem_region(&pdev->dev, r->start,
200				     resource_size(r), dev_name(&pdev->dev))) {
201		dev_err(&pdev->dev, "Error while requesting mem region\n");
202		res = -EBUSY;
203		goto err;
204	}
205
206	base = devm_ioremap(&pdev->dev, r->start, resource_size(r));
207	if (!base) {
208		dev_err(&pdev->dev, "Unable to map regs\n");
209		res = -ENOMEM;
210		goto err;
211	}
212
213	settings = id->data;
214	drvdata->mc_err_base = base + settings->err_offset;
215	drvdata->mc_int_base = base + settings->int_offset;
216
217	control = readl(drvdata->mc_err_base + HB_DDR_ECC_OPT) & 0x3;
218	if (!control || (control == 0x2)) {
219		dev_err(&pdev->dev, "No ECC present, or ECC disabled\n");
220		res = -ENODEV;
221		goto err;
222	}
223
224	mci->mtype_cap = MEM_FLAG_DDR3;
225	mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
226	mci->edac_cap = EDAC_FLAG_SECDED;
227	mci->mod_name = pdev->dev.driver->name;
228	mci->mod_ver = "1";
229	mci->ctl_name = id->compatible;
230	mci->dev_name = dev_name(&pdev->dev);
231	mci->scrub_mode = SCRUB_SW_SRC;
232
233	/* Only a single 4GB DIMM is supported */
234	dimm = *mci->dimms;
235	dimm->nr_pages = (~0UL >> PAGE_SHIFT) + 1;
236	dimm->grain = 8;
237	dimm->dtype = DEV_X8;
238	dimm->mtype = MEM_DDR3;
239	dimm->edac_mode = EDAC_SECDED;
240
241	res = edac_mc_add_mc_with_groups(mci, highbank_dev_groups);
242	if (res < 0)
243		goto err;
244
245	irq = platform_get_irq(pdev, 0);
246	res = devm_request_irq(&pdev->dev, irq, highbank_mc_err_handler,
247			       0, dev_name(&pdev->dev), mci);
248	if (res < 0) {
249		dev_err(&pdev->dev, "Unable to request irq %d\n", irq);
250		goto err2;
251	}
252
253	devres_close_group(&pdev->dev, NULL);
254	return 0;
255err2:
256	edac_mc_del_mc(&pdev->dev);
257err:
258	devres_release_group(&pdev->dev, NULL);
259	edac_mc_free(mci);
260	return res;
261}
262
263static int highbank_mc_remove(struct platform_device *pdev)
264{
265	struct mem_ctl_info *mci = platform_get_drvdata(pdev);
266
267	edac_mc_del_mc(&pdev->dev);
268	edac_mc_free(mci);
269	return 0;
270}
271
272static struct platform_driver highbank_mc_edac_driver = {
273	.probe = highbank_mc_probe,
274	.remove = highbank_mc_remove,
275	.driver = {
276		.name = "hb_mc_edac",
277		.of_match_table = hb_ddr_ctrl_of_match,
278	},
279};
280
281module_platform_driver(highbank_mc_edac_driver);
282
283MODULE_LICENSE("GPL v2");
284MODULE_AUTHOR("Calxeda, Inc.");
285MODULE_DESCRIPTION("EDAC Driver for Calxeda Highbank");
286