1/* 2 * pinmux driver for CSR SiRFprimaII 3 * 4 * Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group 5 * company. 6 * 7 * Licensed under GPLv2 or later. 8 */ 9 10#include <linux/init.h> 11#include <linux/module.h> 12#include <linux/irq.h> 13#include <linux/platform_device.h> 14#include <linux/io.h> 15#include <linux/slab.h> 16#include <linux/err.h> 17#include <linux/pinctrl/pinctrl.h> 18#include <linux/pinctrl/pinmux.h> 19#include <linux/pinctrl/consumer.h> 20#include <linux/pinctrl/machine.h> 21#include <linux/of.h> 22#include <linux/of_address.h> 23#include <linux/of_device.h> 24#include <linux/of_platform.h> 25#include <linux/bitops.h> 26#include <linux/gpio.h> 27#include <linux/of_gpio.h> 28 29#include "pinctrl-sirf.h" 30 31#define DRIVER_NAME "pinmux-sirf" 32 33struct sirfsoc_gpio_bank { 34 int id; 35 int parent_irq; 36 spinlock_t lock; 37}; 38 39struct sirfsoc_gpio_chip { 40 struct of_mm_gpio_chip chip; 41 struct sirfsoc_gpio_bank sgpio_bank[SIRFSOC_GPIO_NO_OF_BANKS]; 42 spinlock_t lock; 43}; 44 45static struct sirfsoc_pin_group *sirfsoc_pin_groups; 46static int sirfsoc_pingrp_cnt; 47 48static int sirfsoc_get_groups_count(struct pinctrl_dev *pctldev) 49{ 50 return sirfsoc_pingrp_cnt; 51} 52 53static const char *sirfsoc_get_group_name(struct pinctrl_dev *pctldev, 54 unsigned selector) 55{ 56 return sirfsoc_pin_groups[selector].name; 57} 58 59static int sirfsoc_get_group_pins(struct pinctrl_dev *pctldev, 60 unsigned selector, 61 const unsigned **pins, 62 unsigned *num_pins) 63{ 64 *pins = sirfsoc_pin_groups[selector].pins; 65 *num_pins = sirfsoc_pin_groups[selector].num_pins; 66 return 0; 67} 68 69static void sirfsoc_pin_dbg_show(struct pinctrl_dev *pctldev, 70 struct seq_file *s, unsigned offset) 71{ 72 seq_printf(s, " " DRIVER_NAME); 73} 74 75static int sirfsoc_dt_node_to_map(struct pinctrl_dev *pctldev, 76 struct device_node *np_config, 77 struct pinctrl_map **map, unsigned *num_maps) 78{ 79 struct sirfsoc_pmx *spmx = pinctrl_dev_get_drvdata(pctldev); 80 struct device_node *np; 81 struct property *prop; 82 const char *function, *group; 83 int ret, index = 0, count = 0; 84 85 /* calculate number of maps required */ 86 for_each_child_of_node(np_config, np) { 87 ret = of_property_read_string(np, "sirf,function", &function); 88 if (ret < 0) 89 return ret; 90 91 ret = of_property_count_strings(np, "sirf,pins"); 92 if (ret < 0) 93 return ret; 94 95 count += ret; 96 } 97 98 if (!count) { 99 dev_err(spmx->dev, "No child nodes passed via DT\n"); 100 return -ENODEV; 101 } 102 103 *map = kzalloc(sizeof(**map) * count, GFP_KERNEL); 104 if (!*map) 105 return -ENOMEM; 106 107 for_each_child_of_node(np_config, np) { 108 of_property_read_string(np, "sirf,function", &function); 109 of_property_for_each_string(np, "sirf,pins", prop, group) { 110 (*map)[index].type = PIN_MAP_TYPE_MUX_GROUP; 111 (*map)[index].data.mux.group = group; 112 (*map)[index].data.mux.function = function; 113 index++; 114 } 115 } 116 117 *num_maps = count; 118 119 return 0; 120} 121 122static void sirfsoc_dt_free_map(struct pinctrl_dev *pctldev, 123 struct pinctrl_map *map, unsigned num_maps) 124{ 125 kfree(map); 126} 127 128static struct pinctrl_ops sirfsoc_pctrl_ops = { 129 .get_groups_count = sirfsoc_get_groups_count, 130 .get_group_name = sirfsoc_get_group_name, 131 .get_group_pins = sirfsoc_get_group_pins, 132 .pin_dbg_show = sirfsoc_pin_dbg_show, 133 .dt_node_to_map = sirfsoc_dt_node_to_map, 134 .dt_free_map = sirfsoc_dt_free_map, 135}; 136 137static struct sirfsoc_pmx_func *sirfsoc_pmx_functions; 138static int sirfsoc_pmxfunc_cnt; 139 140static void sirfsoc_pinmux_endisable(struct sirfsoc_pmx *spmx, 141 unsigned selector, bool enable) 142{ 143 int i; 144 const struct sirfsoc_padmux *mux = 145 sirfsoc_pmx_functions[selector].padmux; 146 const struct sirfsoc_muxmask *mask = mux->muxmask; 147 148 for (i = 0; i < mux->muxmask_counts; i++) { 149 u32 muxval; 150 muxval = readl(spmx->gpio_virtbase + 151 SIRFSOC_GPIO_PAD_EN(mask[i].group)); 152 if (enable) 153 muxval = muxval & ~mask[i].mask; 154 else 155 muxval = muxval | mask[i].mask; 156 writel(muxval, spmx->gpio_virtbase + 157 SIRFSOC_GPIO_PAD_EN(mask[i].group)); 158 } 159 160 if (mux->funcmask && enable) { 161 u32 func_en_val; 162 163 func_en_val = 164 readl(spmx->rsc_virtbase + mux->ctrlreg); 165 func_en_val = 166 (func_en_val & ~mux->funcmask) | (mux->funcval); 167 writel(func_en_val, spmx->rsc_virtbase + mux->ctrlreg); 168 } 169} 170 171static int sirfsoc_pinmux_set_mux(struct pinctrl_dev *pmxdev, 172 unsigned selector, 173 unsigned group) 174{ 175 struct sirfsoc_pmx *spmx; 176 177 spmx = pinctrl_dev_get_drvdata(pmxdev); 178 sirfsoc_pinmux_endisable(spmx, selector, true); 179 180 return 0; 181} 182 183static int sirfsoc_pinmux_get_funcs_count(struct pinctrl_dev *pmxdev) 184{ 185 return sirfsoc_pmxfunc_cnt; 186} 187 188static const char *sirfsoc_pinmux_get_func_name(struct pinctrl_dev *pctldev, 189 unsigned selector) 190{ 191 return sirfsoc_pmx_functions[selector].name; 192} 193 194static int sirfsoc_pinmux_get_groups(struct pinctrl_dev *pctldev, 195 unsigned selector, 196 const char * const **groups, 197 unsigned * const num_groups) 198{ 199 *groups = sirfsoc_pmx_functions[selector].groups; 200 *num_groups = sirfsoc_pmx_functions[selector].num_groups; 201 return 0; 202} 203 204static int sirfsoc_pinmux_request_gpio(struct pinctrl_dev *pmxdev, 205 struct pinctrl_gpio_range *range, unsigned offset) 206{ 207 struct sirfsoc_pmx *spmx; 208 209 int group = range->id; 210 211 u32 muxval; 212 213 spmx = pinctrl_dev_get_drvdata(pmxdev); 214 215 muxval = readl(spmx->gpio_virtbase + 216 SIRFSOC_GPIO_PAD_EN(group)); 217 muxval = muxval | (1 << (offset - range->pin_base)); 218 writel(muxval, spmx->gpio_virtbase + 219 SIRFSOC_GPIO_PAD_EN(group)); 220 221 return 0; 222} 223 224static struct pinmux_ops sirfsoc_pinmux_ops = { 225 .set_mux = sirfsoc_pinmux_set_mux, 226 .get_functions_count = sirfsoc_pinmux_get_funcs_count, 227 .get_function_name = sirfsoc_pinmux_get_func_name, 228 .get_function_groups = sirfsoc_pinmux_get_groups, 229 .gpio_request_enable = sirfsoc_pinmux_request_gpio, 230}; 231 232static struct pinctrl_desc sirfsoc_pinmux_desc = { 233 .name = DRIVER_NAME, 234 .pctlops = &sirfsoc_pctrl_ops, 235 .pmxops = &sirfsoc_pinmux_ops, 236 .owner = THIS_MODULE, 237}; 238 239static void __iomem *sirfsoc_rsc_of_iomap(void) 240{ 241 const struct of_device_id rsc_ids[] = { 242 { .compatible = "sirf,prima2-rsc" }, 243 {} 244 }; 245 struct device_node *np; 246 247 np = of_find_matching_node(NULL, rsc_ids); 248 if (!np) 249 panic("unable to find compatible rsc node in dtb\n"); 250 251 return of_iomap(np, 0); 252} 253 254static int sirfsoc_gpio_of_xlate(struct gpio_chip *gc, 255 const struct of_phandle_args *gpiospec, 256 u32 *flags) 257{ 258 if (gpiospec->args[0] > SIRFSOC_GPIO_NO_OF_BANKS * SIRFSOC_GPIO_BANK_SIZE) 259 return -EINVAL; 260 261 if (flags) 262 *flags = gpiospec->args[1]; 263 264 return gpiospec->args[0]; 265} 266 267static const struct of_device_id pinmux_ids[] = { 268 { .compatible = "sirf,prima2-pinctrl", .data = &prima2_pinctrl_data, }, 269 { .compatible = "sirf,atlas6-pinctrl", .data = &atlas6_pinctrl_data, }, 270 {} 271}; 272 273static int sirfsoc_pinmux_probe(struct platform_device *pdev) 274{ 275 int ret; 276 struct sirfsoc_pmx *spmx; 277 struct device_node *np = pdev->dev.of_node; 278 const struct sirfsoc_pinctrl_data *pdata; 279 280 /* Create state holders etc for this driver */ 281 spmx = devm_kzalloc(&pdev->dev, sizeof(*spmx), GFP_KERNEL); 282 if (!spmx) 283 return -ENOMEM; 284 285 spmx->dev = &pdev->dev; 286 287 platform_set_drvdata(pdev, spmx); 288 289 spmx->gpio_virtbase = of_iomap(np, 0); 290 if (!spmx->gpio_virtbase) { 291 dev_err(&pdev->dev, "can't map gpio registers\n"); 292 return -ENOMEM; 293 } 294 295 spmx->rsc_virtbase = sirfsoc_rsc_of_iomap(); 296 if (!spmx->rsc_virtbase) { 297 ret = -ENOMEM; 298 dev_err(&pdev->dev, "can't map rsc registers\n"); 299 goto out_no_rsc_remap; 300 } 301 302 pdata = of_match_node(pinmux_ids, np)->data; 303 sirfsoc_pin_groups = pdata->grps; 304 sirfsoc_pingrp_cnt = pdata->grps_cnt; 305 sirfsoc_pmx_functions = pdata->funcs; 306 sirfsoc_pmxfunc_cnt = pdata->funcs_cnt; 307 sirfsoc_pinmux_desc.pins = pdata->pads; 308 sirfsoc_pinmux_desc.npins = pdata->pads_cnt; 309 310 311 /* Now register the pin controller and all pins it handles */ 312 spmx->pmx = pinctrl_register(&sirfsoc_pinmux_desc, &pdev->dev, spmx); 313 if (!spmx->pmx) { 314 dev_err(&pdev->dev, "could not register SIRFSOC pinmux driver\n"); 315 ret = -EINVAL; 316 goto out_no_pmx; 317 } 318 319 dev_info(&pdev->dev, "initialized SIRFSOC pinmux driver\n"); 320 321 return 0; 322 323out_no_pmx: 324 iounmap(spmx->rsc_virtbase); 325out_no_rsc_remap: 326 iounmap(spmx->gpio_virtbase); 327 return ret; 328} 329 330#ifdef CONFIG_PM_SLEEP 331static int sirfsoc_pinmux_suspend_noirq(struct device *dev) 332{ 333 int i, j; 334 struct sirfsoc_pmx *spmx = dev_get_drvdata(dev); 335 336 for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) { 337 for (j = 0; j < SIRFSOC_GPIO_BANK_SIZE; j++) { 338 spmx->gpio_regs[i][j] = readl(spmx->gpio_virtbase + 339 SIRFSOC_GPIO_CTRL(i, j)); 340 } 341 spmx->ints_regs[i] = readl(spmx->gpio_virtbase + 342 SIRFSOC_GPIO_INT_STATUS(i)); 343 spmx->paden_regs[i] = readl(spmx->gpio_virtbase + 344 SIRFSOC_GPIO_PAD_EN(i)); 345 } 346 spmx->dspen_regs = readl(spmx->gpio_virtbase + SIRFSOC_GPIO_DSP_EN0); 347 348 for (i = 0; i < 3; i++) 349 spmx->rsc_regs[i] = readl(spmx->rsc_virtbase + 4 * i); 350 351 return 0; 352} 353 354static int sirfsoc_pinmux_resume_noirq(struct device *dev) 355{ 356 int i, j; 357 struct sirfsoc_pmx *spmx = dev_get_drvdata(dev); 358 359 for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) { 360 for (j = 0; j < SIRFSOC_GPIO_BANK_SIZE; j++) { 361 writel(spmx->gpio_regs[i][j], spmx->gpio_virtbase + 362 SIRFSOC_GPIO_CTRL(i, j)); 363 } 364 writel(spmx->ints_regs[i], spmx->gpio_virtbase + 365 SIRFSOC_GPIO_INT_STATUS(i)); 366 writel(spmx->paden_regs[i], spmx->gpio_virtbase + 367 SIRFSOC_GPIO_PAD_EN(i)); 368 } 369 writel(spmx->dspen_regs, spmx->gpio_virtbase + SIRFSOC_GPIO_DSP_EN0); 370 371 for (i = 0; i < 3; i++) 372 writel(spmx->rsc_regs[i], spmx->rsc_virtbase + 4 * i); 373 374 return 0; 375} 376 377static const struct dev_pm_ops sirfsoc_pinmux_pm_ops = { 378 .suspend_noirq = sirfsoc_pinmux_suspend_noirq, 379 .resume_noirq = sirfsoc_pinmux_resume_noirq, 380 .freeze_noirq = sirfsoc_pinmux_suspend_noirq, 381 .restore_noirq = sirfsoc_pinmux_resume_noirq, 382}; 383#endif 384 385static struct platform_driver sirfsoc_pinmux_driver = { 386 .driver = { 387 .name = DRIVER_NAME, 388 .of_match_table = pinmux_ids, 389#ifdef CONFIG_PM_SLEEP 390 .pm = &sirfsoc_pinmux_pm_ops, 391#endif 392 }, 393 .probe = sirfsoc_pinmux_probe, 394}; 395 396static int __init sirfsoc_pinmux_init(void) 397{ 398 return platform_driver_register(&sirfsoc_pinmux_driver); 399} 400arch_initcall(sirfsoc_pinmux_init); 401 402static inline struct sirfsoc_gpio_chip *to_sirfsoc_gpio(struct gpio_chip *gc) 403{ 404 return container_of(gc, struct sirfsoc_gpio_chip, chip.gc); 405} 406 407static inline struct sirfsoc_gpio_bank * 408sirfsoc_gpio_to_bank(struct sirfsoc_gpio_chip *sgpio, unsigned int offset) 409{ 410 return &sgpio->sgpio_bank[offset / SIRFSOC_GPIO_BANK_SIZE]; 411} 412 413static inline int sirfsoc_gpio_to_bankoff(unsigned int offset) 414{ 415 return offset % SIRFSOC_GPIO_BANK_SIZE; 416} 417 418static void sirfsoc_gpio_irq_ack(struct irq_data *d) 419{ 420 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 421 struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(gc); 422 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq); 423 int idx = sirfsoc_gpio_to_bankoff(d->hwirq); 424 u32 val, offset; 425 unsigned long flags; 426 427 offset = SIRFSOC_GPIO_CTRL(bank->id, idx); 428 429 spin_lock_irqsave(&sgpio->lock, flags); 430 431 val = readl(sgpio->chip.regs + offset); 432 433 writel(val, sgpio->chip.regs + offset); 434 435 spin_unlock_irqrestore(&sgpio->lock, flags); 436} 437 438static void __sirfsoc_gpio_irq_mask(struct sirfsoc_gpio_chip *sgpio, 439 struct sirfsoc_gpio_bank *bank, 440 int idx) 441{ 442 u32 val, offset; 443 unsigned long flags; 444 445 offset = SIRFSOC_GPIO_CTRL(bank->id, idx); 446 447 spin_lock_irqsave(&sgpio->lock, flags); 448 449 val = readl(sgpio->chip.regs + offset); 450 val &= ~SIRFSOC_GPIO_CTL_INTR_EN_MASK; 451 val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK; 452 writel(val, sgpio->chip.regs + offset); 453 454 spin_unlock_irqrestore(&sgpio->lock, flags); 455} 456 457static void sirfsoc_gpio_irq_mask(struct irq_data *d) 458{ 459 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 460 struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(gc); 461 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq); 462 463 __sirfsoc_gpio_irq_mask(sgpio, bank, d->hwirq % SIRFSOC_GPIO_BANK_SIZE); 464} 465 466static void sirfsoc_gpio_irq_unmask(struct irq_data *d) 467{ 468 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 469 struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(gc); 470 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq); 471 int idx = sirfsoc_gpio_to_bankoff(d->hwirq); 472 u32 val, offset; 473 unsigned long flags; 474 475 offset = SIRFSOC_GPIO_CTRL(bank->id, idx); 476 477 spin_lock_irqsave(&sgpio->lock, flags); 478 479 val = readl(sgpio->chip.regs + offset); 480 val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK; 481 val |= SIRFSOC_GPIO_CTL_INTR_EN_MASK; 482 writel(val, sgpio->chip.regs + offset); 483 484 spin_unlock_irqrestore(&sgpio->lock, flags); 485} 486 487static int sirfsoc_gpio_irq_type(struct irq_data *d, unsigned type) 488{ 489 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 490 struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(gc); 491 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq); 492 int idx = sirfsoc_gpio_to_bankoff(d->hwirq); 493 u32 val, offset; 494 unsigned long flags; 495 496 offset = SIRFSOC_GPIO_CTRL(bank->id, idx); 497 498 spin_lock_irqsave(&sgpio->lock, flags); 499 500 val = readl(sgpio->chip.regs + offset); 501 val &= ~(SIRFSOC_GPIO_CTL_INTR_STS_MASK | SIRFSOC_GPIO_CTL_OUT_EN_MASK); 502 503 switch (type) { 504 case IRQ_TYPE_NONE: 505 break; 506 case IRQ_TYPE_EDGE_RISING: 507 val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | 508 SIRFSOC_GPIO_CTL_INTR_TYPE_MASK; 509 val &= ~SIRFSOC_GPIO_CTL_INTR_LOW_MASK; 510 break; 511 case IRQ_TYPE_EDGE_FALLING: 512 val &= ~SIRFSOC_GPIO_CTL_INTR_HIGH_MASK; 513 val |= SIRFSOC_GPIO_CTL_INTR_LOW_MASK | 514 SIRFSOC_GPIO_CTL_INTR_TYPE_MASK; 515 break; 516 case IRQ_TYPE_EDGE_BOTH: 517 val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | 518 SIRFSOC_GPIO_CTL_INTR_LOW_MASK | 519 SIRFSOC_GPIO_CTL_INTR_TYPE_MASK; 520 break; 521 case IRQ_TYPE_LEVEL_LOW: 522 val &= ~(SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | 523 SIRFSOC_GPIO_CTL_INTR_TYPE_MASK); 524 val |= SIRFSOC_GPIO_CTL_INTR_LOW_MASK; 525 break; 526 case IRQ_TYPE_LEVEL_HIGH: 527 val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK; 528 val &= ~(SIRFSOC_GPIO_CTL_INTR_LOW_MASK | 529 SIRFSOC_GPIO_CTL_INTR_TYPE_MASK); 530 break; 531 } 532 533 writel(val, sgpio->chip.regs + offset); 534 535 spin_unlock_irqrestore(&sgpio->lock, flags); 536 537 return 0; 538} 539 540static struct irq_chip sirfsoc_irq_chip = { 541 .name = "sirf-gpio-irq", 542 .irq_ack = sirfsoc_gpio_irq_ack, 543 .irq_mask = sirfsoc_gpio_irq_mask, 544 .irq_unmask = sirfsoc_gpio_irq_unmask, 545 .irq_set_type = sirfsoc_gpio_irq_type, 546}; 547 548static void sirfsoc_gpio_handle_irq(unsigned int irq, struct irq_desc *desc) 549{ 550 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 551 struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(gc); 552 struct sirfsoc_gpio_bank *bank; 553 u32 status, ctrl; 554 int idx = 0; 555 struct irq_chip *chip = irq_get_chip(irq); 556 int i; 557 558 for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) { 559 bank = &sgpio->sgpio_bank[i]; 560 if (bank->parent_irq == irq) 561 break; 562 } 563 BUG_ON(i == SIRFSOC_GPIO_NO_OF_BANKS); 564 565 chained_irq_enter(chip, desc); 566 567 status = readl(sgpio->chip.regs + SIRFSOC_GPIO_INT_STATUS(bank->id)); 568 if (!status) { 569 printk(KERN_WARNING 570 "%s: gpio id %d status %#x no interrupt is flagged\n", 571 __func__, bank->id, status); 572 handle_bad_irq(irq, desc); 573 return; 574 } 575 576 while (status) { 577 ctrl = readl(sgpio->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, idx)); 578 579 /* 580 * Here we must check whether the corresponding GPIO's interrupt 581 * has been enabled, otherwise just skip it 582 */ 583 if ((status & 0x1) && (ctrl & SIRFSOC_GPIO_CTL_INTR_EN_MASK)) { 584 pr_debug("%s: gpio id %d idx %d happens\n", 585 __func__, bank->id, idx); 586 generic_handle_irq(irq_find_mapping(gc->irqdomain, idx + 587 bank->id * SIRFSOC_GPIO_BANK_SIZE)); 588 } 589 590 idx++; 591 status = status >> 1; 592 } 593 594 chained_irq_exit(chip, desc); 595} 596 597static inline void sirfsoc_gpio_set_input(struct sirfsoc_gpio_chip *sgpio, 598 unsigned ctrl_offset) 599{ 600 u32 val; 601 602 val = readl(sgpio->chip.regs + ctrl_offset); 603 val &= ~SIRFSOC_GPIO_CTL_OUT_EN_MASK; 604 writel(val, sgpio->chip.regs + ctrl_offset); 605} 606 607static int sirfsoc_gpio_request(struct gpio_chip *chip, unsigned offset) 608{ 609 struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(chip); 610 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset); 611 unsigned long flags; 612 613 if (pinctrl_request_gpio(chip->base + offset)) 614 return -ENODEV; 615 616 spin_lock_irqsave(&bank->lock, flags); 617 618 /* 619 * default status: 620 * set direction as input and mask irq 621 */ 622 sirfsoc_gpio_set_input(sgpio, SIRFSOC_GPIO_CTRL(bank->id, offset)); 623 __sirfsoc_gpio_irq_mask(sgpio, bank, offset); 624 625 spin_unlock_irqrestore(&bank->lock, flags); 626 627 return 0; 628} 629 630static void sirfsoc_gpio_free(struct gpio_chip *chip, unsigned offset) 631{ 632 struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(chip); 633 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset); 634 unsigned long flags; 635 636 spin_lock_irqsave(&bank->lock, flags); 637 638 __sirfsoc_gpio_irq_mask(sgpio, bank, offset); 639 sirfsoc_gpio_set_input(sgpio, SIRFSOC_GPIO_CTRL(bank->id, offset)); 640 641 spin_unlock_irqrestore(&bank->lock, flags); 642 643 pinctrl_free_gpio(chip->base + offset); 644} 645 646static int sirfsoc_gpio_direction_input(struct gpio_chip *chip, unsigned gpio) 647{ 648 struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(chip); 649 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, gpio); 650 int idx = sirfsoc_gpio_to_bankoff(gpio); 651 unsigned long flags; 652 unsigned offset; 653 654 offset = SIRFSOC_GPIO_CTRL(bank->id, idx); 655 656 spin_lock_irqsave(&bank->lock, flags); 657 658 sirfsoc_gpio_set_input(sgpio, offset); 659 660 spin_unlock_irqrestore(&bank->lock, flags); 661 662 return 0; 663} 664 665static inline void sirfsoc_gpio_set_output(struct sirfsoc_gpio_chip *sgpio, 666 struct sirfsoc_gpio_bank *bank, 667 unsigned offset, 668 int value) 669{ 670 u32 out_ctrl; 671 unsigned long flags; 672 673 spin_lock_irqsave(&bank->lock, flags); 674 675 out_ctrl = readl(sgpio->chip.regs + offset); 676 if (value) 677 out_ctrl |= SIRFSOC_GPIO_CTL_DATAOUT_MASK; 678 else 679 out_ctrl &= ~SIRFSOC_GPIO_CTL_DATAOUT_MASK; 680 681 out_ctrl &= ~SIRFSOC_GPIO_CTL_INTR_EN_MASK; 682 out_ctrl |= SIRFSOC_GPIO_CTL_OUT_EN_MASK; 683 writel(out_ctrl, sgpio->chip.regs + offset); 684 685 spin_unlock_irqrestore(&bank->lock, flags); 686} 687 688static int sirfsoc_gpio_direction_output(struct gpio_chip *chip, 689 unsigned gpio, int value) 690{ 691 struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(chip); 692 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, gpio); 693 int idx = sirfsoc_gpio_to_bankoff(gpio); 694 u32 offset; 695 unsigned long flags; 696 697 offset = SIRFSOC_GPIO_CTRL(bank->id, idx); 698 699 spin_lock_irqsave(&sgpio->lock, flags); 700 701 sirfsoc_gpio_set_output(sgpio, bank, offset, value); 702 703 spin_unlock_irqrestore(&sgpio->lock, flags); 704 705 return 0; 706} 707 708static int sirfsoc_gpio_get_value(struct gpio_chip *chip, unsigned offset) 709{ 710 struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(chip); 711 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset); 712 u32 val; 713 unsigned long flags; 714 715 spin_lock_irqsave(&bank->lock, flags); 716 717 val = readl(sgpio->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset)); 718 719 spin_unlock_irqrestore(&bank->lock, flags); 720 721 return !!(val & SIRFSOC_GPIO_CTL_DATAIN_MASK); 722} 723 724static void sirfsoc_gpio_set_value(struct gpio_chip *chip, unsigned offset, 725 int value) 726{ 727 struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(chip); 728 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset); 729 u32 ctrl; 730 unsigned long flags; 731 732 spin_lock_irqsave(&bank->lock, flags); 733 734 ctrl = readl(sgpio->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset)); 735 if (value) 736 ctrl |= SIRFSOC_GPIO_CTL_DATAOUT_MASK; 737 else 738 ctrl &= ~SIRFSOC_GPIO_CTL_DATAOUT_MASK; 739 writel(ctrl, sgpio->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset)); 740 741 spin_unlock_irqrestore(&bank->lock, flags); 742} 743 744static void sirfsoc_gpio_set_pullup(struct sirfsoc_gpio_chip *sgpio, 745 const u32 *pullups) 746{ 747 int i, n; 748 const unsigned long *p = (const unsigned long *)pullups; 749 750 for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) { 751 for_each_set_bit(n, p + i, BITS_PER_LONG) { 752 u32 offset = SIRFSOC_GPIO_CTRL(i, n); 753 u32 val = readl(sgpio->chip.regs + offset); 754 val |= SIRFSOC_GPIO_CTL_PULL_MASK; 755 val |= SIRFSOC_GPIO_CTL_PULL_HIGH; 756 writel(val, sgpio->chip.regs + offset); 757 } 758 } 759} 760 761static void sirfsoc_gpio_set_pulldown(struct sirfsoc_gpio_chip *sgpio, 762 const u32 *pulldowns) 763{ 764 int i, n; 765 const unsigned long *p = (const unsigned long *)pulldowns; 766 767 for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) { 768 for_each_set_bit(n, p + i, BITS_PER_LONG) { 769 u32 offset = SIRFSOC_GPIO_CTRL(i, n); 770 u32 val = readl(sgpio->chip.regs + offset); 771 val |= SIRFSOC_GPIO_CTL_PULL_MASK; 772 val &= ~SIRFSOC_GPIO_CTL_PULL_HIGH; 773 writel(val, sgpio->chip.regs + offset); 774 } 775 } 776} 777 778static int sirfsoc_gpio_probe(struct device_node *np) 779{ 780 int i, err = 0; 781 static struct sirfsoc_gpio_chip *sgpio; 782 struct sirfsoc_gpio_bank *bank; 783 void __iomem *regs; 784 struct platform_device *pdev; 785 786 u32 pullups[SIRFSOC_GPIO_NO_OF_BANKS], pulldowns[SIRFSOC_GPIO_NO_OF_BANKS]; 787 788 pdev = of_find_device_by_node(np); 789 if (!pdev) 790 return -ENODEV; 791 792 sgpio = devm_kzalloc(&pdev->dev, sizeof(*sgpio), GFP_KERNEL); 793 if (!sgpio) 794 return -ENOMEM; 795 spin_lock_init(&sgpio->lock); 796 797 regs = of_iomap(np, 0); 798 if (!regs) 799 return -ENOMEM; 800 801 sgpio->chip.gc.request = sirfsoc_gpio_request; 802 sgpio->chip.gc.free = sirfsoc_gpio_free; 803 sgpio->chip.gc.direction_input = sirfsoc_gpio_direction_input; 804 sgpio->chip.gc.get = sirfsoc_gpio_get_value; 805 sgpio->chip.gc.direction_output = sirfsoc_gpio_direction_output; 806 sgpio->chip.gc.set = sirfsoc_gpio_set_value; 807 sgpio->chip.gc.base = 0; 808 sgpio->chip.gc.ngpio = SIRFSOC_GPIO_BANK_SIZE * SIRFSOC_GPIO_NO_OF_BANKS; 809 sgpio->chip.gc.label = kstrdup(np->full_name, GFP_KERNEL); 810 sgpio->chip.gc.of_node = np; 811 sgpio->chip.gc.of_xlate = sirfsoc_gpio_of_xlate; 812 sgpio->chip.gc.of_gpio_n_cells = 2; 813 sgpio->chip.gc.dev = &pdev->dev; 814 sgpio->chip.regs = regs; 815 816 err = gpiochip_add(&sgpio->chip.gc); 817 if (err) { 818 dev_err(&pdev->dev, "%s: error in probe function with status %d\n", 819 np->full_name, err); 820 goto out; 821 } 822 823 err = gpiochip_irqchip_add(&sgpio->chip.gc, 824 &sirfsoc_irq_chip, 825 0, handle_level_irq, 826 IRQ_TYPE_NONE); 827 if (err) { 828 dev_err(&pdev->dev, 829 "could not connect irqchip to gpiochip\n"); 830 goto out_banks; 831 } 832 833 for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) { 834 bank = &sgpio->sgpio_bank[i]; 835 spin_lock_init(&bank->lock); 836 bank->parent_irq = platform_get_irq(pdev, i); 837 if (bank->parent_irq < 0) { 838 err = bank->parent_irq; 839 goto out_banks; 840 } 841 842 gpiochip_set_chained_irqchip(&sgpio->chip.gc, 843 &sirfsoc_irq_chip, 844 bank->parent_irq, 845 sirfsoc_gpio_handle_irq); 846 } 847 848 err = gpiochip_add_pin_range(&sgpio->chip.gc, dev_name(&pdev->dev), 849 0, 0, SIRFSOC_GPIO_BANK_SIZE * SIRFSOC_GPIO_NO_OF_BANKS); 850 if (err) { 851 dev_err(&pdev->dev, 852 "could not add gpiochip pin range\n"); 853 goto out_no_range; 854 } 855 856 if (!of_property_read_u32_array(np, "sirf,pullups", pullups, 857 SIRFSOC_GPIO_NO_OF_BANKS)) 858 sirfsoc_gpio_set_pullup(sgpio, pullups); 859 860 if (!of_property_read_u32_array(np, "sirf,pulldowns", pulldowns, 861 SIRFSOC_GPIO_NO_OF_BANKS)) 862 sirfsoc_gpio_set_pulldown(sgpio, pulldowns); 863 864 return 0; 865 866out_no_range: 867out_banks: 868 gpiochip_remove(&sgpio->chip.gc); 869out: 870 iounmap(regs); 871 return err; 872} 873 874static int __init sirfsoc_gpio_init(void) 875{ 876 877 struct device_node *np; 878 879 np = of_find_matching_node(NULL, pinmux_ids); 880 881 if (!np) 882 return -ENODEV; 883 884 return sirfsoc_gpio_probe(np); 885} 886subsys_initcall(sirfsoc_gpio_init); 887 888MODULE_AUTHOR("Rongjun Ying <rongjun.ying@csr.com>"); 889MODULE_AUTHOR("Yuping Luo <yuping.luo@csr.com>"); 890MODULE_AUTHOR("Barry Song <baohua.song@csr.com>"); 891MODULE_DESCRIPTION("SIRFSOC pin control driver"); 892MODULE_LICENSE("GPL"); 893