| /linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ |
| H A D | ramseq.h | 5 #define ram_init(s,p) hwsq_init(&(s)->base, (p))
6 #define ram_exec(s,e) hwsq_exec(&(s)->base, (e))
8 #define ram_rd32(s,r) hwsq_rd32(&(s)->base, &(s)->r_##r)
9 #define ram_wr32(s,r,d) hwsq_wr32(&(s)->base, &(s)->r_##r, (d))
10 #define ram_nuke(s,r) hwsq_nuke(&(s)->base, &(s)->r_##r)
11 #define ram_mask(s,r,m,d) hwsq_mask(&(s)->base, &(s)->r_##r, (m), (d))
12 #define ram_setf(s,f,d) hwsq_setf(&(s)->base, (f), (d))
13 #define ram_wait(s,f,d) hwsq_wait(&(s)->base, (f), (d))
14 #define ram_wait_vblank(s) hwsq_wait_vblank(&(s)->base)
15 #define ram_nsec(s,n) hwsq_nsec(&(s)->base, (n))
|
| H A D | ramnv40.h | 3 #define nv40_ram(p) container_of((p), struct nv40_ram, base)
7 struct nvkm_ram base; member in struct:nv40_ram
|
| H A D | rammcp77.c | 24 #define mcp77_ram(p) container_of((p), struct mcp77_ram, base)
28 struct nvkm_ram base; member in struct:mcp77_ram
33 mcp77_ram_init(struct nvkm_ram *base) mcp77_ram_init() argument
35 struct mcp77_ram *ram = mcp77_ram(base); mcp77_ram_init()
36 struct nvkm_device *device = ram->base.fb->subdev.device; mcp77_ram_init()
37 u32 dniso = ((ram->base.size - (ram->poller_base + 0x00)) >> 5) - 1; mcp77_ram_init()
38 u32 hostnb = ((ram->base.size - (ram->poller_base + 0x20)) >> 5) - 1; mcp77_ram_init()
39 u32 flush = ((ram->base.size - (ram->poller_base + 0x40)) >> 5) - 1; mcp77_ram_init()
66 u64 base = (u64)nvkm_rd32(device, 0x100e10) << 12; mcp77_ram_new() local
73 *pram = &ram->base; mcp77_ram_new()
76 size, 0, &ram->base); mcp77_ram_new()
81 ram->base.stolen = base; mcp77_ram_new()
82 nvkm_mm_fini(&ram->base.vram); mcp77_ram_new()
84 return nvkm_mm_init(&ram->base.vram, rsvd_head >> NVKM_RAM_MM_SHIFT, mcp77_ram_new()
|
| H A D | gf100.h | 3 #define gf100_fb(p) container_of((p), struct gf100_fb, base)
7 struct nvkm_fb base; member in struct:gf100_fb
|
| H A D | nv50.h | 3 #define nv50_fb(p) container_of((p), struct nv50_fb, base)
8 struct nvkm_fb base; member in struct:nv50_fb
|
| /linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/subdev/clk/ |
| H A D | seq.h | 5 #define clk_init(s,p) hwsq_init(&(s)->base, (p))
6 #define clk_exec(s,e) hwsq_exec(&(s)->base, (e))
8 #define clk_rd32(s,r) hwsq_rd32(&(s)->base, &(s)->r_##r)
9 #define clk_wr32(s,r,d) hwsq_wr32(&(s)->base, &(s)->r_##r, (d))
10 #define clk_mask(s,r,m,d) hwsq_mask(&(s)->base, &(s)->r_##r, (m), (d))
11 #define clk_setf(s,f,d) hwsq_setf(&(s)->base, (f), (d))
12 #define clk_wait(s,f,d) hwsq_wait(&(s)->base, (f), (d))
13 #define clk_nsec(s,n) hwsq_nsec(&(s)->base, (n))
|
| H A D | nv50.h | 3 #define nv50_clk(p) container_of((p), struct nv50_clk, base)
9 struct hwsq base; member in struct:nv50_clk_hwsq
18 struct nvkm_clk base; member in struct:nv50_clk
|
| H A D | nv50.c | 34 struct nvkm_device *device = clk->base.subdev.device; read_div()
52 read_pll_src(struct nv50_clk *clk, u32 base) read_pll_src() argument
54 struct nvkm_subdev *subdev = &clk->base.subdev; read_pll_src()
56 u32 coef, ref = nvkm_clk_read(&clk->base, nv_clk_src_crystal); read_pll_src()
63 switch (base) { read_pll_src()
69 nvkm_error(subdev, "ref: bad pll %06x\n", base); read_pll_src()
91 switch (base) { read_pll_src()
97 nvkm_error(subdev, "ref: bad pll %06x\n", base); read_pll_src()
103 case 1: return nvkm_clk_read(&clk->base, nv_clk_src_crystal); read_pll_src()
104 case 2: return nvkm_clk_read(&clk->base, nv_clk_src_href); read_pll_src()
125 read_pll_ref(struct nv50_clk *clk, u32 base) read_pll_ref() argument
127 struct nvkm_subdev *subdev = &clk->base.subdev; read_pll_ref()
131 switch (base) { read_pll_ref()
145 return nvkm_clk_read(&clk->base, nv_clk_src_crystal); read_pll_ref()
147 nvkm_error(subdev, "bad pll %06x\n", base); read_pll_ref()
152 return nvkm_clk_read(&clk->base, nv_clk_src_href); read_pll_ref()
154 return read_pll_src(clk, base); read_pll_ref()
158 read_pll(struct nv50_clk *clk, u32 base) read_pll() argument
160 struct nvkm_device *device = clk->base.subdev.device; read_pll()
162 u32 ctrl = nvkm_rd32(device, base + 0); read_pll()
163 u32 coef = nvkm_rd32(device, base + 4); read_pll()
164 u32 ref = read_pll_ref(clk, base); read_pll()
168 if (base == 0x004028 && (mast & 0x00100000)) { read_pll()
171 return nvkm_clk_read(&clk->base, nv_clk_src_dom6); read_pll()
192 nv50_clk_read(struct nvkm_clk *base, enum nv_clk_src src) nv50_clk_read() argument
194 struct nv50_clk *clk = nv50_clk(base); nv50_clk_read()
195 struct nvkm_subdev *subdev = &clk->base.subdev; nv50_clk_read()
206 return div_u64((u64)nvkm_clk_read(&clk->base, nv_clk_src_href) * 27778, 10000); nv50_clk_read()
208 return nvkm_clk_read(&clk->base, nv_clk_src_hclk) * 3; nv50_clk_read()
210 return nvkm_clk_read(&clk->base, nv_clk_src_hclk) * 3 / 2; nv50_clk_read()
213 case 0x00000000: return nvkm_clk_read(&clk->base, nv_clk_src_href); nv50_clk_read()
216 case 0x30000000: return nvkm_clk_read(&clk->base, nv_clk_src_hclk); nv50_clk_read()
223 case 0x00000000: return nvkm_clk_read(&clk->base, nv_clk_src_crystal) >> P; nv50_clk_read()
224 case 0x00000001: return nvkm_clk_read(&clk->base, nv_clk_src_dom6); nv50_clk_read()
234 return nvkm_clk_read(&clk->base, nv_clk_src_host) >> P; nv50_clk_read()
235 return nvkm_clk_read(&clk->base, nv_clk_src_crystal) >> P; nv50_clk_read()
246 return nvkm_clk_read(&clk->base, nv_clk_src_crystal) >> P; nv50_clk_read()
249 return nvkm_clk_read(&clk->base, nv_clk_src_href) >> P; nv50_clk_read()
267 return nvkm_clk_read(&clk->base, nv_clk_src_core) >> P; nv50_clk_read()
268 return nvkm_clk_read(&clk->base, nv_clk_src_crystal) >> P; nv50_clk_read()
276 return nvkm_clk_read(&clk->base, nv_clk_src_core) >> P; nv50_clk_read()
282 return nvkm_clk_read(&clk->base, nv_clk_src_core) >> P; nv50_clk_read()
286 return nvkm_clk_read(&clk->base, nv_clk_src_hclkm3d2) >> P; nv50_clk_read()
288 return nvkm_clk_read(&clk->base, nv_clk_src_mem) >> P; nv50_clk_read()
306 case 0x00000000: return nvkm_clk_read(&clk->base, nv_clk_src_href); nv50_clk_read()
308 case 0x08000000: return nvkm_clk_read(&clk->base, nv_clk_src_hclk); nv50_clk_read()
310 return nvkm_clk_read(&clk->base, nv_clk_src_hclkm3) >> P; nv50_clk_read()
327 struct nvkm_subdev *subdev = &clk->base.subdev; calc_pll()
368 nv50_clk_calc(struct nvkm_clk *base, struct nvkm_cstate *cstate) nv50_clk_calc() argument
370 struct nv50_clk *clk = nv50_clk(base); nv50_clk_calc()
372 struct nvkm_subdev *subdev = &clk->base.subdev; nv50_clk_calc()
405 out = nvkm_clk_read(&clk->base, nv_clk_src_hclkm3d2); nv50_clk_calc()
426 if (clk_same(dom6, nvkm_clk_read(&clk->base, nv_clk_src_href))) { nv50_clk_calc()
429 if (clk_same(dom6, nvkm_clk_read(&clk->base, nv_clk_src_hclk))) { nv50_clk_calc()
432 freq = nvkm_clk_read(&clk->base, nv_clk_src_hclk) * 3; nv50_clk_calc()
495 nv50_clk_prog(struct nvkm_clk *base) nv50_clk_prog() argument
497 struct nv50_clk *clk = nv50_clk(base); nv50_clk_prog()
502 nv50_clk_tidy(struct nvkm_clk *base) nv50_clk_tidy() argument
504 struct nv50_clk *clk = nv50_clk(base); nv50_clk_tidy()
517 ret = nvkm_clk_ctor(func, device, index, allow_reclock, &clk->base); nv50_clk_new_()
518 *pclk = &clk->base; nv50_clk_new_()
|
| H A D | mcp77.c | 24 #define mcp77_clk(p) container_of((p), struct mcp77_clk, base)
33 struct nvkm_clk base; member in struct:mcp77_clk
44 struct nvkm_device *device = clk->base.subdev.device; read_div()
49 read_pll(struct mcp77_clk *clk, u32 base) read_pll() argument
51 struct nvkm_device *device = clk->base.subdev.device; read_pll()
52 u32 ctrl = nvkm_rd32(device, base + 0); read_pll()
53 u32 coef = nvkm_rd32(device, base + 4); read_pll()
54 u32 ref = nvkm_clk_read(&clk->base, nv_clk_src_href); read_pll()
59 switch (base){ read_pll()
81 mcp77_clk_read(struct nvkm_clk *base, enum nv_clk_src src) mcp77_clk_read() argument
83 struct mcp77_clk *clk = mcp77_clk(base); mcp77_clk_read()
84 struct nvkm_subdev *subdev = &clk->base.subdev; mcp77_clk_read()
95 return nvkm_clk_read(&clk->base, nv_clk_src_href) * 4; mcp77_clk_read()
97 return nvkm_clk_read(&clk->base, nv_clk_src_href) * 2 / 3; mcp77_clk_read()
100 case 0x00000000: return nvkm_clk_read(&clk->base, nv_clk_src_hclkm2d3); mcp77_clk_read()
102 case 0x00080000: return nvkm_clk_read(&clk->base, nv_clk_src_hclkm4); mcp77_clk_read()
103 case 0x000c0000: return nvkm_clk_read(&clk->base, nv_clk_src_cclk); mcp77_clk_read()
110 case 0x00000000: return nvkm_clk_read(&clk->base, nv_clk_src_crystal) >> P; mcp77_clk_read()
112 case 0x00000002: return nvkm_clk_read(&clk->base, nv_clk_src_hclkm4) >> P; mcp77_clk_read()
118 return nvkm_clk_read(&clk->base, nv_clk_src_core); mcp77_clk_read()
121 return nvkm_clk_read(&clk->base, nv_clk_src_core); mcp77_clk_read()
124 case 0x00000000: return nvkm_clk_read(&clk->base, nv_clk_src_href); mcp77_clk_read()
125 case 0x00000400: return nvkm_clk_read(&clk->base, nv_clk_src_hclkm4); mcp77_clk_read()
126 case 0x00000800: return nvkm_clk_read(&clk->base, nv_clk_src_hclkm2d3); mcp77_clk_read()
134 return nvkm_clk_read(&clk->base, nv_clk_src_href) >> P; mcp77_clk_read()
135 return nvkm_clk_read(&clk->base, nv_clk_src_crystal) >> P; mcp77_clk_read()
149 return nvkm_clk_read(&clk->base, nv_clk_src_core) >> P; mcp77_clk_read()
168 struct nvkm_subdev *subdev = &clk->base.subdev; calc_pll()
177 pll.refclk = nvkm_clk_read(&clk->base, nv_clk_src_href); calc_pll()
203 mcp77_clk_calc(struct nvkm_clk *base, struct nvkm_cstate *cstate) mcp77_clk_calc() argument
205 struct mcp77_clk *clk = mcp77_clk(base); mcp77_clk_calc()
209 struct nvkm_subdev *subdev = &clk->base.subdev; mcp77_clk_calc()
215 if (core < nvkm_clk_read(&clk->base, nv_clk_src_hclkm4)) mcp77_clk_calc()
216 out = calc_P(nvkm_clk_read(&clk->base, nv_clk_src_hclkm4), core, &divs); mcp77_clk_calc()
242 if (shader == nvkm_clk_read(&clk->base, nv_clk_src_href)) { mcp77_clk_calc()
299 mcp77_clk_prog(struct nvkm_clk *base) mcp77_clk_prog() argument
301 struct mcp77_clk *clk = mcp77_clk(base); mcp77_clk_prog()
302 struct nvkm_subdev *subdev = &clk->base.subdev; mcp77_clk_prog()
309 ret = gt215_clk_pre(&clk->base, f); mcp77_clk_prog()
388 gt215_clk_post(&clk->base, f); mcp77_clk_prog()
393 mcp77_clk_tidy(struct nvkm_clk *base) mcp77_clk_tidy() argument
420 *pclk = &clk->base; mcp77_clk_new()
422 return nvkm_clk_ctor(&mcp77_clk, device, index, true, &clk->base); mcp77_clk_new()
|
| /linux-4.4.14/drivers/gpu/drm/msm/dsi/phy/ |
| H A D | dsi_phy_28nm.c | 20 void __iomem *base = phy->base; dsi_28nm_dphy_set_timing() local
22 dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_0, dsi_28nm_dphy_set_timing()
24 dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_1, dsi_28nm_dphy_set_timing()
26 dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_2, dsi_28nm_dphy_set_timing()
29 dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_3, dsi_28nm_dphy_set_timing()
31 dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_4, dsi_28nm_dphy_set_timing()
33 dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_5, dsi_28nm_dphy_set_timing()
35 dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_6, dsi_28nm_dphy_set_timing()
37 dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_7, dsi_28nm_dphy_set_timing()
39 dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_8, dsi_28nm_dphy_set_timing()
41 dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_9, dsi_28nm_dphy_set_timing()
44 dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_10, dsi_28nm_dphy_set_timing()
46 dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_11, dsi_28nm_dphy_set_timing()
52 void __iomem *base = phy->reg_base; dsi_28nm_phy_regulator_ctrl() local
55 dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CAL_PWR_CFG, 0); dsi_28nm_phy_regulator_ctrl()
59 dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_0, 0x0); dsi_28nm_phy_regulator_ctrl()
60 dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CAL_PWR_CFG, 1); dsi_28nm_phy_regulator_ctrl()
61 dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_5, 0); dsi_28nm_phy_regulator_ctrl()
62 dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_3, 0); dsi_28nm_phy_regulator_ctrl()
63 dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_2, 0x3); dsi_28nm_phy_regulator_ctrl()
64 dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_1, 0x9); dsi_28nm_phy_regulator_ctrl()
65 dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_0, 0x7); dsi_28nm_phy_regulator_ctrl()
66 dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_4, 0x20); dsi_28nm_phy_regulator_ctrl()
74 void __iomem *base = phy->base; dsi_28nm_phy_enable() local
84 dsi_phy_write(base + REG_DSI_28nm_PHY_STRENGTH_0, 0xff); dsi_28nm_phy_enable()
88 dsi_phy_write(base + REG_DSI_28nm_PHY_LDO_CNTRL, 0x00); dsi_28nm_phy_enable()
92 dsi_phy_write(base + REG_DSI_28nm_PHY_CTRL_1, 0x00); dsi_28nm_phy_enable()
93 dsi_phy_write(base + REG_DSI_28nm_PHY_CTRL_0, 0x5f); dsi_28nm_phy_enable()
95 dsi_phy_write(base + REG_DSI_28nm_PHY_STRENGTH_1, 0x6); dsi_28nm_phy_enable()
98 dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_0(i), 0); dsi_28nm_phy_enable()
99 dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_1(i), 0); dsi_28nm_phy_enable()
100 dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_2(i), 0); dsi_28nm_phy_enable()
101 dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_3(i), 0); dsi_28nm_phy_enable()
102 dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_4(i), 0); dsi_28nm_phy_enable()
103 dsi_phy_write(base + REG_DSI_28nm_PHY_LN_TEST_DATAPATH(i), 0); dsi_28nm_phy_enable()
104 dsi_phy_write(base + REG_DSI_28nm_PHY_LN_DEBUG_SEL(i), 0); dsi_28nm_phy_enable()
105 dsi_phy_write(base + REG_DSI_28nm_PHY_LN_TEST_STR_0(i), 0x1); dsi_28nm_phy_enable()
106 dsi_phy_write(base + REG_DSI_28nm_PHY_LN_TEST_STR_1(i), 0x97); dsi_28nm_phy_enable()
109 dsi_phy_write(base + REG_DSI_28nm_PHY_LNCK_CFG_4, 0); dsi_28nm_phy_enable()
110 dsi_phy_write(base + REG_DSI_28nm_PHY_LNCK_CFG_1, 0xc0); dsi_28nm_phy_enable()
111 dsi_phy_write(base + REG_DSI_28nm_PHY_LNCK_TEST_STR0, 0x1); dsi_28nm_phy_enable()
112 dsi_phy_write(base + REG_DSI_28nm_PHY_LNCK_TEST_STR1, 0xbb); dsi_28nm_phy_enable()
114 dsi_phy_write(base + REG_DSI_28nm_PHY_CTRL_0, 0x5f); dsi_28nm_phy_enable()
125 dsi_phy_write(phy->base + REG_DSI_28nm_PHY_CTRL_0, 0); dsi_28nm_phy_disable()
|
| H A D | dsi_phy_20nm.c | 20 void __iomem *base = phy->base; dsi_20nm_dphy_set_timing() local
22 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_0, dsi_20nm_dphy_set_timing()
24 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_1, dsi_20nm_dphy_set_timing()
26 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_2, dsi_20nm_dphy_set_timing()
29 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_3, dsi_20nm_dphy_set_timing()
31 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_4, dsi_20nm_dphy_set_timing()
33 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_5, dsi_20nm_dphy_set_timing()
35 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_6, dsi_20nm_dphy_set_timing()
37 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_7, dsi_20nm_dphy_set_timing()
39 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_8, dsi_20nm_dphy_set_timing()
41 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_9, dsi_20nm_dphy_set_timing()
44 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_10, dsi_20nm_dphy_set_timing()
46 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_11, dsi_20nm_dphy_set_timing()
52 void __iomem *base = phy->reg_base; dsi_20nm_phy_regulator_ctrl() local
55 dsi_phy_write(base + REG_DSI_20nm_PHY_REGULATOR_CAL_PWR_CFG, 0); dsi_20nm_phy_regulator_ctrl()
60 dsi_phy_write(phy->base + REG_DSI_20nm_PHY_LDO_CNTRL, 0x1d); dsi_20nm_phy_regulator_ctrl()
65 dsi_phy_write(base + REG_DSI_20nm_PHY_REGULATOR_CTRL_1, 0x03); dsi_20nm_phy_regulator_ctrl()
66 dsi_phy_write(base + REG_DSI_20nm_PHY_REGULATOR_CTRL_2, 0x03); dsi_20nm_phy_regulator_ctrl()
67 dsi_phy_write(base + REG_DSI_20nm_PHY_REGULATOR_CTRL_3, 0x00); dsi_20nm_phy_regulator_ctrl()
68 dsi_phy_write(base + REG_DSI_20nm_PHY_REGULATOR_CTRL_4, 0x20); dsi_20nm_phy_regulator_ctrl()
69 dsi_phy_write(base + REG_DSI_20nm_PHY_REGULATOR_CAL_PWR_CFG, 0x01); dsi_20nm_phy_regulator_ctrl()
70 dsi_phy_write(phy->base + REG_DSI_20nm_PHY_LDO_CNTRL, 0x00); dsi_20nm_phy_regulator_ctrl()
71 dsi_phy_write(base + REG_DSI_20nm_PHY_REGULATOR_CTRL_0, 0x03); dsi_20nm_phy_regulator_ctrl()
79 void __iomem *base = phy->base; dsi_20nm_phy_enable() local
92 dsi_phy_write(base + REG_DSI_20nm_PHY_STRENGTH_0, 0xff); dsi_20nm_phy_enable()
99 dsi_phy_write(base + REG_DSI_20nm_PHY_LN_CFG_3(i), dsi_20nm_phy_enable()
101 dsi_phy_write(base + REG_DSI_20nm_PHY_LN_TEST_STR_0(i), 0x01); dsi_20nm_phy_enable()
102 dsi_phy_write(base + REG_DSI_20nm_PHY_LN_TEST_STR_1(i), 0x46); dsi_20nm_phy_enable()
103 dsi_phy_write(base + REG_DSI_20nm_PHY_LN_CFG_0(i), 0x02); dsi_20nm_phy_enable()
104 dsi_phy_write(base + REG_DSI_20nm_PHY_LN_CFG_1(i), 0xa0); dsi_20nm_phy_enable()
105 dsi_phy_write(base + REG_DSI_20nm_PHY_LN_CFG_4(i), cfg_4[i]); dsi_20nm_phy_enable()
108 dsi_phy_write(base + REG_DSI_20nm_PHY_LNCK_CFG_3, 0x80); dsi_20nm_phy_enable()
109 dsi_phy_write(base + REG_DSI_20nm_PHY_LNCK_TEST_STR0, 0x01); dsi_20nm_phy_enable()
110 dsi_phy_write(base + REG_DSI_20nm_PHY_LNCK_TEST_STR1, 0x46); dsi_20nm_phy_enable()
111 dsi_phy_write(base + REG_DSI_20nm_PHY_LNCK_CFG_0, 0x00); dsi_20nm_phy_enable()
112 dsi_phy_write(base + REG_DSI_20nm_PHY_LNCK_CFG_1, 0xa0); dsi_20nm_phy_enable()
113 dsi_phy_write(base + REG_DSI_20nm_PHY_LNCK_CFG_2, 0x00); dsi_20nm_phy_enable()
114 dsi_phy_write(base + REG_DSI_20nm_PHY_LNCK_CFG_4, 0x00); dsi_20nm_phy_enable()
118 dsi_phy_write(base + REG_DSI_20nm_PHY_CTRL_1, 0x00); dsi_20nm_phy_enable()
120 dsi_phy_write(base + REG_DSI_20nm_PHY_STRENGTH_1, 0x06); dsi_20nm_phy_enable()
124 dsi_phy_write(base + REG_DSI_20nm_PHY_CTRL_0, 0x7f); dsi_20nm_phy_enable()
131 dsi_phy_write(phy->base + REG_DSI_20nm_PHY_CTRL_0, 0); dsi_20nm_phy_disable()
|
| /linux-4.4.14/drivers/scsi/ |
| H A D | nsp32_io.h | 12 static inline void nsp32_write1(unsigned int base, nsp32_write1() argument
16 outb(val, (base + index)); nsp32_write1()
19 static inline unsigned char nsp32_read1(unsigned int base, nsp32_read1() argument
22 return inb(base + index); nsp32_read1()
25 static inline void nsp32_write2(unsigned int base, nsp32_write2() argument
29 outw(val, (base + index)); nsp32_write2()
32 static inline unsigned short nsp32_read2(unsigned int base, nsp32_read2() argument
35 return inw(base + index); nsp32_read2()
38 static inline void nsp32_write4(unsigned int base, nsp32_write4() argument
42 outl(val, (base + index)); nsp32_write4()
45 static inline unsigned long nsp32_read4(unsigned int base, nsp32_read4() argument
48 return inl(base + index); nsp32_read4()
53 static inline void nsp32_mmio_write1(unsigned long base, nsp32_mmio_write1() argument
59 ptr = (unsigned char *)(base + NSP32_MMIO_OFFSET + index); nsp32_mmio_write1()
64 static inline unsigned char nsp32_mmio_read1(unsigned long base, nsp32_mmio_read1() argument
69 ptr = (unsigned char *)(base + NSP32_MMIO_OFFSET + index); nsp32_mmio_read1()
74 static inline void nsp32_mmio_write2(unsigned long base, nsp32_mmio_write2() argument
80 ptr = (unsigned short *)(base + NSP32_MMIO_OFFSET + index); nsp32_mmio_write2()
85 static inline unsigned short nsp32_mmio_read2(unsigned long base, nsp32_mmio_read2() argument
90 ptr = (unsigned short *)(base + NSP32_MMIO_OFFSET + index); nsp32_mmio_read2()
95 static inline void nsp32_mmio_write4(unsigned long base, nsp32_mmio_write4() argument
101 ptr = (unsigned long *)(base + NSP32_MMIO_OFFSET + index); nsp32_mmio_write4()
106 static inline unsigned long nsp32_mmio_read4(unsigned long base, nsp32_mmio_read4() argument
111 ptr = (unsigned long *)(base + NSP32_MMIO_OFFSET + index); nsp32_mmio_read4()
118 static inline unsigned char nsp32_index_read1(unsigned int base, nsp32_index_read1() argument
121 outb(reg, base + INDEX_REG); nsp32_index_read1()
122 return inb(base + DATA_REG_LOW); nsp32_index_read1()
125 static inline void nsp32_index_write1(unsigned int base, nsp32_index_write1() argument
129 outb(reg, base + INDEX_REG ); nsp32_index_write1()
130 outb(val, base + DATA_REG_LOW); nsp32_index_write1()
133 static inline unsigned short nsp32_index_read2(unsigned int base, nsp32_index_read2() argument
136 outb(reg, base + INDEX_REG); nsp32_index_read2()
137 return inw(base + DATA_REG_LOW); nsp32_index_read2()
140 static inline void nsp32_index_write2(unsigned int base, nsp32_index_write2() argument
144 outb(reg, base + INDEX_REG ); nsp32_index_write2()
145 outw(val, base + DATA_REG_LOW); nsp32_index_write2()
148 static inline unsigned long nsp32_index_read4(unsigned int base, nsp32_index_read4() argument
153 outb(reg, base + INDEX_REG); nsp32_index_read4()
154 l = inw(base + DATA_REG_LOW); nsp32_index_read4()
155 h = inw(base + DATA_REG_HI ); nsp32_index_read4()
160 static inline void nsp32_index_write4(unsigned int base, nsp32_index_write4() argument
169 outb(reg, base + INDEX_REG ); nsp32_index_write4()
170 outw(l, base + DATA_REG_LOW); nsp32_index_write4()
171 outw(h, base + DATA_REG_HI ); nsp32_index_write4()
176 static inline unsigned char nsp32_mmio_index_read1(unsigned long base, nsp32_mmio_index_read1() argument
181 index_ptr = (unsigned short *)(base + NSP32_MMIO_OFFSET + INDEX_REG); nsp32_mmio_index_read1()
182 data_ptr = (unsigned short *)(base + NSP32_MMIO_OFFSET + DATA_REG_LOW); nsp32_mmio_index_read1()
188 static inline void nsp32_mmio_index_write1(unsigned long base, nsp32_mmio_index_write1() argument
194 index_ptr = (unsigned short *)(base + NSP32_MMIO_OFFSET + INDEX_REG); nsp32_mmio_index_write1()
195 data_ptr = (unsigned short *)(base + NSP32_MMIO_OFFSET + DATA_REG_LOW); nsp32_mmio_index_write1()
201 static inline unsigned short nsp32_mmio_index_read2(unsigned long base, nsp32_mmio_index_read2() argument
206 index_ptr = (unsigned short *)(base + NSP32_MMIO_OFFSET + INDEX_REG); nsp32_mmio_index_read2()
207 data_ptr = (unsigned short *)(base + NSP32_MMIO_OFFSET + DATA_REG_LOW); nsp32_mmio_index_read2()
213 static inline void nsp32_mmio_index_write2(unsigned long base, nsp32_mmio_index_write2() argument
219 index_ptr = (unsigned short *)(base + NSP32_MMIO_OFFSET + INDEX_REG); nsp32_mmio_index_write2()
220 data_ptr = (unsigned short *)(base + NSP32_MMIO_OFFSET + DATA_REG_LOW); nsp32_mmio_index_write2()
228 static inline void nsp32_multi_read4(unsigned int base, nsp32_multi_read4() argument
233 insl(base + reg, buf, count); nsp32_multi_read4()
236 static inline void nsp32_fifo_read(unsigned int base, nsp32_fifo_read() argument
240 nsp32_multi_read4(base, FIFO_DATA_LOW, buf, count); nsp32_fifo_read()
243 static inline void nsp32_multi_write4(unsigned int base, nsp32_multi_write4() argument
248 outsl(base + reg, buf, count); nsp32_multi_write4()
251 static inline void nsp32_fifo_write(unsigned int base, nsp32_fifo_write() argument
255 nsp32_multi_write4(base, FIFO_DATA_LOW, buf, count); nsp32_fifo_write()
|
| H A D | aha1740.h | 18 #define HID0(base) (base + 0x0)
19 #define HID1(base) (base + 0x1)
20 #define HID2(base) (base + 0x2)
21 #define HID3(base) (base + 0x3)
22 #define EBCNTRL(base) (base + 0x4)
23 #define PORTADR(base) (base + 0x40)
24 #define BIOSADR(base) (base + 0x41)
25 #define INTDEF(base) (base + 0x42)
26 #define SCSIDEF(base) (base + 0x43)
27 #define BUSDEF(base) (base + 0x44)
28 #define RESV0(base) (base + 0x45)
29 #define RESV1(base) (base + 0x46)
30 #define RESV2(base) (base + 0x47)
38 #define G2INTST(base) (base + 0x56)
39 #define G2STAT(base) (base + 0x57)
40 #define MBOXIN0(base) (base + 0x58)
41 #define MBOXIN1(base) (base + 0x59)
42 #define MBOXIN2(base) (base + 0x5a)
43 #define MBOXIN3(base) (base + 0x5b)
44 #define G2STAT2(base) (base + 0x5c)
62 #define MBOXOUT0(base) (base + 0x50)
63 #define MBOXOUT1(base) (base + 0x51)
64 #define MBOXOUT2(base) (base + 0x52)
65 #define MBOXOUT3(base) (base + 0x53)
66 #define ATTN(base) (base + 0x54)
67 #define G2CNTRL(base) (base + 0x55)
|
| H A D | sym53c416.c | 213 int base; member in struct:__anon10168
232 static void sym53c416_set_transfer_counter(int base, unsigned int len) sym53c416_set_transfer_counter() argument
235 outb(len & 0x0000FF, base + TC_LOW); sym53c416_set_transfer_counter()
236 outb((len & 0x00FF00) >> 8, base + TC_MID); sym53c416_set_transfer_counter()
237 outb((len & 0xFF0000) >> 16, base + TC_HIGH); sym53c416_set_transfer_counter()
243 static __inline__ unsigned int sym53c416_read(int base, unsigned char *buffer, unsigned int len) sym53c416_read() argument
255 bytes_left = inb(base + PIO_FIFO_CNT); /* Number of bytes in the PIO FIFO */ sym53c416_read()
258 insl(base + PIO_FIFO_1, buffer, bytes_left >> 2); sym53c416_read()
266 *(buffer++) = inb(base + PIO_FIFO_1); sym53c416_read()
272 while(time_before(jiffies, i) && (inb(base + PIO_INT_REG) & EMPTY) && timeout) sym53c416_read()
273 if(inb(base + PIO_INT_REG) & SCI) sym53c416_read()
276 if(inb(base + PIO_INT_REG) & EMPTY) sym53c416_read()
285 static __inline__ unsigned int sym53c416_write(int base, unsigned char *buffer, unsigned int len) sym53c416_write() argument
297 bufferfree = PIO_SIZE - inb(base + PIO_FIFO_CNT); sym53c416_write()
302 outsl(base + PIO_FIFO_1, buffer, bufferfree >> 2); sym53c416_write()
310 outb(*(buffer++), base + PIO_FIFO_1); sym53c416_write()
316 while(time_before(jiffies, i) && (inb(base + PIO_INT_REG) & FULL) && timeout) sym53c416_write()
319 if(inb(base + PIO_INT_REG) & FULL) sym53c416_write()
330 int base = dev->io_port; sym53c416_intr_handle() local
338 status_reg = inb(base + STATUS_REG); sym53c416_intr_handle()
339 pio_int_reg = inb(base + PIO_INT_REG); sym53c416_intr_handle()
340 int_reg = inb(base + INT_REG); sym53c416_intr_handle()
356 printk(KERN_WARNING "sym53c416: Illegal Command: 0x%02x.\n", inb(base + COMMAND_REG)); sym53c416_intr_handle()
415 outb(FLUSH_FIFO, base + COMMAND_REG); sym53c416_intr_handle()
416 sym53c416_set_transfer_counter(base, sym53c416_intr_handle()
418 outb(TRANSFER_INFORMATION | PIO_MODE, base + COMMAND_REG); sym53c416_intr_handle()
422 tot_trans += sym53c416_write(base, scsi_for_each_sg()
437 outb(FLUSH_FIFO, base + COMMAND_REG);
438 sym53c416_set_transfer_counter(base,
441 outb(TRANSFER_INFORMATION | PIO_MODE, base + COMMAND_REG);
445 tot_trans += sym53c416_read(base, scsi_for_each_sg()
465 outb(FLUSH_FIFO, base + COMMAND_REG);
466 outb(INIT_COMM_COMPLETE_SEQ, base + COMMAND_REG);
480 outb(SET_ATN, base + COMMAND_REG);
481 outb(MSG_ACCEPTED, base + COMMAND_REG);
488 current_command->SCp.Status = inb(base + SCSI_FIFO);
489 current_command->SCp.Message = inb(base + SCSI_FIFO);
491 outb(SET_ATN, base + COMMAND_REG);
492 outb(MSG_ACCEPTED, base + COMMAND_REG);
500 static void sym53c416_init(int base, int scsi_id) sym53c416_init() argument
502 outb(RESET_CHIP, base + COMMAND_REG); sym53c416_init()
503 outb(NOOP, base + COMMAND_REG); sym53c416_init()
504 outb(0x99, base + TOM); /* Time out of 250 ms */ sym53c416_init()
505 outb(0x05, base + STP); sym53c416_init()
506 outb(0x00, base + SYNC_OFFSET); sym53c416_init()
507 outb(EPC | scsi_id, base + CONF_REG_1); sym53c416_init()
508 outb(FE | SCSI2 | TBPA, base + CONF_REG_2); sym53c416_init()
509 outb(IDMRC | QTE | CDB10 | FSCSI | FCLK, base + CONF_REG_3); sym53c416_init()
510 outb(0x83 | EAN, base + CONF_REG_4); sym53c416_init()
511 outb(IE | WSE0, base + CONF_REG_5); sym53c416_init()
512 outb(0, base + FEATURE_EN); sym53c416_init()
515 static int sym53c416_probeirq(int base, int scsi_id) sym53c416_probeirq() argument
521 inb(base + INT_REG); sym53c416_probeirq()
525 sym53c416_init(base, scsi_id); sym53c416_probeirq()
527 outb(NOOP, base + COMMAND_REG); sym53c416_probeirq()
528 outb(ILLEGAL, base + COMMAND_REG); sym53c416_probeirq()
529 outb(0x07, base + DEST_BUS_ID); sym53c416_probeirq()
530 outb(0x00, base + DEST_BUS_ID); sym53c416_probeirq()
533 while(time_before(jiffies, i) && !(inb(base + STATUS_REG) & SCI)) sym53c416_probeirq()
539 sym53c416_init(base, scsi_id); sym53c416_probeirq()
543 /* Setup: sym53c416=base,irq */ sym53c416_setup()
556 printk(KERN_ERR "sym53c416: usage: sym53c416=<base>[,<irq>]\n"); sym53c416_setup()
560 if(hosts[i].base == ints[1]) sym53c416_setup()
564 hosts[host_index].base = ints[1]; sym53c416_setup()
570 static int sym53c416_test(int base) sym53c416_test() argument
572 outb(RESET_CHIP, base + COMMAND_REG); sym53c416_test()
573 outb(NOOP, base + COMMAND_REG); sym53c416_test()
574 if(inb(base + COMMAND_REG) != NOOP) sym53c416_test()
576 if(!inb(base + TC_HIGH) || inb(base + TC_HIGH) == 0xFF) sym53c416_test()
578 if((inb(base + PIO_INT_REG) & (FULL | EMPTY | CE | OUE | FIE | EIE)) != EMPTY) sym53c416_test()
596 int *base = probeaddrs; sym53c416_probe() local
600 for(; *base; base++) { sym53c416_probe()
601 if (request_region(*base, IO_RANGE, ID)) { sym53c416_probe()
602 if (sym53c416_test(*base)) { sym53c416_probe()
603 ints[1] = *base; sym53c416_probe()
606 release_region(*base, IO_RANGE); sym53c416_probe()
682 if (!request_region(hosts[i].base, IO_RANGE, ID)) sym53c416_detect()
684 if (!sym53c416_test(hosts[i].base)) { sym53c416_detect()
685 printk(KERN_WARNING "No sym53c416 found at address 0x%03x\n", hosts[i].base); sym53c416_detect()
691 hosts[i].irq = sym53c416_probeirq(hosts[i].base, hosts[i].scsi_id); sym53c416_detect()
703 shpnt->unique_id = hosts[i].base; sym53c416_detect()
704 shpnt->io_port = hosts[i].base; sym53c416_detect()
708 sym53c416_init(hosts[i].base, hosts[i].scsi_id); sym53c416_detect()
716 release_region(hosts[i].base, IO_RANGE); sym53c416_detect()
724 int base = SChost->io_port; sym53c416_info() local
727 int rev = inb(base + TC_HIGH); sym53c416_info()
730 if(hosts[i].base == base) sym53c416_info()
732 sprintf(info, "Symbios Logic 53c416 (rev. %d) at 0x%03x, irq %d, SCSI-ID %d, %s pio", rev, base, irq, scsi_id, (fastpio)? "fast" : "slow"); sym53c416_info()
738 int base; sym53c416_queuecommand_lck() local
742 /* Store base register as we can have more than one controller in the system */ sym53c416_queuecommand_lck()
743 base = SCpnt->device->host->io_port; sym53c416_queuecommand_lck()
751 outb(scmd_id(SCpnt), base + DEST_BUS_ID); /* Set scsi id target */ sym53c416_queuecommand_lck()
752 outb(FLUSH_FIFO, base + COMMAND_REG); /* Flush SCSI and PIO FIFO's */ sym53c416_queuecommand_lck()
755 outb(SCpnt->cmnd[i], base + SCSI_FIFO); sym53c416_queuecommand_lck()
757 outb(SEL_WITHOUT_ATN_SEQ, base + COMMAND_REG); sym53c416_queuecommand_lck()
767 int base; sym53c416_host_reset() local
775 base = SCpnt->device->host->io_port; sym53c416_host_reset()
778 if(hosts[i].base == base) sym53c416_host_reset()
780 outb(RESET_CHIP, base + COMMAND_REG); sym53c416_host_reset()
781 outb(NOOP | PIO_MODE, base + COMMAND_REG); sym53c416_host_reset()
782 outb(RESET_SCSI_BUS, base + COMMAND_REG); sym53c416_host_reset()
783 sym53c416_init(base, scsi_id); sym53c416_host_reset()
|
| /linux-4.4.14/drivers/media/platform/s5p-jpeg/ |
| H A D | jpeg-hw-exynos4.h | 16 void exynos4_jpeg_sw_reset(void __iomem *base);
17 void exynos4_jpeg_set_enc_dec_mode(void __iomem *base, unsigned int mode);
18 void __exynos4_jpeg_set_img_fmt(void __iomem *base, unsigned int img_fmt,
20 void __exynos4_jpeg_set_enc_out_fmt(void __iomem *base, unsigned int out_fmt,
22 void exynos4_jpeg_set_enc_tbl(void __iomem *base);
23 void exynos4_jpeg_set_interrupt(void __iomem *base, unsigned int version);
24 unsigned int exynos4_jpeg_get_int_status(void __iomem *base);
25 void exynos4_jpeg_set_huf_table_enable(void __iomem *base, int value);
26 void exynos4_jpeg_set_sys_int_enable(void __iomem *base, int value);
27 void exynos4_jpeg_set_stream_buf_address(void __iomem *base,
29 void exynos4_jpeg_set_stream_size(void __iomem *base,
31 void exynos4_jpeg_set_frame_buf_address(void __iomem *base,
33 void exynos4_jpeg_set_encode_tbl_select(void __iomem *base,
35 void exynos4_jpeg_set_dec_components(void __iomem *base, int n);
36 void exynos4_jpeg_select_dec_q_tbl(void __iomem *base, char c, char x);
37 void exynos4_jpeg_select_dec_h_tbl(void __iomem *base, char c, char x);
38 void exynos4_jpeg_set_encode_hoff_cnt(void __iomem *base, unsigned int fmt);
39 void exynos4_jpeg_set_dec_bitstream_size(void __iomem *base, unsigned int size);
40 unsigned int exynos4_jpeg_get_stream_size(void __iomem *base);
41 void exynos4_jpeg_get_frame_size(void __iomem *base,
43 unsigned int exynos4_jpeg_get_frame_fmt(void __iomem *base);
44 unsigned int exynos4_jpeg_get_fifo_status(void __iomem *base);
45 void exynos4_jpeg_set_timer_count(void __iomem *base, unsigned int size);
|
| H A D | jpeg-hw-exynos4.c | 19 void exynos4_jpeg_sw_reset(void __iomem *base) exynos4_jpeg_sw_reset() argument
23 reg = readl(base + EXYNOS4_JPEG_CNTL_REG); exynos4_jpeg_sw_reset()
24 writel(reg & ~EXYNOS4_SOFT_RESET_HI, base + EXYNOS4_JPEG_CNTL_REG); exynos4_jpeg_sw_reset()
28 writel(reg | EXYNOS4_SOFT_RESET_HI, base + EXYNOS4_JPEG_CNTL_REG); exynos4_jpeg_sw_reset()
31 void exynos4_jpeg_set_enc_dec_mode(void __iomem *base, unsigned int mode) exynos4_jpeg_set_enc_dec_mode() argument
35 reg = readl(base + EXYNOS4_JPEG_CNTL_REG); exynos4_jpeg_set_enc_dec_mode()
40 base + EXYNOS4_JPEG_CNTL_REG); exynos4_jpeg_set_enc_dec_mode()
44 base + EXYNOS4_JPEG_CNTL_REG); exynos4_jpeg_set_enc_dec_mode()
48 void __exynos4_jpeg_set_img_fmt(void __iomem *base, unsigned int img_fmt, __exynos4_jpeg_set_img_fmt() argument
63 reg = readl(base + EXYNOS4_IMG_FMT_REG) & __exynos4_jpeg_set_img_fmt()
129 writel(reg, base + EXYNOS4_IMG_FMT_REG); __exynos4_jpeg_set_img_fmt()
132 void __exynos4_jpeg_set_enc_out_fmt(void __iomem *base, unsigned int out_fmt, __exynos4_jpeg_set_enc_out_fmt() argument
137 reg = readl(base + EXYNOS4_IMG_FMT_REG) & __exynos4_jpeg_set_enc_out_fmt()
162 writel(reg, base + EXYNOS4_IMG_FMT_REG); __exynos4_jpeg_set_enc_out_fmt()
165 void exynos4_jpeg_set_interrupt(void __iomem *base, unsigned int version) exynos4_jpeg_set_interrupt() argument
170 reg = readl(base + EXYNOS4_INT_EN_REG) & ~EXYNOS4_INT_EN_MASK; exynos4_jpeg_set_interrupt()
171 writel(reg | EXYNOS4_INT_EN_ALL, base + EXYNOS4_INT_EN_REG); exynos4_jpeg_set_interrupt()
173 reg = readl(base + EXYNOS4_INT_EN_REG) & exynos4_jpeg_set_interrupt()
175 writel(reg | EXYNOS5433_INT_EN_ALL, base + EXYNOS4_INT_EN_REG); exynos4_jpeg_set_interrupt()
179 unsigned int exynos4_jpeg_get_int_status(void __iomem *base) exynos4_jpeg_get_int_status() argument
183 int_status = readl(base + EXYNOS4_INT_STATUS_REG); exynos4_jpeg_get_int_status()
188 unsigned int exynos4_jpeg_get_fifo_status(void __iomem *base) exynos4_jpeg_get_fifo_status() argument
192 fifo_status = readl(base + EXYNOS4_FIFO_STATUS_REG); exynos4_jpeg_get_fifo_status()
197 void exynos4_jpeg_set_huf_table_enable(void __iomem *base, int value) exynos4_jpeg_set_huf_table_enable() argument
201 reg = readl(base + EXYNOS4_JPEG_CNTL_REG) & ~EXYNOS4_HUF_TBL_EN; exynos4_jpeg_set_huf_table_enable()
205 base + EXYNOS4_JPEG_CNTL_REG); exynos4_jpeg_set_huf_table_enable()
208 base + EXYNOS4_JPEG_CNTL_REG); exynos4_jpeg_set_huf_table_enable()
211 void exynos4_jpeg_set_sys_int_enable(void __iomem *base, int value) exynos4_jpeg_set_sys_int_enable() argument
215 reg = readl(base + EXYNOS4_JPEG_CNTL_REG) & ~(EXYNOS4_SYS_INT_EN); exynos4_jpeg_set_sys_int_enable()
218 writel(reg | EXYNOS4_SYS_INT_EN, base + EXYNOS4_JPEG_CNTL_REG); exynos4_jpeg_set_sys_int_enable()
220 writel(reg & ~EXYNOS4_SYS_INT_EN, base + EXYNOS4_JPEG_CNTL_REG); exynos4_jpeg_set_sys_int_enable()
223 void exynos4_jpeg_set_stream_buf_address(void __iomem *base, exynos4_jpeg_set_stream_buf_address() argument
226 writel(address, base + EXYNOS4_OUT_MEM_BASE_REG); exynos4_jpeg_set_stream_buf_address()
229 void exynos4_jpeg_set_stream_size(void __iomem *base, exynos4_jpeg_set_stream_size() argument
232 writel(0x0, base + EXYNOS4_JPEG_IMG_SIZE_REG); /* clear */ exynos4_jpeg_set_stream_size()
234 base + EXYNOS4_JPEG_IMG_SIZE_REG); exynos4_jpeg_set_stream_size()
237 void exynos4_jpeg_set_frame_buf_address(void __iomem *base, exynos4_jpeg_set_frame_buf_address() argument
240 writel(exynos4_jpeg_addr->y, base + EXYNOS4_IMG_BA_PLANE_1_REG); exynos4_jpeg_set_frame_buf_address()
241 writel(exynos4_jpeg_addr->cb, base + EXYNOS4_IMG_BA_PLANE_2_REG); exynos4_jpeg_set_frame_buf_address()
242 writel(exynos4_jpeg_addr->cr, base + EXYNOS4_IMG_BA_PLANE_3_REG); exynos4_jpeg_set_frame_buf_address()
245 void exynos4_jpeg_set_encode_tbl_select(void __iomem *base, exynos4_jpeg_set_encode_tbl_select() argument
256 writel(reg, base + EXYNOS4_TBL_SEL_REG); exynos4_jpeg_set_encode_tbl_select()
259 void exynos4_jpeg_set_dec_components(void __iomem *base, int n) exynos4_jpeg_set_dec_components() argument
263 reg = readl(base + EXYNOS4_TBL_SEL_REG); exynos4_jpeg_set_dec_components()
266 writel(reg, base + EXYNOS4_TBL_SEL_REG); exynos4_jpeg_set_dec_components()
269 void exynos4_jpeg_select_dec_q_tbl(void __iomem *base, char c, char x) exynos4_jpeg_select_dec_q_tbl() argument
273 reg = readl(base + EXYNOS4_TBL_SEL_REG); exynos4_jpeg_select_dec_q_tbl()
276 writel(reg, base + EXYNOS4_TBL_SEL_REG); exynos4_jpeg_select_dec_q_tbl()
279 void exynos4_jpeg_select_dec_h_tbl(void __iomem *base, char c, char x) exynos4_jpeg_select_dec_h_tbl() argument
283 reg = readl(base + EXYNOS4_TBL_SEL_REG); exynos4_jpeg_select_dec_h_tbl()
286 writel(reg, base + EXYNOS4_TBL_SEL_REG); exynos4_jpeg_select_dec_h_tbl()
289 void exynos4_jpeg_set_encode_hoff_cnt(void __iomem *base, unsigned int fmt) exynos4_jpeg_set_encode_hoff_cnt() argument
292 writel(0xd2, base + EXYNOS4_HUFF_CNT_REG); exynos4_jpeg_set_encode_hoff_cnt()
294 writel(0x1a2, base + EXYNOS4_HUFF_CNT_REG); exynos4_jpeg_set_encode_hoff_cnt()
297 unsigned int exynos4_jpeg_get_stream_size(void __iomem *base) exynos4_jpeg_get_stream_size() argument
301 size = readl(base + EXYNOS4_BITSTREAM_SIZE_REG); exynos4_jpeg_get_stream_size()
305 void exynos4_jpeg_set_dec_bitstream_size(void __iomem *base, unsigned int size) exynos4_jpeg_set_dec_bitstream_size() argument
307 writel(size, base + EXYNOS4_BITSTREAM_SIZE_REG); exynos4_jpeg_set_dec_bitstream_size()
310 void exynos4_jpeg_get_frame_size(void __iomem *base, exynos4_jpeg_get_frame_size() argument
313 *width = (readl(base + EXYNOS4_DECODE_XY_SIZE_REG) & exynos4_jpeg_get_frame_size()
315 *height = (readl(base + EXYNOS4_DECODE_XY_SIZE_REG) >> 16) & exynos4_jpeg_get_frame_size()
319 unsigned int exynos4_jpeg_get_frame_fmt(void __iomem *base) exynos4_jpeg_get_frame_fmt() argument
321 return readl(base + EXYNOS4_DECODE_IMG_FMT_REG) & exynos4_jpeg_get_frame_fmt()
325 void exynos4_jpeg_set_timer_count(void __iomem *base, unsigned int size) exynos4_jpeg_set_timer_count() argument
327 writel(size, base + EXYNOS4_INT_TIMER_COUNT_REG); exynos4_jpeg_set_timer_count()
|
| /linux-4.4.14/drivers/clk/imx/ |
| H A D | clk-imx6ul.c | 109 void __iomem *base; imx6ul_clocks_init() local
122 base = of_iomap(np, 0); imx6ul_clocks_init()
123 WARN_ON(!base); imx6ul_clocks_init()
125 clks[IMX6UL_PLL1_BYPASS_SRC] = imx_clk_mux("pll1_bypass_src", base + 0x00, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); imx6ul_clocks_init()
126 clks[IMX6UL_PLL2_BYPASS_SRC] = imx_clk_mux("pll2_bypass_src", base + 0x30, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); imx6ul_clocks_init()
127 clks[IMX6UL_PLL3_BYPASS_SRC] = imx_clk_mux("pll3_bypass_src", base + 0x10, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); imx6ul_clocks_init()
128 clks[IMX6UL_PLL4_BYPASS_SRC] = imx_clk_mux("pll4_bypass_src", base + 0x70, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); imx6ul_clocks_init()
129 clks[IMX6UL_PLL5_BYPASS_SRC] = imx_clk_mux("pll5_bypass_src", base + 0xa0, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); imx6ul_clocks_init()
130 clks[IMX6UL_PLL6_BYPASS_SRC] = imx_clk_mux("pll6_bypass_src", base + 0xe0, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); imx6ul_clocks_init()
131 clks[IMX6UL_PLL7_BYPASS_SRC] = imx_clk_mux("pll7_bypass_src", base + 0x20, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); imx6ul_clocks_init()
133 clks[IMX6UL_CLK_PLL1] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1", "pll1_bypass_src", base + 0x00, 0x7f); imx6ul_clocks_init()
134 clks[IMX6UL_CLK_PLL2] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2", "pll2_bypass_src", base + 0x30, 0x1); imx6ul_clocks_init()
135 clks[IMX6UL_CLK_PLL3] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3", "pll3_bypass_src", base + 0x10, 0x3); imx6ul_clocks_init()
136 clks[IMX6UL_CLK_PLL4] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4", "pll4_bypass_src", base + 0x70, 0x7f); imx6ul_clocks_init()
137 clks[IMX6UL_CLK_PLL5] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5", "pll5_bypass_src", base + 0xa0, 0x7f); imx6ul_clocks_init()
138 clks[IMX6UL_CLK_PLL6] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6", "pll6_bypass_src", base + 0xe0, 0x3); imx6ul_clocks_init()
139 clks[IMX6UL_CLK_PLL7] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7", "pll7_bypass_src", base + 0x20, 0x3); imx6ul_clocks_init()
141 clks[IMX6UL_PLL1_BYPASS] = imx_clk_mux_flags("pll1_bypass", base + 0x00, 16, 1, pll1_bypass_sels, ARRAY_SIZE(pll1_bypass_sels), CLK_SET_RATE_PARENT); imx6ul_clocks_init()
142 clks[IMX6UL_PLL2_BYPASS] = imx_clk_mux_flags("pll2_bypass", base + 0x30, 16, 1, pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), CLK_SET_RATE_PARENT); imx6ul_clocks_init()
143 clks[IMX6UL_PLL3_BYPASS] = imx_clk_mux_flags("pll3_bypass", base + 0x10, 16, 1, pll3_bypass_sels, ARRAY_SIZE(pll3_bypass_sels), CLK_SET_RATE_PARENT); imx6ul_clocks_init()
144 clks[IMX6UL_PLL4_BYPASS] = imx_clk_mux_flags("pll4_bypass", base + 0x70, 16, 1, pll4_bypass_sels, ARRAY_SIZE(pll4_bypass_sels), CLK_SET_RATE_PARENT); imx6ul_clocks_init()
145 clks[IMX6UL_PLL5_BYPASS] = imx_clk_mux_flags("pll5_bypass", base + 0xa0, 16, 1, pll5_bypass_sels, ARRAY_SIZE(pll5_bypass_sels), CLK_SET_RATE_PARENT); imx6ul_clocks_init()
146 clks[IMX6UL_PLL6_BYPASS] = imx_clk_mux_flags("pll6_bypass", base + 0xe0, 16, 1, pll6_bypass_sels, ARRAY_SIZE(pll6_bypass_sels), CLK_SET_RATE_PARENT); imx6ul_clocks_init()
147 clks[IMX6UL_PLL7_BYPASS] = imx_clk_mux_flags("pll7_bypass", base + 0x20, 16, 1, pll7_bypass_sels, ARRAY_SIZE(pll7_bypass_sels), CLK_SET_RATE_PARENT); imx6ul_clocks_init()
148 clks[IMX6UL_CLK_CSI_SEL] = imx_clk_mux_flags("csi_sel", base + 0x3c, 9, 2, csi_sels, ARRAY_SIZE(csi_sels), CLK_SET_RATE_PARENT); imx6ul_clocks_init()
160 clks[IMX6UL_CLK_PLL2_BUS] = imx_clk_gate("pll2_bus", "pll2_bypass", base + 0x30, 13); imx6ul_clocks_init()
161 clks[IMX6UL_CLK_PLL3_USB_OTG] = imx_clk_gate("pll3_usb_otg", "pll3_bypass", base + 0x10, 13); imx6ul_clocks_init()
162 clks[IMX6UL_CLK_PLL4_AUDIO] = imx_clk_gate("pll4_audio", "pll4_bypass", base + 0x70, 13); imx6ul_clocks_init()
163 clks[IMX6UL_CLK_PLL5_VIDEO] = imx_clk_gate("pll5_video", "pll5_bypass", base + 0xa0, 13); imx6ul_clocks_init()
164 clks[IMX6UL_CLK_PLL6_ENET] = imx_clk_gate("pll6_enet", "pll6_bypass", base + 0xe0, 13); imx6ul_clocks_init()
165 clks[IMX6UL_CLK_PLL7_USB_HOST] = imx_clk_gate("pll7_usb_host", "pll7_bypass", base + 0x20, 13); imx6ul_clocks_init()
173 clks[IMX6UL_CLK_USBPHY1] = imx_clk_gate("usbphy1", "pll3_usb_otg", base + 0x10, 20); imx6ul_clocks_init()
174 clks[IMX6UL_CLK_USBPHY2] = imx_clk_gate("usbphy2", "pll7_usb_host", base + 0x20, 20); imx6ul_clocks_init()
180 clks[IMX6UL_CLK_USBPHY1_GATE] = imx_clk_gate("usbphy1_gate", "dummy", base + 0x10, 6); imx6ul_clocks_init()
181 clks[IMX6UL_CLK_USBPHY2_GATE] = imx_clk_gate("usbphy2_gate", "dummy", base + 0x20, 6); imx6ul_clocks_init()
184 clks[IMX6UL_CLK_PLL2_PFD0] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0); imx6ul_clocks_init()
185 clks[IMX6UL_CLK_PLL2_PFD1] = imx_clk_pfd("pll2_pfd1_594m", "pll2_bus", base + 0x100, 1); imx6ul_clocks_init()
186 clks[IMX6UL_CLK_PLL2_PFD2] = imx_clk_pfd("pll2_pfd2_396m", "pll2_bus", base + 0x100, 2); imx6ul_clocks_init()
187 clks[IMX6UL_CLK_PLL2_PFD3] = imx_clk_pfd("pll2_pfd3_594m", "pll2_bus", base + 0x100, 3); imx6ul_clocks_init()
188 clks[IMX6UL_CLK_PLL3_PFD0] = imx_clk_pfd("pll3_pfd0_720m", "pll3_usb_otg", base + 0xf0, 0); imx6ul_clocks_init()
189 clks[IMX6UL_CLK_PLL3_PFD1] = imx_clk_pfd("pll3_pfd1_540m", "pll3_usb_otg", base + 0xf0, 1); imx6ul_clocks_init()
190 clks[IMX6UL_CLK_PLL3_PFD2] = imx_clk_pfd("pll3_pfd2_508m", "pll3_usb_otg", base + 0xf0, 2); imx6ul_clocks_init()
191 clks[IMX6UL_CLK_PLL3_PFD3] = imx_clk_pfd("pll3_pfd3_454m", "pll3_usb_otg", base + 0xf0, 3); imx6ul_clocks_init()
194 base + 0xe0, 0, 2, 0, clk_enet_ref_table, &imx_ccm_lock); imx6ul_clocks_init()
196 base + 0xe0, 2, 2, 0, clk_enet_ref_table, &imx_ccm_lock); imx6ul_clocks_init()
198 clks[IMX6UL_CLK_ENET2_REF_125M] = imx_clk_gate("enet_ref_125m", "enet2_ref", base + 0xe0, 20); imx6ul_clocks_init()
200 clks[IMX6UL_CLK_ENET_PTP] = imx_clk_gate("enet_ptp", "enet_ptp_ref", base + 0xe0, 21); imx6ul_clocks_init()
203 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock); imx6ul_clocks_init()
205 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x170, 15, 1, 0, &imx_ccm_lock); imx6ul_clocks_init()
207 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock); imx6ul_clocks_init()
209 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock); imx6ul_clocks_init()
218 base = of_iomap(np, 0); imx6ul_clocks_init()
219 WARN_ON(!base); imx6ul_clocks_init()
221 clks[IMX6UL_CA7_SECONDARY_SEL] = imx_clk_mux("ca7_secondary_sel", base + 0xc, 3, 1, ca7_secondary_sels, ARRAY_SIZE(ca7_secondary_sels)); imx6ul_clocks_init()
222 clks[IMX6UL_CLK_STEP] = imx_clk_mux("step", base + 0x0c, 8, 1, step_sels, ARRAY_SIZE(step_sels)); imx6ul_clocks_init()
223 clks[IMX6UL_CLK_PLL1_SW] = imx_clk_mux_flags("pll1_sw", base + 0x0c, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels), 0); imx6ul_clocks_init()
224 clks[IMX6UL_CLK_AXI_ALT_SEL] = imx_clk_mux("axi_alt_sel", base + 0x14, 7, 1, axi_alt_sels, ARRAY_SIZE(axi_alt_sels)); imx6ul_clocks_init()
225 clks[IMX6UL_CLK_AXI_SEL] = imx_clk_mux_flags("axi_sel", base + 0x14, 6, 1, axi_sels, ARRAY_SIZE(axi_sels), 0); imx6ul_clocks_init()
226 clks[IMX6UL_CLK_PERIPH_PRE] = imx_clk_mux("periph_pre", base + 0x18, 18, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels)); imx6ul_clocks_init()
227 clks[IMX6UL_CLK_PERIPH2_PRE] = imx_clk_mux("periph2_pre", base + 0x18, 21, 2, periph2_pre_sels, ARRAY_SIZE(periph2_pre_sels)); imx6ul_clocks_init()
228 clks[IMX6UL_CLK_PERIPH_CLK2_SEL] = imx_clk_mux("periph_clk2_sel", base + 0x18, 12, 2, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels)); imx6ul_clocks_init()
229 clks[IMX6UL_CLK_PERIPH2_CLK2_SEL] = imx_clk_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels)); imx6ul_clocks_init()
230 clks[IMX6UL_CLK_EIM_SLOW_SEL] = imx_clk_mux("eim_slow_sel", base + 0x1c, 29, 2, eim_slow_sels, ARRAY_SIZE(eim_slow_sels)); imx6ul_clocks_init()
231 clks[IMX6UL_CLK_GPMI_SEL] = imx_clk_mux("gpmi_sel", base + 0x1c, 19, 1, gpmi_sels, ARRAY_SIZE(gpmi_sels)); imx6ul_clocks_init()
232 clks[IMX6UL_CLK_BCH_SEL] = imx_clk_mux("bch_sel", base + 0x1c, 18, 1, bch_sels, ARRAY_SIZE(bch_sels)); imx6ul_clocks_init()
233 clks[IMX6UL_CLK_USDHC2_SEL] = imx_clk_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); imx6ul_clocks_init()
234 clks[IMX6UL_CLK_USDHC1_SEL] = imx_clk_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); imx6ul_clocks_init()
235 clks[IMX6UL_CLK_SAI3_SEL] = imx_clk_mux("sai3_sel", base + 0x1c, 14, 2, sai_sels, ARRAY_SIZE(sai_sels)); imx6ul_clocks_init()
236 clks[IMX6UL_CLK_SAI2_SEL] = imx_clk_mux("sai2_sel", base + 0x1c, 12, 2, sai_sels, ARRAY_SIZE(sai_sels)); imx6ul_clocks_init()
237 clks[IMX6UL_CLK_SAI1_SEL] = imx_clk_mux("sai1_sel", base + 0x1c, 10, 2, sai_sels, ARRAY_SIZE(sai_sels)); imx6ul_clocks_init()
238 clks[IMX6UL_CLK_QSPI1_SEL] = imx_clk_mux("qspi1_sel", base + 0x1c, 7, 3, qspi1_sels, ARRAY_SIZE(qspi1_sels)); imx6ul_clocks_init()
239 clks[IMX6UL_CLK_PERCLK_SEL] = imx_clk_mux("perclk_sel", base + 0x1c, 6, 1, perclk_sels, ARRAY_SIZE(perclk_sels)); imx6ul_clocks_init()
240 clks[IMX6UL_CLK_CAN_SEL] = imx_clk_mux("can_sel", base + 0x20, 8, 2, can_sels, ARRAY_SIZE(can_sels)); imx6ul_clocks_init()
241 clks[IMX6UL_CLK_UART_SEL] = imx_clk_mux("uart_sel", base + 0x24, 6, 1, uart_sels, ARRAY_SIZE(uart_sels)); imx6ul_clocks_init()
242 clks[IMX6UL_CLK_ENFC_SEL] = imx_clk_mux("enfc_sel", base + 0x2c, 15, 3, enfc_sels, ARRAY_SIZE(enfc_sels)); imx6ul_clocks_init()
243 clks[IMX6UL_CLK_LDB_DI0_SEL] = imx_clk_mux("ldb_di0_sel", base + 0x2c, 9, 3, ldb_di0_sels, ARRAY_SIZE(ldb_di0_sels)); imx6ul_clocks_init()
244 clks[IMX6UL_CLK_SPDIF_SEL] = imx_clk_mux("spdif_sel", base + 0x30, 20, 2, spdif_sels, ARRAY_SIZE(spdif_sels)); imx6ul_clocks_init()
245 clks[IMX6UL_CLK_SIM_PRE_SEL] = imx_clk_mux("sim_pre_sel", base + 0x34, 15, 3, sim_pre_sels, ARRAY_SIZE(sim_pre_sels)); imx6ul_clocks_init()
246 clks[IMX6UL_CLK_SIM_SEL] = imx_clk_mux("sim_sel", base + 0x34, 9, 3, sim_sels, ARRAY_SIZE(sim_sels)); imx6ul_clocks_init()
247 clks[IMX6UL_CLK_ECSPI_SEL] = imx_clk_mux("ecspi_sel", base + 0x38, 18, 1, ecspi_sels, ARRAY_SIZE(ecspi_sels)); imx6ul_clocks_init()
248 clks[IMX6UL_CLK_LCDIF_PRE_SEL] = imx_clk_mux("lcdif_pre_sel", base + 0x38, 15, 3, lcdif_pre_sels, ARRAY_SIZE(lcdif_pre_sels)); imx6ul_clocks_init()
249 clks[IMX6UL_CLK_LCDIF_SEL] = imx_clk_mux("lcdif_sel", base + 0x38, 9, 3, lcdif_sels, ARRAY_SIZE(lcdif_sels)); imx6ul_clocks_init()
251 clks[IMX6UL_CLK_LDB_DI0_DIV_SEL] = imx_clk_mux("ldb_di0", base + 0x20, 10, 1, ldb_di0_div_sels, ARRAY_SIZE(ldb_di0_div_sels)); imx6ul_clocks_init()
252 clks[IMX6UL_CLK_LDB_DI1_DIV_SEL] = imx_clk_mux("ldb_di1", base + 0x20, 11, 1, ldb_di1_div_sels, ARRAY_SIZE(ldb_di1_div_sels)); imx6ul_clocks_init()
259 clks[IMX6UL_CLK_PERIPH] = imx_clk_busy_mux("periph", base + 0x14, 25, 1, base + 0x48, 5, periph_sels, ARRAY_SIZE(periph_sels)); imx6ul_clocks_init()
260 clks[IMX6UL_CLK_PERIPH2] = imx_clk_busy_mux("periph2", base + 0x14, 26, 1, base + 0x48, 3, periph2_sels, ARRAY_SIZE(periph2_sels)); imx6ul_clocks_init()
262 clks[IMX6UL_CLK_PERIPH_CLK2] = imx_clk_divider("periph_clk2", "periph_clk2_sel", base + 0x14, 27, 3); imx6ul_clocks_init()
263 clks[IMX6UL_CLK_PERIPH2_CLK2] = imx_clk_divider("periph2_clk2", "periph2_clk2_sel", base + 0x14, 0, 3); imx6ul_clocks_init()
264 clks[IMX6UL_CLK_IPG] = imx_clk_divider("ipg", "ahb", base + 0x14, 8, 2); imx6ul_clocks_init()
265 clks[IMX6UL_CLK_LCDIF_PODF] = imx_clk_divider("lcdif_podf", "lcdif_pred", base + 0x18, 23, 3); imx6ul_clocks_init()
266 clks[IMX6UL_CLK_QSPI1_PDOF] = imx_clk_divider("qspi1_podf", "qspi1_sel", base + 0x1c, 26, 3); imx6ul_clocks_init()
267 clks[IMX6UL_CLK_EIM_SLOW_PODF] = imx_clk_divider("eim_slow_podf", "eim_slow_sel", base + 0x1c, 23, 3); imx6ul_clocks_init()
268 clks[IMX6UL_CLK_PERCLK] = imx_clk_divider("perclk", "perclk_sel", base + 0x1c, 0, 6); imx6ul_clocks_init()
269 clks[IMX6UL_CLK_CAN_PODF] = imx_clk_divider("can_podf", "can_sel", base + 0x20, 2, 6); imx6ul_clocks_init()
270 clks[IMX6UL_CLK_GPMI_PODF] = imx_clk_divider("gpmi_podf", "gpmi_sel", base + 0x24, 22, 3); imx6ul_clocks_init()
271 clks[IMX6UL_CLK_BCH_PODF] = imx_clk_divider("bch_podf", "bch_sel", base + 0x24, 19, 3); imx6ul_clocks_init()
272 clks[IMX6UL_CLK_USDHC2_PODF] = imx_clk_divider("usdhc2_podf", "usdhc2_sel", base + 0x24, 16, 3); imx6ul_clocks_init()
273 clks[IMX6UL_CLK_USDHC1_PODF] = imx_clk_divider("usdhc1_podf", "usdhc1_sel", base + 0x24, 11, 3); imx6ul_clocks_init()
274 clks[IMX6UL_CLK_UART_PODF] = imx_clk_divider("uart_podf", "uart_sel", base + 0x24, 0, 6); imx6ul_clocks_init()
275 clks[IMX6UL_CLK_SAI3_PRED] = imx_clk_divider("sai3_pred", "sai3_sel", base + 0x28, 22, 3); imx6ul_clocks_init()
276 clks[IMX6UL_CLK_SAI3_PODF] = imx_clk_divider("sai3_podf", "sai3_pred", base + 0x28, 16, 6); imx6ul_clocks_init()
277 clks[IMX6UL_CLK_SAI1_PRED] = imx_clk_divider("sai1_pred", "sai1_sel", base + 0x28, 6, 3); imx6ul_clocks_init()
278 clks[IMX6UL_CLK_SAI1_PODF] = imx_clk_divider("sai1_podf", "sai1_pred", base + 0x28, 0, 6); imx6ul_clocks_init()
279 clks[IMX6UL_CLK_ENFC_PRED] = imx_clk_divider("enfc_pred", "enfc_sel", base + 0x2c, 18, 3); imx6ul_clocks_init()
280 clks[IMX6UL_CLK_ENFC_PODF] = imx_clk_divider("enfc_podf", "enfc_pred", base + 0x2c, 21, 6); imx6ul_clocks_init()
281 clks[IMX6UL_CLK_SAI2_PRED] = imx_clk_divider("sai2_pred", "sai2_sel", base + 0x2c, 6, 3); imx6ul_clocks_init()
282 clks[IMX6UL_CLK_SAI2_PODF] = imx_clk_divider("sai2_podf", "sai2_pred", base + 0x2c, 0, 6); imx6ul_clocks_init()
283 clks[IMX6UL_CLK_SPDIF_PRED] = imx_clk_divider("spdif_pred", "spdif_sel", base + 0x30, 25, 3); imx6ul_clocks_init()
284 clks[IMX6UL_CLK_SPDIF_PODF] = imx_clk_divider("spdif_podf", "spdif_pred", base + 0x30, 22, 3); imx6ul_clocks_init()
285 clks[IMX6UL_CLK_SIM_PODF] = imx_clk_divider("sim_podf", "sim_pre_sel", base + 0x34, 12, 3); imx6ul_clocks_init()
286 clks[IMX6UL_CLK_ECSPI_PODF] = imx_clk_divider("ecspi_podf", "ecspi_sel", base + 0x38, 19, 6); imx6ul_clocks_init()
287 clks[IMX6UL_CLK_LCDIF_PRED] = imx_clk_divider("lcdif_pred", "lcdif_pre_sel", base + 0x38, 12, 3); imx6ul_clocks_init()
288 clks[IMX6UL_CLK_CSI_PODF] = imx_clk_divider("csi_podf", "csi_sel", base + 0x3c, 11, 3); imx6ul_clocks_init()
290 clks[IMX6UL_CLK_ARM] = imx_clk_busy_divider("arm", "pll1_sw", base + 0x10, 0, 3, base + 0x48, 16); imx6ul_clocks_init()
291 clks[IMX6UL_CLK_MMDC_PODF] = imx_clk_busy_divider("mmdc_podf", "periph2", base + 0x14, 3, 3, base + 0x48, 2); imx6ul_clocks_init()
292 clks[IMX6UL_CLK_AXI_PODF] = imx_clk_busy_divider("axi_podf", "axi_sel", base + 0x14, 16, 3, base + 0x48, 0); imx6ul_clocks_init()
293 clks[IMX6UL_CLK_AHB] = imx_clk_busy_divider("ahb", "periph", base + 0x14, 10, 3, base + 0x48, 1); imx6ul_clocks_init()
296 clks[IMX6UL_CLK_AIPSTZ1] = imx_clk_gate2("aips_tz1", "ahb", base + 0x68, 0); imx6ul_clocks_init()
297 clks[IMX6UL_CLK_AIPSTZ2] = imx_clk_gate2("aips_tz2", "ahb", base + 0x68, 2); imx6ul_clocks_init()
298 clks[IMX6UL_CLK_APBHDMA] = imx_clk_gate2("apbh_dma", "bch_podf", base + 0x68, 4); imx6ul_clocks_init()
299 clks[IMX6UL_CLK_ASRC_IPG] = imx_clk_gate2_shared("asrc_ipg", "ahb", base + 0x68, 6, &share_count_asrc); imx6ul_clocks_init()
300 clks[IMX6UL_CLK_ASRC_MEM] = imx_clk_gate2_shared("asrc_mem", "ahb", base + 0x68, 6, &share_count_asrc); imx6ul_clocks_init()
301 clks[IMX6UL_CLK_CAAM_MEM] = imx_clk_gate2("caam_mem", "ahb", base + 0x68, 8); imx6ul_clocks_init()
302 clks[IMX6UL_CLK_CAAM_ACLK] = imx_clk_gate2("caam_aclk", "ahb", base + 0x68, 10); imx6ul_clocks_init()
303 clks[IMX6UL_CLK_CAAM_IPG] = imx_clk_gate2("caam_ipg", "ipg", base + 0x68, 12); imx6ul_clocks_init()
304 clks[IMX6UL_CLK_CAN1_IPG] = imx_clk_gate2("can1_ipg", "ipg", base + 0x68, 14); imx6ul_clocks_init()
305 clks[IMX6UL_CLK_CAN1_SERIAL] = imx_clk_gate2("can1_serial", "can_podf", base + 0x68, 16); imx6ul_clocks_init()
306 clks[IMX6UL_CLK_CAN2_IPG] = imx_clk_gate2("can2_ipg", "ipg", base + 0x68, 18); imx6ul_clocks_init()
307 clks[IMX6UL_CLK_CAN2_SERIAL] = imx_clk_gate2("can2_serial", "can_podf", base + 0x68, 20); imx6ul_clocks_init()
308 clks[IMX6UL_CLK_GPT2_BUS] = imx_clk_gate2("gpt_bus", "perclk", base + 0x68, 24); imx6ul_clocks_init()
309 clks[IMX6UL_CLK_GPT2_SERIAL] = imx_clk_gate2("gpt_serial", "perclk", base + 0x68, 26); imx6ul_clocks_init()
310 clks[IMX6UL_CLK_UART2_IPG] = imx_clk_gate2("uart2_ipg", "ipg", base + 0x68, 28); imx6ul_clocks_init()
311 clks[IMX6UL_CLK_UART2_SERIAL] = imx_clk_gate2("uart2_serial", "uart_podf", base + 0x68, 28); imx6ul_clocks_init()
312 clks[IMX6UL_CLK_AIPSTZ3] = imx_clk_gate2("aips_tz3", "ahb", base + 0x68, 30); imx6ul_clocks_init()
315 clks[IMX6UL_CLK_ECSPI1] = imx_clk_gate2("ecspi1", "ecspi_podf", base + 0x6c, 0); imx6ul_clocks_init()
316 clks[IMX6UL_CLK_ECSPI2] = imx_clk_gate2("ecspi2", "ecspi_podf", base + 0x6c, 2); imx6ul_clocks_init()
317 clks[IMX6UL_CLK_ECSPI3] = imx_clk_gate2("ecspi3", "ecspi_podf", base + 0x6c, 4); imx6ul_clocks_init()
318 clks[IMX6UL_CLK_ECSPI4] = imx_clk_gate2("ecspi4", "ecspi_podf", base + 0x6c, 6); imx6ul_clocks_init()
319 clks[IMX6UL_CLK_ADC2] = imx_clk_gate2("adc2", "ipg", base + 0x6c, 8); imx6ul_clocks_init()
320 clks[IMX6UL_CLK_UART3_IPG] = imx_clk_gate2("uart3_ipg", "ipg", base + 0x6c, 10); imx6ul_clocks_init()
321 clks[IMX6UL_CLK_UART3_SERIAL] = imx_clk_gate2("uart3_serial", "uart_podf", base + 0x6c, 10); imx6ul_clocks_init()
322 clks[IMX6UL_CLK_EPIT1] = imx_clk_gate2("epit1", "perclk", base + 0x6c, 12); imx6ul_clocks_init()
323 clks[IMX6UL_CLK_EPIT2] = imx_clk_gate2("epit2", "perclk", base + 0x6c, 14); imx6ul_clocks_init()
324 clks[IMX6UL_CLK_ADC1] = imx_clk_gate2("adc1", "ipg", base + 0x6c, 16); imx6ul_clocks_init()
325 clks[IMX6UL_CLK_GPT1_BUS] = imx_clk_gate2("gpt1_bus", "perclk", base + 0x6c, 20); imx6ul_clocks_init()
326 clks[IMX6UL_CLK_GPT1_SERIAL] = imx_clk_gate2("gpt1_serial", "perclk", base + 0x6c, 22); imx6ul_clocks_init()
327 clks[IMX6UL_CLK_UART4_IPG] = imx_clk_gate2("uart4_ipg", "ipg", base + 0x6c, 24); imx6ul_clocks_init()
328 clks[IMX6UL_CLK_UART4_SERIAL] = imx_clk_gate2("uart4_serail", "uart_podf", base + 0x6c, 24); imx6ul_clocks_init()
331 clks[IMX6UL_CLK_CSI] = imx_clk_gate2("csi", "csi_podf", base + 0x70, 2); imx6ul_clocks_init()
332 clks[IMX6UL_CLK_I2C1] = imx_clk_gate2("i2c1", "perclk", base + 0x70, 6); imx6ul_clocks_init()
333 clks[IMX6UL_CLK_I2C2] = imx_clk_gate2("i2c2", "perclk", base + 0x70, 8); imx6ul_clocks_init()
334 clks[IMX6UL_CLK_I2C3] = imx_clk_gate2("i2c3", "perclk", base + 0x70, 10); imx6ul_clocks_init()
335 clks[IMX6UL_CLK_OCOTP] = imx_clk_gate2("ocotp", "ipg", base + 0x70, 12); imx6ul_clocks_init()
336 clks[IMX6UL_CLK_IOMUXC] = imx_clk_gate2("iomuxc", "lcdif_podf", base + 0x70, 14); imx6ul_clocks_init()
337 clks[IMX6UL_CLK_LCDIF_APB] = imx_clk_gate2("lcdif_apb", "axi", base + 0x70, 28); imx6ul_clocks_init()
338 clks[IMX6UL_CLK_PXP] = imx_clk_gate2("pxp", "axi", base + 0x70, 30); imx6ul_clocks_init()
341 clks[IMX6UL_CLK_UART5_IPG] = imx_clk_gate2("uart5_ipg", "ipg", base + 0x74, 2); imx6ul_clocks_init()
342 clks[IMX6UL_CLK_UART5_SERIAL] = imx_clk_gate2("uart5_serial", "uart_podf", base + 0x74, 2); imx6ul_clocks_init()
343 clks[IMX6UL_CLK_ENET] = imx_clk_gate2("enet", "ipg", base + 0x74, 4); imx6ul_clocks_init()
344 clks[IMX6UL_CLK_ENET_AHB] = imx_clk_gate2("enet_ahb", "ahb", base + 0x74, 4); imx6ul_clocks_init()
345 clks[IMX6UL_CLK_UART6_IPG] = imx_clk_gate2("uart6_ipg", "ipg", base + 0x74, 6); imx6ul_clocks_init()
346 clks[IMX6UL_CLK_UART6_SERIAL] = imx_clk_gate2("uart6_serial", "uart_podf", base + 0x74, 6); imx6ul_clocks_init()
347 clks[IMX6UL_CLK_LCDIF_PIX] = imx_clk_gate2("lcdif_pix", "lcdif_podf", base + 0x74, 10); imx6ul_clocks_init()
348 clks[IMX6UL_CLK_QSPI] = imx_clk_gate2("qspi1", "qspi1_podf", base + 0x74, 14); imx6ul_clocks_init()
349 clks[IMX6UL_CLK_WDOG1] = imx_clk_gate2("wdog1", "ipg", base + 0x74, 16); imx6ul_clocks_init()
350 clks[IMX6UL_CLK_MMDC_P0_FAST] = imx_clk_gate("mmdc_p0_fast", "mmdc_podf", base + 0x74, 20); imx6ul_clocks_init()
351 clks[IMX6UL_CLK_MMDC_P0_IPG] = imx_clk_gate2("mmdc_p0_ipg", "ipg", base + 0x74, 24); imx6ul_clocks_init()
352 clks[IMX6UL_CLK_AXI] = imx_clk_gate("axi", "axi_podf", base + 0x74, 28); imx6ul_clocks_init()
355 clks[IMX6UL_CLK_PER_BCH] = imx_clk_gate2("per_bch", "bch_podf", base + 0x78, 12); imx6ul_clocks_init()
356 clks[IMX6UL_CLK_PWM1] = imx_clk_gate2("pwm1", "perclk", base + 0x78, 16); imx6ul_clocks_init()
357 clks[IMX6UL_CLK_PWM2] = imx_clk_gate2("pwm2", "perclk", base + 0x78, 18); imx6ul_clocks_init()
358 clks[IMX6UL_CLK_PWM3] = imx_clk_gate2("pwm3", "perclk", base + 0x78, 20); imx6ul_clocks_init()
359 clks[IMX6UL_CLK_PWM4] = imx_clk_gate2("pwm4", "perclk", base + 0x78, 22); imx6ul_clocks_init()
360 clks[IMX6UL_CLK_GPMI_BCH_APB] = imx_clk_gate2("gpmi_bch_apb", "bch_podf", base + 0x78, 24); imx6ul_clocks_init()
361 clks[IMX6UL_CLK_GPMI_BCH] = imx_clk_gate2("gpmi_bch", "gpmi_podf", base + 0x78, 26); imx6ul_clocks_init()
362 clks[IMX6UL_CLK_GPMI_IO] = imx_clk_gate2("gpmi_io", "enfc_podf", base + 0x78, 28); imx6ul_clocks_init()
363 clks[IMX6UL_CLK_GPMI_APB] = imx_clk_gate2("gpmi_apb", "bch_podf", base + 0x78, 30); imx6ul_clocks_init()
366 clks[IMX6UL_CLK_ROM] = imx_clk_gate2("rom", "ahb", base + 0x7c, 0); imx6ul_clocks_init()
367 clks[IMX6UL_CLK_SDMA] = imx_clk_gate2("sdma", "ahb", base + 0x7c, 6); imx6ul_clocks_init()
368 clks[IMX6UL_CLK_WDOG2] = imx_clk_gate2("wdog2", "ipg", base + 0x7c, 10); imx6ul_clocks_init()
369 clks[IMX6UL_CLK_SPBA] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12); imx6ul_clocks_init()
370 clks[IMX6UL_CLK_SPDIF] = imx_clk_gate2_shared("spdif", "spdif_podf", base + 0x7c, 14, &share_count_audio); imx6ul_clocks_init()
371 clks[IMX6UL_CLK_SPDIF_GCLK] = imx_clk_gate2_shared("spdif_gclk", "ipg", base + 0x7c, 14, &share_count_audio); imx6ul_clocks_init()
372 clks[IMX6UL_CLK_SAI3] = imx_clk_gate2_shared("sai3", "sai3_podf", base + 0x7c, 22, &share_count_sai3); imx6ul_clocks_init()
373 clks[IMX6UL_CLK_SAI3_IPG] = imx_clk_gate2_shared("sai3_ipg", "ipg", base + 0x7c, 22, &share_count_sai3); imx6ul_clocks_init()
374 clks[IMX6UL_CLK_UART1_IPG] = imx_clk_gate2("uart1_ipg", "ipg", base + 0x7c, 24); imx6ul_clocks_init()
375 clks[IMX6UL_CLK_UART1_SERIAL] = imx_clk_gate2("uart1_serial", "uart_podf", base + 0x7c, 24); imx6ul_clocks_init()
376 clks[IMX6UL_CLK_UART7_IPG] = imx_clk_gate2("uart7_ipg", "ipg", base + 0x7c, 26); imx6ul_clocks_init()
377 clks[IMX6UL_CLK_UART7_SERIAL] = imx_clk_gate2("uart7_serial", "uart_podf", base + 0x7c, 26); imx6ul_clocks_init()
378 clks[IMX6UL_CLK_SAI1] = imx_clk_gate2_shared("sai1", "sai1_podf", base + 0x7c, 28, &share_count_sai1); imx6ul_clocks_init()
379 clks[IMX6UL_CLK_SAI1_IPG] = imx_clk_gate2_shared("sai1_ipg", "ipg", base + 0x7c, 28, &share_count_sai1); imx6ul_clocks_init()
380 clks[IMX6UL_CLK_SAI2] = imx_clk_gate2_shared("sai2", "sai2_podf", base + 0x7c, 30, &share_count_sai2); imx6ul_clocks_init()
381 clks[IMX6UL_CLK_SAI2_IPG] = imx_clk_gate2_shared("sai2_ipg", "ipg", base + 0x7c, 30, &share_count_sai2); imx6ul_clocks_init()
384 clks[IMX6UL_CLK_USBOH3] = imx_clk_gate2("usboh3", "ipg", base + 0x80, 0); imx6ul_clocks_init()
385 clks[IMX6UL_CLK_USDHC1] = imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2); imx6ul_clocks_init()
386 clks[IMX6UL_CLK_USDHC2] = imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4); imx6ul_clocks_init()
387 clks[IMX6UL_CLK_SIM1] = imx_clk_gate2("sim1", "sim_sel", base + 0x80, 6); imx6ul_clocks_init()
388 clks[IMX6UL_CLK_SIM2] = imx_clk_gate2("sim2", "sim_sel", base + 0x80, 8); imx6ul_clocks_init()
389 clks[IMX6UL_CLK_EIM] = imx_clk_gate2("eim", "eim_slow_podf", base + 0x80, 10); imx6ul_clocks_init()
390 clks[IMX6UL_CLK_PWM8] = imx_clk_gate2("pwm8", "perclk", base + 0x80, 16); imx6ul_clocks_init()
391 clks[IMX6UL_CLK_UART8_IPG] = imx_clk_gate2("uart8_ipg", "ipg", base + 0x80, 14); imx6ul_clocks_init()
392 clks[IMX6UL_CLK_UART8_SERIAL] = imx_clk_gate2("uart8_serial", "uart_podf", base + 0x80, 14); imx6ul_clocks_init()
393 clks[IMX6UL_CLK_WDOG3] = imx_clk_gate2("wdog3", "ipg", base + 0x80, 20); imx6ul_clocks_init()
394 clks[IMX6UL_CLK_I2C4] = imx_clk_gate2("i2c4", "perclk", base + 0x80, 24); imx6ul_clocks_init()
395 clks[IMX6UL_CLK_PWM5] = imx_clk_gate2("pwm5", "perclk", base + 0x80, 26); imx6ul_clocks_init()
396 clks[IMX6UL_CLK_PWM6] = imx_clk_gate2("pwm6", "perclk", base + 0x80, 28); imx6ul_clocks_init()
397 clks[IMX6UL_CLK_PWM7] = imx_clk_gate2("Pwm7", "perclk", base + 0x80, 30); imx6ul_clocks_init()
400 writel_relaxed(BM_CCM_CCDR_MMDC_CH0_MASK, base + CCDR); imx6ul_clocks_init()
|
| H A D | clk-imx7d.c | 380 void __iomem *base; imx7d_clocks_init() local
387 base = of_iomap(np, 0); imx7d_clocks_init()
388 WARN_ON(!base); imx7d_clocks_init()
390 clks[IMX7D_PLL_ARM_MAIN_SRC] = imx_clk_mux("pll_arm_main_src", base + 0x60, 14, 2, pll_bypass_src_sel, ARRAY_SIZE(pll_bypass_src_sel)); imx7d_clocks_init()
391 clks[IMX7D_PLL_DRAM_MAIN_SRC] = imx_clk_mux("pll_dram_main_src", base + 0x70, 14, 2, pll_bypass_src_sel, ARRAY_SIZE(pll_bypass_src_sel)); imx7d_clocks_init()
392 clks[IMX7D_PLL_SYS_MAIN_SRC] = imx_clk_mux("pll_sys_main_src", base + 0xb0, 14, 2, pll_bypass_src_sel, ARRAY_SIZE(pll_bypass_src_sel)); imx7d_clocks_init()
393 clks[IMX7D_PLL_ENET_MAIN_SRC] = imx_clk_mux("pll_enet_main_src", base + 0xe0, 14, 2, pll_bypass_src_sel, ARRAY_SIZE(pll_bypass_src_sel)); imx7d_clocks_init()
394 clks[IMX7D_PLL_AUDIO_MAIN_SRC] = imx_clk_mux("pll_audio_main_src", base + 0xf0, 14, 2, pll_bypass_src_sel, ARRAY_SIZE(pll_bypass_src_sel)); imx7d_clocks_init()
395 clks[IMX7D_PLL_VIDEO_MAIN_SRC] = imx_clk_mux("pll_video_main_src", base + 0x130, 14, 2, pll_bypass_src_sel, ARRAY_SIZE(pll_bypass_src_sel)); imx7d_clocks_init()
397 clks[IMX7D_PLL_ARM_MAIN] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll_arm_main", "pll_arm_main_src", base + 0x60, 0x7f); imx7d_clocks_init()
398 clks[IMX7D_PLL_DRAM_MAIN] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll_dram_main", "pll_dram_main_src", base + 0x70, 0x7f); imx7d_clocks_init()
399 clks[IMX7D_PLL_SYS_MAIN] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll_sys_main", "pll_sys_main_src", base + 0xb0, 0x1); imx7d_clocks_init()
400 clks[IMX7D_PLL_ENET_MAIN] = imx_clk_pllv3(IMX_PLLV3_ENET_IMX7, "pll_enet_main", "pll_enet_main_src", base + 0xe0, 0x0); imx7d_clocks_init()
401 clks[IMX7D_PLL_AUDIO_MAIN] = imx_clk_pllv3(IMX_PLLV3_AV, "pll_audio_main", "pll_audio_main_src", base + 0xf0, 0x7f); imx7d_clocks_init()
402 clks[IMX7D_PLL_VIDEO_MAIN] = imx_clk_pllv3(IMX_PLLV3_AV, "pll_video_main", "pll_video_main_src", base + 0x130, 0x7f); imx7d_clocks_init()
404 clks[IMX7D_PLL_ARM_MAIN_BYPASS] = imx_clk_mux_flags("pll_arm_main_bypass", base + 0x60, 16, 1, pll_arm_bypass_sel, ARRAY_SIZE(pll_arm_bypass_sel), CLK_SET_RATE_PARENT); imx7d_clocks_init()
405 clks[IMX7D_PLL_DRAM_MAIN_BYPASS] = imx_clk_mux_flags("pll_dram_main_bypass", base + 0x70, 16, 1, pll_dram_bypass_sel, ARRAY_SIZE(pll_dram_bypass_sel), CLK_SET_RATE_PARENT); imx7d_clocks_init()
406 clks[IMX7D_PLL_SYS_MAIN_BYPASS] = imx_clk_mux_flags("pll_sys_main_bypass", base + 0xb0, 16, 1, pll_sys_bypass_sel, ARRAY_SIZE(pll_sys_bypass_sel), CLK_SET_RATE_PARENT); imx7d_clocks_init()
407 clks[IMX7D_PLL_ENET_MAIN_BYPASS] = imx_clk_mux_flags("pll_enet_main_bypass", base + 0xe0, 16, 1, pll_enet_bypass_sel, ARRAY_SIZE(pll_enet_bypass_sel), CLK_SET_RATE_PARENT); imx7d_clocks_init()
408 clks[IMX7D_PLL_AUDIO_MAIN_BYPASS] = imx_clk_mux_flags("pll_audio_main_bypass", base + 0xf0, 16, 1, pll_audio_bypass_sel, ARRAY_SIZE(pll_audio_bypass_sel), CLK_SET_RATE_PARENT); imx7d_clocks_init()
409 clks[IMX7D_PLL_VIDEO_MAIN_BYPASS] = imx_clk_mux_flags("pll_video_main_bypass", base + 0x130, 16, 1, pll_video_bypass_sel, ARRAY_SIZE(pll_video_bypass_sel), CLK_SET_RATE_PARENT); imx7d_clocks_init()
418 clks[IMX7D_PLL_ARM_MAIN_CLK] = imx_clk_gate("pll_arm_main_clk", "pll_arm_main_bypass", base + 0x60, 13); imx7d_clocks_init()
419 clks[IMX7D_PLL_DRAM_MAIN_CLK] = imx_clk_gate("pll_dram_main_clk", "pll_dram_main_bypass", base + 0x70, 13); imx7d_clocks_init()
420 clks[IMX7D_PLL_SYS_MAIN_CLK] = imx_clk_gate("pll_sys_main_clk", "pll_sys_main_bypass", base + 0xb0, 13); imx7d_clocks_init()
421 clks[IMX7D_PLL_AUDIO_MAIN_CLK] = imx_clk_gate("pll_audio_main_clk", "pll_audio_main_bypass", base + 0xf0, 13); imx7d_clocks_init()
422 clks[IMX7D_PLL_VIDEO_MAIN_CLK] = imx_clk_gate("pll_video_main_clk", "pll_video_main_bypass", base + 0x130, 13); imx7d_clocks_init()
424 clks[IMX7D_PLL_SYS_PFD0_392M_CLK] = imx_clk_pfd("pll_sys_pfd0_392m_clk", "pll_sys_main_clk", base + 0xc0, 0); imx7d_clocks_init()
425 clks[IMX7D_PLL_SYS_PFD1_332M_CLK] = imx_clk_pfd("pll_sys_pfd1_332m_clk", "pll_sys_main_clk", base + 0xc0, 1); imx7d_clocks_init()
426 clks[IMX7D_PLL_SYS_PFD2_270M_CLK] = imx_clk_pfd("pll_sys_pfd2_270m_clk", "pll_sys_main_clk", base + 0xc0, 2); imx7d_clocks_init()
428 clks[IMX7D_PLL_SYS_PFD3_CLK] = imx_clk_pfd("pll_sys_pfd3_clk", "pll_sys_main_clk", base + 0xc0, 3); imx7d_clocks_init()
429 clks[IMX7D_PLL_SYS_PFD4_CLK] = imx_clk_pfd("pll_sys_pfd4_clk", "pll_sys_main_clk", base + 0xd0, 0); imx7d_clocks_init()
430 clks[IMX7D_PLL_SYS_PFD5_CLK] = imx_clk_pfd("pll_sys_pfd5_clk", "pll_sys_main_clk", base + 0xd0, 1); imx7d_clocks_init()
431 clks[IMX7D_PLL_SYS_PFD6_CLK] = imx_clk_pfd("pll_sys_pfd6_clk", "pll_sys_main_clk", base + 0xd0, 2); imx7d_clocks_init()
432 clks[IMX7D_PLL_SYS_PFD7_CLK] = imx_clk_pfd("pll_sys_pfd7_clk", "pll_sys_main_clk", base + 0xd0, 3); imx7d_clocks_init()
439 clks[IMX7D_PLL_SYS_MAIN_480M_CLK] = imx_clk_gate_dis("pll_sys_main_480m_clk", "pll_sys_main_480m", base + 0xb0, 4); imx7d_clocks_init()
440 clks[IMX7D_PLL_SYS_MAIN_240M_CLK] = imx_clk_gate_dis("pll_sys_main_240m_clk", "pll_sys_main_240m", base + 0xb0, 5); imx7d_clocks_init()
441 clks[IMX7D_PLL_SYS_MAIN_120M_CLK] = imx_clk_gate_dis("pll_sys_main_120m_clk", "pll_sys_main_120m", base + 0xb0, 6); imx7d_clocks_init()
442 clks[IMX7D_PLL_DRAM_MAIN_533M_CLK] = imx_clk_gate("pll_dram_533m_clk", "pll_dram_533m", base + 0x70, 12); imx7d_clocks_init()
448 clks[IMX7D_PLL_SYS_PFD0_196M_CLK] = imx_clk_gate_dis("pll_sys_pfd0_196m_clk", "pll_sys_pfd0_196m", base + 0xb0, 26); imx7d_clocks_init()
449 clks[IMX7D_PLL_SYS_PFD1_166M_CLK] = imx_clk_gate_dis("pll_sys_pfd1_166m_clk", "pll_sys_pfd1_166m", base + 0xb0, 27); imx7d_clocks_init()
450 clks[IMX7D_PLL_SYS_PFD2_135M_CLK] = imx_clk_gate_dis("pll_sys_pfd2_135m_clk", "pll_sys_pfd2_135m", base + 0xb0, 28); imx7d_clocks_init()
461 clks[IMX7D_PLL_ENET_MAIN_500M_CLK] = imx_clk_gate("pll_enet_500m_clk", "pll_enet_500m", base + 0xe0, 12); imx7d_clocks_init()
462 clks[IMX7D_PLL_ENET_MAIN_250M_CLK] = imx_clk_gate("pll_enet_250m_clk", "pll_enet_250m", base + 0xe0, 11); imx7d_clocks_init()
463 clks[IMX7D_PLL_ENET_MAIN_125M_CLK] = imx_clk_gate("pll_enet_125m_clk", "pll_enet_125m", base + 0xe0, 10); imx7d_clocks_init()
464 clks[IMX7D_PLL_ENET_MAIN_100M_CLK] = imx_clk_gate("pll_enet_100m_clk", "pll_enet_100m", base + 0xe0, 9); imx7d_clocks_init()
465 clks[IMX7D_PLL_ENET_MAIN_50M_CLK] = imx_clk_gate("pll_enet_50m_clk", "pll_enet_50m", base + 0xe0, 8); imx7d_clocks_init()
466 clks[IMX7D_PLL_ENET_MAIN_40M_CLK] = imx_clk_gate("pll_enet_40m_clk", "pll_enet_40m", base + 0xe0, 7); imx7d_clocks_init()
467 clks[IMX7D_PLL_ENET_MAIN_25M_CLK] = imx_clk_gate("pll_enet_25m_clk", "pll_enet_25m", base + 0xe0, 6); imx7d_clocks_init()
469 clks[IMX7D_LVDS1_OUT_SEL] = imx_clk_mux("lvds1_sel", base + 0x170, 0, 5, lvds1_sel, ARRAY_SIZE(lvds1_sel)); imx7d_clocks_init()
470 clks[IMX7D_LVDS1_OUT_CLK] = imx_clk_gate_exclusive("lvds1_out", "lvds1_sel", base + 0x170, 5, BIT(6)); imx7d_clocks_init()
473 base = of_iomap(np, 0); imx7d_clocks_init()
474 WARN_ON(!base); imx7d_clocks_init()
476 clks[IMX7D_ARM_A7_ROOT_SRC] = imx_clk_mux("arm_a7_src", base + 0x8000, 24, 3, arm_a7_sel, ARRAY_SIZE(arm_a7_sel)); imx7d_clocks_init()
477 clks[IMX7D_ARM_M4_ROOT_SRC] = imx_clk_mux("arm_m4_src", base + 0x8080, 24, 3, arm_m4_sel, ARRAY_SIZE(arm_m4_sel)); imx7d_clocks_init()
478 clks[IMX7D_ARM_M0_ROOT_SRC] = imx_clk_mux("arm_m0_src", base + 0x8100, 24, 3, arm_m0_sel, ARRAY_SIZE(arm_m0_sel)); imx7d_clocks_init()
479 clks[IMX7D_MAIN_AXI_ROOT_SRC] = imx_clk_mux("axi_src", base + 0x8800, 24, 3, axi_sel, ARRAY_SIZE(axi_sel)); imx7d_clocks_init()
480 clks[IMX7D_DISP_AXI_ROOT_SRC] = imx_clk_mux("disp_axi_src", base + 0x8880, 24, 3, disp_axi_sel, ARRAY_SIZE(disp_axi_sel)); imx7d_clocks_init()
481 clks[IMX7D_ENET_AXI_ROOT_SRC] = imx_clk_mux("enet_axi_src", base + 0x8900, 24, 3, enet_axi_sel, ARRAY_SIZE(enet_axi_sel)); imx7d_clocks_init()
482 clks[IMX7D_NAND_USDHC_BUS_ROOT_SRC] = imx_clk_mux("nand_usdhc_src", base + 0x8980, 24, 3, nand_usdhc_bus_sel, ARRAY_SIZE(nand_usdhc_bus_sel)); imx7d_clocks_init()
483 clks[IMX7D_AHB_CHANNEL_ROOT_SRC] = imx_clk_mux("ahb_src", base + 0x9000, 24, 3, ahb_channel_sel, ARRAY_SIZE(ahb_channel_sel)); imx7d_clocks_init()
484 clks[IMX7D_DRAM_PHYM_ROOT_SRC] = imx_clk_mux("dram_phym_src", base + 0x9800, 24, 1, dram_phym_sel, ARRAY_SIZE(dram_phym_sel)); imx7d_clocks_init()
485 clks[IMX7D_DRAM_ROOT_SRC] = imx_clk_mux("dram_src", base + 0x9880, 24, 1, dram_sel, ARRAY_SIZE(dram_sel)); imx7d_clocks_init()
486 clks[IMX7D_DRAM_PHYM_ALT_ROOT_SRC] = imx_clk_mux("dram_phym_alt_src", base + 0xa000, 24, 3, dram_phym_alt_sel, ARRAY_SIZE(dram_phym_alt_sel)); imx7d_clocks_init()
487 clks[IMX7D_DRAM_ALT_ROOT_SRC] = imx_clk_mux("dram_alt_src", base + 0xa080, 24, 3, dram_alt_sel, ARRAY_SIZE(dram_alt_sel)); imx7d_clocks_init()
488 clks[IMX7D_USB_HSIC_ROOT_SRC] = imx_clk_mux("usb_hsic_src", base + 0xa100, 24, 3, usb_hsic_sel, ARRAY_SIZE(usb_hsic_sel)); imx7d_clocks_init()
489 clks[IMX7D_PCIE_CTRL_ROOT_SRC] = imx_clk_mux("pcie_ctrl_src", base + 0xa180, 24, 3, pcie_ctrl_sel, ARRAY_SIZE(pcie_ctrl_sel)); imx7d_clocks_init()
490 clks[IMX7D_PCIE_PHY_ROOT_SRC] = imx_clk_mux("pcie_phy_src", base + 0xa200, 24, 3, pcie_phy_sel, ARRAY_SIZE(pcie_phy_sel)); imx7d_clocks_init()
491 clks[IMX7D_EPDC_PIXEL_ROOT_SRC] = imx_clk_mux("epdc_pixel_src", base + 0xa280, 24, 3, epdc_pixel_sel, ARRAY_SIZE(epdc_pixel_sel)); imx7d_clocks_init()
492 clks[IMX7D_LCDIF_PIXEL_ROOT_SRC] = imx_clk_mux("lcdif_pixel_src", base + 0xa300, 24, 3, lcdif_pixel_sel, ARRAY_SIZE(lcdif_pixel_sel)); imx7d_clocks_init()
493 clks[IMX7D_MIPI_DSI_ROOT_SRC] = imx_clk_mux("mipi_dsi_src", base + 0xa380, 24, 3, mipi_dsi_sel, ARRAY_SIZE(mipi_dsi_sel)); imx7d_clocks_init()
494 clks[IMX7D_MIPI_CSI_ROOT_SRC] = imx_clk_mux("mipi_csi_src", base + 0xa400, 24, 3, mipi_csi_sel, ARRAY_SIZE(mipi_csi_sel)); imx7d_clocks_init()
495 clks[IMX7D_MIPI_DPHY_ROOT_SRC] = imx_clk_mux("mipi_dphy_src", base + 0xa480, 24, 3, mipi_dphy_sel, ARRAY_SIZE(mipi_dphy_sel)); imx7d_clocks_init()
496 clks[IMX7D_SAI1_ROOT_SRC] = imx_clk_mux("sai1_src", base + 0xa500, 24, 3, sai1_sel, ARRAY_SIZE(sai1_sel)); imx7d_clocks_init()
497 clks[IMX7D_SAI2_ROOT_SRC] = imx_clk_mux("sai2_src", base + 0xa580, 24, 3, sai2_sel, ARRAY_SIZE(sai2_sel)); imx7d_clocks_init()
498 clks[IMX7D_SAI3_ROOT_SRC] = imx_clk_mux("sai3_src", base + 0xa600, 24, 3, sai3_sel, ARRAY_SIZE(sai3_sel)); imx7d_clocks_init()
499 clks[IMX7D_SPDIF_ROOT_SRC] = imx_clk_mux("spdif_src", base + 0xa680, 24, 3, spdif_sel, ARRAY_SIZE(spdif_sel)); imx7d_clocks_init()
500 clks[IMX7D_ENET1_REF_ROOT_SRC] = imx_clk_mux("enet1_ref_src", base + 0xa700, 24, 3, enet1_ref_sel, ARRAY_SIZE(enet1_ref_sel)); imx7d_clocks_init()
501 clks[IMX7D_ENET1_TIME_ROOT_SRC] = imx_clk_mux("enet1_time_src", base + 0xa780, 24, 3, enet1_time_sel, ARRAY_SIZE(enet1_time_sel)); imx7d_clocks_init()
502 clks[IMX7D_ENET2_REF_ROOT_SRC] = imx_clk_mux("enet2_ref_src", base + 0xa800, 24, 3, enet2_ref_sel, ARRAY_SIZE(enet2_ref_sel)); imx7d_clocks_init()
503 clks[IMX7D_ENET2_TIME_ROOT_SRC] = imx_clk_mux("enet2_time_src", base + 0xa880, 24, 3, enet2_time_sel, ARRAY_SIZE(enet2_time_sel)); imx7d_clocks_init()
504 clks[IMX7D_ENET_PHY_REF_ROOT_SRC] = imx_clk_mux("enet_phy_ref_src", base + 0xa900, 24, 3, enet_phy_ref_sel, ARRAY_SIZE(enet_phy_ref_sel)); imx7d_clocks_init()
505 clks[IMX7D_EIM_ROOT_SRC] = imx_clk_mux("eim_src", base + 0xa980, 24, 3, eim_sel, ARRAY_SIZE(eim_sel)); imx7d_clocks_init()
506 clks[IMX7D_NAND_ROOT_SRC] = imx_clk_mux("nand_src", base + 0xaa00, 24, 3, nand_sel, ARRAY_SIZE(nand_sel)); imx7d_clocks_init()
507 clks[IMX7D_QSPI_ROOT_SRC] = imx_clk_mux("qspi_src", base + 0xaa80, 24, 3, qspi_sel, ARRAY_SIZE(qspi_sel)); imx7d_clocks_init()
508 clks[IMX7D_USDHC1_ROOT_SRC] = imx_clk_mux("usdhc1_src", base + 0xab00, 24, 3, usdhc1_sel, ARRAY_SIZE(usdhc1_sel)); imx7d_clocks_init()
509 clks[IMX7D_USDHC2_ROOT_SRC] = imx_clk_mux("usdhc2_src", base + 0xab80, 24, 3, usdhc2_sel, ARRAY_SIZE(usdhc2_sel)); imx7d_clocks_init()
510 clks[IMX7D_USDHC3_ROOT_SRC] = imx_clk_mux("usdhc3_src", base + 0xac00, 24, 3, usdhc3_sel, ARRAY_SIZE(usdhc3_sel)); imx7d_clocks_init()
511 clks[IMX7D_CAN1_ROOT_SRC] = imx_clk_mux("can1_src", base + 0xac80, 24, 3, can1_sel, ARRAY_SIZE(can1_sel)); imx7d_clocks_init()
512 clks[IMX7D_CAN2_ROOT_SRC] = imx_clk_mux("can2_src", base + 0xad00, 24, 3, can2_sel, ARRAY_SIZE(can2_sel)); imx7d_clocks_init()
513 clks[IMX7D_I2C1_ROOT_SRC] = imx_clk_mux("i2c1_src", base + 0xad80, 24, 3, i2c1_sel, ARRAY_SIZE(i2c1_sel)); imx7d_clocks_init()
514 clks[IMX7D_I2C2_ROOT_SRC] = imx_clk_mux("i2c2_src", base + 0xae00, 24, 3, i2c2_sel, ARRAY_SIZE(i2c2_sel)); imx7d_clocks_init()
515 clks[IMX7D_I2C3_ROOT_SRC] = imx_clk_mux("i2c3_src", base + 0xae80, 24, 3, i2c3_sel, ARRAY_SIZE(i2c3_sel)); imx7d_clocks_init()
516 clks[IMX7D_I2C4_ROOT_SRC] = imx_clk_mux("i2c4_src", base + 0xaf00, 24, 3, i2c4_sel, ARRAY_SIZE(i2c4_sel)); imx7d_clocks_init()
517 clks[IMX7D_UART1_ROOT_SRC] = imx_clk_mux("uart1_src", base + 0xaf80, 24, 3, uart1_sel, ARRAY_SIZE(uart1_sel)); imx7d_clocks_init()
518 clks[IMX7D_UART2_ROOT_SRC] = imx_clk_mux("uart2_src", base + 0xb000, 24, 3, uart2_sel, ARRAY_SIZE(uart2_sel)); imx7d_clocks_init()
519 clks[IMX7D_UART3_ROOT_SRC] = imx_clk_mux("uart3_src", base + 0xb080, 24, 3, uart3_sel, ARRAY_SIZE(uart3_sel)); imx7d_clocks_init()
520 clks[IMX7D_UART4_ROOT_SRC] = imx_clk_mux("uart4_src", base + 0xb100, 24, 3, uart4_sel, ARRAY_SIZE(uart4_sel)); imx7d_clocks_init()
521 clks[IMX7D_UART5_ROOT_SRC] = imx_clk_mux("uart5_src", base + 0xb180, 24, 3, uart5_sel, ARRAY_SIZE(uart5_sel)); imx7d_clocks_init()
522 clks[IMX7D_UART6_ROOT_SRC] = imx_clk_mux("uart6_src", base + 0xb200, 24, 3, uart6_sel, ARRAY_SIZE(uart6_sel)); imx7d_clocks_init()
523 clks[IMX7D_UART7_ROOT_SRC] = imx_clk_mux("uart7_src", base + 0xb280, 24, 3, uart7_sel, ARRAY_SIZE(uart7_sel)); imx7d_clocks_init()
524 clks[IMX7D_ECSPI1_ROOT_SRC] = imx_clk_mux("ecspi1_src", base + 0xb300, 24, 3, ecspi1_sel, ARRAY_SIZE(ecspi1_sel)); imx7d_clocks_init()
525 clks[IMX7D_ECSPI2_ROOT_SRC] = imx_clk_mux("ecspi2_src", base + 0xb380, 24, 3, ecspi2_sel, ARRAY_SIZE(ecspi2_sel)); imx7d_clocks_init()
526 clks[IMX7D_ECSPI3_ROOT_SRC] = imx_clk_mux("ecspi3_src", base + 0xb400, 24, 3, ecspi3_sel, ARRAY_SIZE(ecspi3_sel)); imx7d_clocks_init()
527 clks[IMX7D_ECSPI4_ROOT_SRC] = imx_clk_mux("ecspi4_src", base + 0xb480, 24, 3, ecspi4_sel, ARRAY_SIZE(ecspi4_sel)); imx7d_clocks_init()
528 clks[IMX7D_PWM1_ROOT_SRC] = imx_clk_mux("pwm1_src", base + 0xb500, 24, 3, pwm1_sel, ARRAY_SIZE(pwm1_sel)); imx7d_clocks_init()
529 clks[IMX7D_PWM2_ROOT_SRC] = imx_clk_mux("pwm2_src", base + 0xb580, 24, 3, pwm2_sel, ARRAY_SIZE(pwm2_sel)); imx7d_clocks_init()
530 clks[IMX7D_PWM3_ROOT_SRC] = imx_clk_mux("pwm3_src", base + 0xb600, 24, 3, pwm3_sel, ARRAY_SIZE(pwm3_sel)); imx7d_clocks_init()
531 clks[IMX7D_PWM4_ROOT_SRC] = imx_clk_mux("pwm4_src", base + 0xb680, 24, 3, pwm4_sel, ARRAY_SIZE(pwm4_sel)); imx7d_clocks_init()
532 clks[IMX7D_FLEXTIMER1_ROOT_SRC] = imx_clk_mux("flextimer1_src", base + 0xb700, 24, 3, flextimer1_sel, ARRAY_SIZE(flextimer1_sel)); imx7d_clocks_init()
533 clks[IMX7D_FLEXTIMER2_ROOT_SRC] = imx_clk_mux("flextimer2_src", base + 0xb780, 24, 3, flextimer2_sel, ARRAY_SIZE(flextimer2_sel)); imx7d_clocks_init()
534 clks[IMX7D_SIM1_ROOT_SRC] = imx_clk_mux("sim1_src", base + 0xb800, 24, 3, sim1_sel, ARRAY_SIZE(sim1_sel)); imx7d_clocks_init()
535 clks[IMX7D_SIM2_ROOT_SRC] = imx_clk_mux("sim2_src", base + 0xb880, 24, 3, sim2_sel, ARRAY_SIZE(sim2_sel)); imx7d_clocks_init()
536 clks[IMX7D_GPT1_ROOT_SRC] = imx_clk_mux("gpt1_src", base + 0xb900, 24, 3, gpt1_sel, ARRAY_SIZE(gpt1_sel)); imx7d_clocks_init()
537 clks[IMX7D_GPT2_ROOT_SRC] = imx_clk_mux("gpt2_src", base + 0xb980, 24, 3, gpt2_sel, ARRAY_SIZE(gpt2_sel)); imx7d_clocks_init()
538 clks[IMX7D_GPT3_ROOT_SRC] = imx_clk_mux("gpt3_src", base + 0xba00, 24, 3, gpt3_sel, ARRAY_SIZE(gpt3_sel)); imx7d_clocks_init()
539 clks[IMX7D_GPT4_ROOT_SRC] = imx_clk_mux("gpt4_src", base + 0xba80, 24, 3, gpt4_sel, ARRAY_SIZE(gpt4_sel)); imx7d_clocks_init()
540 clks[IMX7D_TRACE_ROOT_SRC] = imx_clk_mux("trace_src", base + 0xbb00, 24, 3, trace_sel, ARRAY_SIZE(trace_sel)); imx7d_clocks_init()
541 clks[IMX7D_WDOG_ROOT_SRC] = imx_clk_mux("wdog_src", base + 0xbb80, 24, 3, wdog_sel, ARRAY_SIZE(wdog_sel)); imx7d_clocks_init()
542 clks[IMX7D_CSI_MCLK_ROOT_SRC] = imx_clk_mux("csi_mclk_src", base + 0xbc00, 24, 3, csi_mclk_sel, ARRAY_SIZE(csi_mclk_sel)); imx7d_clocks_init()
543 clks[IMX7D_AUDIO_MCLK_ROOT_SRC] = imx_clk_mux("audio_mclk_src", base + 0xbc80, 24, 3, audio_mclk_sel, ARRAY_SIZE(audio_mclk_sel)); imx7d_clocks_init()
544 clks[IMX7D_WRCLK_ROOT_SRC] = imx_clk_mux("wrclk_src", base + 0xbd00, 24, 3, wrclk_sel, ARRAY_SIZE(wrclk_sel)); imx7d_clocks_init()
545 clks[IMX7D_CLKO1_ROOT_SRC] = imx_clk_mux("clko1_src", base + 0xbd80, 24, 3, clko1_sel, ARRAY_SIZE(clko1_sel)); imx7d_clocks_init()
546 clks[IMX7D_CLKO2_ROOT_SRC] = imx_clk_mux("clko2_src", base + 0xbe00, 24, 3, clko2_sel, ARRAY_SIZE(clko2_sel)); imx7d_clocks_init()
548 clks[IMX7D_ARM_A7_ROOT_CG] = imx_clk_gate("arm_a7_cg", "arm_a7_src", base + 0x8000, 28); imx7d_clocks_init()
549 clks[IMX7D_ARM_M4_ROOT_CG] = imx_clk_gate("arm_m4_cg", "arm_m4_src", base + 0x8080, 28); imx7d_clocks_init()
550 clks[IMX7D_ARM_M0_ROOT_CG] = imx_clk_gate("arm_m0_cg", "arm_m0_src", base + 0x8100, 28); imx7d_clocks_init()
551 clks[IMX7D_MAIN_AXI_ROOT_CG] = imx_clk_gate("axi_cg", "axi_src", base + 0x8800, 28); imx7d_clocks_init()
552 clks[IMX7D_DISP_AXI_ROOT_CG] = imx_clk_gate("disp_axi_cg", "disp_axi_src", base + 0x8880, 28); imx7d_clocks_init()
553 clks[IMX7D_ENET_AXI_ROOT_CG] = imx_clk_gate("enet_axi_cg", "enet_axi_src", base + 0x8900, 28); imx7d_clocks_init()
554 clks[IMX7D_NAND_USDHC_BUS_ROOT_CG] = imx_clk_gate("nand_usdhc_cg", "nand_usdhc_src", base + 0x8980, 28); imx7d_clocks_init()
555 clks[IMX7D_AHB_CHANNEL_ROOT_CG] = imx_clk_gate("ahb_cg", "ahb_src", base + 0x9000, 28); imx7d_clocks_init()
556 clks[IMX7D_DRAM_PHYM_ROOT_CG] = imx_clk_gate("dram_phym_cg", "dram_phym_src", base + 0x9800, 28); imx7d_clocks_init()
557 clks[IMX7D_DRAM_ROOT_CG] = imx_clk_gate("dram_cg", "dram_src", base + 0x9880, 28); imx7d_clocks_init()
558 clks[IMX7D_DRAM_PHYM_ALT_ROOT_CG] = imx_clk_gate("dram_phym_alt_cg", "dram_phym_alt_src", base + 0xa000, 28); imx7d_clocks_init()
559 clks[IMX7D_DRAM_ALT_ROOT_CG] = imx_clk_gate("dram_alt_cg", "dram_alt_src", base + 0xa080, 28); imx7d_clocks_init()
560 clks[IMX7D_USB_HSIC_ROOT_CG] = imx_clk_gate("usb_hsic_cg", "usb_hsic_src", base + 0xa100, 28); imx7d_clocks_init()
561 clks[IMX7D_PCIE_CTRL_ROOT_CG] = imx_clk_gate("pcie_ctrl_cg", "pcie_ctrl_src", base + 0xa180, 28); imx7d_clocks_init()
562 clks[IMX7D_PCIE_PHY_ROOT_CG] = imx_clk_gate("pcie_phy_cg", "pcie_phy_src", base + 0xa200, 28); imx7d_clocks_init()
563 clks[IMX7D_EPDC_PIXEL_ROOT_CG] = imx_clk_gate("epdc_pixel_cg", "epdc_pixel_src", base + 0xa280, 28); imx7d_clocks_init()
564 clks[IMX7D_LCDIF_PIXEL_ROOT_CG] = imx_clk_gate("lcdif_pixel_cg", "lcdif_pixel_src", base + 0xa300, 28); imx7d_clocks_init()
565 clks[IMX7D_MIPI_DSI_ROOT_CG] = imx_clk_gate("mipi_dsi_cg", "mipi_dsi_src", base + 0xa380, 28); imx7d_clocks_init()
566 clks[IMX7D_MIPI_CSI_ROOT_CG] = imx_clk_gate("mipi_csi_cg", "mipi_csi_src", base + 0xa400, 28); imx7d_clocks_init()
567 clks[IMX7D_MIPI_DPHY_ROOT_CG] = imx_clk_gate("mipi_dphy_cg", "mipi_dphy_src", base + 0xa480, 28); imx7d_clocks_init()
568 clks[IMX7D_SAI1_ROOT_CG] = imx_clk_gate("sai1_cg", "sai1_src", base + 0xa500, 28); imx7d_clocks_init()
569 clks[IMX7D_SAI2_ROOT_CG] = imx_clk_gate("sai2_cg", "sai2_src", base + 0xa580, 28); imx7d_clocks_init()
570 clks[IMX7D_SAI3_ROOT_CG] = imx_clk_gate("sai3_cg", "sai3_src", base + 0xa600, 28); imx7d_clocks_init()
571 clks[IMX7D_SPDIF_ROOT_CG] = imx_clk_gate("spdif_cg", "spdif_src", base + 0xa680, 28); imx7d_clocks_init()
572 clks[IMX7D_ENET1_REF_ROOT_CG] = imx_clk_gate("enet1_ref_cg", "enet1_ref_src", base + 0xa700, 28); imx7d_clocks_init()
573 clks[IMX7D_ENET1_TIME_ROOT_CG] = imx_clk_gate("enet1_time_cg", "enet1_time_src", base + 0xa780, 28); imx7d_clocks_init()
574 clks[IMX7D_ENET2_REF_ROOT_CG] = imx_clk_gate("enet2_ref_cg", "enet2_ref_src", base + 0xa800, 28); imx7d_clocks_init()
575 clks[IMX7D_ENET2_TIME_ROOT_CG] = imx_clk_gate("enet2_time_cg", "enet2_time_src", base + 0xa880, 28); imx7d_clocks_init()
576 clks[IMX7D_ENET_PHY_REF_ROOT_CG] = imx_clk_gate("enet_phy_ref_cg", "enet_phy_ref_src", base + 0xa900, 28); imx7d_clocks_init()
577 clks[IMX7D_EIM_ROOT_CG] = imx_clk_gate("eim_cg", "eim_src", base + 0xa980, 28); imx7d_clocks_init()
578 clks[IMX7D_NAND_ROOT_CG] = imx_clk_gate("nand_cg", "nand_src", base + 0xaa00, 28); imx7d_clocks_init()
579 clks[IMX7D_QSPI_ROOT_CG] = imx_clk_gate("qspi_cg", "qspi_src", base + 0xaa80, 28); imx7d_clocks_init()
580 clks[IMX7D_USDHC1_ROOT_CG] = imx_clk_gate("usdhc1_cg", "usdhc1_src", base + 0xab00, 28); imx7d_clocks_init()
581 clks[IMX7D_USDHC2_ROOT_CG] = imx_clk_gate("usdhc2_cg", "usdhc2_src", base + 0xab80, 28); imx7d_clocks_init()
582 clks[IMX7D_USDHC3_ROOT_CG] = imx_clk_gate("usdhc3_cg", "usdhc3_src", base + 0xac00, 28); imx7d_clocks_init()
583 clks[IMX7D_CAN1_ROOT_CG] = imx_clk_gate("can1_cg", "can1_src", base + 0xac80, 28); imx7d_clocks_init()
584 clks[IMX7D_CAN2_ROOT_CG] = imx_clk_gate("can2_cg", "can2_src", base + 0xad00, 28); imx7d_clocks_init()
585 clks[IMX7D_I2C1_ROOT_CG] = imx_clk_gate("i2c1_cg", "i2c1_src", base + 0xad80, 28); imx7d_clocks_init()
586 clks[IMX7D_I2C2_ROOT_CG] = imx_clk_gate("i2c2_cg", "i2c2_src", base + 0xae00, 28); imx7d_clocks_init()
587 clks[IMX7D_I2C3_ROOT_CG] = imx_clk_gate("i2c3_cg", "i2c3_src", base + 0xae80, 28); imx7d_clocks_init()
588 clks[IMX7D_I2C4_ROOT_CG] = imx_clk_gate("i2c4_cg", "i2c4_src", base + 0xaf00, 28); imx7d_clocks_init()
589 clks[IMX7D_UART1_ROOT_CG] = imx_clk_gate("uart1_cg", "uart1_src", base + 0xaf80, 28); imx7d_clocks_init()
590 clks[IMX7D_UART2_ROOT_CG] = imx_clk_gate("uart2_cg", "uart2_src", base + 0xb000, 28); imx7d_clocks_init()
591 clks[IMX7D_UART3_ROOT_CG] = imx_clk_gate("uart3_cg", "uart3_src", base + 0xb080, 28); imx7d_clocks_init()
592 clks[IMX7D_UART4_ROOT_CG] = imx_clk_gate("uart4_cg", "uart4_src", base + 0xb100, 28); imx7d_clocks_init()
593 clks[IMX7D_UART5_ROOT_CG] = imx_clk_gate("uart5_cg", "uart5_src", base + 0xb180, 28); imx7d_clocks_init()
594 clks[IMX7D_UART6_ROOT_CG] = imx_clk_gate("uart6_cg", "uart6_src", base + 0xb200, 28); imx7d_clocks_init()
595 clks[IMX7D_UART7_ROOT_CG] = imx_clk_gate("uart7_cg", "uart7_src", base + 0xb280, 28); imx7d_clocks_init()
596 clks[IMX7D_ECSPI1_ROOT_CG] = imx_clk_gate("ecspi1_cg", "ecspi1_src", base + 0xb300, 28); imx7d_clocks_init()
597 clks[IMX7D_ECSPI2_ROOT_CG] = imx_clk_gate("ecspi2_cg", "ecspi2_src", base + 0xb380, 28); imx7d_clocks_init()
598 clks[IMX7D_ECSPI3_ROOT_CG] = imx_clk_gate("ecspi3_cg", "ecspi3_src", base + 0xb400, 28); imx7d_clocks_init()
599 clks[IMX7D_ECSPI4_ROOT_CG] = imx_clk_gate("ecspi4_cg", "ecspi4_src", base + 0xb480, 28); imx7d_clocks_init()
600 clks[IMX7D_PWM1_ROOT_CG] = imx_clk_gate("pwm1_cg", "pwm1_src", base + 0xb500, 28); imx7d_clocks_init()
601 clks[IMX7D_PWM2_ROOT_CG] = imx_clk_gate("pwm2_cg", "pwm2_src", base + 0xb580, 28); imx7d_clocks_init()
602 clks[IMX7D_PWM3_ROOT_CG] = imx_clk_gate("pwm3_cg", "pwm3_src", base + 0xb600, 28); imx7d_clocks_init()
603 clks[IMX7D_PWM4_ROOT_CG] = imx_clk_gate("pwm4_cg", "pwm4_src", base + 0xb680, 28); imx7d_clocks_init()
604 clks[IMX7D_FLEXTIMER1_ROOT_CG] = imx_clk_gate("flextimer1_cg", "flextimer1_src", base + 0xb700, 28); imx7d_clocks_init()
605 clks[IMX7D_FLEXTIMER2_ROOT_CG] = imx_clk_gate("flextimer2_cg", "flextimer2_src", base + 0xb780, 28); imx7d_clocks_init()
606 clks[IMX7D_SIM1_ROOT_CG] = imx_clk_gate("sim1_cg", "sim1_src", base + 0xb800, 28); imx7d_clocks_init()
607 clks[IMX7D_SIM2_ROOT_CG] = imx_clk_gate("sim2_cg", "sim2_src", base + 0xb880, 28); imx7d_clocks_init()
608 clks[IMX7D_GPT1_ROOT_CG] = imx_clk_gate("gpt1_cg", "gpt1_src", base + 0xb900, 28); imx7d_clocks_init()
609 clks[IMX7D_GPT2_ROOT_CG] = imx_clk_gate("gpt2_cg", "gpt2_src", base + 0xb980, 28); imx7d_clocks_init()
610 clks[IMX7D_GPT3_ROOT_CG] = imx_clk_gate("gpt3_cg", "gpt3_src", base + 0xbA00, 28); imx7d_clocks_init()
611 clks[IMX7D_GPT4_ROOT_CG] = imx_clk_gate("gpt4_cg", "gpt4_src", base + 0xbA80, 28); imx7d_clocks_init()
612 clks[IMX7D_TRACE_ROOT_CG] = imx_clk_gate("trace_cg", "trace_src", base + 0xbb00, 28); imx7d_clocks_init()
613 clks[IMX7D_WDOG_ROOT_CG] = imx_clk_gate("wdog_cg", "wdog_src", base + 0xbb80, 28); imx7d_clocks_init()
614 clks[IMX7D_CSI_MCLK_ROOT_CG] = imx_clk_gate("csi_mclk_cg", "csi_mclk_src", base + 0xbc00, 28); imx7d_clocks_init()
615 clks[IMX7D_AUDIO_MCLK_ROOT_CG] = imx_clk_gate("audio_mclk_cg", "audio_mclk_src", base + 0xbc80, 28); imx7d_clocks_init()
616 clks[IMX7D_WRCLK_ROOT_CG] = imx_clk_gate("wrclk_cg", "wrclk_src", base + 0xbd00, 28); imx7d_clocks_init()
617 clks[IMX7D_CLKO1_ROOT_CG] = imx_clk_gate("clko1_cg", "clko1_src", base + 0xbd80, 28); imx7d_clocks_init()
618 clks[IMX7D_CLKO2_ROOT_CG] = imx_clk_gate("clko2_cg", "clko2_src", base + 0xbe00, 28); imx7d_clocks_init()
620 clks[IMX7D_MAIN_AXI_ROOT_PRE_DIV] = imx_clk_divider("axi_pre_div", "axi_cg", base + 0x8800, 16, 3); imx7d_clocks_init()
621 clks[IMX7D_DISP_AXI_ROOT_PRE_DIV] = imx_clk_divider("disp_axi_pre_div", "disp_axi_cg", base + 0x8880, 16, 3); imx7d_clocks_init()
622 clks[IMX7D_ENET_AXI_ROOT_PRE_DIV] = imx_clk_divider("enet_axi_pre_div", "enet_axi_cg", base + 0x8900, 16, 3); imx7d_clocks_init()
623 clks[IMX7D_NAND_USDHC_BUS_ROOT_PRE_DIV] = imx_clk_divider("nand_usdhc_pre_div", "nand_usdhc_cg", base + 0x8980, 16, 3); imx7d_clocks_init()
624 clks[IMX7D_AHB_CHANNEL_ROOT_PRE_DIV] = imx_clk_divider("ahb_pre_div", "ahb_cg", base + 0x9000, 16, 3); imx7d_clocks_init()
625 clks[IMX7D_DRAM_PHYM_ALT_ROOT_PRE_DIV] = imx_clk_divider("dram_phym_alt_pre_div", "dram_phym_alt_cg", base + 0xa000, 16, 3); imx7d_clocks_init()
626 clks[IMX7D_DRAM_ALT_ROOT_PRE_DIV] = imx_clk_divider("dram_alt_pre_div", "dram_alt_cg", base + 0xa080, 16, 3); imx7d_clocks_init()
627 clks[IMX7D_USB_HSIC_ROOT_PRE_DIV] = imx_clk_divider("usb_hsic_pre_div", "usb_hsic_cg", base + 0xa100, 16, 3); imx7d_clocks_init()
628 clks[IMX7D_PCIE_CTRL_ROOT_PRE_DIV] = imx_clk_divider("pcie_ctrl_pre_div", "pcie_ctrl_cg", base + 0xa180, 16, 3); imx7d_clocks_init()
629 clks[IMX7D_PCIE_PHY_ROOT_PRE_DIV] = imx_clk_divider("pcie_phy_pre_div", "pcie_phy_cg", base + 0xa200, 16, 3); imx7d_clocks_init()
630 clks[IMX7D_EPDC_PIXEL_ROOT_PRE_DIV] = imx_clk_divider("epdc_pixel_pre_div", "epdc_pixel_cg", base + 0xa280, 16, 3); imx7d_clocks_init()
631 clks[IMX7D_LCDIF_PIXEL_ROOT_PRE_DIV] = imx_clk_divider("lcdif_pixel_pre_div", "lcdif_pixel_cg", base + 0xa300, 16, 3); imx7d_clocks_init()
632 clks[IMX7D_MIPI_DSI_ROOT_PRE_DIV] = imx_clk_divider("mipi_dsi_pre_div", "mipi_dsi_cg", base + 0xa380, 16, 3); imx7d_clocks_init()
633 clks[IMX7D_MIPI_CSI_ROOT_PRE_DIV] = imx_clk_divider("mipi_csi_pre_div", "mipi_csi_cg", base + 0xa400, 16, 3); imx7d_clocks_init()
634 clks[IMX7D_MIPI_DPHY_ROOT_PRE_DIV] = imx_clk_divider("mipi_dphy_pre_div", "mipi_dphy_cg", base + 0xa480, 16, 3); imx7d_clocks_init()
635 clks[IMX7D_SAI1_ROOT_PRE_DIV] = imx_clk_divider("sai1_pre_div", "sai1_cg", base + 0xa500, 16, 3); imx7d_clocks_init()
636 clks[IMX7D_SAI2_ROOT_PRE_DIV] = imx_clk_divider("sai2_pre_div", "sai2_cg", base + 0xa580, 16, 3); imx7d_clocks_init()
637 clks[IMX7D_SAI3_ROOT_PRE_DIV] = imx_clk_divider("sai3_pre_div", "sai3_cg", base + 0xa600, 16, 3); imx7d_clocks_init()
638 clks[IMX7D_SPDIF_ROOT_PRE_DIV] = imx_clk_divider("spdif_pre_div", "spdif_cg", base + 0xa680, 16, 3); imx7d_clocks_init()
639 clks[IMX7D_ENET1_REF_ROOT_PRE_DIV] = imx_clk_divider("enet1_ref_pre_div", "enet1_ref_cg", base + 0xa700, 16, 3); imx7d_clocks_init()
640 clks[IMX7D_ENET1_TIME_ROOT_PRE_DIV] = imx_clk_divider("enet1_time_pre_div", "enet1_time_cg", base + 0xa780, 16, 3); imx7d_clocks_init()
641 clks[IMX7D_ENET2_REF_ROOT_PRE_DIV] = imx_clk_divider("enet2_ref_pre_div", "enet2_ref_cg", base + 0xa800, 16, 3); imx7d_clocks_init()
642 clks[IMX7D_ENET2_TIME_ROOT_PRE_DIV] = imx_clk_divider("enet2_time_pre_div", "enet2_time_cg", base + 0xa880, 16, 3); imx7d_clocks_init()
643 clks[IMX7D_ENET_PHY_REF_ROOT_PRE_DIV] = imx_clk_divider("enet_phy_ref_pre_div", "enet_phy_ref_cg", base + 0xa900, 16, 3); imx7d_clocks_init()
644 clks[IMX7D_EIM_ROOT_PRE_DIV] = imx_clk_divider("eim_pre_div", "eim_cg", base + 0xa980, 16, 3); imx7d_clocks_init()
645 clks[IMX7D_NAND_ROOT_PRE_DIV] = imx_clk_divider("nand_pre_div", "nand_cg", base + 0xaa00, 16, 3); imx7d_clocks_init()
646 clks[IMX7D_QSPI_ROOT_PRE_DIV] = imx_clk_divider("qspi_pre_div", "qspi_cg", base + 0xaa80, 16, 3); imx7d_clocks_init()
647 clks[IMX7D_USDHC1_ROOT_PRE_DIV] = imx_clk_divider("usdhc1_pre_div", "usdhc1_cg", base + 0xab00, 16, 3); imx7d_clocks_init()
648 clks[IMX7D_USDHC2_ROOT_PRE_DIV] = imx_clk_divider("usdhc2_pre_div", "usdhc2_cg", base + 0xab80, 16, 3); imx7d_clocks_init()
649 clks[IMX7D_USDHC3_ROOT_PRE_DIV] = imx_clk_divider("usdhc3_pre_div", "usdhc3_cg", base + 0xac00, 16, 3); imx7d_clocks_init()
650 clks[IMX7D_CAN1_ROOT_PRE_DIV] = imx_clk_divider("can1_pre_div", "can1_cg", base + 0xac80, 16, 3); imx7d_clocks_init()
651 clks[IMX7D_CAN2_ROOT_PRE_DIV] = imx_clk_divider("can2_pre_div", "can2_cg", base + 0xad00, 16, 3); imx7d_clocks_init()
652 clks[IMX7D_I2C1_ROOT_PRE_DIV] = imx_clk_divider("i2c1_pre_div", "i2c1_cg", base + 0xad80, 16, 3); imx7d_clocks_init()
653 clks[IMX7D_I2C2_ROOT_PRE_DIV] = imx_clk_divider("i2c2_pre_div", "i2c2_cg", base + 0xae00, 16, 3); imx7d_clocks_init()
654 clks[IMX7D_I2C3_ROOT_PRE_DIV] = imx_clk_divider("i2c3_pre_div", "i2c3_cg", base + 0xae80, 16, 3); imx7d_clocks_init()
655 clks[IMX7D_I2C4_ROOT_PRE_DIV] = imx_clk_divider("i2c4_pre_div", "i2c4_cg", base + 0xaf00, 16, 3); imx7d_clocks_init()
656 clks[IMX7D_UART1_ROOT_PRE_DIV] = imx_clk_divider("uart1_pre_div", "uart1_cg", base + 0xaf80, 16, 3); imx7d_clocks_init()
657 clks[IMX7D_UART2_ROOT_PRE_DIV] = imx_clk_divider("uart2_pre_div", "uart2_cg", base + 0xb000, 16, 3); imx7d_clocks_init()
658 clks[IMX7D_UART3_ROOT_PRE_DIV] = imx_clk_divider("uart3_pre_div", "uart3_cg", base + 0xb080, 16, 3); imx7d_clocks_init()
659 clks[IMX7D_UART4_ROOT_PRE_DIV] = imx_clk_divider("uart4_pre_div", "uart4_cg", base + 0xb100, 16, 3); imx7d_clocks_init()
660 clks[IMX7D_UART5_ROOT_PRE_DIV] = imx_clk_divider("uart5_pre_div", "uart5_cg", base + 0xb180, 16, 3); imx7d_clocks_init()
661 clks[IMX7D_UART6_ROOT_PRE_DIV] = imx_clk_divider("uart6_pre_div", "uart6_cg", base + 0xb200, 16, 3); imx7d_clocks_init()
662 clks[IMX7D_UART7_ROOT_PRE_DIV] = imx_clk_divider("uart7_pre_div", "uart7_cg", base + 0xb280, 16, 3); imx7d_clocks_init()
663 clks[IMX7D_ECSPI1_ROOT_PRE_DIV] = imx_clk_divider("ecspi1_pre_div", "ecspi1_cg", base + 0xb300, 16, 3); imx7d_clocks_init()
664 clks[IMX7D_ECSPI2_ROOT_PRE_DIV] = imx_clk_divider("ecspi2_pre_div", "ecspi2_cg", base + 0xb380, 16, 3); imx7d_clocks_init()
665 clks[IMX7D_ECSPI3_ROOT_PRE_DIV] = imx_clk_divider("ecspi3_pre_div", "ecspi3_cg", base + 0xb400, 16, 3); imx7d_clocks_init()
666 clks[IMX7D_ECSPI4_ROOT_PRE_DIV] = imx_clk_divider("ecspi4_pre_div", "ecspi4_cg", base + 0xb480, 16, 3); imx7d_clocks_init()
667 clks[IMX7D_PWM1_ROOT_PRE_DIV] = imx_clk_divider("pwm1_pre_div", "pwm1_cg", base + 0xb500, 16, 3); imx7d_clocks_init()
668 clks[IMX7D_PWM2_ROOT_PRE_DIV] = imx_clk_divider("pwm2_pre_div", "pwm2_cg", base + 0xb580, 16, 3); imx7d_clocks_init()
669 clks[IMX7D_PWM3_ROOT_PRE_DIV] = imx_clk_divider("pwm3_pre_div", "pwm3_cg", base + 0xb600, 16, 3); imx7d_clocks_init()
670 clks[IMX7D_PWM4_ROOT_PRE_DIV] = imx_clk_divider("pwm4_pre_div", "pwm4_cg", base + 0xb680, 16, 3); imx7d_clocks_init()
671 clks[IMX7D_FLEXTIMER1_ROOT_PRE_DIV] = imx_clk_divider("flextimer1_pre_div", "flextimer1_cg", base + 0xb700, 16, 3); imx7d_clocks_init()
672 clks[IMX7D_FLEXTIMER2_ROOT_PRE_DIV] = imx_clk_divider("flextimer2_pre_div", "flextimer2_cg", base + 0xb780, 16, 3); imx7d_clocks_init()
673 clks[IMX7D_SIM1_ROOT_PRE_DIV] = imx_clk_divider("sim1_pre_div", "sim1_cg", base + 0xb800, 16, 3); imx7d_clocks_init()
674 clks[IMX7D_SIM2_ROOT_PRE_DIV] = imx_clk_divider("sim2_pre_div", "sim2_cg", base + 0xb880, 16, 3); imx7d_clocks_init()
675 clks[IMX7D_GPT1_ROOT_PRE_DIV] = imx_clk_divider("gpt1_pre_div", "gpt1_cg", base + 0xb900, 16, 3); imx7d_clocks_init()
676 clks[IMX7D_GPT2_ROOT_PRE_DIV] = imx_clk_divider("gpt2_pre_div", "gpt2_cg", base + 0xb980, 16, 3); imx7d_clocks_init()
677 clks[IMX7D_GPT3_ROOT_PRE_DIV] = imx_clk_divider("gpt3_pre_div", "gpt3_cg", base + 0xba00, 16, 3); imx7d_clocks_init()
678 clks[IMX7D_GPT4_ROOT_PRE_DIV] = imx_clk_divider("gpt4_pre_div", "gpt4_cg", base + 0xba80, 16, 3); imx7d_clocks_init()
679 clks[IMX7D_TRACE_ROOT_PRE_DIV] = imx_clk_divider("trace_pre_div", "trace_cg", base + 0xbb00, 16, 3); imx7d_clocks_init()
680 clks[IMX7D_WDOG_ROOT_PRE_DIV] = imx_clk_divider("wdog_pre_div", "wdog_cg", base + 0xbb80, 16, 3); imx7d_clocks_init()
681 clks[IMX7D_CSI_MCLK_ROOT_PRE_DIV] = imx_clk_divider("csi_mclk_pre_div", "csi_mclk_cg", base + 0xbc00, 16, 3); imx7d_clocks_init()
682 clks[IMX7D_AUDIO_MCLK_ROOT_PRE_DIV] = imx_clk_divider("audio_mclk_pre_div", "audio_mclk_cg", base + 0xbc80, 16, 3); imx7d_clocks_init()
683 clks[IMX7D_WRCLK_ROOT_PRE_DIV] = imx_clk_divider("wrclk_pre_div", "wrclk_cg", base + 0xbd00, 16, 3); imx7d_clocks_init()
684 clks[IMX7D_CLKO1_ROOT_PRE_DIV] = imx_clk_divider("clko1_pre_div", "clko1_cg", base + 0xbd80, 16, 3); imx7d_clocks_init()
685 clks[IMX7D_CLKO2_ROOT_PRE_DIV] = imx_clk_divider("clko2_pre_div", "clko2_cg", base + 0xbe00, 16, 3); imx7d_clocks_init()
687 clks[IMX7D_ARM_A7_ROOT_DIV] = imx_clk_divider("arm_a7_div", "arm_a7_cg", base + 0x8000, 0, 3); imx7d_clocks_init()
688 clks[IMX7D_ARM_M4_ROOT_DIV] = imx_clk_divider("arm_m4_div", "arm_m4_cg", base + 0x8080, 0, 3); imx7d_clocks_init()
689 clks[IMX7D_ARM_M0_ROOT_DIV] = imx_clk_divider("arm_m0_div", "arm_m0_cg", base + 0x8100, 0, 3); imx7d_clocks_init()
690 clks[IMX7D_MAIN_AXI_ROOT_DIV] = imx_clk_divider("axi_post_div", "axi_pre_div", base + 0x8800, 0, 6); imx7d_clocks_init()
691 clks[IMX7D_DISP_AXI_ROOT_DIV] = imx_clk_divider("disp_axi_post_div", "disp_axi_pre_div", base + 0x8880, 0, 6); imx7d_clocks_init()
692 clks[IMX7D_ENET_AXI_ROOT_DIV] = imx_clk_divider("enet_axi_post_div", "enet_axi_pre_div", base + 0x8900, 0, 6); imx7d_clocks_init()
693 clks[IMX7D_NAND_USDHC_BUS_ROOT_DIV] = imx_clk_divider("nand_usdhc_post_div", "nand_usdhc_pre_div", base + 0x8980, 0, 6); imx7d_clocks_init()
694 clks[IMX7D_AHB_CHANNEL_ROOT_DIV] = imx_clk_divider("ahb_post_div", "ahb_pre_div", base + 0x9000, 0, 6); imx7d_clocks_init()
695 clks[IMX7D_DRAM_ROOT_DIV] = imx_clk_divider("dram_post_div", "dram_cg", base + 0x9880, 0, 3); imx7d_clocks_init()
696 clks[IMX7D_DRAM_PHYM_ALT_ROOT_DIV] = imx_clk_divider("dram_phym_alt_post_div", "dram_phym_alt_pre_div", base + 0xa000, 0, 3); imx7d_clocks_init()
697 clks[IMX7D_DRAM_ALT_ROOT_DIV] = imx_clk_divider("dram_alt_post_div", "dram_alt_pre_div", base + 0xa080, 0, 3); imx7d_clocks_init()
698 clks[IMX7D_USB_HSIC_ROOT_DIV] = imx_clk_divider("usb_hsic_post_div", "usb_hsic_pre_div", base + 0xa100, 0, 6); imx7d_clocks_init()
699 clks[IMX7D_PCIE_CTRL_ROOT_DIV] = imx_clk_divider("pcie_ctrl_post_div", "pcie_ctrl_pre_div", base + 0xa180, 0, 6); imx7d_clocks_init()
700 clks[IMX7D_PCIE_PHY_ROOT_DIV] = imx_clk_divider("pcie_phy_post_div", "pcie_phy_pre_div", base + 0xa200, 0, 6); imx7d_clocks_init()
701 clks[IMX7D_EPDC_PIXEL_ROOT_DIV] = imx_clk_divider("epdc_pixel_post_div", "epdc_pixel_pre_div", base + 0xa280, 0, 6); imx7d_clocks_init()
702 clks[IMX7D_LCDIF_PIXEL_ROOT_DIV] = imx_clk_divider("lcdif_pixel_post_div", "lcdif_pixel_pre_div", base + 0xa300, 0, 6); imx7d_clocks_init()
703 clks[IMX7D_MIPI_DSI_ROOT_DIV] = imx_clk_divider("mipi_dsi_post_div", "mipi_dsi_pre_div", base + 0xa380, 0, 6); imx7d_clocks_init()
704 clks[IMX7D_MIPI_CSI_ROOT_DIV] = imx_clk_divider("mipi_csi_post_div", "mipi_csi_pre_div", base + 0xa400, 0, 6); imx7d_clocks_init()
705 clks[IMX7D_MIPI_DPHY_ROOT_DIV] = imx_clk_divider("mipi_dphy_post_div", "mipi_csi_dphy_div", base + 0xa480, 0, 6); imx7d_clocks_init()
706 clks[IMX7D_SAI1_ROOT_DIV] = imx_clk_divider("sai1_post_div", "sai1_pre_div", base + 0xa500, 0, 6); imx7d_clocks_init()
707 clks[IMX7D_SAI2_ROOT_DIV] = imx_clk_divider("sai2_post_div", "sai2_pre_div", base + 0xa580, 0, 6); imx7d_clocks_init()
708 clks[IMX7D_SAI3_ROOT_DIV] = imx_clk_divider("sai3_post_div", "sai3_pre_div", base + 0xa600, 0, 6); imx7d_clocks_init()
709 clks[IMX7D_SPDIF_ROOT_DIV] = imx_clk_divider("spdif_post_div", "spdif_pre_div", base + 0xa680, 0, 6); imx7d_clocks_init()
710 clks[IMX7D_ENET1_REF_ROOT_DIV] = imx_clk_divider("enet1_ref_post_div", "enet1_ref_pre_div", base + 0xa700, 0, 6); imx7d_clocks_init()
711 clks[IMX7D_ENET1_TIME_ROOT_DIV] = imx_clk_divider("enet1_time_post_div", "enet1_time_pre_div", base + 0xa780, 0, 6); imx7d_clocks_init()
712 clks[IMX7D_ENET2_REF_ROOT_DIV] = imx_clk_divider("enet2_ref_post_div", "enet2_ref_pre_div", base + 0xa800, 0, 6); imx7d_clocks_init()
713 clks[IMX7D_ENET2_TIME_ROOT_DIV] = imx_clk_divider("enet2_time_post_div", "enet2_time_pre_div", base + 0xa880, 0, 6); imx7d_clocks_init()
714 clks[IMX7D_ENET_PHY_REF_ROOT_DIV] = imx_clk_divider("enet_phy_ref_post_div", "enet_phy_ref_pre_div", base + 0xa900, 0, 6); imx7d_clocks_init()
715 clks[IMX7D_EIM_ROOT_DIV] = imx_clk_divider("eim_post_div", "eim_pre_div", base + 0xa980, 0, 6); imx7d_clocks_init()
716 clks[IMX7D_NAND_ROOT_DIV] = imx_clk_divider("nand_post_div", "nand_pre_div", base + 0xaa00, 0, 6); imx7d_clocks_init()
717 clks[IMX7D_QSPI_ROOT_DIV] = imx_clk_divider("qspi_post_div", "qspi_pre_div", base + 0xaa80, 0, 6); imx7d_clocks_init()
718 clks[IMX7D_USDHC1_ROOT_DIV] = imx_clk_divider("usdhc1_post_div", "usdhc1_pre_div", base + 0xab00, 0, 6); imx7d_clocks_init()
719 clks[IMX7D_USDHC2_ROOT_DIV] = imx_clk_divider("usdhc2_post_div", "usdhc2_pre_div", base + 0xab80, 0, 6); imx7d_clocks_init()
720 clks[IMX7D_USDHC3_ROOT_DIV] = imx_clk_divider("usdhc3_post_div", "usdhc3_pre_div", base + 0xac00, 0, 6); imx7d_clocks_init()
721 clks[IMX7D_CAN1_ROOT_DIV] = imx_clk_divider("can1_post_div", "can1_pre_div", base + 0xac80, 0, 6); imx7d_clocks_init()
722 clks[IMX7D_CAN2_ROOT_DIV] = imx_clk_divider("can2_post_div", "can2_pre_div", base + 0xad00, 0, 6); imx7d_clocks_init()
723 clks[IMX7D_I2C1_ROOT_DIV] = imx_clk_divider("i2c1_post_div", "i2c1_pre_div", base + 0xad80, 0, 6); imx7d_clocks_init()
724 clks[IMX7D_I2C2_ROOT_DIV] = imx_clk_divider("i2c2_post_div", "i2c2_pre_div", base + 0xae00, 0, 6); imx7d_clocks_init()
725 clks[IMX7D_I2C3_ROOT_DIV] = imx_clk_divider("i2c3_post_div", "i2c3_pre_div", base + 0xae80, 0, 6); imx7d_clocks_init()
726 clks[IMX7D_I2C4_ROOT_DIV] = imx_clk_divider("i2c4_post_div", "i2c4_pre_div", base + 0xaf00, 0, 6); imx7d_clocks_init()
727 clks[IMX7D_UART1_ROOT_DIV] = imx_clk_divider("uart1_post_div", "uart1_pre_div", base + 0xaf80, 0, 6); imx7d_clocks_init()
728 clks[IMX7D_UART2_ROOT_DIV] = imx_clk_divider("uart2_post_div", "uart2_pre_div", base + 0xb000, 0, 6); imx7d_clocks_init()
729 clks[IMX7D_UART3_ROOT_DIV] = imx_clk_divider("uart3_post_div", "uart3_pre_div", base + 0xb080, 0, 6); imx7d_clocks_init()
730 clks[IMX7D_UART4_ROOT_DIV] = imx_clk_divider("uart4_post_div", "uart4_pre_div", base + 0xb100, 0, 6); imx7d_clocks_init()
731 clks[IMX7D_UART5_ROOT_DIV] = imx_clk_divider("uart5_post_div", "uart5_pre_div", base + 0xb180, 0, 6); imx7d_clocks_init()
732 clks[IMX7D_UART6_ROOT_DIV] = imx_clk_divider("uart6_post_div", "uart6_pre_div", base + 0xb200, 0, 6); imx7d_clocks_init()
733 clks[IMX7D_UART7_ROOT_DIV] = imx_clk_divider("uart7_post_div", "uart7_pre_div", base + 0xb280, 0, 6); imx7d_clocks_init()
734 clks[IMX7D_ECSPI1_ROOT_DIV] = imx_clk_divider("ecspi1_post_div", "ecspi1_pre_div", base + 0xb300, 0, 6); imx7d_clocks_init()
735 clks[IMX7D_ECSPI2_ROOT_DIV] = imx_clk_divider("ecspi2_post_div", "ecspi2_pre_div", base + 0xb380, 0, 6); imx7d_clocks_init()
736 clks[IMX7D_ECSPI3_ROOT_DIV] = imx_clk_divider("ecspi3_post_div", "ecspi3_pre_div", base + 0xb400, 0, 6); imx7d_clocks_init()
737 clks[IMX7D_ECSPI4_ROOT_DIV] = imx_clk_divider("ecspi4_post_div", "ecspi4_pre_div", base + 0xb480, 0, 6); imx7d_clocks_init()
738 clks[IMX7D_PWM1_ROOT_DIV] = imx_clk_divider("pwm1_post_div", "pwm1_pre_div", base + 0xb500, 0, 6); imx7d_clocks_init()
739 clks[IMX7D_PWM2_ROOT_DIV] = imx_clk_divider("pwm2_post_div", "pwm2_pre_div", base + 0xb580, 0, 6); imx7d_clocks_init()
740 clks[IMX7D_PWM3_ROOT_DIV] = imx_clk_divider("pwm3_post_div", "pwm3_pre_div", base + 0xb600, 0, 6); imx7d_clocks_init()
741 clks[IMX7D_PWM4_ROOT_DIV] = imx_clk_divider("pwm4_post_div", "pwm4_pre_div", base + 0xb680, 0, 6); imx7d_clocks_init()
742 clks[IMX7D_FLEXTIMER1_ROOT_DIV] = imx_clk_divider("flextimer1_post_div", "flextimer1_pre_div", base + 0xb700, 0, 6); imx7d_clocks_init()
743 clks[IMX7D_FLEXTIMER2_ROOT_DIV] = imx_clk_divider("flextimer2_post_div", "flextimer2_pre_div", base + 0xb780, 0, 6); imx7d_clocks_init()
744 clks[IMX7D_SIM1_ROOT_DIV] = imx_clk_divider("sim1_post_div", "sim1_pre_div", base + 0xb800, 0, 6); imx7d_clocks_init()
745 clks[IMX7D_SIM2_ROOT_DIV] = imx_clk_divider("sim2_post_div", "sim2_pre_div", base + 0xb880, 0, 6); imx7d_clocks_init()
746 clks[IMX7D_GPT1_ROOT_DIV] = imx_clk_divider("gpt1_post_div", "gpt1_pre_div", base + 0xb900, 0, 6); imx7d_clocks_init()
747 clks[IMX7D_GPT2_ROOT_DIV] = imx_clk_divider("gpt2_post_div", "gpt2_pre_div", base + 0xb980, 0, 6); imx7d_clocks_init()
748 clks[IMX7D_GPT3_ROOT_DIV] = imx_clk_divider("gpt3_post_div", "gpt3_pre_div", base + 0xba00, 0, 6); imx7d_clocks_init()
749 clks[IMX7D_GPT4_ROOT_DIV] = imx_clk_divider("gpt4_post_div", "gpt4_pre_div", base + 0xba80, 0, 6); imx7d_clocks_init()
750 clks[IMX7D_TRACE_ROOT_DIV] = imx_clk_divider("trace_post_div", "trace_pre_div", base + 0xbb00, 0, 6); imx7d_clocks_init()
751 clks[IMX7D_WDOG_ROOT_DIV] = imx_clk_divider("wdog_post_div", "wdog_pre_div", base + 0xbb80, 0, 6); imx7d_clocks_init()
752 clks[IMX7D_CSI_MCLK_ROOT_DIV] = imx_clk_divider("csi_mclk_post_div", "csi_mclk_pre_div", base + 0xbc00, 0, 6); imx7d_clocks_init()
753 clks[IMX7D_AUDIO_MCLK_ROOT_DIV] = imx_clk_divider("audio_mclk_post_div", "audio_mclk_pre_div", base + 0xbc80, 0, 6); imx7d_clocks_init()
754 clks[IMX7D_WRCLK_ROOT_DIV] = imx_clk_divider("wrclk_post_div", "wrclk_pre_div", base + 0xbd00, 0, 6); imx7d_clocks_init()
755 clks[IMX7D_CLKO1_ROOT_DIV] = imx_clk_divider("clko1_post_div", "clko1_pre_div", base + 0xbd80, 0, 6); imx7d_clocks_init()
756 clks[IMX7D_CLKO2_ROOT_DIV] = imx_clk_divider("clko2_post_div", "clko2_pre_div", base + 0xbe00, 0, 6); imx7d_clocks_init()
758 clks[IMX7D_ARM_A7_ROOT_CLK] = imx_clk_gate2("arm_a7_root_clk", "arm_a7_div", base + 0x4000, 0); imx7d_clocks_init()
759 clks[IMX7D_ARM_M4_ROOT_CLK] = imx_clk_gate2("arm_m4_root_clk", "arm_m4_div", base + 0x4010, 0); imx7d_clocks_init()
760 clks[IMX7D_ARM_M0_ROOT_CLK] = imx_clk_gate2("arm_m0_root_clk", "arm_m0_div", base + 0x4020, 0); imx7d_clocks_init()
761 clks[IMX7D_MAIN_AXI_ROOT_CLK] = imx_clk_gate2("main_axi_root_clk", "axi_post_div", base + 0x4040, 0); imx7d_clocks_init()
762 clks[IMX7D_DISP_AXI_ROOT_CLK] = imx_clk_gate2("disp_axi_root_clk", "disp_axi_post_div", base + 0x4050, 0); imx7d_clocks_init()
763 clks[IMX7D_ENET_AXI_ROOT_CLK] = imx_clk_gate2("enet_axi_root_clk", "enet_axi_post_div", base + 0x4060, 0); imx7d_clocks_init()
764 clks[IMX7D_OCRAM_CLK] = imx_clk_gate2("ocram_clk", "axi_post_div", base + 0x4110, 0); imx7d_clocks_init()
765 clks[IMX7D_OCRAM_S_CLK] = imx_clk_gate2("ocram_s_clk", "ahb_post_div", base + 0x4120, 0); imx7d_clocks_init()
766 clks[IMX7D_NAND_USDHC_BUS_ROOT_CLK] = imx_clk_gate2("nand_usdhc_root_clk", "nand_usdhc_post_div", base + 0x4130, 0); imx7d_clocks_init()
767 clks[IMX7D_AHB_CHANNEL_ROOT_CLK] = imx_clk_gate2("ahb_root_clk", "ahb_post_div", base + 0x4200, 0); imx7d_clocks_init()
768 clks[IMX7D_DRAM_ROOT_CLK] = imx_clk_gate2("dram_root_clk", "dram_post_div", base + 0x4130, 0); imx7d_clocks_init()
769 clks[IMX7D_DRAM_PHYM_ROOT_CLK] = imx_clk_gate2("dram_phym_root_clk", "dram_phym_cg", base + 0x4130, 0); imx7d_clocks_init()
770 clks[IMX7D_DRAM_PHYM_ALT_ROOT_CLK] = imx_clk_gate2("dram_phym_alt_root_clk", "dram_phym_alt_post_div", base + 0x4130, 0); imx7d_clocks_init()
771 clks[IMX7D_DRAM_ALT_ROOT_CLK] = imx_clk_gate2("dram_alt_root_clk", "dram_alt_post_div", base + 0x4130, 0); imx7d_clocks_init()
772 clks[IMX7D_USB_HSIC_ROOT_CLK] = imx_clk_gate2("usb_hsic_root_clk", "usb_hsic_post_div", base + 0x4420, 0); imx7d_clocks_init()
773 clks[IMX7D_PCIE_CTRL_ROOT_CLK] = imx_clk_gate2("pcie_ctrl_root_clk", "pcie_ctrl_post_div", base + 0x4600, 0); imx7d_clocks_init()
774 clks[IMX7D_PCIE_PHY_ROOT_CLK] = imx_clk_gate2("pcie_phy_root_clk", "pcie_phy_post_div", base + 0x4600, 0); imx7d_clocks_init()
775 clks[IMX7D_EPDC_PIXEL_ROOT_CLK] = imx_clk_gate2("epdc_pixel_root_clk", "epdc_pixel_post_div", base + 0x44a0, 0); imx7d_clocks_init()
776 clks[IMX7D_LCDIF_PIXEL_ROOT_CLK] = imx_clk_gate2("lcdif_pixel_root_clk", "lcdif_pixel_post_div", base + 0x44b0, 0); imx7d_clocks_init()
777 clks[IMX7D_MIPI_DSI_ROOT_CLK] = imx_clk_gate2("mipi_dsi_root_clk", "mipi_dsi_post_div", base + 0x4650, 0); imx7d_clocks_init()
778 clks[IMX7D_MIPI_CSI_ROOT_CLK] = imx_clk_gate2("mipi_csi_root_clk", "mipi_csi_post_div", base + 0x4640, 0); imx7d_clocks_init()
779 clks[IMX7D_MIPI_DPHY_ROOT_CLK] = imx_clk_gate2("mipi_dphy_root_clk", "mipi_dphy_post_div", base + 0x4660, 0); imx7d_clocks_init()
780 clks[IMX7D_SAI1_ROOT_CLK] = imx_clk_gate2("sai1_root_clk", "sai1_post_div", base + 0x48c0, 0); imx7d_clocks_init()
781 clks[IMX7D_SAI2_ROOT_CLK] = imx_clk_gate2("sai2_root_clk", "sai2_post_div", base + 0x48d0, 0); imx7d_clocks_init()
782 clks[IMX7D_SAI3_ROOT_CLK] = imx_clk_gate2("sai3_root_clk", "sai3_post_div", base + 0x48e0, 0); imx7d_clocks_init()
783 clks[IMX7D_SPDIF_ROOT_CLK] = imx_clk_gate2("spdif_root_clk", "spdif_post_div", base + 0x44d0, 0); imx7d_clocks_init()
784 clks[IMX7D_ENET1_REF_ROOT_CLK] = imx_clk_gate2("enet1_ref_root_clk", "enet1_ref_post_div", base + 0x44e0, 0); imx7d_clocks_init()
785 clks[IMX7D_ENET1_TIME_ROOT_CLK] = imx_clk_gate2("enet1_time_root_clk", "enet1_time_post_div", base + 0x44f0, 0); imx7d_clocks_init()
786 clks[IMX7D_ENET2_REF_ROOT_CLK] = imx_clk_gate2("enet2_ref_root_clk", "enet2_ref_post_div", base + 0x4500, 0); imx7d_clocks_init()
787 clks[IMX7D_ENET2_TIME_ROOT_CLK] = imx_clk_gate2("enet2_time_root_clk", "enet2_time_post_div", base + 0x4510, 0); imx7d_clocks_init()
788 clks[IMX7D_ENET_PHY_REF_ROOT_CLK] = imx_clk_gate2("enet_phy_ref_root_clk", "enet_phy_ref_post_div", base + 0x4520, 0); imx7d_clocks_init()
789 clks[IMX7D_EIM_ROOT_CLK] = imx_clk_gate2("eim_root_clk", "eim_post_div", base + 0x4160, 0); imx7d_clocks_init()
790 clks[IMX7D_NAND_ROOT_CLK] = imx_clk_gate2("nand_root_clk", "nand_post_div", base + 0x4140, 0); imx7d_clocks_init()
791 clks[IMX7D_QSPI_ROOT_CLK] = imx_clk_gate2("qspi_root_clk", "qspi_post_div", base + 0x4150, 0); imx7d_clocks_init()
792 clks[IMX7D_USDHC1_ROOT_CLK] = imx_clk_gate2("usdhc1_root_clk", "usdhc1_post_div", base + 0x46c0, 0); imx7d_clocks_init()
793 clks[IMX7D_USDHC2_ROOT_CLK] = imx_clk_gate2("usdhc2_root_clk", "usdhc2_post_div", base + 0x46d0, 0); imx7d_clocks_init()
794 clks[IMX7D_USDHC3_ROOT_CLK] = imx_clk_gate2("usdhc3_root_clk", "usdhc3_post_div", base + 0x46e0, 0); imx7d_clocks_init()
795 clks[IMX7D_CAN1_ROOT_CLK] = imx_clk_gate2("can1_root_clk", "can1_post_div", base + 0x4740, 0); imx7d_clocks_init()
796 clks[IMX7D_CAN2_ROOT_CLK] = imx_clk_gate2("can2_root_clk", "can2_post_div", base + 0x4750, 0); imx7d_clocks_init()
797 clks[IMX7D_I2C1_ROOT_CLK] = imx_clk_gate2("i2c1_root_clk", "i2c1_post_div", base + 0x4880, 0); imx7d_clocks_init()
798 clks[IMX7D_I2C2_ROOT_CLK] = imx_clk_gate2("i2c2_root_clk", "i2c2_post_div", base + 0x4890, 0); imx7d_clocks_init()
799 clks[IMX7D_I2C3_ROOT_CLK] = imx_clk_gate2("i2c3_root_clk", "i2c3_post_div", base + 0x48a0, 0); imx7d_clocks_init()
800 clks[IMX7D_I2C4_ROOT_CLK] = imx_clk_gate2("i2c4_root_clk", "i2c4_post_div", base + 0x48b0, 0); imx7d_clocks_init()
801 clks[IMX7D_UART1_ROOT_CLK] = imx_clk_gate2("uart1_root_clk", "uart1_post_div", base + 0x4940, 0); imx7d_clocks_init()
802 clks[IMX7D_UART2_ROOT_CLK] = imx_clk_gate2("uart2_root_clk", "uart2_post_div", base + 0x4950, 0); imx7d_clocks_init()
803 clks[IMX7D_UART3_ROOT_CLK] = imx_clk_gate2("uart3_root_clk", "uart3_post_div", base + 0x4960, 0); imx7d_clocks_init()
804 clks[IMX7D_UART4_ROOT_CLK] = imx_clk_gate2("uart4_root_clk", "uart4_post_div", base + 0x4970, 0); imx7d_clocks_init()
805 clks[IMX7D_UART5_ROOT_CLK] = imx_clk_gate2("uart5_root_clk", "uart5_post_div", base + 0x4980, 0); imx7d_clocks_init()
806 clks[IMX7D_UART6_ROOT_CLK] = imx_clk_gate2("uart6_root_clk", "uart6_post_div", base + 0x4990, 0); imx7d_clocks_init()
807 clks[IMX7D_UART7_ROOT_CLK] = imx_clk_gate2("uart7_root_clk", "uart7_post_div", base + 0x49a0, 0); imx7d_clocks_init()
808 clks[IMX7D_ECSPI1_ROOT_CLK] = imx_clk_gate2("ecspi1_root_clk", "ecspi1_post_div", base + 0x4780, 0); imx7d_clocks_init()
809 clks[IMX7D_ECSPI2_ROOT_CLK] = imx_clk_gate2("ecspi2_root_clk", "ecspi2_post_div", base + 0x4790, 0); imx7d_clocks_init()
810 clks[IMX7D_ECSPI3_ROOT_CLK] = imx_clk_gate2("ecspi3_root_clk", "ecspi3_post_div", base + 0x47a0, 0); imx7d_clocks_init()
811 clks[IMX7D_ECSPI4_ROOT_CLK] = imx_clk_gate2("ecspi4_root_clk", "ecspi4_post_div", base + 0x47b0, 0); imx7d_clocks_init()
812 clks[IMX7D_PWM1_ROOT_CLK] = imx_clk_gate2("pwm1_root_clk", "pwm1_post_div", base + 0x4840, 0); imx7d_clocks_init()
813 clks[IMX7D_PWM2_ROOT_CLK] = imx_clk_gate2("pwm2_root_clk", "pwm2_post_div", base + 0x4850, 0); imx7d_clocks_init()
814 clks[IMX7D_PWM3_ROOT_CLK] = imx_clk_gate2("pwm3_root_clk", "pwm3_post_div", base + 0x4860, 0); imx7d_clocks_init()
815 clks[IMX7D_PWM4_ROOT_CLK] = imx_clk_gate2("pwm4_root_clk", "pwm4_post_div", base + 0x4870, 0); imx7d_clocks_init()
816 clks[IMX7D_FLEXTIMER1_ROOT_CLK] = imx_clk_gate2("flextimer1_root_clk", "flextimer1_post_div", base + 0x4800, 0); imx7d_clocks_init()
817 clks[IMX7D_FLEXTIMER2_ROOT_CLK] = imx_clk_gate2("flextimer2_root_clk", "flextimer2_post_div", base + 0x4810, 0); imx7d_clocks_init()
818 clks[IMX7D_SIM1_ROOT_CLK] = imx_clk_gate2("sim1_root_clk", "sim1_post_div", base + 0x4900, 0); imx7d_clocks_init()
819 clks[IMX7D_SIM2_ROOT_CLK] = imx_clk_gate2("sim2_root_clk", "sim2_post_div", base + 0x4910, 0); imx7d_clocks_init()
820 clks[IMX7D_GPT1_ROOT_CLK] = imx_clk_gate2("gpt1_root_clk", "gpt1_post_div", base + 0x47c0, 0); imx7d_clocks_init()
821 clks[IMX7D_GPT2_ROOT_CLK] = imx_clk_gate2("gpt2_root_clk", "gpt2_post_div", base + 0x47d0, 0); imx7d_clocks_init()
822 clks[IMX7D_GPT3_ROOT_CLK] = imx_clk_gate2("gpt3_root_clk", "gpt3_post_div", base + 0x47e0, 0); imx7d_clocks_init()
823 clks[IMX7D_GPT4_ROOT_CLK] = imx_clk_gate2("gpt4_root_clk", "gpt4_post_div", base + 0x47f0, 0); imx7d_clocks_init()
824 clks[IMX7D_TRACE_ROOT_CLK] = imx_clk_gate2("trace_root_clk", "trace_post_div", base + 0x4300, 0); imx7d_clocks_init()
825 clks[IMX7D_WDOG1_ROOT_CLK] = imx_clk_gate2("wdog1_root_clk", "wdog_post_div", base + 0x49c0, 0); imx7d_clocks_init()
826 clks[IMX7D_WDOG2_ROOT_CLK] = imx_clk_gate2("wdog2_root_clk", "wdog_post_div", base + 0x49d0, 0); imx7d_clocks_init()
827 clks[IMX7D_WDOG3_ROOT_CLK] = imx_clk_gate2("wdog3_root_clk", "wdog_post_div", base + 0x49e0, 0); imx7d_clocks_init()
828 clks[IMX7D_WDOG4_ROOT_CLK] = imx_clk_gate2("wdog4_root_clk", "wdog_post_div", base + 0x49f0, 0); imx7d_clocks_init()
829 clks[IMX7D_CSI_MCLK_ROOT_CLK] = imx_clk_gate2("csi_mclk_root_clk", "csi_mclk_post_div", base + 0x4490, 0); imx7d_clocks_init()
830 clks[IMX7D_AUDIO_MCLK_ROOT_CLK] = imx_clk_gate2("audio_mclk_root_clk", "audio_mclk_post_div", base + 0x4790, 0); imx7d_clocks_init()
831 clks[IMX7D_WRCLK_ROOT_CLK] = imx_clk_gate2("wrclk_root_clk", "wrclk_post_div", base + 0x47a0, 0); imx7d_clocks_init()
832 clks[IMX7D_ADC_ROOT_CLK] = imx_clk_gate2("adc_root_clk", "ipg_root_clk", base + 0x4200, 0); imx7d_clocks_init()
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| H A D | clk-imx6sl.c | 197 void __iomem *base; imx6sl_clocks_init() local
208 base = of_iomap(np, 0); imx6sl_clocks_init()
209 WARN_ON(!base); imx6sl_clocks_init()
210 anatop_base = base; imx6sl_clocks_init()
212 clks[IMX6SL_PLL1_BYPASS_SRC] = imx_clk_mux("pll1_bypass_src", base + 0x00, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); imx6sl_clocks_init()
213 clks[IMX6SL_PLL2_BYPASS_SRC] = imx_clk_mux("pll2_bypass_src", base + 0x30, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); imx6sl_clocks_init()
214 clks[IMX6SL_PLL3_BYPASS_SRC] = imx_clk_mux("pll3_bypass_src", base + 0x10, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); imx6sl_clocks_init()
215 clks[IMX6SL_PLL4_BYPASS_SRC] = imx_clk_mux("pll4_bypass_src", base + 0x70, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); imx6sl_clocks_init()
216 clks[IMX6SL_PLL5_BYPASS_SRC] = imx_clk_mux("pll5_bypass_src", base + 0xa0, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); imx6sl_clocks_init()
217 clks[IMX6SL_PLL6_BYPASS_SRC] = imx_clk_mux("pll6_bypass_src", base + 0xe0, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); imx6sl_clocks_init()
218 clks[IMX6SL_PLL7_BYPASS_SRC] = imx_clk_mux("pll7_bypass_src", base + 0x20, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); imx6sl_clocks_init()
220 /* type name parent_name base div_mask */ imx6sl_clocks_init()
221 clks[IMX6SL_CLK_PLL1] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1", "pll1_bypass_src", base + 0x00, 0x7f); imx6sl_clocks_init()
222 clks[IMX6SL_CLK_PLL2] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2", "pll2_bypass_src", base + 0x30, 0x1); imx6sl_clocks_init()
223 clks[IMX6SL_CLK_PLL3] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3", "pll3_bypass_src", base + 0x10, 0x3); imx6sl_clocks_init()
224 clks[IMX6SL_CLK_PLL4] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4", "pll4_bypass_src", base + 0x70, 0x7f); imx6sl_clocks_init()
225 clks[IMX6SL_CLK_PLL5] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5", "pll5_bypass_src", base + 0xa0, 0x7f); imx6sl_clocks_init()
226 clks[IMX6SL_CLK_PLL6] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6", "pll6_bypass_src", base + 0xe0, 0x3); imx6sl_clocks_init()
227 clks[IMX6SL_CLK_PLL7] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7", "pll7_bypass_src", base + 0x20, 0x3); imx6sl_clocks_init()
229 clks[IMX6SL_PLL1_BYPASS] = imx_clk_mux_flags("pll1_bypass", base + 0x00, 16, 1, pll1_bypass_sels, ARRAY_SIZE(pll1_bypass_sels), CLK_SET_RATE_PARENT); imx6sl_clocks_init()
230 clks[IMX6SL_PLL2_BYPASS] = imx_clk_mux_flags("pll2_bypass", base + 0x30, 16, 1, pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), CLK_SET_RATE_PARENT); imx6sl_clocks_init()
231 clks[IMX6SL_PLL3_BYPASS] = imx_clk_mux_flags("pll3_bypass", base + 0x10, 16, 1, pll3_bypass_sels, ARRAY_SIZE(pll3_bypass_sels), CLK_SET_RATE_PARENT); imx6sl_clocks_init()
232 clks[IMX6SL_PLL4_BYPASS] = imx_clk_mux_flags("pll4_bypass", base + 0x70, 16, 1, pll4_bypass_sels, ARRAY_SIZE(pll4_bypass_sels), CLK_SET_RATE_PARENT); imx6sl_clocks_init()
233 clks[IMX6SL_PLL5_BYPASS] = imx_clk_mux_flags("pll5_bypass", base + 0xa0, 16, 1, pll5_bypass_sels, ARRAY_SIZE(pll5_bypass_sels), CLK_SET_RATE_PARENT); imx6sl_clocks_init()
234 clks[IMX6SL_PLL6_BYPASS] = imx_clk_mux_flags("pll6_bypass", base + 0xe0, 16, 1, pll6_bypass_sels, ARRAY_SIZE(pll6_bypass_sels), CLK_SET_RATE_PARENT); imx6sl_clocks_init()
235 clks[IMX6SL_PLL7_BYPASS] = imx_clk_mux_flags("pll7_bypass", base + 0x20, 16, 1, pll7_bypass_sels, ARRAY_SIZE(pll7_bypass_sels), CLK_SET_RATE_PARENT); imx6sl_clocks_init()
246 clks[IMX6SL_CLK_PLL1_SYS] = imx_clk_gate("pll1_sys", "pll1_bypass", base + 0x00, 13); imx6sl_clocks_init()
247 clks[IMX6SL_CLK_PLL2_BUS] = imx_clk_gate("pll2_bus", "pll2_bypass", base + 0x30, 13); imx6sl_clocks_init()
248 clks[IMX6SL_CLK_PLL3_USB_OTG] = imx_clk_gate("pll3_usb_otg", "pll3_bypass", base + 0x10, 13); imx6sl_clocks_init()
249 clks[IMX6SL_CLK_PLL4_AUDIO] = imx_clk_gate("pll4_audio", "pll4_bypass", base + 0x70, 13); imx6sl_clocks_init()
250 clks[IMX6SL_CLK_PLL5_VIDEO] = imx_clk_gate("pll5_video", "pll5_bypass", base + 0xa0, 13); imx6sl_clocks_init()
251 clks[IMX6SL_CLK_PLL6_ENET] = imx_clk_gate("pll6_enet", "pll6_bypass", base + 0xe0, 13); imx6sl_clocks_init()
252 clks[IMX6SL_CLK_PLL7_USB_HOST] = imx_clk_gate("pll7_usb_host", "pll7_bypass", base + 0x20, 13); imx6sl_clocks_init()
254 clks[IMX6SL_CLK_LVDS1_SEL] = imx_clk_mux("lvds1_sel", base + 0x160, 0, 5, lvds_sels, ARRAY_SIZE(lvds_sels)); imx6sl_clocks_init()
255 clks[IMX6SL_CLK_LVDS1_OUT] = imx_clk_gate_exclusive("lvds1_out", "lvds1_sel", base + 0x160, 10, BIT(12)); imx6sl_clocks_init()
256 clks[IMX6SL_CLK_LVDS1_IN] = imx_clk_gate_exclusive("lvds1_in", "anaclk1", base + 0x160, 12, BIT(10)); imx6sl_clocks_init()
265 clks[IMX6SL_CLK_USBPHY1] = imx_clk_gate("usbphy1", "pll3_usb_otg", base + 0x10, 20); imx6sl_clocks_init()
266 clks[IMX6SL_CLK_USBPHY2] = imx_clk_gate("usbphy2", "pll7_usb_host", base + 0x20, 20); imx6sl_clocks_init()
267 clks[IMX6SL_CLK_USBPHY1_GATE] = imx_clk_gate("usbphy1_gate", "dummy", base + 0x10, 6); imx6sl_clocks_init()
268 clks[IMX6SL_CLK_USBPHY2_GATE] = imx_clk_gate("usbphy2_gate", "dummy", base + 0x20, 6); imx6sl_clocks_init()
271 clks[IMX6SL_CLK_PLL4_POST_DIV] = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock); imx6sl_clocks_init()
272 clks[IMX6SL_CLK_PLL4_AUDIO_DIV] = clk_register_divider(NULL, "pll4_audio_div", "pll4_post_div", CLK_SET_RATE_PARENT, base + 0x170, 15, 1, 0, &imx_ccm_lock); imx6sl_clocks_init()
273 clks[IMX6SL_CLK_PLL5_POST_DIV] = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock); imx6sl_clocks_init()
274 clks[IMX6SL_CLK_PLL5_VIDEO_DIV] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock); imx6sl_clocks_init()
275 clks[IMX6SL_CLK_ENET_REF] = clk_register_divider_table(NULL, "enet_ref", "pll6_enet", 0, base + 0xe0, 0, 2, 0, clk_enet_ref_table, &imx_ccm_lock); imx6sl_clocks_init()
278 clks[IMX6SL_CLK_PLL2_PFD0] = imx_clk_pfd("pll2_pfd0", "pll2_bus", base + 0x100, 0); imx6sl_clocks_init()
279 clks[IMX6SL_CLK_PLL2_PFD1] = imx_clk_pfd("pll2_pfd1", "pll2_bus", base + 0x100, 1); imx6sl_clocks_init()
280 clks[IMX6SL_CLK_PLL2_PFD2] = imx_clk_pfd("pll2_pfd2", "pll2_bus", base + 0x100, 2); imx6sl_clocks_init()
281 clks[IMX6SL_CLK_PLL3_PFD0] = imx_clk_pfd("pll3_pfd0", "pll3_usb_otg", base + 0xf0, 0); imx6sl_clocks_init()
282 clks[IMX6SL_CLK_PLL3_PFD1] = imx_clk_pfd("pll3_pfd1", "pll3_usb_otg", base + 0xf0, 1); imx6sl_clocks_init()
283 clks[IMX6SL_CLK_PLL3_PFD2] = imx_clk_pfd("pll3_pfd2", "pll3_usb_otg", base + 0xf0, 2); imx6sl_clocks_init()
284 clks[IMX6SL_CLK_PLL3_PFD3] = imx_clk_pfd("pll3_pfd3", "pll3_usb_otg", base + 0xf0, 3); imx6sl_clocks_init()
293 base = of_iomap(np, 0); imx6sl_clocks_init()
294 WARN_ON(!base); imx6sl_clocks_init()
295 ccm_base = base; imx6sl_clocks_init()
298 clks[IMX6SL_CLK_STEP] = imx_clk_mux("step", base + 0xc, 8, 1, step_sels, ARRAY_SIZE(step_sels)); imx6sl_clocks_init()
299 clks[IMX6SL_CLK_PLL1_SW] = imx_clk_mux("pll1_sw", base + 0xc, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels)); imx6sl_clocks_init()
300 clks[IMX6SL_CLK_OCRAM_ALT_SEL] = imx_clk_mux("ocram_alt_sel", base + 0x14, 7, 1, ocram_alt_sels, ARRAY_SIZE(ocram_alt_sels)); imx6sl_clocks_init()
301 clks[IMX6SL_CLK_OCRAM_SEL] = imx_clk_mux("ocram_sel", base + 0x14, 6, 1, ocram_sels, ARRAY_SIZE(ocram_sels)); imx6sl_clocks_init()
302 clks[IMX6SL_CLK_PRE_PERIPH2_SEL] = imx_clk_mux("pre_periph2_sel", base + 0x18, 21, 2, pre_periph_sels, ARRAY_SIZE(pre_periph_sels)); imx6sl_clocks_init()
303 clks[IMX6SL_CLK_PRE_PERIPH_SEL] = imx_clk_mux("pre_periph_sel", base + 0x18, 18, 2, pre_periph_sels, ARRAY_SIZE(pre_periph_sels)); imx6sl_clocks_init()
304 clks[IMX6SL_CLK_PERIPH2_CLK2_SEL] = imx_clk_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels)); imx6sl_clocks_init()
305 clks[IMX6SL_CLK_PERIPH_CLK2_SEL] = imx_clk_mux("periph_clk2_sel", base + 0x18, 12, 2, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels)); imx6sl_clocks_init()
306 clks[IMX6SL_CLK_CSI_SEL] = imx_clk_mux("csi_sel", base + 0x3c, 9, 2, csi_sels, ARRAY_SIZE(csi_sels)); imx6sl_clocks_init()
307 clks[IMX6SL_CLK_LCDIF_AXI_SEL] = imx_clk_mux("lcdif_axi_sel", base + 0x3c, 14, 2, lcdif_axi_sels, ARRAY_SIZE(lcdif_axi_sels)); imx6sl_clocks_init()
308 clks[IMX6SL_CLK_USDHC1_SEL] = imx_clk_fixup_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); imx6sl_clocks_init()
309 clks[IMX6SL_CLK_USDHC2_SEL] = imx_clk_fixup_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); imx6sl_clocks_init()
310 clks[IMX6SL_CLK_USDHC3_SEL] = imx_clk_fixup_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); imx6sl_clocks_init()
311 clks[IMX6SL_CLK_USDHC4_SEL] = imx_clk_fixup_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); imx6sl_clocks_init()
312 clks[IMX6SL_CLK_SSI1_SEL] = imx_clk_fixup_mux("ssi1_sel", base + 0x1c, 10, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup); imx6sl_clocks_init()
313 clks[IMX6SL_CLK_SSI2_SEL] = imx_clk_fixup_mux("ssi2_sel", base + 0x1c, 12, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup); imx6sl_clocks_init()
314 clks[IMX6SL_CLK_SSI3_SEL] = imx_clk_fixup_mux("ssi3_sel", base + 0x1c, 14, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup); imx6sl_clocks_init()
315 clks[IMX6SL_CLK_PERCLK_SEL] = imx_clk_fixup_mux("perclk_sel", base + 0x1c, 6, 1, perclk_sels, ARRAY_SIZE(perclk_sels), imx_cscmr1_fixup); imx6sl_clocks_init()
316 clks[IMX6SL_CLK_PXP_AXI_SEL] = imx_clk_mux("pxp_axi_sel", base + 0x34, 6, 3, pxp_axi_sels, ARRAY_SIZE(pxp_axi_sels)); imx6sl_clocks_init()
317 clks[IMX6SL_CLK_EPDC_AXI_SEL] = imx_clk_mux("epdc_axi_sel", base + 0x34, 15, 3, epdc_axi_sels, ARRAY_SIZE(epdc_axi_sels)); imx6sl_clocks_init()
318 clks[IMX6SL_CLK_GPU2D_OVG_SEL] = imx_clk_mux("gpu2d_ovg_sel", base + 0x18, 4, 2, gpu2d_ovg_sels, ARRAY_SIZE(gpu2d_ovg_sels)); imx6sl_clocks_init()
319 clks[IMX6SL_CLK_GPU2D_SEL] = imx_clk_mux("gpu2d_sel", base + 0x18, 8, 2, gpu2d_sels, ARRAY_SIZE(gpu2d_sels)); imx6sl_clocks_init()
320 clks[IMX6SL_CLK_LCDIF_PIX_SEL] = imx_clk_mux("lcdif_pix_sel", base + 0x38, 6, 3, lcdif_pix_sels, ARRAY_SIZE(lcdif_pix_sels)); imx6sl_clocks_init()
321 clks[IMX6SL_CLK_EPDC_PIX_SEL] = imx_clk_mux("epdc_pix_sel", base + 0x38, 15, 3, epdc_pix_sels, ARRAY_SIZE(epdc_pix_sels)); imx6sl_clocks_init()
322 clks[IMX6SL_CLK_SPDIF0_SEL] = imx_clk_mux("spdif0_sel", base + 0x30, 20, 2, audio_sels, ARRAY_SIZE(audio_sels)); imx6sl_clocks_init()
323 clks[IMX6SL_CLK_SPDIF1_SEL] = imx_clk_mux("spdif1_sel", base + 0x30, 7, 2, audio_sels, ARRAY_SIZE(audio_sels)); imx6sl_clocks_init()
324 clks[IMX6SL_CLK_EXTERN_AUDIO_SEL] = imx_clk_mux("extern_audio_sel", base + 0x20, 19, 2, audio_sels, ARRAY_SIZE(audio_sels)); imx6sl_clocks_init()
325 clks[IMX6SL_CLK_ECSPI_SEL] = imx_clk_mux("ecspi_sel", base + 0x38, 18, 1, ecspi_sels, ARRAY_SIZE(ecspi_sels)); imx6sl_clocks_init()
326 clks[IMX6SL_CLK_UART_SEL] = imx_clk_mux("uart_sel", base + 0x24, 6, 1, uart_sels, ARRAY_SIZE(uart_sels)); imx6sl_clocks_init()
329 clks[IMX6SL_CLK_PERIPH] = imx_clk_busy_mux("periph", base + 0x14, 25, 1, base + 0x48, 5, periph_sels, ARRAY_SIZE(periph_sels)); imx6sl_clocks_init()
330 clks[IMX6SL_CLK_PERIPH2] = imx_clk_busy_mux("periph2", base + 0x14, 26, 1, base + 0x48, 3, periph2_sels, ARRAY_SIZE(periph2_sels)); imx6sl_clocks_init()
333 clks[IMX6SL_CLK_OCRAM_PODF] = imx_clk_divider("ocram_podf", "ocram_sel", base + 0x14, 16, 3); imx6sl_clocks_init()
334 clks[IMX6SL_CLK_PERIPH_CLK2_PODF] = imx_clk_divider("periph_clk2_podf", "periph_clk2_sel", base + 0x14, 27, 3); imx6sl_clocks_init()
335 clks[IMX6SL_CLK_PERIPH2_CLK2_PODF] = imx_clk_divider("periph2_clk2_podf", "periph2_clk2_sel", base + 0x14, 0, 3); imx6sl_clocks_init()
336 clks[IMX6SL_CLK_IPG] = imx_clk_divider("ipg", "ahb", base + 0x14, 8, 2); imx6sl_clocks_init()
337 clks[IMX6SL_CLK_CSI_PODF] = imx_clk_divider("csi_podf", "csi_sel", base + 0x3c, 11, 3); imx6sl_clocks_init()
338 clks[IMX6SL_CLK_LCDIF_AXI_PODF] = imx_clk_divider("lcdif_axi_podf", "lcdif_axi_sel", base + 0x3c, 16, 3); imx6sl_clocks_init()
339 clks[IMX6SL_CLK_USDHC1_PODF] = imx_clk_divider("usdhc1_podf", "usdhc1_sel", base + 0x24, 11, 3); imx6sl_clocks_init()
340 clks[IMX6SL_CLK_USDHC2_PODF] = imx_clk_divider("usdhc2_podf", "usdhc2_sel", base + 0x24, 16, 3); imx6sl_clocks_init()
341 clks[IMX6SL_CLK_USDHC3_PODF] = imx_clk_divider("usdhc3_podf", "usdhc3_sel", base + 0x24, 19, 3); imx6sl_clocks_init()
342 clks[IMX6SL_CLK_USDHC4_PODF] = imx_clk_divider("usdhc4_podf", "usdhc4_sel", base + 0x24, 22, 3); imx6sl_clocks_init()
343 clks[IMX6SL_CLK_SSI1_PRED] = imx_clk_divider("ssi1_pred", "ssi1_sel", base + 0x28, 6, 3); imx6sl_clocks_init()
344 clks[IMX6SL_CLK_SSI1_PODF] = imx_clk_divider("ssi1_podf", "ssi1_pred", base + 0x28, 0, 6); imx6sl_clocks_init()
345 clks[IMX6SL_CLK_SSI2_PRED] = imx_clk_divider("ssi2_pred", "ssi2_sel", base + 0x2c, 6, 3); imx6sl_clocks_init()
346 clks[IMX6SL_CLK_SSI2_PODF] = imx_clk_divider("ssi2_podf", "ssi2_pred", base + 0x2c, 0, 6); imx6sl_clocks_init()
347 clks[IMX6SL_CLK_SSI3_PRED] = imx_clk_divider("ssi3_pred", "ssi3_sel", base + 0x28, 22, 3); imx6sl_clocks_init()
348 clks[IMX6SL_CLK_SSI3_PODF] = imx_clk_divider("ssi3_podf", "ssi3_pred", base + 0x28, 16, 6); imx6sl_clocks_init()
349 clks[IMX6SL_CLK_PERCLK] = imx_clk_fixup_divider("perclk", "perclk_sel", base + 0x1c, 0, 6, imx_cscmr1_fixup); imx6sl_clocks_init()
350 clks[IMX6SL_CLK_PXP_AXI_PODF] = imx_clk_divider("pxp_axi_podf", "pxp_axi_sel", base + 0x34, 3, 3); imx6sl_clocks_init()
351 clks[IMX6SL_CLK_EPDC_AXI_PODF] = imx_clk_divider("epdc_axi_podf", "epdc_axi_sel", base + 0x34, 12, 3); imx6sl_clocks_init()
352 clks[IMX6SL_CLK_GPU2D_OVG_PODF] = imx_clk_divider("gpu2d_ovg_podf", "gpu2d_ovg_sel", base + 0x18, 26, 3); imx6sl_clocks_init()
353 clks[IMX6SL_CLK_GPU2D_PODF] = imx_clk_divider("gpu2d_podf", "gpu2d_sel", base + 0x18, 29, 3); imx6sl_clocks_init()
354 clks[IMX6SL_CLK_LCDIF_PIX_PRED] = imx_clk_divider("lcdif_pix_pred", "lcdif_pix_sel", base + 0x38, 3, 3); imx6sl_clocks_init()
355 clks[IMX6SL_CLK_EPDC_PIX_PRED] = imx_clk_divider("epdc_pix_pred", "epdc_pix_sel", base + 0x38, 12, 3); imx6sl_clocks_init()
356 clks[IMX6SL_CLK_LCDIF_PIX_PODF] = imx_clk_fixup_divider("lcdif_pix_podf", "lcdif_pix_pred", base + 0x1c, 20, 3, imx_cscmr1_fixup); imx6sl_clocks_init()
357 clks[IMX6SL_CLK_EPDC_PIX_PODF] = imx_clk_divider("epdc_pix_podf", "epdc_pix_pred", base + 0x18, 23, 3); imx6sl_clocks_init()
358 clks[IMX6SL_CLK_SPDIF0_PRED] = imx_clk_divider("spdif0_pred", "spdif0_sel", base + 0x30, 25, 3); imx6sl_clocks_init()
359 clks[IMX6SL_CLK_SPDIF0_PODF] = imx_clk_divider("spdif0_podf", "spdif0_pred", base + 0x30, 22, 3); imx6sl_clocks_init()
360 clks[IMX6SL_CLK_SPDIF1_PRED] = imx_clk_divider("spdif1_pred", "spdif1_sel", base + 0x30, 12, 3); imx6sl_clocks_init()
361 clks[IMX6SL_CLK_SPDIF1_PODF] = imx_clk_divider("spdif1_podf", "spdif1_pred", base + 0x30, 9, 3); imx6sl_clocks_init()
362 clks[IMX6SL_CLK_EXTERN_AUDIO_PRED] = imx_clk_divider("extern_audio_pred", "extern_audio_sel", base + 0x28, 9, 3); imx6sl_clocks_init()
363 clks[IMX6SL_CLK_EXTERN_AUDIO_PODF] = imx_clk_divider("extern_audio_podf", "extern_audio_pred", base + 0x28, 25, 3); imx6sl_clocks_init()
364 clks[IMX6SL_CLK_ECSPI_ROOT] = imx_clk_divider("ecspi_root", "ecspi_sel", base + 0x38, 19, 6); imx6sl_clocks_init()
365 clks[IMX6SL_CLK_UART_ROOT] = imx_clk_divider("uart_root", "uart_sel", base + 0x24, 0, 6); imx6sl_clocks_init()
368 clks[IMX6SL_CLK_AHB] = imx_clk_busy_divider("ahb", "periph", base + 0x14, 10, 3, base + 0x48, 1); imx6sl_clocks_init()
369 clks[IMX6SL_CLK_MMDC_ROOT] = imx_clk_busy_divider("mmdc", "periph2", base + 0x14, 3, 3, base + 0x48, 2); imx6sl_clocks_init()
370 clks[IMX6SL_CLK_ARM] = imx_clk_busy_divider("arm", "pll1_sw", base + 0x10, 0, 3, base + 0x48, 16); imx6sl_clocks_init()
373 clks[IMX6SL_CLK_ECSPI1] = imx_clk_gate2("ecspi1", "ecspi_root", base + 0x6c, 0); imx6sl_clocks_init()
374 clks[IMX6SL_CLK_ECSPI2] = imx_clk_gate2("ecspi2", "ecspi_root", base + 0x6c, 2); imx6sl_clocks_init()
375 clks[IMX6SL_CLK_ECSPI3] = imx_clk_gate2("ecspi3", "ecspi_root", base + 0x6c, 4); imx6sl_clocks_init()
376 clks[IMX6SL_CLK_ECSPI4] = imx_clk_gate2("ecspi4", "ecspi_root", base + 0x6c, 6); imx6sl_clocks_init()
377 clks[IMX6SL_CLK_ENET] = imx_clk_gate2("enet", "ipg", base + 0x6c, 10); imx6sl_clocks_init()
378 clks[IMX6SL_CLK_EPIT1] = imx_clk_gate2("epit1", "perclk", base + 0x6c, 12); imx6sl_clocks_init()
379 clks[IMX6SL_CLK_EPIT2] = imx_clk_gate2("epit2", "perclk", base + 0x6c, 14); imx6sl_clocks_init()
380 clks[IMX6SL_CLK_EXTERN_AUDIO] = imx_clk_gate2("extern_audio", "extern_audio_podf", base + 0x6c, 16); imx6sl_clocks_init()
381 clks[IMX6SL_CLK_GPT] = imx_clk_gate2("gpt", "perclk", base + 0x6c, 20); imx6sl_clocks_init()
382 clks[IMX6SL_CLK_GPT_SERIAL] = imx_clk_gate2("gpt_serial", "perclk", base + 0x6c, 22); imx6sl_clocks_init()
383 clks[IMX6SL_CLK_GPU2D_OVG] = imx_clk_gate2("gpu2d_ovg", "gpu2d_ovg_podf", base + 0x6c, 26); imx6sl_clocks_init()
384 clks[IMX6SL_CLK_I2C1] = imx_clk_gate2("i2c1", "perclk", base + 0x70, 6); imx6sl_clocks_init()
385 clks[IMX6SL_CLK_I2C2] = imx_clk_gate2("i2c2", "perclk", base + 0x70, 8); imx6sl_clocks_init()
386 clks[IMX6SL_CLK_I2C3] = imx_clk_gate2("i2c3", "perclk", base + 0x70, 10); imx6sl_clocks_init()
387 clks[IMX6SL_CLK_OCOTP] = imx_clk_gate2("ocotp", "ipg", base + 0x70, 12); imx6sl_clocks_init()
388 clks[IMX6SL_CLK_CSI] = imx_clk_gate2("csi", "csi_podf", base + 0x74, 0); imx6sl_clocks_init()
389 clks[IMX6SL_CLK_PXP_AXI] = imx_clk_gate2("pxp_axi", "pxp_axi_podf", base + 0x74, 2); imx6sl_clocks_init()
390 clks[IMX6SL_CLK_EPDC_AXI] = imx_clk_gate2("epdc_axi", "epdc_axi_podf", base + 0x74, 4); imx6sl_clocks_init()
391 clks[IMX6SL_CLK_LCDIF_AXI] = imx_clk_gate2("lcdif_axi", "lcdif_axi_podf", base + 0x74, 6); imx6sl_clocks_init()
392 clks[IMX6SL_CLK_LCDIF_PIX] = imx_clk_gate2("lcdif_pix", "lcdif_pix_podf", base + 0x74, 8); imx6sl_clocks_init()
393 clks[IMX6SL_CLK_EPDC_PIX] = imx_clk_gate2("epdc_pix", "epdc_pix_podf", base + 0x74, 10); imx6sl_clocks_init()
394 clks[IMX6SL_CLK_OCRAM] = imx_clk_gate2("ocram", "ocram_podf", base + 0x74, 28); imx6sl_clocks_init()
395 clks[IMX6SL_CLK_PWM1] = imx_clk_gate2("pwm1", "perclk", base + 0x78, 16); imx6sl_clocks_init()
396 clks[IMX6SL_CLK_PWM2] = imx_clk_gate2("pwm2", "perclk", base + 0x78, 18); imx6sl_clocks_init()
397 clks[IMX6SL_CLK_PWM3] = imx_clk_gate2("pwm3", "perclk", base + 0x78, 20); imx6sl_clocks_init()
398 clks[IMX6SL_CLK_PWM4] = imx_clk_gate2("pwm4", "perclk", base + 0x78, 22); imx6sl_clocks_init()
399 clks[IMX6SL_CLK_SDMA] = imx_clk_gate2("sdma", "ipg", base + 0x7c, 6); imx6sl_clocks_init()
400 clks[IMX6SL_CLK_SPBA] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12); imx6sl_clocks_init()
401 clks[IMX6SL_CLK_SPDIF] = imx_clk_gate2_shared("spdif", "spdif0_podf", base + 0x7c, 14, &share_count_spdif); imx6sl_clocks_init()
402 clks[IMX6SL_CLK_SPDIF_GCLK] = imx_clk_gate2_shared("spdif_gclk", "ipg", base + 0x7c, 14, &share_count_spdif); imx6sl_clocks_init()
403 clks[IMX6SL_CLK_SSI1_IPG] = imx_clk_gate2_shared("ssi1_ipg", "ipg", base + 0x7c, 18, &share_count_ssi1); imx6sl_clocks_init()
404 clks[IMX6SL_CLK_SSI2_IPG] = imx_clk_gate2_shared("ssi2_ipg", "ipg", base + 0x7c, 20, &share_count_ssi2); imx6sl_clocks_init()
405 clks[IMX6SL_CLK_SSI3_IPG] = imx_clk_gate2_shared("ssi3_ipg", "ipg", base + 0x7c, 22, &share_count_ssi3); imx6sl_clocks_init()
406 clks[IMX6SL_CLK_SSI1] = imx_clk_gate2_shared("ssi1", "ssi1_podf", base + 0x7c, 18, &share_count_ssi1); imx6sl_clocks_init()
407 clks[IMX6SL_CLK_SSI2] = imx_clk_gate2_shared("ssi2", "ssi2_podf", base + 0x7c, 20, &share_count_ssi2); imx6sl_clocks_init()
408 clks[IMX6SL_CLK_SSI3] = imx_clk_gate2_shared("ssi3", "ssi3_podf", base + 0x7c, 22, &share_count_ssi3); imx6sl_clocks_init()
409 clks[IMX6SL_CLK_UART] = imx_clk_gate2("uart", "ipg", base + 0x7c, 24); imx6sl_clocks_init()
410 clks[IMX6SL_CLK_UART_SERIAL] = imx_clk_gate2("uart_serial", "uart_root", base + 0x7c, 26); imx6sl_clocks_init()
411 clks[IMX6SL_CLK_USBOH3] = imx_clk_gate2("usboh3", "ipg", base + 0x80, 0); imx6sl_clocks_init()
412 clks[IMX6SL_CLK_USDHC1] = imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2); imx6sl_clocks_init()
413 clks[IMX6SL_CLK_USDHC2] = imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4); imx6sl_clocks_init()
414 clks[IMX6SL_CLK_USDHC3] = imx_clk_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6); imx6sl_clocks_init()
415 clks[IMX6SL_CLK_USDHC4] = imx_clk_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8); imx6sl_clocks_init()
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| H A D | clk-imx6sx.c | 147 void __iomem *base; imx6sx_clocks_init() local
163 base = of_iomap(np, 0); imx6sx_clocks_init()
164 WARN_ON(!base); imx6sx_clocks_init()
166 clks[IMX6SX_PLL1_BYPASS_SRC] = imx_clk_mux("pll1_bypass_src", base + 0x00, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); imx6sx_clocks_init()
167 clks[IMX6SX_PLL2_BYPASS_SRC] = imx_clk_mux("pll2_bypass_src", base + 0x30, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); imx6sx_clocks_init()
168 clks[IMX6SX_PLL3_BYPASS_SRC] = imx_clk_mux("pll3_bypass_src", base + 0x10, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); imx6sx_clocks_init()
169 clks[IMX6SX_PLL4_BYPASS_SRC] = imx_clk_mux("pll4_bypass_src", base + 0x70, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); imx6sx_clocks_init()
170 clks[IMX6SX_PLL5_BYPASS_SRC] = imx_clk_mux("pll5_bypass_src", base + 0xa0, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); imx6sx_clocks_init()
171 clks[IMX6SX_PLL6_BYPASS_SRC] = imx_clk_mux("pll6_bypass_src", base + 0xe0, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); imx6sx_clocks_init()
172 clks[IMX6SX_PLL7_BYPASS_SRC] = imx_clk_mux("pll7_bypass_src", base + 0x20, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); imx6sx_clocks_init()
174 /* type name parent_name base div_mask */ imx6sx_clocks_init()
175 clks[IMX6SX_CLK_PLL1] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1", "pll1_bypass_src", base + 0x00, 0x7f); imx6sx_clocks_init()
176 clks[IMX6SX_CLK_PLL2] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2", "pll2_bypass_src", base + 0x30, 0x1); imx6sx_clocks_init()
177 clks[IMX6SX_CLK_PLL3] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3", "pll3_bypass_src", base + 0x10, 0x3); imx6sx_clocks_init()
178 clks[IMX6SX_CLK_PLL4] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4", "pll4_bypass_src", base + 0x70, 0x7f); imx6sx_clocks_init()
179 clks[IMX6SX_CLK_PLL5] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5", "pll5_bypass_src", base + 0xa0, 0x7f); imx6sx_clocks_init()
180 clks[IMX6SX_CLK_PLL6] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6", "pll6_bypass_src", base + 0xe0, 0x3); imx6sx_clocks_init()
181 clks[IMX6SX_CLK_PLL7] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7", "pll7_bypass_src", base + 0x20, 0x3); imx6sx_clocks_init()
183 clks[IMX6SX_PLL1_BYPASS] = imx_clk_mux_flags("pll1_bypass", base + 0x00, 16, 1, pll1_bypass_sels, ARRAY_SIZE(pll1_bypass_sels), CLK_SET_RATE_PARENT); imx6sx_clocks_init()
184 clks[IMX6SX_PLL2_BYPASS] = imx_clk_mux_flags("pll2_bypass", base + 0x30, 16, 1, pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), CLK_SET_RATE_PARENT); imx6sx_clocks_init()
185 clks[IMX6SX_PLL3_BYPASS] = imx_clk_mux_flags("pll3_bypass", base + 0x10, 16, 1, pll3_bypass_sels, ARRAY_SIZE(pll3_bypass_sels), CLK_SET_RATE_PARENT); imx6sx_clocks_init()
186 clks[IMX6SX_PLL4_BYPASS] = imx_clk_mux_flags("pll4_bypass", base + 0x70, 16, 1, pll4_bypass_sels, ARRAY_SIZE(pll4_bypass_sels), CLK_SET_RATE_PARENT); imx6sx_clocks_init()
187 clks[IMX6SX_PLL5_BYPASS] = imx_clk_mux_flags("pll5_bypass", base + 0xa0, 16, 1, pll5_bypass_sels, ARRAY_SIZE(pll5_bypass_sels), CLK_SET_RATE_PARENT); imx6sx_clocks_init()
188 clks[IMX6SX_PLL6_BYPASS] = imx_clk_mux_flags("pll6_bypass", base + 0xe0, 16, 1, pll6_bypass_sels, ARRAY_SIZE(pll6_bypass_sels), CLK_SET_RATE_PARENT); imx6sx_clocks_init()
189 clks[IMX6SX_PLL7_BYPASS] = imx_clk_mux_flags("pll7_bypass", base + 0x20, 16, 1, pll7_bypass_sels, ARRAY_SIZE(pll7_bypass_sels), CLK_SET_RATE_PARENT); imx6sx_clocks_init()
200 clks[IMX6SX_CLK_PLL1_SYS] = imx_clk_gate("pll1_sys", "pll1_bypass", base + 0x00, 13); imx6sx_clocks_init()
201 clks[IMX6SX_CLK_PLL2_BUS] = imx_clk_gate("pll2_bus", "pll2_bypass", base + 0x30, 13); imx6sx_clocks_init()
202 clks[IMX6SX_CLK_PLL3_USB_OTG] = imx_clk_gate("pll3_usb_otg", "pll3_bypass", base + 0x10, 13); imx6sx_clocks_init()
203 clks[IMX6SX_CLK_PLL4_AUDIO] = imx_clk_gate("pll4_audio", "pll4_bypass", base + 0x70, 13); imx6sx_clocks_init()
204 clks[IMX6SX_CLK_PLL5_VIDEO] = imx_clk_gate("pll5_video", "pll5_bypass", base + 0xa0, 13); imx6sx_clocks_init()
205 clks[IMX6SX_CLK_PLL6_ENET] = imx_clk_gate("pll6_enet", "pll6_bypass", base + 0xe0, 13); imx6sx_clocks_init()
206 clks[IMX6SX_CLK_PLL7_USB_HOST] = imx_clk_gate("pll7_usb_host", "pll7_bypass", base + 0x20, 13); imx6sx_clocks_init()
214 clks[IMX6SX_CLK_USBPHY1] = imx_clk_gate("usbphy1", "pll3_usb_otg", base + 0x10, 20); imx6sx_clocks_init()
215 clks[IMX6SX_CLK_USBPHY2] = imx_clk_gate("usbphy2", "pll7_usb_host", base + 0x20, 20); imx6sx_clocks_init()
221 clks[IMX6SX_CLK_USBPHY1_GATE] = imx_clk_gate("usbphy1_gate", "dummy", base + 0x10, 6); imx6sx_clocks_init()
222 clks[IMX6SX_CLK_USBPHY2_GATE] = imx_clk_gate("usbphy2_gate", "dummy", base + 0x20, 6); imx6sx_clocks_init()
226 clks[IMX6SX_CLK_PCIE_REF_125M] = imx_clk_gate("pcie_ref_125m", "pcie_ref", base + 0xe0, 19); imx6sx_clocks_init()
228 clks[IMX6SX_CLK_LVDS1_OUT] = imx_clk_gate_exclusive("lvds1_out", "lvds1_sel", base + 0x160, 10, BIT(12)); imx6sx_clocks_init()
229 clks[IMX6SX_CLK_LVDS1_IN] = imx_clk_gate_exclusive("lvds1_in", "anaclk1", base + 0x160, 12, BIT(10)); imx6sx_clocks_init()
232 base + 0xe0, 0, 2, 0, clk_enet_ref_table, imx6sx_clocks_init()
235 base + 0xe0, 2, 2, 0, clk_enet_ref_table, imx6sx_clocks_init()
237 clks[IMX6SX_CLK_ENET2_REF_125M] = imx_clk_gate("enet2_ref_125m", "enet2_ref", base + 0xe0, 20); imx6sx_clocks_init()
240 clks[IMX6SX_CLK_ENET_PTP] = imx_clk_gate("enet_ptp_25m", "enet_ptp_ref", base + 0xe0, 21); imx6sx_clocks_init()
243 clks[IMX6SX_CLK_PLL2_PFD0] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0); imx6sx_clocks_init()
244 clks[IMX6SX_CLK_PLL2_PFD1] = imx_clk_pfd("pll2_pfd1_594m", "pll2_bus", base + 0x100, 1); imx6sx_clocks_init()
245 clks[IMX6SX_CLK_PLL2_PFD2] = imx_clk_pfd("pll2_pfd2_396m", "pll2_bus", base + 0x100, 2); imx6sx_clocks_init()
246 clks[IMX6SX_CLK_PLL2_PFD3] = imx_clk_pfd("pll2_pfd3_594m", "pll2_bus", base + 0x100, 3); imx6sx_clocks_init()
247 clks[IMX6SX_CLK_PLL3_PFD0] = imx_clk_pfd("pll3_pfd0_720m", "pll3_usb_otg", base + 0xf0, 0); imx6sx_clocks_init()
248 clks[IMX6SX_CLK_PLL3_PFD1] = imx_clk_pfd("pll3_pfd1_540m", "pll3_usb_otg", base + 0xf0, 1); imx6sx_clocks_init()
249 clks[IMX6SX_CLK_PLL3_PFD2] = imx_clk_pfd("pll3_pfd2_508m", "pll3_usb_otg", base + 0xf0, 2); imx6sx_clocks_init()
250 clks[IMX6SX_CLK_PLL3_PFD3] = imx_clk_pfd("pll3_pfd3_454m", "pll3_usb_otg", base + 0xf0, 3); imx6sx_clocks_init()
261 CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock); imx6sx_clocks_init()
263 CLK_SET_RATE_PARENT, base + 0x170, 15, 1, 0, &imx_ccm_lock); imx6sx_clocks_init()
265 CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock); imx6sx_clocks_init()
267 CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock); imx6sx_clocks_init()
270 clks[IMX6SX_CLK_LVDS1_SEL] = imx_clk_mux("lvds1_sel", base + 0x160, 0, 5, lvds_sels, ARRAY_SIZE(lvds_sels)); imx6sx_clocks_init()
273 base = of_iomap(np, 0); imx6sx_clocks_init()
274 WARN_ON(!base); imx6sx_clocks_init()
277 clks[IMX6SX_CLK_STEP] = imx_clk_mux("step", base + 0xc, 8, 1, step_sels, ARRAY_SIZE(step_sels)); imx6sx_clocks_init()
278 clks[IMX6SX_CLK_PLL1_SW] = imx_clk_mux("pll1_sw", base + 0xc, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels)); imx6sx_clocks_init()
279 clks[IMX6SX_CLK_OCRAM_SEL] = imx_clk_mux("ocram_sel", base + 0x14, 6, 2, ocram_sels, ARRAY_SIZE(ocram_sels)); imx6sx_clocks_init()
280 clks[IMX6SX_CLK_PERIPH_PRE] = imx_clk_mux("periph_pre", base + 0x18, 18, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels)); imx6sx_clocks_init()
281 clks[IMX6SX_CLK_PERIPH2_PRE] = imx_clk_mux("periph2_pre", base + 0x18, 21, 2, periph2_pre_sels, ARRAY_SIZE(periph2_pre_sels)); imx6sx_clocks_init()
282 clks[IMX6SX_CLK_PERIPH_CLK2_SEL] = imx_clk_mux("periph_clk2_sel", base + 0x18, 12, 2, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels)); imx6sx_clocks_init()
283 clks[IMX6SX_CLK_PERIPH2_CLK2_SEL] = imx_clk_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels)); imx6sx_clocks_init()
284 clks[IMX6SX_CLK_PCIE_AXI_SEL] = imx_clk_mux("pcie_axi_sel", base + 0x18, 10, 1, pcie_axi_sels, ARRAY_SIZE(pcie_axi_sels)); imx6sx_clocks_init()
285 clks[IMX6SX_CLK_GPU_AXI_SEL] = imx_clk_mux("gpu_axi_sel", base + 0x18, 8, 2, gpu_axi_sels, ARRAY_SIZE(gpu_axi_sels)); imx6sx_clocks_init()
286 clks[IMX6SX_CLK_GPU_CORE_SEL] = imx_clk_mux("gpu_core_sel", base + 0x18, 4, 2, gpu_core_sels, ARRAY_SIZE(gpu_core_sels)); imx6sx_clocks_init()
287 clks[IMX6SX_CLK_EIM_SLOW_SEL] = imx_clk_mux("eim_slow_sel", base + 0x1c, 29, 2, eim_slow_sels, ARRAY_SIZE(eim_slow_sels)); imx6sx_clocks_init()
288 clks[IMX6SX_CLK_USDHC1_SEL] = imx_clk_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); imx6sx_clocks_init()
289 clks[IMX6SX_CLK_USDHC2_SEL] = imx_clk_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); imx6sx_clocks_init()
290 clks[IMX6SX_CLK_USDHC3_SEL] = imx_clk_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); imx6sx_clocks_init()
291 clks[IMX6SX_CLK_USDHC4_SEL] = imx_clk_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); imx6sx_clocks_init()
292 clks[IMX6SX_CLK_SSI3_SEL] = imx_clk_mux("ssi3_sel", base + 0x1c, 14, 2, ssi_sels, ARRAY_SIZE(ssi_sels)); imx6sx_clocks_init()
293 clks[IMX6SX_CLK_SSI2_SEL] = imx_clk_mux("ssi2_sel", base + 0x1c, 12, 2, ssi_sels, ARRAY_SIZE(ssi_sels)); imx6sx_clocks_init()
294 clks[IMX6SX_CLK_SSI1_SEL] = imx_clk_mux("ssi1_sel", base + 0x1c, 10, 2, ssi_sels, ARRAY_SIZE(ssi_sels)); imx6sx_clocks_init()
295 clks[IMX6SX_CLK_QSPI1_SEL] = imx_clk_mux_flags("qspi1_sel", base + 0x1c, 7, 3, qspi1_sels, ARRAY_SIZE(qspi1_sels), CLK_SET_RATE_PARENT); imx6sx_clocks_init()
296 clks[IMX6SX_CLK_PERCLK_SEL] = imx_clk_mux("perclk_sel", base + 0x1c, 6, 1, perclk_sels, ARRAY_SIZE(perclk_sels)); imx6sx_clocks_init()
297 clks[IMX6SX_CLK_VID_SEL] = imx_clk_mux("vid_sel", base + 0x20, 21, 3, vid_sels, ARRAY_SIZE(vid_sels)); imx6sx_clocks_init()
298 clks[IMX6SX_CLK_ESAI_SEL] = imx_clk_mux("esai_sel", base + 0x20, 19, 2, audio_sels, ARRAY_SIZE(audio_sels)); imx6sx_clocks_init()
299 clks[IMX6SX_CLK_CAN_SEL] = imx_clk_mux("can_sel", base + 0x20, 8, 2, can_sels, ARRAY_SIZE(can_sels)); imx6sx_clocks_init()
300 clks[IMX6SX_CLK_UART_SEL] = imx_clk_mux("uart_sel", base + 0x24, 6, 1, uart_sels, ARRAY_SIZE(uart_sels)); imx6sx_clocks_init()
301 clks[IMX6SX_CLK_QSPI2_SEL] = imx_clk_mux_flags("qspi2_sel", base + 0x2c, 15, 3, qspi2_sels, ARRAY_SIZE(qspi2_sels), CLK_SET_RATE_PARENT); imx6sx_clocks_init()
302 clks[IMX6SX_CLK_SPDIF_SEL] = imx_clk_mux("spdif_sel", base + 0x30, 20, 2, audio_sels, ARRAY_SIZE(audio_sels)); imx6sx_clocks_init()
303 clks[IMX6SX_CLK_AUDIO_SEL] = imx_clk_mux("audio_sel", base + 0x30, 7, 2, audio_sels, ARRAY_SIZE(audio_sels)); imx6sx_clocks_init()
304 clks[IMX6SX_CLK_ENET_PRE_SEL] = imx_clk_mux("enet_pre_sel", base + 0x34, 15, 3, enet_pre_sels, ARRAY_SIZE(enet_pre_sels)); imx6sx_clocks_init()
305 clks[IMX6SX_CLK_ENET_SEL] = imx_clk_mux("enet_sel", base + 0x34, 9, 3, enet_sels, ARRAY_SIZE(enet_sels)); imx6sx_clocks_init()
306 clks[IMX6SX_CLK_M4_PRE_SEL] = imx_clk_mux("m4_pre_sel", base + 0x34, 6, 3, m4_pre_sels, ARRAY_SIZE(m4_pre_sels)); imx6sx_clocks_init()
307 clks[IMX6SX_CLK_M4_SEL] = imx_clk_mux("m4_sel", base + 0x34, 0, 3, m4_sels, ARRAY_SIZE(m4_sels)); imx6sx_clocks_init()
308 clks[IMX6SX_CLK_ECSPI_SEL] = imx_clk_mux("ecspi_sel", base + 0x38, 18, 1, ecspi_sels, ARRAY_SIZE(ecspi_sels)); imx6sx_clocks_init()
309 clks[IMX6SX_CLK_LCDIF2_PRE_SEL] = imx_clk_mux("lcdif2_pre_sel", base + 0x38, 6, 3, lcdif2_pre_sels, ARRAY_SIZE(lcdif2_pre_sels)); imx6sx_clocks_init()
310 clks[IMX6SX_CLK_LCDIF2_SEL] = imx_clk_mux("lcdif2_sel", base + 0x38, 0, 3, lcdif2_sels, ARRAY_SIZE(lcdif2_sels)); imx6sx_clocks_init()
311 clks[IMX6SX_CLK_DISPLAY_SEL] = imx_clk_mux("display_sel", base + 0x3c, 14, 2, display_sels, ARRAY_SIZE(display_sels)); imx6sx_clocks_init()
312 clks[IMX6SX_CLK_CSI_SEL] = imx_clk_mux("csi_sel", base + 0x3c, 9, 2, csi_sels, ARRAY_SIZE(csi_sels)); imx6sx_clocks_init()
313 clks[IMX6SX_CLK_CKO1_SEL] = imx_clk_mux("cko1_sel", base + 0x60, 0, 4, cko1_sels, ARRAY_SIZE(cko1_sels)); imx6sx_clocks_init()
314 clks[IMX6SX_CLK_CKO2_SEL] = imx_clk_mux("cko2_sel", base + 0x60, 16, 5, cko2_sels, ARRAY_SIZE(cko2_sels)); imx6sx_clocks_init()
315 clks[IMX6SX_CLK_CKO] = imx_clk_mux("cko", base + 0x60, 8, 1, cko_sels, ARRAY_SIZE(cko_sels)); imx6sx_clocks_init()
317 clks[IMX6SX_CLK_LDB_DI1_DIV_SEL] = imx_clk_mux_flags("ldb_di1_div_sel", base + 0x20, 11, 1, ldb_di1_div_sels, ARRAY_SIZE(ldb_di1_div_sels), CLK_SET_RATE_PARENT); imx6sx_clocks_init()
318 clks[IMX6SX_CLK_LDB_DI0_DIV_SEL] = imx_clk_mux_flags("ldb_di0_div_sel", base + 0x20, 10, 1, ldb_di0_div_sels, ARRAY_SIZE(ldb_di0_div_sels), CLK_SET_RATE_PARENT); imx6sx_clocks_init()
319 clks[IMX6SX_CLK_LDB_DI1_SEL] = imx_clk_mux_flags("ldb_di1_sel", base + 0x2c, 12, 3, ldb_di1_sels, ARRAY_SIZE(ldb_di1_sels), CLK_SET_RATE_PARENT); imx6sx_clocks_init()
320 clks[IMX6SX_CLK_LDB_DI0_SEL] = imx_clk_mux_flags("ldb_di0_sel", base + 0x2c, 9, 3, ldb_di0_sels, ARRAY_SIZE(ldb_di0_sels), CLK_SET_RATE_PARENT); imx6sx_clocks_init()
321 clks[IMX6SX_CLK_LCDIF1_PRE_SEL] = imx_clk_mux_flags("lcdif1_pre_sel", base + 0x38, 15, 3, lcdif1_pre_sels, ARRAY_SIZE(lcdif1_pre_sels), CLK_SET_RATE_PARENT); imx6sx_clocks_init()
322 clks[IMX6SX_CLK_LCDIF1_SEL] = imx_clk_mux_flags("lcdif1_sel", base + 0x38, 9, 3, lcdif1_sels, ARRAY_SIZE(lcdif1_sels), CLK_SET_RATE_PARENT); imx6sx_clocks_init()
325 clks[IMX6SX_CLK_PERIPH_CLK2] = imx_clk_divider("periph_clk2", "periph_clk2_sel", base + 0x14, 27, 3); imx6sx_clocks_init()
326 clks[IMX6SX_CLK_PERIPH2_CLK2] = imx_clk_divider("periph2_clk2", "periph2_clk2_sel", base + 0x14, 0, 3); imx6sx_clocks_init()
327 clks[IMX6SX_CLK_IPG] = imx_clk_divider("ipg", "ahb", base + 0x14, 8, 2); imx6sx_clocks_init()
328 clks[IMX6SX_CLK_GPU_CORE_PODF] = imx_clk_divider("gpu_core_podf", "gpu_core_sel", base + 0x18, 29, 3); imx6sx_clocks_init()
329 clks[IMX6SX_CLK_GPU_AXI_PODF] = imx_clk_divider("gpu_axi_podf", "gpu_axi_sel", base + 0x18, 26, 3); imx6sx_clocks_init()
330 clks[IMX6SX_CLK_LCDIF1_PODF] = imx_clk_divider("lcdif1_podf", "lcdif1_pred", base + 0x18, 23, 3); imx6sx_clocks_init()
331 clks[IMX6SX_CLK_QSPI1_PODF] = imx_clk_divider("qspi1_podf", "qspi1_sel", base + 0x1c, 26, 3); imx6sx_clocks_init()
332 clks[IMX6SX_CLK_EIM_SLOW_PODF] = imx_clk_divider("eim_slow_podf", "eim_slow_sel", base + 0x1c, 23, 3); imx6sx_clocks_init()
333 clks[IMX6SX_CLK_LCDIF2_PODF] = imx_clk_divider("lcdif2_podf", "lcdif2_pred", base + 0x1c, 20, 3); imx6sx_clocks_init()
334 clks[IMX6SX_CLK_PERCLK] = imx_clk_divider("perclk", "perclk_sel", base + 0x1c, 0, 6); imx6sx_clocks_init()
335 clks[IMX6SX_CLK_VID_PODF] = imx_clk_divider("vid_podf", "vid_sel", base + 0x20, 24, 2); imx6sx_clocks_init()
336 clks[IMX6SX_CLK_CAN_PODF] = imx_clk_divider("can_podf", "can_sel", base + 0x20, 2, 6); imx6sx_clocks_init()
337 clks[IMX6SX_CLK_USDHC4_PODF] = imx_clk_divider("usdhc4_podf", "usdhc4_sel", base + 0x24, 22, 3); imx6sx_clocks_init()
338 clks[IMX6SX_CLK_USDHC3_PODF] = imx_clk_divider("usdhc3_podf", "usdhc3_sel", base + 0x24, 19, 3); imx6sx_clocks_init()
339 clks[IMX6SX_CLK_USDHC2_PODF] = imx_clk_divider("usdhc2_podf", "usdhc2_sel", base + 0x24, 16, 3); imx6sx_clocks_init()
340 clks[IMX6SX_CLK_USDHC1_PODF] = imx_clk_divider("usdhc1_podf", "usdhc1_sel", base + 0x24, 11, 3); imx6sx_clocks_init()
341 clks[IMX6SX_CLK_UART_PODF] = imx_clk_divider("uart_podf", "uart_sel", base + 0x24, 0, 6); imx6sx_clocks_init()
342 clks[IMX6SX_CLK_ESAI_PRED] = imx_clk_divider("esai_pred", "esai_sel", base + 0x28, 9, 3); imx6sx_clocks_init()
343 clks[IMX6SX_CLK_ESAI_PODF] = imx_clk_divider("esai_podf", "esai_pred", base + 0x28, 25, 3); imx6sx_clocks_init()
344 clks[IMX6SX_CLK_SSI3_PRED] = imx_clk_divider("ssi3_pred", "ssi3_sel", base + 0x28, 22, 3); imx6sx_clocks_init()
345 clks[IMX6SX_CLK_SSI3_PODF] = imx_clk_divider("ssi3_podf", "ssi3_pred", base + 0x28, 16, 6); imx6sx_clocks_init()
346 clks[IMX6SX_CLK_SSI1_PRED] = imx_clk_divider("ssi1_pred", "ssi1_sel", base + 0x28, 6, 3); imx6sx_clocks_init()
347 clks[IMX6SX_CLK_SSI1_PODF] = imx_clk_divider("ssi1_podf", "ssi1_pred", base + 0x28, 0, 6); imx6sx_clocks_init()
348 clks[IMX6SX_CLK_QSPI2_PRED] = imx_clk_divider("qspi2_pred", "qspi2_sel", base + 0x2c, 18, 3); imx6sx_clocks_init()
349 clks[IMX6SX_CLK_QSPI2_PODF] = imx_clk_divider("qspi2_podf", "qspi2_pred", base + 0x2c, 21, 6); imx6sx_clocks_init()
350 clks[IMX6SX_CLK_SSI2_PRED] = imx_clk_divider("ssi2_pred", "ssi2_sel", base + 0x2c, 6, 3); imx6sx_clocks_init()
351 clks[IMX6SX_CLK_SSI2_PODF] = imx_clk_divider("ssi2_podf", "ssi2_pred", base + 0x2c, 0, 6); imx6sx_clocks_init()
352 clks[IMX6SX_CLK_SPDIF_PRED] = imx_clk_divider("spdif_pred", "spdif_sel", base + 0x30, 25, 3); imx6sx_clocks_init()
353 clks[IMX6SX_CLK_SPDIF_PODF] = imx_clk_divider("spdif_podf", "spdif_pred", base + 0x30, 22, 3); imx6sx_clocks_init()
354 clks[IMX6SX_CLK_AUDIO_PRED] = imx_clk_divider("audio_pred", "audio_sel", base + 0x30, 12, 3); imx6sx_clocks_init()
355 clks[IMX6SX_CLK_AUDIO_PODF] = imx_clk_divider("audio_podf", "audio_pred", base + 0x30, 9, 3); imx6sx_clocks_init()
356 clks[IMX6SX_CLK_ENET_PODF] = imx_clk_divider("enet_podf", "enet_pre_sel", base + 0x34, 12, 3); imx6sx_clocks_init()
357 clks[IMX6SX_CLK_M4_PODF] = imx_clk_divider("m4_podf", "m4_sel", base + 0x34, 3, 3); imx6sx_clocks_init()
358 clks[IMX6SX_CLK_ECSPI_PODF] = imx_clk_divider("ecspi_podf", "ecspi_sel", base + 0x38, 19, 6); imx6sx_clocks_init()
359 clks[IMX6SX_CLK_LCDIF1_PRED] = imx_clk_divider("lcdif1_pred", "lcdif1_pre_sel", base + 0x38, 12, 3); imx6sx_clocks_init()
360 clks[IMX6SX_CLK_LCDIF2_PRED] = imx_clk_divider("lcdif2_pred", "lcdif2_pre_sel", base + 0x38, 3, 3); imx6sx_clocks_init()
361 clks[IMX6SX_CLK_DISPLAY_PODF] = imx_clk_divider("display_podf", "display_sel", base + 0x3c, 16, 3); imx6sx_clocks_init()
362 clks[IMX6SX_CLK_CSI_PODF] = imx_clk_divider("csi_podf", "csi_sel", base + 0x3c, 11, 3); imx6sx_clocks_init()
363 clks[IMX6SX_CLK_CKO1_PODF] = imx_clk_divider("cko1_podf", "cko1_sel", base + 0x60, 4, 3); imx6sx_clocks_init()
364 clks[IMX6SX_CLK_CKO2_PODF] = imx_clk_divider("cko2_podf", "cko2_sel", base + 0x60, 21, 3); imx6sx_clocks_init()
372 clks[IMX6SX_CLK_PERIPH] = imx_clk_busy_mux("periph", base + 0x14, 25, 1, base + 0x48, 5, periph_sels, ARRAY_SIZE(periph_sels)); imx6sx_clocks_init()
373 clks[IMX6SX_CLK_PERIPH2] = imx_clk_busy_mux("periph2", base + 0x14, 26, 1, base + 0x48, 3, periph2_sels, ARRAY_SIZE(periph2_sels)); imx6sx_clocks_init()
375 clks[IMX6SX_CLK_OCRAM_PODF] = imx_clk_busy_divider("ocram_podf", "ocram_sel", base + 0x14, 16, 3, base + 0x48, 0); imx6sx_clocks_init()
376 clks[IMX6SX_CLK_AHB] = imx_clk_busy_divider("ahb", "periph", base + 0x14, 10, 3, base + 0x48, 1); imx6sx_clocks_init()
377 clks[IMX6SX_CLK_MMDC_PODF] = imx_clk_busy_divider("mmdc_podf", "periph2", base + 0x14, 3, 3, base + 0x48, 2); imx6sx_clocks_init()
378 clks[IMX6SX_CLK_ARM] = imx_clk_busy_divider("arm", "pll1_sw", base + 0x10, 0, 3, base + 0x48, 16); imx6sx_clocks_init()
382 clks[IMX6SX_CLK_AIPS_TZ1] = imx_clk_gate2("aips_tz1", "ahb", base + 0x68, 0); imx6sx_clocks_init()
383 clks[IMX6SX_CLK_AIPS_TZ2] = imx_clk_gate2("aips_tz2", "ahb", base + 0x68, 2); imx6sx_clocks_init()
384 clks[IMX6SX_CLK_APBH_DMA] = imx_clk_gate2("apbh_dma", "usdhc3", base + 0x68, 4); imx6sx_clocks_init()
385 clks[IMX6SX_CLK_ASRC_MEM] = imx_clk_gate2_shared("asrc_mem", "ahb", base + 0x68, 6, &share_count_asrc); imx6sx_clocks_init()
386 clks[IMX6SX_CLK_ASRC_IPG] = imx_clk_gate2_shared("asrc_ipg", "ahb", base + 0x68, 6, &share_count_asrc); imx6sx_clocks_init()
387 clks[IMX6SX_CLK_CAAM_MEM] = imx_clk_gate2("caam_mem", "ahb", base + 0x68, 8); imx6sx_clocks_init()
388 clks[IMX6SX_CLK_CAAM_ACLK] = imx_clk_gate2("caam_aclk", "ahb", base + 0x68, 10); imx6sx_clocks_init()
389 clks[IMX6SX_CLK_CAAM_IPG] = imx_clk_gate2("caam_ipg", "ipg", base + 0x68, 12); imx6sx_clocks_init()
390 clks[IMX6SX_CLK_CAN1_IPG] = imx_clk_gate2("can1_ipg", "ipg", base + 0x68, 14); imx6sx_clocks_init()
391 clks[IMX6SX_CLK_CAN1_SERIAL] = imx_clk_gate2("can1_serial", "can_podf", base + 0x68, 16); imx6sx_clocks_init()
392 clks[IMX6SX_CLK_CAN2_IPG] = imx_clk_gate2("can2_ipg", "ipg", base + 0x68, 18); imx6sx_clocks_init()
393 clks[IMX6SX_CLK_CAN2_SERIAL] = imx_clk_gate2("can2_serial", "can_podf", base + 0x68, 20); imx6sx_clocks_init()
394 clks[IMX6SX_CLK_DCIC1] = imx_clk_gate2("dcic1", "display_podf", base + 0x68, 24); imx6sx_clocks_init()
395 clks[IMX6SX_CLK_DCIC2] = imx_clk_gate2("dcic2", "display_podf", base + 0x68, 26); imx6sx_clocks_init()
396 clks[IMX6SX_CLK_AIPS_TZ3] = imx_clk_gate2("aips_tz3", "ahb", base + 0x68, 30); imx6sx_clocks_init()
399 clks[IMX6SX_CLK_ECSPI1] = imx_clk_gate2("ecspi1", "ecspi_podf", base + 0x6c, 0); imx6sx_clocks_init()
400 clks[IMX6SX_CLK_ECSPI2] = imx_clk_gate2("ecspi2", "ecspi_podf", base + 0x6c, 2); imx6sx_clocks_init()
401 clks[IMX6SX_CLK_ECSPI3] = imx_clk_gate2("ecspi3", "ecspi_podf", base + 0x6c, 4); imx6sx_clocks_init()
402 clks[IMX6SX_CLK_ECSPI4] = imx_clk_gate2("ecspi4", "ecspi_podf", base + 0x6c, 6); imx6sx_clocks_init()
403 clks[IMX6SX_CLK_ECSPI5] = imx_clk_gate2("ecspi5", "ecspi_podf", base + 0x6c, 8); imx6sx_clocks_init()
404 clks[IMX6SX_CLK_EPIT1] = imx_clk_gate2("epit1", "perclk", base + 0x6c, 12); imx6sx_clocks_init()
405 clks[IMX6SX_CLK_EPIT2] = imx_clk_gate2("epit2", "perclk", base + 0x6c, 14); imx6sx_clocks_init()
406 clks[IMX6SX_CLK_ESAI_EXTAL] = imx_clk_gate2_shared("esai_extal", "esai_podf", base + 0x6c, 16, &share_count_esai); imx6sx_clocks_init()
407 clks[IMX6SX_CLK_ESAI_IPG] = imx_clk_gate2_shared("esai_ipg", "ahb", base + 0x6c, 16, &share_count_esai); imx6sx_clocks_init()
408 clks[IMX6SX_CLK_ESAI_MEM] = imx_clk_gate2_shared("esai_mem", "ahb", base + 0x6c, 16, &share_count_esai); imx6sx_clocks_init()
409 clks[IMX6SX_CLK_WAKEUP] = imx_clk_gate2("wakeup", "ipg", base + 0x6c, 18); imx6sx_clocks_init()
410 clks[IMX6SX_CLK_GPT_BUS] = imx_clk_gate2("gpt_bus", "perclk", base + 0x6c, 20); imx6sx_clocks_init()
411 clks[IMX6SX_CLK_GPT_SERIAL] = imx_clk_gate2("gpt_serial", "perclk", base + 0x6c, 22); imx6sx_clocks_init()
412 clks[IMX6SX_CLK_GPU] = imx_clk_gate2("gpu", "gpu_core_podf", base + 0x6c, 26); imx6sx_clocks_init()
413 clks[IMX6SX_CLK_CANFD] = imx_clk_gate2("canfd", "can_podf", base + 0x6c, 30); imx6sx_clocks_init()
416 clks[IMX6SX_CLK_CSI] = imx_clk_gate2("csi", "csi_podf", base + 0x70, 2); imx6sx_clocks_init()
417 clks[IMX6SX_CLK_I2C1] = imx_clk_gate2("i2c1", "perclk", base + 0x70, 6); imx6sx_clocks_init()
418 clks[IMX6SX_CLK_I2C2] = imx_clk_gate2("i2c2", "perclk", base + 0x70, 8); imx6sx_clocks_init()
419 clks[IMX6SX_CLK_I2C3] = imx_clk_gate2("i2c3", "perclk", base + 0x70, 10); imx6sx_clocks_init()
420 clks[IMX6SX_CLK_OCOTP] = imx_clk_gate2("ocotp", "ipg", base + 0x70, 12); imx6sx_clocks_init()
421 clks[IMX6SX_CLK_IOMUXC] = imx_clk_gate2("iomuxc", "lcdif1_podf", base + 0x70, 14); imx6sx_clocks_init()
422 clks[IMX6SX_CLK_IPMUX1] = imx_clk_gate2("ipmux1", "ahb", base + 0x70, 16); imx6sx_clocks_init()
423 clks[IMX6SX_CLK_IPMUX2] = imx_clk_gate2("ipmux2", "ahb", base + 0x70, 18); imx6sx_clocks_init()
424 clks[IMX6SX_CLK_IPMUX3] = imx_clk_gate2("ipmux3", "ahb", base + 0x70, 20); imx6sx_clocks_init()
425 clks[IMX6SX_CLK_TZASC1] = imx_clk_gate2("tzasc1", "mmdc_podf", base + 0x70, 22); imx6sx_clocks_init()
426 clks[IMX6SX_CLK_LCDIF_APB] = imx_clk_gate2("lcdif_apb", "display_podf", base + 0x70, 28); imx6sx_clocks_init()
427 clks[IMX6SX_CLK_PXP_AXI] = imx_clk_gate2("pxp_axi", "display_podf", base + 0x70, 30); imx6sx_clocks_init()
430 clks[IMX6SX_CLK_M4] = imx_clk_gate2("m4", "m4_podf", base + 0x74, 2); imx6sx_clocks_init()
431 clks[IMX6SX_CLK_ENET] = imx_clk_gate2("enet", "ipg", base + 0x74, 4); imx6sx_clocks_init()
432 clks[IMX6SX_CLK_ENET_AHB] = imx_clk_gate2("enet_ahb", "enet_sel", base + 0x74, 4); imx6sx_clocks_init()
433 clks[IMX6SX_CLK_DISPLAY_AXI] = imx_clk_gate2("display_axi", "display_podf", base + 0x74, 6); imx6sx_clocks_init()
434 clks[IMX6SX_CLK_LCDIF2_PIX] = imx_clk_gate2("lcdif2_pix", "lcdif2_sel", base + 0x74, 8); imx6sx_clocks_init()
435 clks[IMX6SX_CLK_LCDIF1_PIX] = imx_clk_gate2("lcdif1_pix", "lcdif1_sel", base + 0x74, 10); imx6sx_clocks_init()
436 clks[IMX6SX_CLK_LDB_DI0] = imx_clk_gate2("ldb_di0", "ldb_di0_div_sel", base + 0x74, 12); imx6sx_clocks_init()
437 clks[IMX6SX_CLK_QSPI1] = imx_clk_gate2("qspi1", "qspi1_podf", base + 0x74, 14); imx6sx_clocks_init()
438 clks[IMX6SX_CLK_MLB] = imx_clk_gate2("mlb", "ahb", base + 0x74, 18); imx6sx_clocks_init()
439 clks[IMX6SX_CLK_MMDC_P0_FAST] = imx_clk_gate2("mmdc_p0_fast", "mmdc_podf", base + 0x74, 20); imx6sx_clocks_init()
440 clks[IMX6SX_CLK_MMDC_P0_IPG] = imx_clk_gate2("mmdc_p0_ipg", "ipg", base + 0x74, 24); imx6sx_clocks_init()
441 clks[IMX6SX_CLK_OCRAM] = imx_clk_gate2("ocram", "ocram_podf", base + 0x74, 28); imx6sx_clocks_init()
444 clks[IMX6SX_CLK_PCIE_AXI] = imx_clk_gate2("pcie_axi", "display_podf", base + 0x78, 0); imx6sx_clocks_init()
445 clks[IMX6SX_CLK_QSPI2] = imx_clk_gate2("qspi2", "qspi2_podf", base + 0x78, 10); imx6sx_clocks_init()
446 clks[IMX6SX_CLK_PER1_BCH] = imx_clk_gate2("per1_bch", "usdhc3", base + 0x78, 12); imx6sx_clocks_init()
447 clks[IMX6SX_CLK_PER2_MAIN] = imx_clk_gate2("per2_main", "ahb", base + 0x78, 14); imx6sx_clocks_init()
448 clks[IMX6SX_CLK_PWM1] = imx_clk_gate2("pwm1", "perclk", base + 0x78, 16); imx6sx_clocks_init()
449 clks[IMX6SX_CLK_PWM2] = imx_clk_gate2("pwm2", "perclk", base + 0x78, 18); imx6sx_clocks_init()
450 clks[IMX6SX_CLK_PWM3] = imx_clk_gate2("pwm3", "perclk", base + 0x78, 20); imx6sx_clocks_init()
451 clks[IMX6SX_CLK_PWM4] = imx_clk_gate2("pwm4", "perclk", base + 0x78, 22); imx6sx_clocks_init()
452 clks[IMX6SX_CLK_GPMI_BCH_APB] = imx_clk_gate2("gpmi_bch_apb", "usdhc3", base + 0x78, 24); imx6sx_clocks_init()
453 clks[IMX6SX_CLK_GPMI_BCH] = imx_clk_gate2("gpmi_bch", "usdhc4", base + 0x78, 26); imx6sx_clocks_init()
454 clks[IMX6SX_CLK_GPMI_IO] = imx_clk_gate2("gpmi_io", "qspi2_podf", base + 0x78, 28); imx6sx_clocks_init()
455 clks[IMX6SX_CLK_GPMI_APB] = imx_clk_gate2("gpmi_apb", "usdhc3", base + 0x78, 30); imx6sx_clocks_init()
458 clks[IMX6SX_CLK_ROM] = imx_clk_gate2("rom", "ahb", base + 0x7c, 0); imx6sx_clocks_init()
459 clks[IMX6SX_CLK_SDMA] = imx_clk_gate2("sdma", "ahb", base + 0x7c, 6); imx6sx_clocks_init()
460 clks[IMX6SX_CLK_SPBA] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12); imx6sx_clocks_init()
461 clks[IMX6SX_CLK_AUDIO] = imx_clk_gate2_shared("audio", "audio_podf", base + 0x7c, 14, &share_count_audio); imx6sx_clocks_init()
462 clks[IMX6SX_CLK_SPDIF] = imx_clk_gate2_shared("spdif", "spdif_podf", base + 0x7c, 14, &share_count_audio); imx6sx_clocks_init()
463 clks[IMX6SX_CLK_SPDIF_GCLK] = imx_clk_gate2_shared("spdif_gclk", "ipg", base + 0x7c, 14, &share_count_audio); imx6sx_clocks_init()
464 clks[IMX6SX_CLK_SSI1_IPG] = imx_clk_gate2_shared("ssi1_ipg", "ipg", base + 0x7c, 18, &share_count_ssi1); imx6sx_clocks_init()
465 clks[IMX6SX_CLK_SSI2_IPG] = imx_clk_gate2_shared("ssi2_ipg", "ipg", base + 0x7c, 20, &share_count_ssi2); imx6sx_clocks_init()
466 clks[IMX6SX_CLK_SSI3_IPG] = imx_clk_gate2_shared("ssi3_ipg", "ipg", base + 0x7c, 22, &share_count_ssi3); imx6sx_clocks_init()
467 clks[IMX6SX_CLK_SSI1] = imx_clk_gate2_shared("ssi1", "ssi1_podf", base + 0x7c, 18, &share_count_ssi1); imx6sx_clocks_init()
468 clks[IMX6SX_CLK_SSI2] = imx_clk_gate2_shared("ssi2", "ssi2_podf", base + 0x7c, 20, &share_count_ssi2); imx6sx_clocks_init()
469 clks[IMX6SX_CLK_SSI3] = imx_clk_gate2_shared("ssi3", "ssi3_podf", base + 0x7c, 22, &share_count_ssi3); imx6sx_clocks_init()
470 clks[IMX6SX_CLK_UART_IPG] = imx_clk_gate2("uart_ipg", "ipg", base + 0x7c, 24); imx6sx_clocks_init()
471 clks[IMX6SX_CLK_UART_SERIAL] = imx_clk_gate2("uart_serial", "uart_podf", base + 0x7c, 26); imx6sx_clocks_init()
472 clks[IMX6SX_CLK_SAI1_IPG] = imx_clk_gate2("sai1_ipg", "ipg", base + 0x7c, 28); imx6sx_clocks_init()
473 clks[IMX6SX_CLK_SAI2_IPG] = imx_clk_gate2("sai2_ipg", "ipg", base + 0x7c, 30); imx6sx_clocks_init()
474 clks[IMX6SX_CLK_SAI1] = imx_clk_gate2("sai1", "ssi1_podf", base + 0x7c, 28); imx6sx_clocks_init()
475 clks[IMX6SX_CLK_SAI2] = imx_clk_gate2("sai2", "ssi2_podf", base + 0x7c, 30); imx6sx_clocks_init()
478 clks[IMX6SX_CLK_USBOH3] = imx_clk_gate2("usboh3", "ipg", base + 0x80, 0); imx6sx_clocks_init()
479 clks[IMX6SX_CLK_USDHC1] = imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2); imx6sx_clocks_init()
480 clks[IMX6SX_CLK_USDHC2] = imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4); imx6sx_clocks_init()
481 clks[IMX6SX_CLK_USDHC3] = imx_clk_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6); imx6sx_clocks_init()
482 clks[IMX6SX_CLK_USDHC4] = imx_clk_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8); imx6sx_clocks_init()
483 clks[IMX6SX_CLK_EIM_SLOW] = imx_clk_gate2("eim_slow", "eim_slow_podf", base + 0x80, 10); imx6sx_clocks_init()
484 clks[IMX6SX_CLK_PWM8] = imx_clk_gate2("pwm8", "perclk", base + 0x80, 16); imx6sx_clocks_init()
485 clks[IMX6SX_CLK_VADC] = imx_clk_gate2("vadc", "vid_podf", base + 0x80, 20); imx6sx_clocks_init()
486 clks[IMX6SX_CLK_GIS] = imx_clk_gate2("gis", "display_podf", base + 0x80, 22); imx6sx_clocks_init()
487 clks[IMX6SX_CLK_I2C4] = imx_clk_gate2("i2c4", "perclk", base + 0x80, 24); imx6sx_clocks_init()
488 clks[IMX6SX_CLK_PWM5] = imx_clk_gate2("pwm5", "perclk", base + 0x80, 26); imx6sx_clocks_init()
489 clks[IMX6SX_CLK_PWM6] = imx_clk_gate2("pwm6", "perclk", base + 0x80, 28); imx6sx_clocks_init()
490 clks[IMX6SX_CLK_PWM7] = imx_clk_gate2("pwm7", "perclk", base + 0x80, 30); imx6sx_clocks_init()
492 clks[IMX6SX_CLK_CKO1] = imx_clk_gate("cko1", "cko1_podf", base + 0x60, 7); imx6sx_clocks_init()
493 clks[IMX6SX_CLK_CKO2] = imx_clk_gate("cko2", "cko2_podf", base + 0x60, 24); imx6sx_clocks_init()
496 writel_relaxed(BM_CCM_CCDR_MMDC_CH0_MASK, base + CCDR); imx6sx_clocks_init()
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| H A D | clk-imx6q.c | 143 void __iomem *base; imx6q_clocks_init() local
156 base = of_iomap(np, 0); imx6q_clocks_init()
157 WARN_ON(!base); imx6q_clocks_init()
167 clk[IMX6QDL_PLL1_BYPASS_SRC] = imx_clk_mux("pll1_bypass_src", base + 0x00, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); imx6q_clocks_init()
168 clk[IMX6QDL_PLL2_BYPASS_SRC] = imx_clk_mux("pll2_bypass_src", base + 0x30, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); imx6q_clocks_init()
169 clk[IMX6QDL_PLL3_BYPASS_SRC] = imx_clk_mux("pll3_bypass_src", base + 0x10, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); imx6q_clocks_init()
170 clk[IMX6QDL_PLL4_BYPASS_SRC] = imx_clk_mux("pll4_bypass_src", base + 0x70, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); imx6q_clocks_init()
171 clk[IMX6QDL_PLL5_BYPASS_SRC] = imx_clk_mux("pll5_bypass_src", base + 0xa0, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); imx6q_clocks_init()
172 clk[IMX6QDL_PLL6_BYPASS_SRC] = imx_clk_mux("pll6_bypass_src", base + 0xe0, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); imx6q_clocks_init()
173 clk[IMX6QDL_PLL7_BYPASS_SRC] = imx_clk_mux("pll7_bypass_src", base + 0x20, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); imx6q_clocks_init()
175 /* type name parent_name base div_mask */ imx6q_clocks_init()
176 clk[IMX6QDL_CLK_PLL1] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1", "pll1_bypass_src", base + 0x00, 0x7f); imx6q_clocks_init()
177 clk[IMX6QDL_CLK_PLL2] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2", "pll2_bypass_src", base + 0x30, 0x1); imx6q_clocks_init()
178 clk[IMX6QDL_CLK_PLL3] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3", "pll3_bypass_src", base + 0x10, 0x3); imx6q_clocks_init()
179 clk[IMX6QDL_CLK_PLL4] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4", "pll4_bypass_src", base + 0x70, 0x7f); imx6q_clocks_init()
180 clk[IMX6QDL_CLK_PLL5] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5", "pll5_bypass_src", base + 0xa0, 0x7f); imx6q_clocks_init()
181 clk[IMX6QDL_CLK_PLL6] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6", "pll6_bypass_src", base + 0xe0, 0x3); imx6q_clocks_init()
182 clk[IMX6QDL_CLK_PLL7] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7", "pll7_bypass_src", base + 0x20, 0x3); imx6q_clocks_init()
184 clk[IMX6QDL_PLL1_BYPASS] = imx_clk_mux_flags("pll1_bypass", base + 0x00, 16, 1, pll1_bypass_sels, ARRAY_SIZE(pll1_bypass_sels), CLK_SET_RATE_PARENT); imx6q_clocks_init()
185 clk[IMX6QDL_PLL2_BYPASS] = imx_clk_mux_flags("pll2_bypass", base + 0x30, 16, 1, pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), CLK_SET_RATE_PARENT); imx6q_clocks_init()
186 clk[IMX6QDL_PLL3_BYPASS] = imx_clk_mux_flags("pll3_bypass", base + 0x10, 16, 1, pll3_bypass_sels, ARRAY_SIZE(pll3_bypass_sels), CLK_SET_RATE_PARENT); imx6q_clocks_init()
187 clk[IMX6QDL_PLL4_BYPASS] = imx_clk_mux_flags("pll4_bypass", base + 0x70, 16, 1, pll4_bypass_sels, ARRAY_SIZE(pll4_bypass_sels), CLK_SET_RATE_PARENT); imx6q_clocks_init()
188 clk[IMX6QDL_PLL5_BYPASS] = imx_clk_mux_flags("pll5_bypass", base + 0xa0, 16, 1, pll5_bypass_sels, ARRAY_SIZE(pll5_bypass_sels), CLK_SET_RATE_PARENT); imx6q_clocks_init()
189 clk[IMX6QDL_PLL6_BYPASS] = imx_clk_mux_flags("pll6_bypass", base + 0xe0, 16, 1, pll6_bypass_sels, ARRAY_SIZE(pll6_bypass_sels), CLK_SET_RATE_PARENT); imx6q_clocks_init()
190 clk[IMX6QDL_PLL7_BYPASS] = imx_clk_mux_flags("pll7_bypass", base + 0x20, 16, 1, pll7_bypass_sels, ARRAY_SIZE(pll7_bypass_sels), CLK_SET_RATE_PARENT); imx6q_clocks_init()
201 clk[IMX6QDL_CLK_PLL1_SYS] = imx_clk_gate("pll1_sys", "pll1_bypass", base + 0x00, 13); imx6q_clocks_init()
202 clk[IMX6QDL_CLK_PLL2_BUS] = imx_clk_gate("pll2_bus", "pll2_bypass", base + 0x30, 13); imx6q_clocks_init()
203 clk[IMX6QDL_CLK_PLL3_USB_OTG] = imx_clk_gate("pll3_usb_otg", "pll3_bypass", base + 0x10, 13); imx6q_clocks_init()
204 clk[IMX6QDL_CLK_PLL4_AUDIO] = imx_clk_gate("pll4_audio", "pll4_bypass", base + 0x70, 13); imx6q_clocks_init()
205 clk[IMX6QDL_CLK_PLL5_VIDEO] = imx_clk_gate("pll5_video", "pll5_bypass", base + 0xa0, 13); imx6q_clocks_init()
206 clk[IMX6QDL_CLK_PLL6_ENET] = imx_clk_gate("pll6_enet", "pll6_bypass", base + 0xe0, 13); imx6q_clocks_init()
207 clk[IMX6QDL_CLK_PLL7_USB_HOST] = imx_clk_gate("pll7_usb_host", "pll7_bypass", base + 0x20, 13); imx6q_clocks_init()
215 clk[IMX6QDL_CLK_USBPHY1] = imx_clk_gate("usbphy1", "pll3_usb_otg", base + 0x10, 20); imx6q_clocks_init()
216 clk[IMX6QDL_CLK_USBPHY2] = imx_clk_gate("usbphy2", "pll7_usb_host", base + 0x20, 20); imx6q_clocks_init()
222 clk[IMX6QDL_CLK_USBPHY1_GATE] = imx_clk_gate("usbphy1_gate", "dummy", base + 0x10, 6); imx6q_clocks_init()
223 clk[IMX6QDL_CLK_USBPHY2_GATE] = imx_clk_gate("usbphy2_gate", "dummy", base + 0x20, 6); imx6q_clocks_init()
228 clk[IMX6QDL_CLK_SATA_REF_100M] = imx_clk_gate("sata_ref_100m", "sata_ref", base + 0xe0, 20); imx6q_clocks_init()
229 clk[IMX6QDL_CLK_PCIE_REF_125M] = imx_clk_gate("pcie_ref_125m", "pcie_ref", base + 0xe0, 19); imx6q_clocks_init()
232 base + 0xe0, 0, 2, 0, clk_enet_ref_table, imx6q_clocks_init()
235 clk[IMX6QDL_CLK_LVDS1_SEL] = imx_clk_mux("lvds1_sel", base + 0x160, 0, 5, lvds_sels, ARRAY_SIZE(lvds_sels)); imx6q_clocks_init()
236 clk[IMX6QDL_CLK_LVDS2_SEL] = imx_clk_mux("lvds2_sel", base + 0x160, 5, 5, lvds_sels, ARRAY_SIZE(lvds_sels)); imx6q_clocks_init()
244 clk[IMX6QDL_CLK_LVDS1_GATE] = imx_clk_gate_exclusive("lvds1_gate", "lvds1_sel", base + 0x160, 10, BIT(12)); imx6q_clocks_init()
245 clk[IMX6QDL_CLK_LVDS2_GATE] = imx_clk_gate_exclusive("lvds2_gate", "lvds2_sel", base + 0x160, 11, BIT(13)); imx6q_clocks_init()
247 clk[IMX6QDL_CLK_LVDS1_IN] = imx_clk_gate_exclusive("lvds1_in", "anaclk1", base + 0x160, 12, BIT(10)); imx6q_clocks_init()
248 clk[IMX6QDL_CLK_LVDS2_IN] = imx_clk_gate_exclusive("lvds2_in", "anaclk2", base + 0x160, 13, BIT(11)); imx6q_clocks_init()
251 clk[IMX6QDL_CLK_PLL2_PFD0_352M] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0); imx6q_clocks_init()
252 clk[IMX6QDL_CLK_PLL2_PFD1_594M] = imx_clk_pfd("pll2_pfd1_594m", "pll2_bus", base + 0x100, 1); imx6q_clocks_init()
253 clk[IMX6QDL_CLK_PLL2_PFD2_396M] = imx_clk_pfd("pll2_pfd2_396m", "pll2_bus", base + 0x100, 2); imx6q_clocks_init()
254 clk[IMX6QDL_CLK_PLL3_PFD0_720M] = imx_clk_pfd("pll3_pfd0_720m", "pll3_usb_otg", base + 0xf0, 0); imx6q_clocks_init()
255 clk[IMX6QDL_CLK_PLL3_PFD1_540M] = imx_clk_pfd("pll3_pfd1_540m", "pll3_usb_otg", base + 0xf0, 1); imx6q_clocks_init()
256 clk[IMX6QDL_CLK_PLL3_PFD2_508M] = imx_clk_pfd("pll3_pfd2_508m", "pll3_usb_otg", base + 0xf0, 2); imx6q_clocks_init()
257 clk[IMX6QDL_CLK_PLL3_PFD3_454M] = imx_clk_pfd("pll3_pfd3_454m", "pll3_usb_otg", base + 0xf0, 3); imx6q_clocks_init()
272 clk[IMX6QDL_CLK_PLL4_POST_DIV] = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock); imx6q_clocks_init()
273 clk[IMX6QDL_CLK_PLL4_AUDIO_DIV] = clk_register_divider(NULL, "pll4_audio_div", "pll4_post_div", CLK_SET_RATE_PARENT, base + 0x170, 15, 1, 0, &imx_ccm_lock); imx6q_clocks_init()
274 clk[IMX6QDL_CLK_PLL5_POST_DIV] = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock); imx6q_clocks_init()
275 clk[IMX6QDL_CLK_PLL5_VIDEO_DIV] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock); imx6q_clocks_init()
278 base = of_iomap(np, 0); imx6q_clocks_init()
279 WARN_ON(!base); imx6q_clocks_init()
282 clk[IMX6QDL_CLK_STEP] = imx_clk_mux("step", base + 0xc, 8, 1, step_sels, ARRAY_SIZE(step_sels)); imx6q_clocks_init()
283 clk[IMX6QDL_CLK_PLL1_SW] = imx_clk_mux("pll1_sw", base + 0xc, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels)); imx6q_clocks_init()
284 clk[IMX6QDL_CLK_PERIPH_PRE] = imx_clk_mux("periph_pre", base + 0x18, 18, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels)); imx6q_clocks_init()
285 clk[IMX6QDL_CLK_PERIPH2_PRE] = imx_clk_mux("periph2_pre", base + 0x18, 21, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels)); imx6q_clocks_init()
286 clk[IMX6QDL_CLK_PERIPH_CLK2_SEL] = imx_clk_mux("periph_clk2_sel", base + 0x18, 12, 2, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels)); imx6q_clocks_init()
287 clk[IMX6QDL_CLK_PERIPH2_CLK2_SEL] = imx_clk_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels)); imx6q_clocks_init()
288 clk[IMX6QDL_CLK_AXI_SEL] = imx_clk_mux("axi_sel", base + 0x14, 6, 2, axi_sels, ARRAY_SIZE(axi_sels)); imx6q_clocks_init()
289 clk[IMX6QDL_CLK_ESAI_SEL] = imx_clk_mux("esai_sel", base + 0x20, 19, 2, audio_sels, ARRAY_SIZE(audio_sels)); imx6q_clocks_init()
290 clk[IMX6QDL_CLK_ASRC_SEL] = imx_clk_mux("asrc_sel", base + 0x30, 7, 2, audio_sels, ARRAY_SIZE(audio_sels)); imx6q_clocks_init()
291 clk[IMX6QDL_CLK_SPDIF_SEL] = imx_clk_mux("spdif_sel", base + 0x30, 20, 2, audio_sels, ARRAY_SIZE(audio_sels)); imx6q_clocks_init()
293 clk[IMX6QDL_CLK_GPU2D_AXI] = imx_clk_mux("gpu2d_axi", base + 0x18, 0, 1, gpu_axi_sels, ARRAY_SIZE(gpu_axi_sels)); imx6q_clocks_init()
294 clk[IMX6QDL_CLK_GPU3D_AXI] = imx_clk_mux("gpu3d_axi", base + 0x18, 1, 1, gpu_axi_sels, ARRAY_SIZE(gpu_axi_sels)); imx6q_clocks_init()
296 clk[IMX6QDL_CLK_GPU2D_CORE_SEL] = imx_clk_mux("gpu2d_core_sel", base + 0x18, 16, 2, gpu2d_core_sels, ARRAY_SIZE(gpu2d_core_sels)); imx6q_clocks_init()
297 clk[IMX6QDL_CLK_GPU3D_CORE_SEL] = imx_clk_mux("gpu3d_core_sel", base + 0x18, 4, 2, gpu3d_core_sels, ARRAY_SIZE(gpu3d_core_sels)); imx6q_clocks_init()
298 clk[IMX6QDL_CLK_GPU3D_SHADER_SEL] = imx_clk_mux("gpu3d_shader_sel", base + 0x18, 8, 2, gpu3d_shader_sels, ARRAY_SIZE(gpu3d_shader_sels)); imx6q_clocks_init()
299 clk[IMX6QDL_CLK_IPU1_SEL] = imx_clk_mux("ipu1_sel", base + 0x3c, 9, 2, ipu_sels, ARRAY_SIZE(ipu_sels)); imx6q_clocks_init()
300 clk[IMX6QDL_CLK_IPU2_SEL] = imx_clk_mux("ipu2_sel", base + 0x3c, 14, 2, ipu_sels, ARRAY_SIZE(ipu_sels)); imx6q_clocks_init()
301 clk[IMX6QDL_CLK_LDB_DI0_SEL] = imx_clk_mux_flags("ldb_di0_sel", base + 0x2c, 9, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT); imx6q_clocks_init()
302 clk[IMX6QDL_CLK_LDB_DI1_SEL] = imx_clk_mux_flags("ldb_di1_sel", base + 0x2c, 12, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT); imx6q_clocks_init()
303 clk[IMX6QDL_CLK_IPU1_DI0_PRE_SEL] = imx_clk_mux_flags("ipu1_di0_pre_sel", base + 0x34, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT); imx6q_clocks_init()
304 clk[IMX6QDL_CLK_IPU1_DI1_PRE_SEL] = imx_clk_mux_flags("ipu1_di1_pre_sel", base + 0x34, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT); imx6q_clocks_init()
305 clk[IMX6QDL_CLK_IPU2_DI0_PRE_SEL] = imx_clk_mux_flags("ipu2_di0_pre_sel", base + 0x38, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT); imx6q_clocks_init()
306 clk[IMX6QDL_CLK_IPU2_DI1_PRE_SEL] = imx_clk_mux_flags("ipu2_di1_pre_sel", base + 0x38, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT); imx6q_clocks_init()
307 clk[IMX6QDL_CLK_IPU1_DI0_SEL] = imx_clk_mux_flags("ipu1_di0_sel", base + 0x34, 0, 3, ipu1_di0_sels, ARRAY_SIZE(ipu1_di0_sels), CLK_SET_RATE_PARENT); imx6q_clocks_init()
308 clk[IMX6QDL_CLK_IPU1_DI1_SEL] = imx_clk_mux_flags("ipu1_di1_sel", base + 0x34, 9, 3, ipu1_di1_sels, ARRAY_SIZE(ipu1_di1_sels), CLK_SET_RATE_PARENT); imx6q_clocks_init()
309 clk[IMX6QDL_CLK_IPU2_DI0_SEL] = imx_clk_mux_flags("ipu2_di0_sel", base + 0x38, 0, 3, ipu2_di0_sels, ARRAY_SIZE(ipu2_di0_sels), CLK_SET_RATE_PARENT); imx6q_clocks_init()
310 clk[IMX6QDL_CLK_IPU2_DI1_SEL] = imx_clk_mux_flags("ipu2_di1_sel", base + 0x38, 9, 3, ipu2_di1_sels, ARRAY_SIZE(ipu2_di1_sels), CLK_SET_RATE_PARENT); imx6q_clocks_init()
311 clk[IMX6QDL_CLK_HSI_TX_SEL] = imx_clk_mux("hsi_tx_sel", base + 0x30, 28, 1, hsi_tx_sels, ARRAY_SIZE(hsi_tx_sels)); imx6q_clocks_init()
312 clk[IMX6QDL_CLK_PCIE_AXI_SEL] = imx_clk_mux("pcie_axi_sel", base + 0x18, 10, 1, pcie_axi_sels, ARRAY_SIZE(pcie_axi_sels)); imx6q_clocks_init()
313 clk[IMX6QDL_CLK_SSI1_SEL] = imx_clk_fixup_mux("ssi1_sel", base + 0x1c, 10, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup); imx6q_clocks_init()
314 clk[IMX6QDL_CLK_SSI2_SEL] = imx_clk_fixup_mux("ssi2_sel", base + 0x1c, 12, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup); imx6q_clocks_init()
315 clk[IMX6QDL_CLK_SSI3_SEL] = imx_clk_fixup_mux("ssi3_sel", base + 0x1c, 14, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup); imx6q_clocks_init()
316 clk[IMX6QDL_CLK_USDHC1_SEL] = imx_clk_fixup_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); imx6q_clocks_init()
317 clk[IMX6QDL_CLK_USDHC2_SEL] = imx_clk_fixup_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); imx6q_clocks_init()
318 clk[IMX6QDL_CLK_USDHC3_SEL] = imx_clk_fixup_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); imx6q_clocks_init()
319 clk[IMX6QDL_CLK_USDHC4_SEL] = imx_clk_fixup_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); imx6q_clocks_init()
320 clk[IMX6QDL_CLK_ENFC_SEL] = imx_clk_mux("enfc_sel", base + 0x2c, 16, 2, enfc_sels, ARRAY_SIZE(enfc_sels)); imx6q_clocks_init()
321 clk[IMX6QDL_CLK_EIM_SEL] = imx_clk_fixup_mux("eim_sel", base + 0x1c, 27, 2, eim_sels, ARRAY_SIZE(eim_sels), imx_cscmr1_fixup); imx6q_clocks_init()
322 clk[IMX6QDL_CLK_EIM_SLOW_SEL] = imx_clk_fixup_mux("eim_slow_sel", base + 0x1c, 29, 2, eim_slow_sels, ARRAY_SIZE(eim_slow_sels), imx_cscmr1_fixup); imx6q_clocks_init()
323 clk[IMX6QDL_CLK_VDO_AXI_SEL] = imx_clk_mux("vdo_axi_sel", base + 0x18, 11, 1, vdo_axi_sels, ARRAY_SIZE(vdo_axi_sels)); imx6q_clocks_init()
324 clk[IMX6QDL_CLK_VPU_AXI_SEL] = imx_clk_mux("vpu_axi_sel", base + 0x18, 14, 2, vpu_axi_sels, ARRAY_SIZE(vpu_axi_sels)); imx6q_clocks_init()
325 clk[IMX6QDL_CLK_CKO1_SEL] = imx_clk_mux("cko1_sel", base + 0x60, 0, 4, cko1_sels, ARRAY_SIZE(cko1_sels)); imx6q_clocks_init()
326 clk[IMX6QDL_CLK_CKO2_SEL] = imx_clk_mux("cko2_sel", base + 0x60, 16, 5, cko2_sels, ARRAY_SIZE(cko2_sels)); imx6q_clocks_init()
327 clk[IMX6QDL_CLK_CKO] = imx_clk_mux("cko", base + 0x60, 8, 1, cko_sels, ARRAY_SIZE(cko_sels)); imx6q_clocks_init()
330 clk[IMX6QDL_CLK_PERIPH] = imx_clk_busy_mux("periph", base + 0x14, 25, 1, base + 0x48, 5, periph_sels, ARRAY_SIZE(periph_sels)); imx6q_clocks_init()
331 clk[IMX6QDL_CLK_PERIPH2] = imx_clk_busy_mux("periph2", base + 0x14, 26, 1, base + 0x48, 3, periph2_sels, ARRAY_SIZE(periph2_sels)); imx6q_clocks_init()
334 clk[IMX6QDL_CLK_PERIPH_CLK2] = imx_clk_divider("periph_clk2", "periph_clk2_sel", base + 0x14, 27, 3); imx6q_clocks_init()
335 clk[IMX6QDL_CLK_PERIPH2_CLK2] = imx_clk_divider("periph2_clk2", "periph2_clk2_sel", base + 0x14, 0, 3); imx6q_clocks_init()
336 clk[IMX6QDL_CLK_IPG] = imx_clk_divider("ipg", "ahb", base + 0x14, 8, 2); imx6q_clocks_init()
337 clk[IMX6QDL_CLK_IPG_PER] = imx_clk_fixup_divider("ipg_per", "ipg", base + 0x1c, 0, 6, imx_cscmr1_fixup); imx6q_clocks_init()
338 clk[IMX6QDL_CLK_ESAI_PRED] = imx_clk_divider("esai_pred", "esai_sel", base + 0x28, 9, 3); imx6q_clocks_init()
339 clk[IMX6QDL_CLK_ESAI_PODF] = imx_clk_divider("esai_podf", "esai_pred", base + 0x28, 25, 3); imx6q_clocks_init()
340 clk[IMX6QDL_CLK_ASRC_PRED] = imx_clk_divider("asrc_pred", "asrc_sel", base + 0x30, 12, 3); imx6q_clocks_init()
341 clk[IMX6QDL_CLK_ASRC_PODF] = imx_clk_divider("asrc_podf", "asrc_pred", base + 0x30, 9, 3); imx6q_clocks_init()
342 clk[IMX6QDL_CLK_SPDIF_PRED] = imx_clk_divider("spdif_pred", "spdif_sel", base + 0x30, 25, 3); imx6q_clocks_init()
343 clk[IMX6QDL_CLK_SPDIF_PODF] = imx_clk_divider("spdif_podf", "spdif_pred", base + 0x30, 22, 3); imx6q_clocks_init()
344 clk[IMX6QDL_CLK_CAN_ROOT] = imx_clk_divider("can_root", "pll3_60m", base + 0x20, 2, 6); imx6q_clocks_init()
345 clk[IMX6QDL_CLK_ECSPI_ROOT] = imx_clk_divider("ecspi_root", "pll3_60m", base + 0x38, 19, 6); imx6q_clocks_init()
346 clk[IMX6QDL_CLK_GPU2D_CORE_PODF] = imx_clk_divider("gpu2d_core_podf", "gpu2d_core_sel", base + 0x18, 23, 3); imx6q_clocks_init()
347 clk[IMX6QDL_CLK_GPU3D_CORE_PODF] = imx_clk_divider("gpu3d_core_podf", "gpu3d_core_sel", base + 0x18, 26, 3); imx6q_clocks_init()
348 clk[IMX6QDL_CLK_GPU3D_SHADER] = imx_clk_divider("gpu3d_shader", "gpu3d_shader_sel", base + 0x18, 29, 3); imx6q_clocks_init()
349 clk[IMX6QDL_CLK_IPU1_PODF] = imx_clk_divider("ipu1_podf", "ipu1_sel", base + 0x3c, 11, 3); imx6q_clocks_init()
350 clk[IMX6QDL_CLK_IPU2_PODF] = imx_clk_divider("ipu2_podf", "ipu2_sel", base + 0x3c, 16, 3); imx6q_clocks_init()
352 clk[IMX6QDL_CLK_LDB_DI0_PODF] = imx_clk_divider_flags("ldb_di0_podf", "ldb_di0_div_3_5", base + 0x20, 10, 1, 0); imx6q_clocks_init()
354 clk[IMX6QDL_CLK_LDB_DI1_PODF] = imx_clk_divider_flags("ldb_di1_podf", "ldb_di1_div_3_5", base + 0x20, 11, 1, 0); imx6q_clocks_init()
355 clk[IMX6QDL_CLK_IPU1_DI0_PRE] = imx_clk_divider("ipu1_di0_pre", "ipu1_di0_pre_sel", base + 0x34, 3, 3); imx6q_clocks_init()
356 clk[IMX6QDL_CLK_IPU1_DI1_PRE] = imx_clk_divider("ipu1_di1_pre", "ipu1_di1_pre_sel", base + 0x34, 12, 3); imx6q_clocks_init()
357 clk[IMX6QDL_CLK_IPU2_DI0_PRE] = imx_clk_divider("ipu2_di0_pre", "ipu2_di0_pre_sel", base + 0x38, 3, 3); imx6q_clocks_init()
358 clk[IMX6QDL_CLK_IPU2_DI1_PRE] = imx_clk_divider("ipu2_di1_pre", "ipu2_di1_pre_sel", base + 0x38, 12, 3); imx6q_clocks_init()
359 clk[IMX6QDL_CLK_HSI_TX_PODF] = imx_clk_divider("hsi_tx_podf", "hsi_tx_sel", base + 0x30, 29, 3); imx6q_clocks_init()
360 clk[IMX6QDL_CLK_SSI1_PRED] = imx_clk_divider("ssi1_pred", "ssi1_sel", base + 0x28, 6, 3); imx6q_clocks_init()
361 clk[IMX6QDL_CLK_SSI1_PODF] = imx_clk_divider("ssi1_podf", "ssi1_pred", base + 0x28, 0, 6); imx6q_clocks_init()
362 clk[IMX6QDL_CLK_SSI2_PRED] = imx_clk_divider("ssi2_pred", "ssi2_sel", base + 0x2c, 6, 3); imx6q_clocks_init()
363 clk[IMX6QDL_CLK_SSI2_PODF] = imx_clk_divider("ssi2_podf", "ssi2_pred", base + 0x2c, 0, 6); imx6q_clocks_init()
364 clk[IMX6QDL_CLK_SSI3_PRED] = imx_clk_divider("ssi3_pred", "ssi3_sel", base + 0x28, 22, 3); imx6q_clocks_init()
365 clk[IMX6QDL_CLK_SSI3_PODF] = imx_clk_divider("ssi3_podf", "ssi3_pred", base + 0x28, 16, 6); imx6q_clocks_init()
366 clk[IMX6QDL_CLK_UART_SERIAL_PODF] = imx_clk_divider("uart_serial_podf", "pll3_80m", base + 0x24, 0, 6); imx6q_clocks_init()
367 clk[IMX6QDL_CLK_USDHC1_PODF] = imx_clk_divider("usdhc1_podf", "usdhc1_sel", base + 0x24, 11, 3); imx6q_clocks_init()
368 clk[IMX6QDL_CLK_USDHC2_PODF] = imx_clk_divider("usdhc2_podf", "usdhc2_sel", base + 0x24, 16, 3); imx6q_clocks_init()
369 clk[IMX6QDL_CLK_USDHC3_PODF] = imx_clk_divider("usdhc3_podf", "usdhc3_sel", base + 0x24, 19, 3); imx6q_clocks_init()
370 clk[IMX6QDL_CLK_USDHC4_PODF] = imx_clk_divider("usdhc4_podf", "usdhc4_sel", base + 0x24, 22, 3); imx6q_clocks_init()
371 clk[IMX6QDL_CLK_ENFC_PRED] = imx_clk_divider("enfc_pred", "enfc_sel", base + 0x2c, 18, 3); imx6q_clocks_init()
372 clk[IMX6QDL_CLK_ENFC_PODF] = imx_clk_divider("enfc_podf", "enfc_pred", base + 0x2c, 21, 6); imx6q_clocks_init()
373 clk[IMX6QDL_CLK_EIM_PODF] = imx_clk_fixup_divider("eim_podf", "eim_sel", base + 0x1c, 20, 3, imx_cscmr1_fixup); imx6q_clocks_init()
374 clk[IMX6QDL_CLK_EIM_SLOW_PODF] = imx_clk_fixup_divider("eim_slow_podf", "eim_slow_sel", base + 0x1c, 23, 3, imx_cscmr1_fixup); imx6q_clocks_init()
375 clk[IMX6QDL_CLK_VPU_AXI_PODF] = imx_clk_divider("vpu_axi_podf", "vpu_axi_sel", base + 0x24, 25, 3); imx6q_clocks_init()
376 clk[IMX6QDL_CLK_CKO1_PODF] = imx_clk_divider("cko1_podf", "cko1_sel", base + 0x60, 4, 3); imx6q_clocks_init()
377 clk[IMX6QDL_CLK_CKO2_PODF] = imx_clk_divider("cko2_podf", "cko2_sel", base + 0x60, 21, 3); imx6q_clocks_init()
380 clk[IMX6QDL_CLK_AXI] = imx_clk_busy_divider("axi", "axi_sel", base + 0x14, 16, 3, base + 0x48, 0); imx6q_clocks_init()
381 clk[IMX6QDL_CLK_MMDC_CH0_AXI_PODF] = imx_clk_busy_divider("mmdc_ch0_axi_podf", "periph", base + 0x14, 19, 3, base + 0x48, 4); imx6q_clocks_init()
382 clk[IMX6QDL_CLK_MMDC_CH1_AXI_PODF] = imx_clk_busy_divider("mmdc_ch1_axi_podf", "periph2", base + 0x14, 3, 3, base + 0x48, 2); imx6q_clocks_init()
383 clk[IMX6QDL_CLK_ARM] = imx_clk_busy_divider("arm", "pll1_sw", base + 0x10, 0, 3, base + 0x48, 16); imx6q_clocks_init()
384 clk[IMX6QDL_CLK_AHB] = imx_clk_busy_divider("ahb", "periph", base + 0x14, 10, 3, base + 0x48, 1); imx6q_clocks_init()
387 clk[IMX6QDL_CLK_APBH_DMA] = imx_clk_gate2("apbh_dma", "usdhc3", base + 0x68, 4); imx6q_clocks_init()
388 clk[IMX6QDL_CLK_ASRC] = imx_clk_gate2_shared("asrc", "asrc_podf", base + 0x68, 6, &share_count_asrc); imx6q_clocks_init()
389 clk[IMX6QDL_CLK_ASRC_IPG] = imx_clk_gate2_shared("asrc_ipg", "ahb", base + 0x68, 6, &share_count_asrc); imx6q_clocks_init()
390 clk[IMX6QDL_CLK_ASRC_MEM] = imx_clk_gate2_shared("asrc_mem", "ahb", base + 0x68, 6, &share_count_asrc); imx6q_clocks_init()
391 clk[IMX6QDL_CLK_CAAM_MEM] = imx_clk_gate2("caam_mem", "ahb", base + 0x68, 8); imx6q_clocks_init()
392 clk[IMX6QDL_CLK_CAAM_ACLK] = imx_clk_gate2("caam_aclk", "ahb", base + 0x68, 10); imx6q_clocks_init()
393 clk[IMX6QDL_CLK_CAAM_IPG] = imx_clk_gate2("caam_ipg", "ipg", base + 0x68, 12); imx6q_clocks_init()
394 clk[IMX6QDL_CLK_CAN1_IPG] = imx_clk_gate2("can1_ipg", "ipg", base + 0x68, 14); imx6q_clocks_init()
395 clk[IMX6QDL_CLK_CAN1_SERIAL] = imx_clk_gate2("can1_serial", "can_root", base + 0x68, 16); imx6q_clocks_init()
396 clk[IMX6QDL_CLK_CAN2_IPG] = imx_clk_gate2("can2_ipg", "ipg", base + 0x68, 18); imx6q_clocks_init()
397 clk[IMX6QDL_CLK_CAN2_SERIAL] = imx_clk_gate2("can2_serial", "can_root", base + 0x68, 20); imx6q_clocks_init()
398 clk[IMX6QDL_CLK_ECSPI1] = imx_clk_gate2("ecspi1", "ecspi_root", base + 0x6c, 0); imx6q_clocks_init()
399 clk[IMX6QDL_CLK_ECSPI2] = imx_clk_gate2("ecspi2", "ecspi_root", base + 0x6c, 2); imx6q_clocks_init()
400 clk[IMX6QDL_CLK_ECSPI3] = imx_clk_gate2("ecspi3", "ecspi_root", base + 0x6c, 4); imx6q_clocks_init()
401 clk[IMX6QDL_CLK_ECSPI4] = imx_clk_gate2("ecspi4", "ecspi_root", base + 0x6c, 6); imx6q_clocks_init()
403 clk[IMX6DL_CLK_I2C4] = imx_clk_gate2("i2c4", "ipg_per", base + 0x6c, 8); imx6q_clocks_init()
405 clk[IMX6Q_CLK_ECSPI5] = imx_clk_gate2("ecspi5", "ecspi_root", base + 0x6c, 8); imx6q_clocks_init()
406 clk[IMX6QDL_CLK_ENET] = imx_clk_gate2("enet", "ipg", base + 0x6c, 10); imx6q_clocks_init()
407 clk[IMX6QDL_CLK_ESAI_EXTAL] = imx_clk_gate2_shared("esai_extal", "esai_podf", base + 0x6c, 16, &share_count_esai); imx6q_clocks_init()
408 clk[IMX6QDL_CLK_ESAI_IPG] = imx_clk_gate2_shared("esai_ipg", "ahb", base + 0x6c, 16, &share_count_esai); imx6q_clocks_init()
409 clk[IMX6QDL_CLK_ESAI_MEM] = imx_clk_gate2_shared("esai_mem", "ahb", base + 0x6c, 16, &share_count_esai); imx6q_clocks_init()
410 clk[IMX6QDL_CLK_GPT_IPG] = imx_clk_gate2("gpt_ipg", "ipg", base + 0x6c, 20); imx6q_clocks_init()
411 clk[IMX6QDL_CLK_GPT_IPG_PER] = imx_clk_gate2("gpt_ipg_per", "ipg_per", base + 0x6c, 22); imx6q_clocks_init()
417 clk[IMX6QDL_CLK_GPU2D_CORE] = imx_clk_gate2("gpu2d_core", "gpu3d_shader", base + 0x6c, 24); imx6q_clocks_init()
419 clk[IMX6QDL_CLK_GPU2D_CORE] = imx_clk_gate2("gpu2d_core", "gpu2d_core_podf", base + 0x6c, 24); imx6q_clocks_init()
420 clk[IMX6QDL_CLK_GPU3D_CORE] = imx_clk_gate2("gpu3d_core", "gpu3d_core_podf", base + 0x6c, 26); imx6q_clocks_init()
421 clk[IMX6QDL_CLK_HDMI_IAHB] = imx_clk_gate2("hdmi_iahb", "ahb", base + 0x70, 0); imx6q_clocks_init()
422 clk[IMX6QDL_CLK_HDMI_ISFR] = imx_clk_gate2("hdmi_isfr", "video_27m", base + 0x70, 4); imx6q_clocks_init()
423 clk[IMX6QDL_CLK_I2C1] = imx_clk_gate2("i2c1", "ipg_per", base + 0x70, 6); imx6q_clocks_init()
424 clk[IMX6QDL_CLK_I2C2] = imx_clk_gate2("i2c2", "ipg_per", base + 0x70, 8); imx6q_clocks_init()
425 clk[IMX6QDL_CLK_I2C3] = imx_clk_gate2("i2c3", "ipg_per", base + 0x70, 10); imx6q_clocks_init()
426 clk[IMX6QDL_CLK_IIM] = imx_clk_gate2("iim", "ipg", base + 0x70, 12); imx6q_clocks_init()
427 clk[IMX6QDL_CLK_ENFC] = imx_clk_gate2("enfc", "enfc_podf", base + 0x70, 14); imx6q_clocks_init()
428 clk[IMX6QDL_CLK_VDOA] = imx_clk_gate2("vdoa", "vdo_axi", base + 0x70, 26); imx6q_clocks_init()
429 clk[IMX6QDL_CLK_IPU1] = imx_clk_gate2("ipu1", "ipu1_podf", base + 0x74, 0); imx6q_clocks_init()
430 clk[IMX6QDL_CLK_IPU1_DI0] = imx_clk_gate2("ipu1_di0", "ipu1_di0_sel", base + 0x74, 2); imx6q_clocks_init()
431 clk[IMX6QDL_CLK_IPU1_DI1] = imx_clk_gate2("ipu1_di1", "ipu1_di1_sel", base + 0x74, 4); imx6q_clocks_init()
432 clk[IMX6QDL_CLK_IPU2] = imx_clk_gate2("ipu2", "ipu2_podf", base + 0x74, 6); imx6q_clocks_init()
433 clk[IMX6QDL_CLK_IPU2_DI0] = imx_clk_gate2("ipu2_di0", "ipu2_di0_sel", base + 0x74, 8); imx6q_clocks_init()
434 clk[IMX6QDL_CLK_LDB_DI0] = imx_clk_gate2("ldb_di0", "ldb_di0_podf", base + 0x74, 12); imx6q_clocks_init()
435 clk[IMX6QDL_CLK_LDB_DI1] = imx_clk_gate2("ldb_di1", "ldb_di1_podf", base + 0x74, 14); imx6q_clocks_init()
436 clk[IMX6QDL_CLK_IPU2_DI1] = imx_clk_gate2("ipu2_di1", "ipu2_di1_sel", base + 0x74, 10); imx6q_clocks_init()
437 clk[IMX6QDL_CLK_HSI_TX] = imx_clk_gate2_shared("hsi_tx", "hsi_tx_podf", base + 0x74, 16, &share_count_mipi_core_cfg); imx6q_clocks_init()
438 clk[IMX6QDL_CLK_MIPI_CORE_CFG] = imx_clk_gate2_shared("mipi_core_cfg", "video_27m", base + 0x74, 16, &share_count_mipi_core_cfg); imx6q_clocks_init()
439 clk[IMX6QDL_CLK_MIPI_IPG] = imx_clk_gate2_shared("mipi_ipg", "ipg", base + 0x74, 16, &share_count_mipi_core_cfg); imx6q_clocks_init()
445 clk[IMX6QDL_CLK_MLB] = imx_clk_gate2("mlb", "gpu2d_core_podf", base + 0x74, 18); imx6q_clocks_init()
447 clk[IMX6QDL_CLK_MLB] = imx_clk_gate2("mlb", "axi", base + 0x74, 18); imx6q_clocks_init()
448 clk[IMX6QDL_CLK_MMDC_CH0_AXI] = imx_clk_gate2("mmdc_ch0_axi", "mmdc_ch0_axi_podf", base + 0x74, 20); imx6q_clocks_init()
449 clk[IMX6QDL_CLK_MMDC_CH1_AXI] = imx_clk_gate2("mmdc_ch1_axi", "mmdc_ch1_axi_podf", base + 0x74, 22); imx6q_clocks_init()
450 clk[IMX6QDL_CLK_OCRAM] = imx_clk_gate2("ocram", "ahb", base + 0x74, 28); imx6q_clocks_init()
451 clk[IMX6QDL_CLK_OPENVG_AXI] = imx_clk_gate2("openvg_axi", "axi", base + 0x74, 30); imx6q_clocks_init()
452 clk[IMX6QDL_CLK_PCIE_AXI] = imx_clk_gate2("pcie_axi", "pcie_axi_sel", base + 0x78, 0); imx6q_clocks_init()
453 clk[IMX6QDL_CLK_PER1_BCH] = imx_clk_gate2("per1_bch", "usdhc3", base + 0x78, 12); imx6q_clocks_init()
454 clk[IMX6QDL_CLK_PWM1] = imx_clk_gate2("pwm1", "ipg_per", base + 0x78, 16); imx6q_clocks_init()
455 clk[IMX6QDL_CLK_PWM2] = imx_clk_gate2("pwm2", "ipg_per", base + 0x78, 18); imx6q_clocks_init()
456 clk[IMX6QDL_CLK_PWM3] = imx_clk_gate2("pwm3", "ipg_per", base + 0x78, 20); imx6q_clocks_init()
457 clk[IMX6QDL_CLK_PWM4] = imx_clk_gate2("pwm4", "ipg_per", base + 0x78, 22); imx6q_clocks_init()
458 clk[IMX6QDL_CLK_GPMI_BCH_APB] = imx_clk_gate2("gpmi_bch_apb", "usdhc3", base + 0x78, 24); imx6q_clocks_init()
459 clk[IMX6QDL_CLK_GPMI_BCH] = imx_clk_gate2("gpmi_bch", "usdhc4", base + 0x78, 26); imx6q_clocks_init()
460 clk[IMX6QDL_CLK_GPMI_IO] = imx_clk_gate2("gpmi_io", "enfc", base + 0x78, 28); imx6q_clocks_init()
461 clk[IMX6QDL_CLK_GPMI_APB] = imx_clk_gate2("gpmi_apb", "usdhc3", base + 0x78, 30); imx6q_clocks_init()
462 clk[IMX6QDL_CLK_ROM] = imx_clk_gate2("rom", "ahb", base + 0x7c, 0); imx6q_clocks_init()
463 clk[IMX6QDL_CLK_SATA] = imx_clk_gate2("sata", "ahb", base + 0x7c, 4); imx6q_clocks_init()
464 clk[IMX6QDL_CLK_SDMA] = imx_clk_gate2("sdma", "ahb", base + 0x7c, 6); imx6q_clocks_init()
465 clk[IMX6QDL_CLK_SPBA] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12); imx6q_clocks_init()
466 clk[IMX6QDL_CLK_SPDIF] = imx_clk_gate2_shared("spdif", "spdif_podf", base + 0x7c, 14, &share_count_spdif); imx6q_clocks_init()
467 clk[IMX6QDL_CLK_SPDIF_GCLK] = imx_clk_gate2_shared("spdif_gclk", "ipg", base + 0x7c, 14, &share_count_spdif); imx6q_clocks_init()
468 clk[IMX6QDL_CLK_SSI1_IPG] = imx_clk_gate2_shared("ssi1_ipg", "ipg", base + 0x7c, 18, &share_count_ssi1); imx6q_clocks_init()
469 clk[IMX6QDL_CLK_SSI2_IPG] = imx_clk_gate2_shared("ssi2_ipg", "ipg", base + 0x7c, 20, &share_count_ssi2); imx6q_clocks_init()
470 clk[IMX6QDL_CLK_SSI3_IPG] = imx_clk_gate2_shared("ssi3_ipg", "ipg", base + 0x7c, 22, &share_count_ssi3); imx6q_clocks_init()
471 clk[IMX6QDL_CLK_SSI1] = imx_clk_gate2_shared("ssi1", "ssi1_podf", base + 0x7c, 18, &share_count_ssi1); imx6q_clocks_init()
472 clk[IMX6QDL_CLK_SSI2] = imx_clk_gate2_shared("ssi2", "ssi2_podf", base + 0x7c, 20, &share_count_ssi2); imx6q_clocks_init()
473 clk[IMX6QDL_CLK_SSI3] = imx_clk_gate2_shared("ssi3", "ssi3_podf", base + 0x7c, 22, &share_count_ssi3); imx6q_clocks_init()
474 clk[IMX6QDL_CLK_UART_IPG] = imx_clk_gate2("uart_ipg", "ipg", base + 0x7c, 24); imx6q_clocks_init()
475 clk[IMX6QDL_CLK_UART_SERIAL] = imx_clk_gate2("uart_serial", "uart_serial_podf", base + 0x7c, 26); imx6q_clocks_init()
476 clk[IMX6QDL_CLK_USBOH3] = imx_clk_gate2("usboh3", "ipg", base + 0x80, 0); imx6q_clocks_init()
477 clk[IMX6QDL_CLK_USDHC1] = imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2); imx6q_clocks_init()
478 clk[IMX6QDL_CLK_USDHC2] = imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4); imx6q_clocks_init()
479 clk[IMX6QDL_CLK_USDHC3] = imx_clk_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6); imx6q_clocks_init()
480 clk[IMX6QDL_CLK_USDHC4] = imx_clk_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8); imx6q_clocks_init()
481 clk[IMX6QDL_CLK_EIM_SLOW] = imx_clk_gate2("eim_slow", "eim_slow_podf", base + 0x80, 10); imx6q_clocks_init()
482 clk[IMX6QDL_CLK_VDO_AXI] = imx_clk_gate2("vdo_axi", "vdo_axi_sel", base + 0x80, 12); imx6q_clocks_init()
483 clk[IMX6QDL_CLK_VPU_AXI] = imx_clk_gate2("vpu_axi", "vpu_axi_podf", base + 0x80, 14); imx6q_clocks_init()
484 clk[IMX6QDL_CLK_CKO1] = imx_clk_gate("cko1", "cko1_podf", base + 0x60, 7); imx6q_clocks_init()
485 clk[IMX6QDL_CLK_CKO2] = imx_clk_gate("cko2", "cko2_podf", base + 0x60, 24); imx6q_clocks_init()
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| H A D | clk-imx31.c | 77 void __iomem *base; _mx31_clocks_init() local
80 base = ioremap(MX31_CCM_BASE_ADDR, SZ_4K); _mx31_clocks_init()
81 BUG_ON(!base); _mx31_clocks_init()
86 clk[mpll] = imx_clk_pllv1(IMX_PLLV1_IMX31, "mpll", "ckih", base + MXC_CCM_MPCTL); _mx31_clocks_init()
87 clk[spll] = imx_clk_pllv1(IMX_PLLV1_IMX31, "spll", "ckih", base + MXC_CCM_SRPCTL); _mx31_clocks_init()
88 clk[upll] = imx_clk_pllv1(IMX_PLLV1_IMX31, "upll", "ckih", base + MXC_CCM_UPCTL); _mx31_clocks_init()
89 clk[mcu_main] = imx_clk_mux("mcu_main", base + MXC_CCM_PMCR0, 31, 1, mcu_main_sel, ARRAY_SIZE(mcu_main_sel)); _mx31_clocks_init()
90 clk[hsp] = imx_clk_divider("hsp", "mcu_main", base + MXC_CCM_PDR0, 11, 3); _mx31_clocks_init()
91 clk[ahb] = imx_clk_divider("ahb", "mcu_main", base + MXC_CCM_PDR0, 3, 3); _mx31_clocks_init()
92 clk[nfc] = imx_clk_divider("nfc", "ahb", base + MXC_CCM_PDR0, 8, 3); _mx31_clocks_init()
93 clk[ipg] = imx_clk_divider("ipg", "ahb", base + MXC_CCM_PDR0, 6, 2); _mx31_clocks_init()
94 clk[per_div] = imx_clk_divider("per_div", "upll", base + MXC_CCM_PDR0, 16, 5); _mx31_clocks_init()
95 clk[per] = imx_clk_mux("per", base + MXC_CCM_CCMR, 24, 1, per_sel, ARRAY_SIZE(per_sel)); _mx31_clocks_init()
96 clk[csi] = imx_clk_mux("csi_sel", base + MXC_CCM_CCMR, 25, 1, csi_sel, ARRAY_SIZE(csi_sel)); _mx31_clocks_init()
97 clk[fir] = imx_clk_mux("fir_sel", base + MXC_CCM_CCMR, 11, 2, fir_sel, ARRAY_SIZE(fir_sel)); _mx31_clocks_init()
98 clk[csi_div] = imx_clk_divider("csi_div", "csi_sel", base + MXC_CCM_PDR0, 23, 9); _mx31_clocks_init()
99 clk[usb_div_pre] = imx_clk_divider("usb_div_pre", "upll", base + MXC_CCM_PDR1, 30, 2); _mx31_clocks_init()
100 clk[usb_div_post] = imx_clk_divider("usb_div_post", "usb_div_pre", base + MXC_CCM_PDR1, 27, 3); _mx31_clocks_init()
101 clk[fir_div_pre] = imx_clk_divider("fir_div_pre", "fir_sel", base + MXC_CCM_PDR1, 24, 3); _mx31_clocks_init()
102 clk[fir_div_post] = imx_clk_divider("fir_div_post", "fir_div_pre", base + MXC_CCM_PDR1, 23, 6); _mx31_clocks_init()
103 clk[sdhc1_gate] = imx_clk_gate2("sdhc1_gate", "per", base + MXC_CCM_CGR0, 0); _mx31_clocks_init()
104 clk[sdhc2_gate] = imx_clk_gate2("sdhc2_gate", "per", base + MXC_CCM_CGR0, 2); _mx31_clocks_init()
105 clk[gpt_gate] = imx_clk_gate2("gpt_gate", "per", base + MXC_CCM_CGR0, 4); _mx31_clocks_init()
106 clk[epit1_gate] = imx_clk_gate2("epit1_gate", "per", base + MXC_CCM_CGR0, 6); _mx31_clocks_init()
107 clk[epit2_gate] = imx_clk_gate2("epit2_gate", "per", base + MXC_CCM_CGR0, 8); _mx31_clocks_init()
108 clk[iim_gate] = imx_clk_gate2("iim_gate", "ipg", base + MXC_CCM_CGR0, 10); _mx31_clocks_init()
109 clk[ata_gate] = imx_clk_gate2("ata_gate", "ipg", base + MXC_CCM_CGR0, 12); _mx31_clocks_init()
110 clk[sdma_gate] = imx_clk_gate2("sdma_gate", "ahb", base + MXC_CCM_CGR0, 14); _mx31_clocks_init()
111 clk[cspi3_gate] = imx_clk_gate2("cspi3_gate", "ipg", base + MXC_CCM_CGR0, 16); _mx31_clocks_init()
112 clk[rng_gate] = imx_clk_gate2("rng_gate", "ipg", base + MXC_CCM_CGR0, 18); _mx31_clocks_init()
113 clk[uart1_gate] = imx_clk_gate2("uart1_gate", "per", base + MXC_CCM_CGR0, 20); _mx31_clocks_init()
114 clk[uart2_gate] = imx_clk_gate2("uart2_gate", "per", base + MXC_CCM_CGR0, 22); _mx31_clocks_init()
115 clk[ssi1_gate] = imx_clk_gate2("ssi1_gate", "spll", base + MXC_CCM_CGR0, 24); _mx31_clocks_init()
116 clk[i2c1_gate] = imx_clk_gate2("i2c1_gate", "per", base + MXC_CCM_CGR0, 26); _mx31_clocks_init()
117 clk[i2c2_gate] = imx_clk_gate2("i2c2_gate", "per", base + MXC_CCM_CGR0, 28); _mx31_clocks_init()
118 clk[i2c3_gate] = imx_clk_gate2("i2c3_gate", "per", base + MXC_CCM_CGR0, 30); _mx31_clocks_init()
119 clk[hantro_gate] = imx_clk_gate2("hantro_gate", "per", base + MXC_CCM_CGR1, 0); _mx31_clocks_init()
120 clk[mstick1_gate] = imx_clk_gate2("mstick1_gate", "per", base + MXC_CCM_CGR1, 2); _mx31_clocks_init()
121 clk[mstick2_gate] = imx_clk_gate2("mstick2_gate", "per", base + MXC_CCM_CGR1, 4); _mx31_clocks_init()
122 clk[csi_gate] = imx_clk_gate2("csi_gate", "csi_div", base + MXC_CCM_CGR1, 6); _mx31_clocks_init()
123 clk[rtc_gate] = imx_clk_gate2("rtc_gate", "ipg", base + MXC_CCM_CGR1, 8); _mx31_clocks_init()
124 clk[wdog_gate] = imx_clk_gate2("wdog_gate", "ipg", base + MXC_CCM_CGR1, 10); _mx31_clocks_init()
125 clk[pwm_gate] = imx_clk_gate2("pwm_gate", "per", base + MXC_CCM_CGR1, 12); _mx31_clocks_init()
126 clk[sim_gate] = imx_clk_gate2("sim_gate", "per", base + MXC_CCM_CGR1, 14); _mx31_clocks_init()
127 clk[ect_gate] = imx_clk_gate2("ect_gate", "per", base + MXC_CCM_CGR1, 16); _mx31_clocks_init()
128 clk[usb_gate] = imx_clk_gate2("usb_gate", "ahb", base + MXC_CCM_CGR1, 18); _mx31_clocks_init()
129 clk[kpp_gate] = imx_clk_gate2("kpp_gate", "ipg", base + MXC_CCM_CGR1, 20); _mx31_clocks_init()
130 clk[ipu_gate] = imx_clk_gate2("ipu_gate", "hsp", base + MXC_CCM_CGR1, 22); _mx31_clocks_init()
131 clk[uart3_gate] = imx_clk_gate2("uart3_gate", "per", base + MXC_CCM_CGR1, 24); _mx31_clocks_init()
132 clk[uart4_gate] = imx_clk_gate2("uart4_gate", "per", base + MXC_CCM_CGR1, 26); _mx31_clocks_init()
133 clk[uart5_gate] = imx_clk_gate2("uart5_gate", "per", base + MXC_CCM_CGR1, 28); _mx31_clocks_init()
134 clk[owire_gate] = imx_clk_gate2("owire_gate", "per", base + MXC_CCM_CGR1, 30); _mx31_clocks_init()
135 clk[ssi2_gate] = imx_clk_gate2("ssi2_gate", "spll", base + MXC_CCM_CGR2, 0); _mx31_clocks_init()
136 clk[cspi1_gate] = imx_clk_gate2("cspi1_gate", "ipg", base + MXC_CCM_CGR2, 2); _mx31_clocks_init()
137 clk[cspi2_gate] = imx_clk_gate2("cspi2_gate", "ipg", base + MXC_CCM_CGR2, 4); _mx31_clocks_init()
138 clk[gacc_gate] = imx_clk_gate2("gacc_gate", "per", base + MXC_CCM_CGR2, 6); _mx31_clocks_init()
139 clk[emi_gate] = imx_clk_gate2("emi_gate", "ahb", base + MXC_CCM_CGR2, 8); _mx31_clocks_init()
140 clk[rtic_gate] = imx_clk_gate2("rtic_gate", "ahb", base + MXC_CCM_CGR2, 10); _mx31_clocks_init()
141 clk[firi_gate] = imx_clk_gate2("firi_gate", "upll", base+MXC_CCM_CGR2, 12); _mx31_clocks_init()
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| H A D | clk-imx35.c | 97 void __iomem *base; _mx35_clocks_init() local
102 base = ioremap(MX35_CCM_BASE_ADDR, SZ_4K); _mx35_clocks_init()
103 BUG_ON(!base); _mx35_clocks_init()
105 pdr0 = __raw_readl(base + MXC_CCM_PDR0); _mx35_clocks_init()
119 clk[mpll] = imx_clk_pllv1(IMX_PLLV1_IMX35, "mpll", "ckih", base + MX35_CCM_MPCTL); _mx35_clocks_init()
120 clk[ppll] = imx_clk_pllv1(IMX_PLLV1_IMX35, "ppll", "ckih", base + MX35_CCM_PPCTL); _mx35_clocks_init()
145 clk[arm_per_div] = imx_clk_divider("arm_per_div", "arm", base + MX35_CCM_PDR4, 16, 6); _mx35_clocks_init()
146 clk[ahb_per_div] = imx_clk_divider("ahb_per_div", "ahb", base + MXC_CCM_PDR0, 12, 3); _mx35_clocks_init()
147 clk[ipg_per] = imx_clk_mux("ipg_per", base + MXC_CCM_PDR0, 26, 1, ipg_per_sel, ARRAY_SIZE(ipg_per_sel)); _mx35_clocks_init()
149 clk[uart_sel] = imx_clk_mux("uart_sel", base + MX35_CCM_PDR3, 14, 1, std_sel, ARRAY_SIZE(std_sel)); _mx35_clocks_init()
150 clk[uart_div] = imx_clk_divider("uart_div", "uart_sel", base + MX35_CCM_PDR4, 10, 6); _mx35_clocks_init()
152 clk[esdhc_sel] = imx_clk_mux("esdhc_sel", base + MX35_CCM_PDR4, 9, 1, std_sel, ARRAY_SIZE(std_sel)); _mx35_clocks_init()
153 clk[esdhc1_div] = imx_clk_divider("esdhc1_div", "esdhc_sel", base + MX35_CCM_PDR3, 0, 6); _mx35_clocks_init()
154 clk[esdhc2_div] = imx_clk_divider("esdhc2_div", "esdhc_sel", base + MX35_CCM_PDR3, 8, 6); _mx35_clocks_init()
155 clk[esdhc3_div] = imx_clk_divider("esdhc3_div", "esdhc_sel", base + MX35_CCM_PDR3, 16, 6); _mx35_clocks_init()
157 clk[spdif_sel] = imx_clk_mux("spdif_sel", base + MX35_CCM_PDR3, 22, 1, std_sel, ARRAY_SIZE(std_sel)); _mx35_clocks_init()
158 clk[spdif_div_pre] = imx_clk_divider("spdif_div_pre", "spdif_sel", base + MX35_CCM_PDR3, 29, 3); /* divide by 1 not allowed */ _mx35_clocks_init()
159 clk[spdif_div_post] = imx_clk_divider("spdif_div_post", "spdif_div_pre", base + MX35_CCM_PDR3, 23, 6); _mx35_clocks_init()
161 clk[ssi_sel] = imx_clk_mux("ssi_sel", base + MX35_CCM_PDR2, 6, 1, std_sel, ARRAY_SIZE(std_sel)); _mx35_clocks_init()
162 clk[ssi1_div_pre] = imx_clk_divider("ssi1_div_pre", "ssi_sel", base + MX35_CCM_PDR2, 24, 3); _mx35_clocks_init()
163 clk[ssi1_div_post] = imx_clk_divider("ssi1_div_post", "ssi1_div_pre", base + MX35_CCM_PDR2, 0, 6); _mx35_clocks_init()
164 clk[ssi2_div_pre] = imx_clk_divider("ssi2_div_pre", "ssi_sel", base + MX35_CCM_PDR2, 27, 3); _mx35_clocks_init()
165 clk[ssi2_div_post] = imx_clk_divider("ssi2_div_post", "ssi2_div_pre", base + MX35_CCM_PDR2, 8, 6); _mx35_clocks_init()
167 clk[usb_sel] = imx_clk_mux("usb_sel", base + MX35_CCM_PDR4, 9, 1, std_sel, ARRAY_SIZE(std_sel)); _mx35_clocks_init()
168 clk[usb_div] = imx_clk_divider("usb_div", "usb_sel", base + MX35_CCM_PDR4, 22, 6); _mx35_clocks_init()
170 clk[nfc_div] = imx_clk_divider("nfc_div", "ahb", base + MX35_CCM_PDR4, 28, 4); _mx35_clocks_init()
172 clk[csi_sel] = imx_clk_mux("csi_sel", base + MX35_CCM_PDR2, 7, 1, std_sel, ARRAY_SIZE(std_sel)); _mx35_clocks_init()
173 clk[csi_div] = imx_clk_divider("csi_div", "csi_sel", base + MX35_CCM_PDR2, 16, 6); _mx35_clocks_init()
175 clk[asrc_gate] = imx_clk_gate2("asrc_gate", "ipg", base + MX35_CCM_CGR0, 0); _mx35_clocks_init()
176 clk[pata_gate] = imx_clk_gate2("pata_gate", "ipg", base + MX35_CCM_CGR0, 2); _mx35_clocks_init()
177 clk[audmux_gate] = imx_clk_gate2("audmux_gate", "ipg", base + MX35_CCM_CGR0, 4); _mx35_clocks_init()
178 clk[can1_gate] = imx_clk_gate2("can1_gate", "ipg", base + MX35_CCM_CGR0, 6); _mx35_clocks_init()
179 clk[can2_gate] = imx_clk_gate2("can2_gate", "ipg", base + MX35_CCM_CGR0, 8); _mx35_clocks_init()
180 clk[cspi1_gate] = imx_clk_gate2("cspi1_gate", "ipg", base + MX35_CCM_CGR0, 10); _mx35_clocks_init()
181 clk[cspi2_gate] = imx_clk_gate2("cspi2_gate", "ipg", base + MX35_CCM_CGR0, 12); _mx35_clocks_init()
182 clk[ect_gate] = imx_clk_gate2("ect_gate", "ipg", base + MX35_CCM_CGR0, 14); _mx35_clocks_init()
183 clk[edio_gate] = imx_clk_gate2("edio_gate", "ipg", base + MX35_CCM_CGR0, 16); _mx35_clocks_init()
184 clk[emi_gate] = imx_clk_gate2("emi_gate", "ipg", base + MX35_CCM_CGR0, 18); _mx35_clocks_init()
185 clk[epit1_gate] = imx_clk_gate2("epit1_gate", "ipg", base + MX35_CCM_CGR0, 20); _mx35_clocks_init()
186 clk[epit2_gate] = imx_clk_gate2("epit2_gate", "ipg", base + MX35_CCM_CGR0, 22); _mx35_clocks_init()
187 clk[esai_gate] = imx_clk_gate2("esai_gate", "ipg", base + MX35_CCM_CGR0, 24); _mx35_clocks_init()
188 clk[esdhc1_gate] = imx_clk_gate2("esdhc1_gate", "esdhc1_div", base + MX35_CCM_CGR0, 26); _mx35_clocks_init()
189 clk[esdhc2_gate] = imx_clk_gate2("esdhc2_gate", "esdhc2_div", base + MX35_CCM_CGR0, 28); _mx35_clocks_init()
190 clk[esdhc3_gate] = imx_clk_gate2("esdhc3_gate", "esdhc3_div", base + MX35_CCM_CGR0, 30); _mx35_clocks_init()
192 clk[fec_gate] = imx_clk_gate2("fec_gate", "ipg", base + MX35_CCM_CGR1, 0); _mx35_clocks_init()
193 clk[gpio1_gate] = imx_clk_gate2("gpio1_gate", "ipg", base + MX35_CCM_CGR1, 2); _mx35_clocks_init()
194 clk[gpio2_gate] = imx_clk_gate2("gpio2_gate", "ipg", base + MX35_CCM_CGR1, 4); _mx35_clocks_init()
195 clk[gpio3_gate] = imx_clk_gate2("gpio3_gate", "ipg", base + MX35_CCM_CGR1, 6); _mx35_clocks_init()
196 clk[gpt_gate] = imx_clk_gate2("gpt_gate", "ipg", base + MX35_CCM_CGR1, 8); _mx35_clocks_init()
197 clk[i2c1_gate] = imx_clk_gate2("i2c1_gate", "ipg_per", base + MX35_CCM_CGR1, 10); _mx35_clocks_init()
198 clk[i2c2_gate] = imx_clk_gate2("i2c2_gate", "ipg_per", base + MX35_CCM_CGR1, 12); _mx35_clocks_init()
199 clk[i2c3_gate] = imx_clk_gate2("i2c3_gate", "ipg_per", base + MX35_CCM_CGR1, 14); _mx35_clocks_init()
200 clk[iomuxc_gate] = imx_clk_gate2("iomuxc_gate", "ipg", base + MX35_CCM_CGR1, 16); _mx35_clocks_init()
201 clk[ipu_gate] = imx_clk_gate2("ipu_gate", "hsp", base + MX35_CCM_CGR1, 18); _mx35_clocks_init()
202 clk[kpp_gate] = imx_clk_gate2("kpp_gate", "ipg", base + MX35_CCM_CGR1, 20); _mx35_clocks_init()
203 clk[mlb_gate] = imx_clk_gate2("mlb_gate", "ahb", base + MX35_CCM_CGR1, 22); _mx35_clocks_init()
204 clk[mshc_gate] = imx_clk_gate2("mshc_gate", "dummy", base + MX35_CCM_CGR1, 24); _mx35_clocks_init()
205 clk[owire_gate] = imx_clk_gate2("owire_gate", "ipg_per", base + MX35_CCM_CGR1, 26); _mx35_clocks_init()
206 clk[pwm_gate] = imx_clk_gate2("pwm_gate", "ipg_per", base + MX35_CCM_CGR1, 28); _mx35_clocks_init()
207 clk[rngc_gate] = imx_clk_gate2("rngc_gate", "ipg", base + MX35_CCM_CGR1, 30); _mx35_clocks_init()
209 clk[rtc_gate] = imx_clk_gate2("rtc_gate", "ipg", base + MX35_CCM_CGR2, 0); _mx35_clocks_init()
210 clk[rtic_gate] = imx_clk_gate2("rtic_gate", "ahb", base + MX35_CCM_CGR2, 2); _mx35_clocks_init()
211 clk[scc_gate] = imx_clk_gate2("scc_gate", "ipg", base + MX35_CCM_CGR2, 4); _mx35_clocks_init()
212 clk[sdma_gate] = imx_clk_gate2("sdma_gate", "ahb", base + MX35_CCM_CGR2, 6); _mx35_clocks_init()
213 clk[spba_gate] = imx_clk_gate2("spba_gate", "ipg", base + MX35_CCM_CGR2, 8); _mx35_clocks_init()
214 clk[spdif_gate] = imx_clk_gate2("spdif_gate", "spdif_div_post", base + MX35_CCM_CGR2, 10); _mx35_clocks_init()
215 clk[ssi1_gate] = imx_clk_gate2("ssi1_gate", "ssi1_div_post", base + MX35_CCM_CGR2, 12); _mx35_clocks_init()
216 clk[ssi2_gate] = imx_clk_gate2("ssi2_gate", "ssi2_div_post", base + MX35_CCM_CGR2, 14); _mx35_clocks_init()
217 clk[uart1_gate] = imx_clk_gate2("uart1_gate", "uart_div", base + MX35_CCM_CGR2, 16); _mx35_clocks_init()
218 clk[uart2_gate] = imx_clk_gate2("uart2_gate", "uart_div", base + MX35_CCM_CGR2, 18); _mx35_clocks_init()
219 clk[uart3_gate] = imx_clk_gate2("uart3_gate", "uart_div", base + MX35_CCM_CGR2, 20); _mx35_clocks_init()
220 clk[usbotg_gate] = imx_clk_gate2("usbotg_gate", "ahb", base + MX35_CCM_CGR2, 22); _mx35_clocks_init()
221 clk[wdog_gate] = imx_clk_gate2("wdog_gate", "ipg", base + MX35_CCM_CGR2, 24); _mx35_clocks_init()
222 clk[max_gate] = imx_clk_gate2("max_gate", "dummy", base + MX35_CCM_CGR2, 26); _mx35_clocks_init()
223 clk[admux_gate] = imx_clk_gate2("admux_gate", "ipg", base + MX35_CCM_CGR2, 30); _mx35_clocks_init()
225 clk[csi_gate] = imx_clk_gate2("csi_gate", "csi_div", base + MX35_CCM_CGR3, 0); _mx35_clocks_init()
226 clk[iim_gate] = imx_clk_gate2("iim_gate", "ipg", base + MX35_CCM_CGR3, 2); _mx35_clocks_init()
227 clk[gpu2d_gate] = imx_clk_gate2("gpu2d_gate", "ahb", base + MX35_CCM_CGR3, 4); _mx35_clocks_init()
|
| /linux-4.4.14/arch/arm/include/asm/ |
| H A D | vfpmacros.h | 20 .macro VFPFLDMIA, base, tmp variable
22 LDC p11, cr0, [\base],#33*4 @ FLDMIAX \base!, {d0-d15} variable
24 LDC p11, cr0, [\base],#32*4 @ FLDMIAD \base!, {d0-d15}
31 ldcnel p11, cr0, [\base],#32*4 @ FLDMIAD \base!, {d16-d31} variable
32 addeq \base, \base, #32*4 @ step over unused register space variable
37 ldceql p11, cr0, [\base],#32*4 @ FLDMIAD \base!, {d16-d31}
38 addne \base, \base, #32*4 @ step over unused register space
44 .macro VFPFSTMIA, base, tmp variable
46 STC p11, cr0, [\base],#33*4 @ FSTMIAX \base!, {d0-d15} variable
48 STC p11, cr0, [\base],#32*4 @ FSTMIAD \base!, {d0-d15}
55 stcnel p11, cr0, [\base],#32*4 @ FSTMIAD \base!, {d16-d31} variable
56 addeq \base, \base, #32*4 @ step over unused register space variable
61 stceql p11, cr0, [\base],#32*4 @ FSTMIAD \base!, {d16-d31}
62 addne \base, \base, #32*4 @ step over unused register space
|
| H A D | dma-contiguous.h | 9 void dma_contiguous_early_fixup(phys_addr_t base, unsigned long size);
|
| H A D | cti.h | 41 * @base: mapped virtual address for the cti base
49 void __iomem *base; member in struct:cti
57 * @base: mapped virtual address for the cti base
63 * @base, @irq and @trig_out to cti.
66 void __iomem *base, int irq, int trig_out) cti_init()
68 cti->base = base; cti_init()
86 void __iomem *base = cti->base; cti_map_trigger() local
89 val = __raw_readl(base + CTIINEN + trig_in * 4); cti_map_trigger()
91 __raw_writel(val, base + CTIINEN + trig_in * 4); cti_map_trigger()
93 val = __raw_readl(base + CTIOUTEN + trig_out * 4); cti_map_trigger()
95 __raw_writel(val, base + CTIOUTEN + trig_out * 4); cti_map_trigger()
106 __raw_writel(0x1, cti->base + CTICONTROL); cti_enable()
117 __raw_writel(0, cti->base + CTICONTROL); cti_disable()
128 void __iomem *base = cti->base; cti_irq_ack() local
131 val = __raw_readl(base + CTIINTACK); cti_irq_ack()
133 __raw_writel(val, base + CTIINTACK); cti_irq_ack()
145 __raw_writel(CS_LAR_KEY, cti->base + LOCKACCESS); cti_unlock()
157 __raw_writel(~CS_LAR_KEY, cti->base + LOCKACCESS); cti_lock()
65 cti_init(struct cti *cti, void __iomem *base, int irq, int trig_out) cti_init() argument
|
| /linux-4.4.14/drivers/video/fbdev/omap2/dss/ |
| H A D | hdmi5_core.c | 52 void __iomem *base = core->base; hdmi_core_ddc_init() local
67 REG_FLD_MOD(base, HDMI_CORE_I2CM_SOFTRSTZ, 0, 0, 0); hdmi_core_ddc_init()
68 if (hdmi_wait_for_bit_change(base, HDMI_CORE_I2CM_SOFTRSTZ, hdmi_core_ddc_init()
73 REG_FLD_MOD(base, HDMI_CORE_I2CM_DIV, 0, 3, 3); hdmi_core_ddc_init()
77 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_HCNT_1_ADDR, hdmi_core_ddc_init()
79 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_HCNT_0_ADDR, hdmi_core_ddc_init()
84 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_LCNT_1_ADDR, hdmi_core_ddc_init()
86 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_LCNT_0_ADDR, hdmi_core_ddc_init()
91 REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_HCNT_1_ADDR, hdmi_core_ddc_init()
93 REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_HCNT_0_ADDR, hdmi_core_ddc_init()
98 REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_LCNT_1_ADDR, hdmi_core_ddc_init()
100 REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_LCNT_0_ADDR, hdmi_core_ddc_init()
105 REG_FLD_MOD(base, HDMI_CORE_I2CM_SDA_HOLD_ADDR, v & 0xff, 7, 0); hdmi_core_ddc_init()
107 REG_FLD_MOD(base, HDMI_CORE_I2CM_SLAVE, 0x50, 6, 0); hdmi_core_ddc_init()
108 REG_FLD_MOD(base, HDMI_CORE_I2CM_SEGADDR, 0x30, 6, 0); hdmi_core_ddc_init()
111 REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 7, 7); hdmi_core_ddc_init()
114 REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x0, 6, 6); hdmi_core_ddc_init()
117 REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 3, 3); hdmi_core_ddc_init()
120 REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x0, 2, 2); hdmi_core_ddc_init()
123 REG_FLD_MOD(base, HDMI_CORE_I2CM_INT, 0x1, 3, 3); hdmi_core_ddc_init()
126 REG_FLD_MOD(base, HDMI_CORE_I2CM_INT, 0x0, 2, 2); hdmi_core_ddc_init()
131 void __iomem *base = core->base; hdmi_core_ddc_uninit() local
134 REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 6, 6); hdmi_core_ddc_uninit()
135 REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 2, 2); hdmi_core_ddc_uninit()
136 REG_FLD_MOD(base, HDMI_CORE_I2CM_INT, 0x1, 2, 2); hdmi_core_ddc_uninit()
141 void __iomem *base = core->base; hdmi_core_ddc_edid() local
148 REG_FLD_MOD(base, HDMI_CORE_I2CM_SEGPTR, seg_ptr, 7, 0); hdmi_core_ddc_edid()
158 REG_FLD_MOD(base, HDMI_CORE_IH_I2CM_STAT0, 0x3, 1, 0); hdmi_core_ddc_edid()
160 REG_FLD_MOD(base, HDMI_CORE_I2CM_ADDRESS, hdmi_core_ddc_edid()
164 REG_FLD_MOD(base, HDMI_CORE_I2CM_OPERATION, 1, 1, 1); hdmi_core_ddc_edid()
166 REG_FLD_MOD(base, HDMI_CORE_I2CM_OPERATION, 1, 0, 0); hdmi_core_ddc_edid()
171 stat = REG_GET(base, HDMI_CORE_IH_I2CM_STAT0, 1, 0); hdmi_core_ddc_edid()
191 pedid[cur_addr] = REG_GET(base, HDMI_CORE_I2CM_DATAI, 7, 0); hdmi_core_ddc_edid()
234 hdmi_read_reg(core->base, r)) hdmi5_core_dump()
320 void __iomem *base = core->base; hdmi_core_video_config() local
330 r = hdmi_read_reg(base, HDMI_CORE_FC_INVIDCONF); hdmi_core_video_config()
336 hdmi_write_reg(base, HDMI_CORE_FC_INVIDCONF, r); hdmi_core_video_config()
339 REG_FLD_MOD(base, HDMI_CORE_FC_INHACTIV1, hdmi_core_video_config()
341 REG_FLD_MOD(base, HDMI_CORE_FC_INHACTIV0, hdmi_core_video_config()
345 REG_FLD_MOD(base, HDMI_CORE_FC_INVACTIV1, hdmi_core_video_config()
347 REG_FLD_MOD(base, HDMI_CORE_FC_INVACTIV0, hdmi_core_video_config()
351 REG_FLD_MOD(base, HDMI_CORE_FC_INHBLANK1, cfg->hblank >> 8, 4, 0); hdmi_core_video_config()
352 REG_FLD_MOD(base, HDMI_CORE_FC_INHBLANK0, cfg->hblank & 0xFF, 7, 0); hdmi_core_video_config()
355 REG_FLD_MOD(base, HDMI_CORE_FC_INVBLANK, cfg->vblank, 7, 0); hdmi_core_video_config()
358 REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINDELAY1, hdmi_core_video_config()
360 REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINDELAY0, hdmi_core_video_config()
364 REG_FLD_MOD(base, HDMI_CORE_FC_VSYNCINDELAY, hdmi_core_video_config()
368 REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINWIDTH1, hdmi_core_video_config()
370 REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINWIDTH0, hdmi_core_video_config()
374 REG_FLD_MOD(base, HDMI_CORE_FC_VSYNCINWIDTH, hdmi_core_video_config()
378 REG_FLD_MOD(base, HDMI_CORE_FC_INVIDCONF, hdmi_core_video_config()
384 void __iomem *base = core->base; hdmi_core_config_video_packetizer() local
388 REG_FLD_MOD(base, HDMI_CORE_VP_PR_CD, clr_depth, 7, 4); hdmi_core_config_video_packetizer()
390 REG_FLD_MOD(base, HDMI_CORE_VP_CONF, clr_depth ? 0 : 1, 6, 6); hdmi_core_config_video_packetizer()
392 REG_FLD_MOD(base, HDMI_CORE_VP_CONF, clr_depth ? 1 : 0, 5, 5); hdmi_core_config_video_packetizer()
394 REG_FLD_MOD(base, HDMI_CORE_VP_CONF, 0, 3, 3); hdmi_core_config_video_packetizer()
396 REG_FLD_MOD(base, HDMI_CORE_VP_STUFF, clr_depth ? 1 : 0, 1, 1); hdmi_core_config_video_packetizer()
398 REG_FLD_MOD(base, HDMI_CORE_VP_STUFF, 1, 2, 2); hdmi_core_config_video_packetizer()
400 REG_FLD_MOD(base, HDMI_CORE_VP_CONF, clr_depth ? 0 : 2, 1, 0); hdmi_core_config_video_packetizer()
408 REG_FLD_MOD(core->base, HDMI_CORE_CSC_SCALE, clr_depth, 7, 4); hdmi_core_config_csc()
416 REG_FLD_MOD(core->base, HDMI_CORE_TX_INVID0, video_mapping, 4, 0); hdmi_core_config_video_sampler()
422 void __iomem *base = core->base; hdmi_core_write_avi_infoframe() local
458 hdmi_write_reg(base, HDMI_CORE_FC_AVICONF0, hdmi_core_write_avi_infoframe()
461 hdmi_write_reg(base, HDMI_CORE_FC_AVICONF1, hdmi_core_write_avi_infoframe()
464 hdmi_write_reg(base, HDMI_CORE_FC_AVICONF2, hdmi_core_write_avi_infoframe()
467 hdmi_write_reg(base, HDMI_CORE_FC_AVIVID, vic); hdmi_core_write_avi_infoframe()
469 hdmi_write_reg(base, HDMI_CORE_FC_AVICONF3, hdmi_core_write_avi_infoframe()
472 REG_FLD_MOD(base, HDMI_CORE_FC_PRCONF, pr, 3, 0); hdmi_core_write_avi_infoframe()
478 void __iomem *base = core->base; hdmi_core_csc_config() local
480 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A1_MSB, csc_coeff.a1 >> 8 , 6, 0); hdmi_core_csc_config()
481 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A1_LSB, csc_coeff.a1, 7, 0); hdmi_core_csc_config()
482 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A2_MSB, csc_coeff.a2 >> 8, 6, 0); hdmi_core_csc_config()
483 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A2_LSB, csc_coeff.a2, 7, 0); hdmi_core_csc_config()
484 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A3_MSB, csc_coeff.a3 >> 8, 6, 0); hdmi_core_csc_config()
485 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A3_LSB, csc_coeff.a3, 7, 0); hdmi_core_csc_config()
486 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A4_MSB, csc_coeff.a4 >> 8, 6, 0); hdmi_core_csc_config()
487 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A4_LSB, csc_coeff.a4, 7, 0); hdmi_core_csc_config()
488 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B1_MSB, csc_coeff.b1 >> 8, 6, 0); hdmi_core_csc_config()
489 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B1_LSB, csc_coeff.b1, 7, 0); hdmi_core_csc_config()
490 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B2_MSB, csc_coeff.b2 >> 8, 6, 0); hdmi_core_csc_config()
491 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B2_LSB, csc_coeff.b2, 7, 0); hdmi_core_csc_config()
492 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B3_MSB, csc_coeff.b3 >> 8, 6, 0); hdmi_core_csc_config()
493 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B3_LSB, csc_coeff.b3, 7, 0); hdmi_core_csc_config()
494 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B4_MSB, csc_coeff.b4 >> 8, 6, 0); hdmi_core_csc_config()
495 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B4_LSB, csc_coeff.b4, 7, 0); hdmi_core_csc_config()
496 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C1_MSB, csc_coeff.c1 >> 8, 6, 0); hdmi_core_csc_config()
497 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C1_LSB, csc_coeff.c1, 7, 0); hdmi_core_csc_config()
498 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C2_MSB, csc_coeff.c2 >> 8, 6, 0); hdmi_core_csc_config()
499 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C2_LSB, csc_coeff.c2, 7, 0); hdmi_core_csc_config()
500 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C3_MSB, csc_coeff.c3 >> 8, 6, 0); hdmi_core_csc_config()
501 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C3_LSB, csc_coeff.c3, 7, 0); hdmi_core_csc_config()
502 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C4_MSB, csc_coeff.c4 >> 8, 6, 0); hdmi_core_csc_config()
503 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C4_LSB, csc_coeff.c4, 7, 0); hdmi_core_csc_config()
505 REG_FLD_MOD(base, HDMI_CORE_MC_FLOWCTRL, 0x1, 0, 0); hdmi_core_csc_config()
520 void __iomem *base = core->base; hdmi_core_enable_video_path() local
524 REG_FLD_MOD(base, HDMI_CORE_FC_CTRLDUR, 0x0C, 7, 0); hdmi_core_enable_video_path()
525 REG_FLD_MOD(base, HDMI_CORE_FC_EXCTRLDUR, 0x20, 7, 0); hdmi_core_enable_video_path()
526 REG_FLD_MOD(base, HDMI_CORE_FC_EXCTRLSPAC, 0x01, 7, 0); hdmi_core_enable_video_path()
527 REG_FLD_MOD(base, HDMI_CORE_FC_CH0PREAM, 0x0B, 7, 0); hdmi_core_enable_video_path()
528 REG_FLD_MOD(base, HDMI_CORE_FC_CH1PREAM, 0x16, 5, 0); hdmi_core_enable_video_path()
529 REG_FLD_MOD(base, HDMI_CORE_FC_CH2PREAM, 0x21, 5, 0); hdmi_core_enable_video_path()
530 REG_FLD_MOD(base, HDMI_CORE_MC_CLKDIS, 0x00, 0, 0); hdmi_core_enable_video_path()
531 REG_FLD_MOD(base, HDMI_CORE_MC_CLKDIS, 0x00, 1, 1); hdmi_core_enable_video_path()
536 void __iomem *base = core->base; hdmi_core_mask_interrupts() local
539 REG_FLD_MOD(base, HDMI_CORE_IH_MUTE, 0x3, 1, 0); hdmi_core_mask_interrupts()
543 REG_FLD_MOD(base, HDMI_CORE_VP_MASK, 0xff, 7, 0); hdmi_core_mask_interrupts()
544 REG_FLD_MOD(base, HDMI_CORE_FC_MASK0, 0xe7, 7, 0); hdmi_core_mask_interrupts()
545 REG_FLD_MOD(base, HDMI_CORE_FC_MASK1, 0xfb, 7, 0); hdmi_core_mask_interrupts()
546 REG_FLD_MOD(base, HDMI_CORE_FC_MASK2, 0x3, 1, 0); hdmi_core_mask_interrupts()
548 REG_FLD_MOD(base, HDMI_CORE_AUD_INT, 0x3, 3, 2); hdmi_core_mask_interrupts()
549 REG_FLD_MOD(base, HDMI_CORE_AUD_GP_MASK, 0x3, 1, 0); hdmi_core_mask_interrupts()
551 REG_FLD_MOD(base, HDMI_CORE_CEC_MASK, 0x7f, 6, 0); hdmi_core_mask_interrupts()
553 REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 6, 6); hdmi_core_mask_interrupts()
554 REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 2, 2); hdmi_core_mask_interrupts()
555 REG_FLD_MOD(base, HDMI_CORE_I2CM_INT, 0x1, 2, 2); hdmi_core_mask_interrupts()
557 REG_FLD_MOD(base, HDMI_CORE_PHY_MASK0, 0xf3, 7, 0); hdmi_core_mask_interrupts()
559 REG_FLD_MOD(base, HDMI_CORE_IH_PHY_STAT0, 0xff, 7, 0); hdmi_core_mask_interrupts()
563 REG_FLD_MOD(base, HDMI_CORE_IH_VP_STAT0, 0xff, 7, 0); hdmi_core_mask_interrupts()
564 REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT0, 0xe7, 7, 0); hdmi_core_mask_interrupts()
565 REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT1, 0xfb, 7, 0); hdmi_core_mask_interrupts()
566 REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT2, 0x3, 1, 0); hdmi_core_mask_interrupts()
568 REG_FLD_MOD(base, HDMI_CORE_IH_AS_STAT0, 0x7, 2, 0); hdmi_core_mask_interrupts()
570 REG_FLD_MOD(base, HDMI_CORE_IH_CEC_STAT0, 0x7f, 6, 0); hdmi_core_mask_interrupts()
572 REG_FLD_MOD(base, HDMI_CORE_IH_I2CM_STAT0, 0x3, 1, 0); hdmi_core_mask_interrupts()
574 REG_FLD_MOD(base, HDMI_CORE_IH_PHY_STAT0, 0xff, 7, 0); hdmi_core_mask_interrupts()
580 REG_FLD_MOD(core->base, HDMI_CORE_IH_MUTE, 0x0, 1, 0); hdmi_core_enable_interrupts()
585 void __iomem *base = core->base; hdmi5_core_handle_irqs() local
587 REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT0, 0xff, 7, 0); hdmi5_core_handle_irqs()
588 REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT1, 0xff, 7, 0); hdmi5_core_handle_irqs()
589 REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT2, 0xff, 7, 0); hdmi5_core_handle_irqs()
590 REG_FLD_MOD(base, HDMI_CORE_IH_AS_STAT0, 0xff, 7, 0); hdmi5_core_handle_irqs()
591 REG_FLD_MOD(base, HDMI_CORE_IH_PHY_STAT0, 0xff, 7, 0); hdmi5_core_handle_irqs()
592 REG_FLD_MOD(base, HDMI_CORE_IH_I2CM_STAT0, 0xff, 7, 0); hdmi5_core_handle_irqs()
593 REG_FLD_MOD(base, HDMI_CORE_IH_CEC_STAT0, 0xff, 7, 0); hdmi5_core_handle_irqs()
594 REG_FLD_MOD(base, HDMI_CORE_IH_VP_STAT0, 0xff, 7, 0); hdmi5_core_handle_irqs()
595 REG_FLD_MOD(base, HDMI_CORE_IH_I2CMPHY_STAT0, 0xff, 7, 0); hdmi5_core_handle_irqs()
648 void __iomem *base = core->base; hdmi5_core_audio_config() local
652 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCONF, 0xf, 7, 4); hdmi5_core_audio_config()
655 REG_FLD_MOD(base, HDMI_CORE_AUD_N1, cfg->n, 7, 0); hdmi5_core_audio_config()
656 REG_FLD_MOD(base, HDMI_CORE_AUD_N2, cfg->n >> 8, 7, 0); hdmi5_core_audio_config()
657 REG_FLD_MOD(base, HDMI_CORE_AUD_N3, cfg->n >> 16, 3, 0); hdmi5_core_audio_config()
663 REG_FLD_MOD(base, HDMI_CORE_AUD_CTS3, 1, 4, 4); hdmi5_core_audio_config()
664 REG_FLD_MOD(base, HDMI_CORE_AUD_CTS1, cfg->cts, 7, 0); hdmi5_core_audio_config()
665 REG_FLD_MOD(base, HDMI_CORE_AUD_CTS2, cfg->cts >> 8, 7, 0); hdmi5_core_audio_config()
666 REG_FLD_MOD(base, HDMI_CORE_AUD_CTS3, cfg->cts >> 16, 3, 0); hdmi5_core_audio_config()
670 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCONF, 0, 0, 0); hdmi5_core_audio_config()
672 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCONF, 1, 0, 0); hdmi5_core_audio_config()
676 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, 0, 0, 0); hdmi5_core_audio_config()
677 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, 0, 4, 4); hdmi5_core_audio_config()
685 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 1, 1); hdmi5_core_audio_config()
686 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 5, 5); hdmi5_core_audio_config()
687 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 2, 2); hdmi5_core_audio_config()
688 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 6, 6); hdmi5_core_audio_config()
692 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 3, 3); hdmi5_core_audio_config()
693 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 7, 7); hdmi5_core_audio_config()
697 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSU, 0, 7, 0); hdmi5_core_audio_config()
702 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(0), val, 5, 4); hdmi5_core_audio_config()
707 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(0), val, 0, 0); hdmi5_core_audio_config()
710 hdmi_write_reg(base, HDMI_CORE_FC_AUDSCHNLS(1), hdmi5_core_audio_config()
715 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(2), val, 6, 4); hdmi5_core_audio_config()
719 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(2), val, 3, 0); hdmi5_core_audio_config()
722 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(3), 2, 3, 0); hdmi5_core_audio_config()
724 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(3), 4, 7, 4); hdmi5_core_audio_config()
726 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(4), 6, 3, 0); hdmi5_core_audio_config()
728 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(4), 8, 7, 4); hdmi5_core_audio_config()
730 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(5), 1, 3, 0); hdmi5_core_audio_config()
732 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(5), 3, 7, 4); hdmi5_core_audio_config()
734 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(6), 5, 3, 0); hdmi5_core_audio_config()
736 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(6), 7, 7, 4); hdmi5_core_audio_config()
739 hdmi_write_reg(base, HDMI_CORE_FC_AUDSCHNLS(7), hdmi5_core_audio_config()
743 hdmi_write_reg(base, HDMI_CORE_FC_AUDSCHNLS(8), hdmi5_core_audio_config()
747 REG_FLD_MOD(base, HDMI_CORE_AUD_INT, 3, 3, 2); hdmi5_core_audio_config()
753 REG_FLD_MOD(base, HDMI_CORE_AUD_CONF0, 0, 5, 5); hdmi5_core_audio_config()
755 REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF1, 3, 7, 0); hdmi5_core_audio_config()
758 REG_FLD_MOD(base, HDMI_CORE_AUD_CONF0, 0, 5, 5); hdmi5_core_audio_config()
760 REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF1, 0x3F, 7, 0); hdmi5_core_audio_config()
763 REG_FLD_MOD(base, HDMI_CORE_AUD_CONF0, 0, 5, 5); hdmi5_core_audio_config()
765 REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF1, 0xFF, 7, 0); hdmi5_core_audio_config()
769 REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF2, 0, 0, 0); hdmi5_core_audio_config()
771 REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF2, 1, 1, 1); hdmi5_core_audio_config()
773 REG_FLD_MOD(base, HDMI_CORE_AUD_GP_MASK, 3, 1, 0); hdmi5_core_audio_config()
775 REG_FLD_MOD(base, HDMI_CORE_AUD_GP_POL, 1, 0, 0); hdmi5_core_audio_config()
778 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCONF, 0, 7, 4); hdmi5_core_audio_config()
784 void __iomem *base = core->base; hdmi5_core_audio_infoframe_cfg() local
787 hdmi_write_reg(base, HDMI_CORE_FC_AUDICONF0, hdmi5_core_audio_infoframe_cfg()
791 hdmi_write_reg(base, HDMI_CORE_FC_AUDICONF1, info_aud->db2_sf_ss); hdmi5_core_audio_infoframe_cfg()
792 hdmi_write_reg(base, HDMI_CORE_FC_AUDICONF2, info_aud->db4_ca); hdmi5_core_audio_infoframe_cfg()
793 hdmi_write_reg(base, HDMI_CORE_FC_AUDICONF3, hdmi5_core_audio_infoframe_cfg()
909 core->base = devm_ioremap_resource(&pdev->dev, res); hdmi5_core_init()
910 if (IS_ERR(core->base)) { hdmi5_core_init()
912 return PTR_ERR(core->base); hdmi5_core_init()
|
| H A D | hdmi_wp.c | 24 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, hdmi_read_reg(wp->base, r)) hdmi_wp_dump()
48 return hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS); hdmi_wp_get_irqstatus()
53 hdmi_write_reg(wp->base, HDMI_WP_IRQSTATUS, irqstatus); hdmi_wp_set_irqstatus()
55 hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS); hdmi_wp_set_irqstatus()
60 hdmi_write_reg(wp->base, HDMI_WP_IRQENABLE_SET, mask); hdmi_wp_set_irqenable()
65 hdmi_write_reg(wp->base, HDMI_WP_IRQENABLE_CLR, mask); hdmi_wp_clear_irqenable()
72 if (REG_GET(wp->base, HDMI_WP_PWR_CTRL, 5, 4) == val) hdmi_wp_set_phy_pwr()
76 REG_FLD_MOD(wp->base, HDMI_WP_PWR_CTRL, val, 7, 6); hdmi_wp_set_phy_pwr()
79 if (hdmi_wait_for_bit_change(wp->base, HDMI_WP_PWR_CTRL, 5, 4, val) hdmi_wp_set_phy_pwr()
92 REG_FLD_MOD(wp->base, HDMI_WP_PWR_CTRL, val, 3, 2); hdmi_wp_set_pll_pwr()
95 if (hdmi_wait_for_bit_change(wp->base, HDMI_WP_PWR_CTRL, 1, 0, val) hdmi_wp_set_pll_pwr()
106 REG_FLD_MOD(wp->base, HDMI_WP_VIDEO_CFG, true, 31, 31); hdmi_wp_video_start()
115 hdmi_write_reg(wp->base, HDMI_WP_IRQSTATUS, HDMI_IRQ_VIDEO_FRAME_DONE); hdmi_wp_video_stop()
117 REG_FLD_MOD(wp->base, HDMI_WP_VIDEO_CFG, false, 31, 31); hdmi_wp_video_stop()
124 v = hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS_RAW); hdmi_wp_video_stop()
137 REG_FLD_MOD(wp->base, HDMI_WP_VIDEO_CFG, video_fmt->packing_mode, hdmi_wp_video_config_format()
142 hdmi_write_reg(wp->base, HDMI_WP_VIDEO_SIZE, l); hdmi_wp_video_config_format()
155 r = hdmi_read_reg(wp->base, HDMI_WP_VIDEO_CFG); hdmi_wp_video_config_interface()
160 hdmi_write_reg(wp->base, HDMI_WP_VIDEO_CFG, r); hdmi_wp_video_config_interface()
174 hdmi_write_reg(wp->base, HDMI_WP_VIDEO_TIMING_H, timing_h); hdmi_wp_video_config_timing()
179 hdmi_write_reg(wp->base, HDMI_WP_VIDEO_TIMING_V, timing_v); hdmi_wp_video_config_timing()
211 r = hdmi_read_reg(wp->base, HDMI_WP_AUDIO_CFG); hdmi_wp_audio_config_format()
224 hdmi_write_reg(wp->base, HDMI_WP_AUDIO_CFG, r); hdmi_wp_audio_config_format()
234 r = hdmi_read_reg(wp->base, HDMI_WP_AUDIO_CFG2); hdmi_wp_audio_config_dma()
237 hdmi_write_reg(wp->base, HDMI_WP_AUDIO_CFG2, r); hdmi_wp_audio_config_dma()
239 r = hdmi_read_reg(wp->base, HDMI_WP_AUDIO_CTRL); hdmi_wp_audio_config_dma()
242 hdmi_write_reg(wp->base, HDMI_WP_AUDIO_CTRL, r); hdmi_wp_audio_config_dma()
247 REG_FLD_MOD(wp->base, HDMI_WP_AUDIO_CTRL, enable, 31, 31); hdmi_wp_audio_enable()
254 REG_FLD_MOD(wp->base, HDMI_WP_AUDIO_CTRL, enable, 30, 30); hdmi_wp_audio_core_req_enable()
270 wp->base = devm_ioremap_resource(&pdev->dev, res); hdmi_wp_init()
271 if (IS_ERR(wp->base)) { hdmi_wp_init()
273 return PTR_ERR(wp->base); hdmi_wp_init()
|
| /linux-4.4.14/drivers/vfio/platform/ |
| H A D | Makefile | 1 vfio-platform-base-y := vfio_platform_common.o vfio_platform_irq.o
5 obj-$(CONFIG_VFIO_PLATFORM) += vfio-platform-base.o
11 obj-$(CONFIG_VFIO_AMBA) += vfio-platform-base.o
|
| /linux-4.4.14/include/clocksource/ |
| H A D | timer-sp804.h | 12 static inline void sp804_clocksource_init(void __iomem *base, const char *name) sp804_clocksource_init() argument
14 __sp804_clocksource_and_sched_clock_init(base, name, NULL, 0); sp804_clocksource_init()
17 static inline void sp804_clocksource_and_sched_clock_init(void __iomem *base, sp804_clocksource_and_sched_clock_init() argument
20 __sp804_clocksource_and_sched_clock_init(base, name, NULL, 1); sp804_clocksource_and_sched_clock_init()
23 static inline void sp804_clockevents_init(void __iomem *base, unsigned int irq, const char *name) sp804_clockevents_init() argument
25 __sp804_clockevents_init(base, irq, NULL, name); sp804_clockevents_init()
|
| /linux-4.4.14/arch/alpha/kernel/ |
| H A D | pc873xx.c | 12 static unsigned int base, model; variable
17 return base; pc873xx_get_base()
25 static unsigned char __init pc873xx_read(unsigned int base, int reg) pc873xx_read() argument
27 outb(reg, base); pc873xx_read()
28 return inb(base + 1); pc873xx_read()
31 static void __init pc873xx_write(unsigned int base, int reg, unsigned char data) pc873xx_write() argument
36 outb(reg, base); pc873xx_write()
37 outb(data, base + 1); pc873xx_write()
38 outb(data, base + 1); /* Must be written twice */ pc873xx_write()
46 while ((base = pc873xx_probelist[index++])) { pc873xx_probe()
48 if (request_region(base, 2, "Super IO PC873xx") == NULL) pc873xx_probe()
51 val = pc873xx_read(base, REG_SID); pc873xx_probe()
66 release_region(base, 2); pc873xx_probe()
69 return (base == 0) ? -1 : 1; pc873xx_probe()
77 data = pc873xx_read(base, REG_PCR); pc873xx_enable_epp19()
78 pc873xx_write(base, REG_PCR, (data & 0xFC) | 0x02); pc873xx_enable_epp19()
86 data = pc873xx_read(base, REG_FER); pc873xx_enable_ide()
87 pc873xx_write(base, REG_FER, data | 0x40); pc873xx_enable_ide()
|
| /linux-4.4.14/lib/ |
| H A D | kstrtox.h | 5 const char *_parse_integer_fixup_radix(const char *s, unsigned int *base);
6 unsigned int _parse_integer(const char *s, unsigned int base, unsigned long long *res);
|
| H A D | sort.c | 11 static int alignment_ok(const void *base, int align) alignment_ok() argument
14 ((unsigned long)base & (align - 1)) == 0; alignment_ok()
44 * @base: pointer to data to sort
59 void sort(void *base, size_t num, size_t size, sort() argument
67 if (size == 4 && alignment_ok(base, 4)) sort()
69 else if (size == 8 && alignment_ok(base, 8)) sort()
80 cmp_func(base + c, base + c + size) < 0) sort()
82 if (cmp_func(base + r, base + c) >= 0) sort()
84 swap_func(base + r, base + c, size); sort()
90 swap_func(base, base + i, size); sort()
94 cmp_func(base + c, base + c + size) < 0) sort()
96 if (cmp_func(base + r, base + c) >= 0) sort()
98 swap_func(base + r, base + c, size); sort()
|
| H A D | kstrtox.c | 23 const char *_parse_integer_fixup_radix(const char *s, unsigned int *base) _parse_integer_fixup_radix() argument
25 if (*base == 0) { _parse_integer_fixup_radix()
28 *base = 16; _parse_integer_fixup_radix()
30 *base = 8; _parse_integer_fixup_radix()
32 *base = 10; _parse_integer_fixup_radix()
34 if (*base == 16 && s[0] == '0' && _tolower(s[1]) == 'x') _parse_integer_fixup_radix()
47 unsigned int _parse_integer(const char *s, unsigned int base, unsigned long long *p) _parse_integer() argument
66 if (val >= base) _parse_integer()
70 * it in the max base we support (16) _parse_integer()
73 if (res > div_u64(ULLONG_MAX - val, base)) _parse_integer()
76 res = res * base + val; _parse_integer()
86 static int _kstrtoull(const char *s, unsigned int base, unsigned long long *res) _kstrtoull() argument
91 s = _parse_integer_fixup_radix(s, &base); _kstrtoull()
92 rv = _parse_integer(s, base, &_res); _kstrtoull()
111 * @base: The number base to use. The maximum supported base is 16. If base is
112 * given as 0, then the base of the string is automatically detected with the
122 int kstrtoull(const char *s, unsigned int base, unsigned long long *res) kstrtoull() argument
126 return _kstrtoull(s, base, res); kstrtoull()
135 * @base: The number base to use. The maximum supported base is 16. If base is
136 * given as 0, then the base of the string is automatically detected with the
146 int kstrtoll(const char *s, unsigned int base, long long *res) kstrtoll() argument
152 rv = _kstrtoull(s + 1, base, &tmp); kstrtoll()
159 rv = kstrtoull(s, base, &tmp); kstrtoll()
171 int _kstrtoul(const char *s, unsigned int base, unsigned long *res) _kstrtoul() argument
176 rv = kstrtoull(s, base, &tmp); _kstrtoul()
187 int _kstrtol(const char *s, unsigned int base, long *res) _kstrtol() argument
192 rv = kstrtoll(s, base, &tmp); _kstrtol()
207 * @base: The number base to use. The maximum supported base is 16. If base is
208 * given as 0, then the base of the string is automatically detected with the
218 int kstrtouint(const char *s, unsigned int base, unsigned int *res) kstrtouint() argument
223 rv = kstrtoull(s, base, &tmp); kstrtouint()
238 * @base: The number base to use. The maximum supported base is 16. If base is
239 * given as 0, then the base of the string is automatically detected with the
249 int kstrtoint(const char *s, unsigned int base, int *res) kstrtoint() argument
254 rv = kstrtoll(s, base, &tmp); kstrtoint()
264 int kstrtou16(const char *s, unsigned int base, u16 *res) kstrtou16() argument
269 rv = kstrtoull(s, base, &tmp); kstrtou16()
279 int kstrtos16(const char *s, unsigned int base, s16 *res) kstrtos16() argument
284 rv = kstrtoll(s, base, &tmp); kstrtos16()
294 int kstrtou8(const char *s, unsigned int base, u8 *res) kstrtou8() argument
299 rv = kstrtoull(s, base, &tmp); kstrtou8()
309 int kstrtos8(const char *s, unsigned int base, s8 *res) kstrtos8() argument
314 rv = kstrtoll(s, base, &tmp); kstrtos8()
325 int f(const char __user *s, size_t count, unsigned int base, type *res) \
327 /* sign, base 2 representation, newline, terminator */ \
334 return g(buf, base, res); \
|
| /linux-4.4.14/arch/sparc/kernel/ |
| H A D | kstack.h | 12 unsigned long base = (unsigned long) tp; kstack_valid() local
18 if (sp >= (base + sizeof(struct thread_info)) && kstack_valid()
19 sp <= (base + THREAD_SIZE - sizeof(struct sparc_stackf))) kstack_valid()
23 base = (unsigned long) hardirq_stack[tp->cpu]; kstack_valid()
24 if (sp >= base && kstack_valid()
25 sp <= (base + THREAD_SIZE - sizeof(struct sparc_stackf))) kstack_valid()
27 base = (unsigned long) softirq_stack[tp->cpu]; kstack_valid()
28 if (sp >= base && kstack_valid()
29 sp <= (base + THREAD_SIZE - sizeof(struct sparc_stackf))) kstack_valid()
38 unsigned long base = (unsigned long) tp; kstack_is_trap_frame() local
41 if (addr >= base && kstack_is_trap_frame()
42 addr <= (base + THREAD_SIZE - sizeof(*regs))) kstack_is_trap_frame()
46 base = (unsigned long) hardirq_stack[tp->cpu]; kstack_is_trap_frame()
47 if (addr >= base && kstack_is_trap_frame()
48 addr <= (base + THREAD_SIZE - sizeof(*regs))) kstack_is_trap_frame()
50 base = (unsigned long) softirq_stack[tp->cpu]; kstack_is_trap_frame()
51 if (addr >= base && kstack_is_trap_frame()
52 addr <= (base + THREAD_SIZE - sizeof(*regs))) kstack_is_trap_frame()
|
| /linux-4.4.14/arch/mips/ath25/ |
| H A D | early_printk.c | 17 static inline void prom_uart_wr(void __iomem *base, unsigned reg, prom_uart_wr() argument
20 __raw_writel(ch, base + 4 * reg); prom_uart_wr()
23 static inline unsigned char prom_uart_rr(void __iomem *base, unsigned reg) prom_uart_rr() argument
25 return __raw_readl(base + 4 * reg); prom_uart_rr()
30 static void __iomem *base; prom_putchar() local
32 if (unlikely(base == NULL)) { prom_putchar()
34 base = (void __iomem *)(KSEG1ADDR(AR2315_UART0_BASE)); prom_putchar()
36 base = (void __iomem *)(KSEG1ADDR(AR5312_UART0_BASE)); prom_putchar()
39 while ((prom_uart_rr(base, UART_LSR) & UART_LSR_THRE) == 0) prom_putchar()
41 prom_uart_wr(base, UART_TX, ch); prom_putchar()
42 while ((prom_uart_rr(base, UART_LSR) & UART_LSR_THRE) == 0) prom_putchar()
|
| /linux-4.4.14/arch/arm/plat-orion/include/plat/ |
| H A D | pcie.h | 16 u32 orion_pcie_dev_id(void __iomem *base);
17 u32 orion_pcie_rev(void __iomem *base);
18 int orion_pcie_link_up(void __iomem *base);
19 int orion_pcie_x4_mode(void __iomem *base);
20 int orion_pcie_get_local_bus_nr(void __iomem *base);
21 void orion_pcie_set_local_bus_nr(void __iomem *base, int nr);
22 void orion_pcie_reset(void __iomem *base);
23 void orion_pcie_setup(void __iomem *base);
24 int orion_pcie_rd_conf(void __iomem *base, struct pci_bus *bus,
26 int orion_pcie_rd_conf_tlp(void __iomem *base, struct pci_bus *bus,
30 int orion_pcie_wr_conf(void __iomem *base, struct pci_bus *bus,
|
| /linux-4.4.14/drivers/irqchip/ |
| H A D | irq-sirfsoc.c | 32 static __init void sirfsoc_alloc_gc(void __iomem *base) sirfsoc_alloc_gc() argument
46 gc->reg_base = base + i * SIRFSOC_INT_BASE_OFFSET; sirfsoc_alloc_gc()
56 void __iomem *base = sirfsoc_irqdomain->host_data; sirfsoc_handle_irq() local
59 irqstat = readl_relaxed(base + SIRFSOC_INIT_IRQ_ID); sirfsoc_handle_irq()
66 void __iomem *base = of_iomap(np, 0); sirfsoc_irq_init() local
67 if (!base) sirfsoc_irq_init()
71 &irq_generic_chip_ops, base); sirfsoc_irq_init()
72 sirfsoc_alloc_gc(base); sirfsoc_irq_init()
74 writel_relaxed(0, base + SIRFSOC_INT_RISC_LEVEL0); sirfsoc_irq_init()
75 writel_relaxed(0, base + SIRFSOC_INT_RISC_LEVEL1); sirfsoc_irq_init()
77 writel_relaxed(0, base + SIRFSOC_INT_RISC_MASK0); sirfsoc_irq_init()
78 writel_relaxed(0, base + SIRFSOC_INT_RISC_MASK1); sirfsoc_irq_init()
97 void __iomem *base = sirfsoc_irqdomain->host_data; sirfsoc_irq_suspend() local
99 sirfsoc_irq_st.mask0 = readl_relaxed(base + SIRFSOC_INT_RISC_MASK0); sirfsoc_irq_suspend()
100 sirfsoc_irq_st.mask1 = readl_relaxed(base + SIRFSOC_INT_RISC_MASK1); sirfsoc_irq_suspend()
101 sirfsoc_irq_st.level0 = readl_relaxed(base + SIRFSOC_INT_RISC_LEVEL0); sirfsoc_irq_suspend()
102 sirfsoc_irq_st.level1 = readl_relaxed(base + SIRFSOC_INT_RISC_LEVEL1); sirfsoc_irq_suspend()
109 void __iomem *base = sirfsoc_irqdomain->host_data; sirfsoc_irq_resume() local
111 writel_relaxed(sirfsoc_irq_st.mask0, base + SIRFSOC_INT_RISC_MASK0); sirfsoc_irq_resume()
112 writel_relaxed(sirfsoc_irq_st.mask1, base + SIRFSOC_INT_RISC_MASK1); sirfsoc_irq_resume()
113 writel_relaxed(sirfsoc_irq_st.level0, base + SIRFSOC_INT_RISC_LEVEL0); sirfsoc_irq_resume()
114 writel_relaxed(sirfsoc_irq_st.level1, base + SIRFSOC_INT_RISC_LEVEL1); sirfsoc_irq_resume()
|
| H A D | irq-vic.c | 61 * @irq: The IRQ number for the base of the VIC.
62 * @base: The register base for the VIC.
73 void __iomem *base; member in struct:vic_device
94 * @base: Base of the VIC.
99 static void vic_init2(void __iomem *base) vic_init2() argument
104 void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4); vic_init2()
108 writel(32, base + VIC_PL190_DEF_VECT_ADDR); vic_init2()
114 void __iomem *base = vic->base; resume_one_vic() local
116 printk(KERN_DEBUG "%s: resuming vic at %p\n", __func__, base); resume_one_vic()
119 vic_init2(base); resume_one_vic()
121 writel(vic->int_select, base + VIC_INT_SELECT); resume_one_vic()
122 writel(vic->protect, base + VIC_PROTECT); resume_one_vic()
125 writel(vic->int_enable, base + VIC_INT_ENABLE); resume_one_vic()
126 writel(~vic->int_enable, base + VIC_INT_ENABLE_CLEAR); resume_one_vic()
130 writel(vic->soft_int, base + VIC_INT_SOFT); resume_one_vic()
131 writel(~vic->soft_int, base + VIC_INT_SOFT_CLEAR); resume_one_vic()
144 void __iomem *base = vic->base; suspend_one_vic() local
146 printk(KERN_DEBUG "%s: suspending vic at %p\n", __func__, base); suspend_one_vic()
148 vic->int_select = readl(base + VIC_INT_SELECT); suspend_one_vic()
149 vic->int_enable = readl(base + VIC_INT_ENABLE); suspend_one_vic()
150 vic->soft_int = readl(base + VIC_INT_SOFT); suspend_one_vic()
151 vic->protect = readl(base + VIC_PROTECT); suspend_one_vic()
156 writel(vic->resume_irqs, base + VIC_INT_ENABLE); suspend_one_vic()
157 writel(~vic->resume_irqs, base + VIC_INT_ENABLE_CLEAR); suspend_one_vic()
203 irq_set_chip_data(irq, v->base); vic_irqdomain_map()
219 while ((stat = readl_relaxed(vic->base + VIC_IRQ_STATUS))) { handle_one_vic()
236 while ((stat = readl_relaxed(vic->base + VIC_IRQ_STATUS))) { vic_handle_irq_cascaded()
265 * @base: The base address of the VIC.
267 * @irq: The base IRQ for the VIC.
278 static void __init vic_register(void __iomem *base, unsigned int parent_irq, vic_register() argument
292 v->base = base; vic_register()
309 /* If no base IRQ was passed, figure out our allocated base */ vic_register()
318 void __iomem *base = irq_data_get_irq_chip_data(d); vic_ack_irq() local
320 writel(1 << irq, base + VIC_INT_ENABLE_CLEAR); vic_ack_irq()
322 writel(1 << irq, base + VIC_INT_SOFT_CLEAR); vic_ack_irq()
327 void __iomem *base = irq_data_get_irq_chip_data(d); vic_mask_irq() local
329 writel(1 << irq, base + VIC_INT_ENABLE_CLEAR); vic_mask_irq()
334 void __iomem *base = irq_data_get_irq_chip_data(d); vic_unmask_irq() local
336 writel(1 << irq, base + VIC_INT_ENABLE); vic_unmask_irq()
385 static void __init vic_disable(void __iomem *base) vic_disable() argument
387 writel(0, base + VIC_INT_SELECT); vic_disable()
388 writel(0, base + VIC_INT_ENABLE); vic_disable()
389 writel(~0, base + VIC_INT_ENABLE_CLEAR); vic_disable()
390 writel(0, base + VIC_ITCR); vic_disable()
391 writel(~0, base + VIC_INT_SOFT_CLEAR); vic_disable()
394 static void __init vic_clear_interrupts(void __iomem *base) vic_clear_interrupts() argument
398 writel(0, base + VIC_PL190_VECT_ADDR); vic_clear_interrupts()
402 value = readl(base + VIC_PL190_VECT_ADDR); vic_clear_interrupts()
403 writel(value, base + VIC_PL190_VECT_ADDR); vic_clear_interrupts()
411 * the probe function is called twice, with base set to offset 000
414 static void __init vic_init_st(void __iomem *base, unsigned int irq_start, vic_init_st() argument
418 int vic_2nd_block = ((unsigned long)base & ~PAGE_MASK) != 0; vic_init_st()
421 vic_disable(base); vic_init_st()
427 * the second base address, which is 0x20 in the page vic_init_st()
430 vic_clear_interrupts(base); vic_init_st()
434 void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4); vic_init_st()
438 writel(32, base + VIC_PL190_DEF_VECT_ADDR); vic_init_st()
441 vic_register(base, 0, irq_start, vic_sources, 0, node); vic_init_st()
444 void __init __vic_init(void __iomem *base, int parent_irq, int irq_start, __vic_init() argument
455 addr = (void __iomem *)((u32)base & PAGE_MASK) + 0xfe0 + (i * 4); __vic_init()
460 base, cellid, vendor); __vic_init()
464 vic_init_st(base, irq_start, vic_sources, node); __vic_init()
474 vic_disable(base); __vic_init()
477 vic_clear_interrupts(base); __vic_init()
479 vic_init2(base); __vic_init()
481 vic_register(base, parent_irq, irq_start, vic_sources, resume_sources, node); __vic_init()
486 * @base: iomem base address
491 void __init vic_init(void __iomem *base, unsigned int irq_start, vic_init() argument
494 __vic_init(base, 0, irq_start, vic_sources, resume_sources, NULL); vic_init()
499 * @base: iomem base address
505 * This returns the base for the new interrupts or negative on error.
507 int __init vic_init_cascaded(void __iomem *base, unsigned int parent_irq, vic_init_cascaded() argument
513 __vic_init(base, parent_irq, 0, vic_sources, resume_sources, NULL); vic_init_cascaded()
514 /* Return out acquired base */ vic_init_cascaded()
|
| H A D | irq-gic-common.c | 36 void __iomem *base, void (*sync_access)(void)) gic_configure_irq()
47 val = oldval = readl_relaxed(base + GIC_DIST_CONFIG + confoff); gic_configure_irq()
58 writel_relaxed(val, base + GIC_DIST_CONFIG + confoff); gic_configure_irq()
59 if (readl_relaxed(base + GIC_DIST_CONFIG + confoff) != val && val != oldval) gic_configure_irq()
68 void __init gic_dist_config(void __iomem *base, int gic_irqs, gic_dist_config() argument
78 base + GIC_DIST_CONFIG + i / 4); gic_dist_config()
84 writel_relaxed(GICD_INT_DEF_PRI_X4, base + GIC_DIST_PRI + i); gic_dist_config()
92 base + GIC_DIST_ACTIVE_CLEAR + i / 8); gic_dist_config()
94 base + GIC_DIST_ENABLE_CLEAR + i / 8); gic_dist_config()
101 void gic_cpu_config(void __iomem *base, void (*sync_access)(void)) gic_cpu_config() argument
110 writel_relaxed(GICD_INT_EN_CLR_X32, base + GIC_DIST_ACTIVE_CLEAR); gic_cpu_config()
111 writel_relaxed(GICD_INT_EN_CLR_PPI, base + GIC_DIST_ENABLE_CLEAR); gic_cpu_config()
112 writel_relaxed(GICD_INT_EN_SET_SGI, base + GIC_DIST_ENABLE_SET); gic_cpu_config()
119 base + GIC_DIST_PRI + i * 4 / 4); gic_cpu_config()
35 gic_configure_irq(unsigned int irq, unsigned int type, void __iomem *base, void (*sync_access)(void)) gic_configure_irq() argument
|
| H A D | irq-moxart.c | 39 void __iomem *base; member in struct:moxart_irq_data
51 irqstat = readl(intc.base + IRQ_STATUS_REG); handle_irq()
67 intc.base = of_iomap(node, 0); moxart_of_intc_init()
68 if (!intc.base) { moxart_of_intc_init()
75 intc.base); moxart_of_intc_init()
99 gc->reg_base = intc.base; moxart_of_intc_init()
106 writel(0, intc.base + IRQ_MASK_REG); moxart_of_intc_init()
107 writel(0xffffffff, intc.base + IRQ_CLEAR_REG); moxart_of_intc_init()
109 writel(intc.interrupt_mask, intc.base + IRQ_MODE_REG); moxart_of_intc_init()
110 writel(intc.interrupt_mask, intc.base + IRQ_LEVEL_REG); moxart_of_intc_init()
|
| H A D | irq-versatile-fpga.c | 34 * @base: memory offset in virtual memory
41 void __iomem *base; member in struct:fpga_irq_data
57 writel(mask, f->base + IRQ_ENABLE_CLEAR); fpga_irq_mask()
65 writel(mask, f->base + IRQ_ENABLE_SET); fpga_irq_unmask()
71 u32 status = readl(f->base + IRQ_STATUS); fpga_irq_handle()
97 while ((status = readl(f->base + IRQ_STATUS))) { handle_one_fpga()
140 void __init fpga_irq_init(void __iomem *base, const char *name, int irq_start, fpga_irq_init() argument
151 f->base = base; fpga_irq_init()
176 fpga_irq_id, name, base, f->used_irqs); fpga_irq_init()
189 void __iomem *base; fpga_irq_of_init() local
197 base = of_iomap(node, 0); fpga_irq_of_init()
198 WARN(!base, "unable to map fpga irq registers\n"); fpga_irq_of_init()
214 fpga_irq_init(base, node->name, IRQ_SIC_START, parent_irq, valid_mask, fpga_irq_of_init()
217 fpga_irq_init(base, node->name, 0, parent_irq, valid_mask, node); fpga_irq_of_init()
220 writel(clear_mask, base + IRQ_ENABLE_CLEAR); fpga_irq_of_init()
221 writel(clear_mask, base + FIQ_ENABLE_CLEAR); fpga_irq_of_init()
229 writel(0xffd00000, base + PIC_ENABLES); fpga_irq_of_init()
|
| /linux-4.4.14/drivers/clk/ |
| H A D | clk-efm32gg.c | 27 void __iomem *base; efm32gg_cmu_init() local
32 base = of_iomap(np, 0); efm32gg_cmu_init()
33 if (!base) { efm32gg_cmu_init()
42 "HFXO", 0, base + CMU_HFPERCLKEN0, 0, 0, NULL); efm32gg_cmu_init()
44 "HFXO", 0, base + CMU_HFPERCLKEN0, 1, 0, NULL); efm32gg_cmu_init()
46 "HFXO", 0, base + CMU_HFPERCLKEN0, 2, 0, NULL); efm32gg_cmu_init()
48 "HFXO", 0, base + CMU_HFPERCLKEN0, 3, 0, NULL); efm32gg_cmu_init()
50 "HFXO", 0, base + CMU_HFPERCLKEN0, 4, 0, NULL); efm32gg_cmu_init()
52 "HFXO", 0, base + CMU_HFPERCLKEN0, 5, 0, NULL); efm32gg_cmu_init()
54 "HFXO", 0, base + CMU_HFPERCLKEN0, 6, 0, NULL); efm32gg_cmu_init()
56 "HFXO", 0, base + CMU_HFPERCLKEN0, 7, 0, NULL); efm32gg_cmu_init()
58 "HFXO", 0, base + CMU_HFPERCLKEN0, 8, 0, NULL); efm32gg_cmu_init()
60 "HFXO", 0, base + CMU_HFPERCLKEN0, 9, 0, NULL); efm32gg_cmu_init()
62 "HFXO", 0, base + CMU_HFPERCLKEN0, 10, 0, NULL); efm32gg_cmu_init()
64 "HFXO", 0, base + CMU_HFPERCLKEN0, 11, 0, NULL); efm32gg_cmu_init()
66 "HFXO", 0, base + CMU_HFPERCLKEN0, 12, 0, NULL); efm32gg_cmu_init()
68 "HFXO", 0, base + CMU_HFPERCLKEN0, 13, 0, NULL); efm32gg_cmu_init()
70 "HFXO", 0, base + CMU_HFPERCLKEN0, 14, 0, NULL); efm32gg_cmu_init()
72 "HFXO", 0, base + CMU_HFPERCLKEN0, 15, 0, NULL); efm32gg_cmu_init()
74 "HFXO", 0, base + CMU_HFPERCLKEN0, 16, 0, NULL); efm32gg_cmu_init()
76 "HFXO", 0, base + CMU_HFPERCLKEN0, 17, 0, NULL); efm32gg_cmu_init()
|
| H A D | clk-moxart.c | 21 static void __iomem *base; moxart_of_pll_clk_init() local
30 base = of_iomap(node, 0); moxart_of_pll_clk_init()
31 if (!base) { moxart_of_pll_clk_init()
36 mul = readl(base + 0x30) >> 3 & 0x3f; moxart_of_pll_clk_init()
37 iounmap(base); moxart_of_pll_clk_init()
59 static void __iomem *base; moxart_of_apb_clk_init() local
69 base = of_iomap(node, 0); moxart_of_apb_clk_init()
70 if (!base) { moxart_of_apb_clk_init()
75 val = readl(base + 0xc) >> 4 & 0x7; moxart_of_apb_clk_init()
76 iounmap(base); moxart_of_apb_clk_init()
|
| /linux-4.4.14/include/linux/spi/ |
| H A D | mc33880.h | 6 unsigned base; member in struct:mc33880_platform_data
|
| /linux-4.4.14/arch/mips/alchemy/common/ |
| H A D | vss.c | 24 void __iomem *base = (void __iomem *)VSS_ADDR(block); __enable_block() local
26 __raw_writel(3, base + VSS_CLKRST); /* enable clock, assert reset */ __enable_block()
29 __raw_writel(0x01fffffe, base + VSS_GATE); /* maximum setup time */ __enable_block()
33 __raw_writel(0x01, base + VSS_FTR); __enable_block()
35 __raw_writel(0x03, base + VSS_FTR); __enable_block()
37 __raw_writel(0x07, base + VSS_FTR); __enable_block()
39 __raw_writel(0x0f, base + VSS_FTR); __enable_block()
42 __raw_writel(0x01ffffff, base + VSS_GATE); /* start FSM too */ __enable_block()
45 __raw_writel(2, base + VSS_CLKRST); /* deassert reset */ __enable_block()
48 __raw_writel(0x1f, base + VSS_FTR); /* enable isolation cells */ __enable_block()
55 void __iomem *base = (void __iomem *)VSS_ADDR(block); __disable_block() local
57 __raw_writel(0x0f, base + VSS_FTR); /* disable isolation cells */ __disable_block()
59 __raw_writel(0, base + VSS_GATE); /* disable FSM */ __disable_block()
61 __raw_writel(3, base + VSS_CLKRST); /* assert reset */ __disable_block()
63 __raw_writel(1, base + VSS_CLKRST); /* disable clock */ __disable_block()
65 __raw_writel(0, base + VSS_FTR); /* disable all footers */ __disable_block()
|
| H A D | usb.c | 5 * area. Au1550 has OHCI on different base address. No need to handle
97 static inline void __au1300_usb_phyctl(void __iomem *base, int enable) __au1300_usb_phyctl() argument
101 r = __raw_readl(base + USB_DWC_CTRL2); __au1300_usb_phyctl()
102 s = __raw_readl(base + USB_DWC_CTRL3); __au1300_usb_phyctl()
111 __raw_writel(r, base + USB_DWC_CTRL2); __au1300_usb_phyctl()
117 __raw_writel(r, base + USB_DWC_CTRL2); __au1300_usb_phyctl()
122 static inline void __au1300_ohci_control(void __iomem *base, int enable, int id) __au1300_ohci_control() argument
127 __raw_writel(1, base + USB_DWC_CTRL7); /* start OHCI clock */ __au1300_ohci_control()
130 r = __raw_readl(base + USB_DWC_CTRL3); /* enable OHCI block */ __au1300_ohci_control()
133 __raw_writel(r, base + USB_DWC_CTRL3); __au1300_ohci_control()
136 __au1300_usb_phyctl(base, enable); /* power up the PHYs */ __au1300_ohci_control()
138 r = __raw_readl(base + USB_INT_ENABLE); __au1300_ohci_control()
140 __raw_writel(r, base + USB_INT_ENABLE); __au1300_ohci_control()
144 __raw_writel(0, base + USB_DWC_CTRL7); __au1300_ohci_control()
147 r = __raw_readl(base + USB_INT_ENABLE); __au1300_ohci_control()
149 __raw_writel(r, base + USB_INT_ENABLE); __au1300_ohci_control()
152 r = __raw_readl(base + USB_DWC_CTRL3); __au1300_ohci_control()
155 __raw_writel(r, base + USB_DWC_CTRL3); __au1300_ohci_control()
158 __au1300_usb_phyctl(base, enable); __au1300_ohci_control()
162 static inline void __au1300_ehci_control(void __iomem *base, int enable) __au1300_ehci_control() argument
167 r = __raw_readl(base + USB_DWC_CTRL3); __au1300_ehci_control()
169 __raw_writel(r, base + USB_DWC_CTRL3); __au1300_ehci_control()
172 r = __raw_readl(base + USB_DWC_CTRL1); __au1300_ehci_control()
174 __raw_writel(r, base + USB_DWC_CTRL1); __au1300_ehci_control()
177 __au1300_usb_phyctl(base, enable); __au1300_ehci_control()
179 r = __raw_readl(base + USB_INT_ENABLE); __au1300_ehci_control()
181 __raw_writel(r, base + USB_INT_ENABLE); __au1300_ehci_control()
184 r = __raw_readl(base + USB_INT_ENABLE); __au1300_ehci_control()
186 __raw_writel(r, base + USB_INT_ENABLE); __au1300_ehci_control()
189 r = __raw_readl(base + USB_DWC_CTRL1); __au1300_ehci_control()
191 __raw_writel(r, base + USB_DWC_CTRL1); __au1300_ehci_control()
194 r = __raw_readl(base + USB_DWC_CTRL3); __au1300_ehci_control()
196 __raw_writel(r, base + USB_DWC_CTRL3); __au1300_ehci_control()
199 __au1300_usb_phyctl(base, enable); __au1300_ehci_control()
203 static inline void __au1300_udc_control(void __iomem *base, int enable) __au1300_udc_control() argument
208 r = __raw_readl(base + USB_DWC_CTRL1); __au1300_udc_control()
210 __raw_writel(r, base + USB_DWC_CTRL1); __au1300_udc_control()
213 __au1300_usb_phyctl(base, enable); __au1300_udc_control()
215 r = __raw_readl(base + USB_INT_ENABLE); __au1300_udc_control()
217 __raw_writel(r, base + USB_INT_ENABLE); __au1300_udc_control()
220 r = __raw_readl(base + USB_INT_ENABLE); __au1300_udc_control()
222 __raw_writel(r, base + USB_INT_ENABLE); __au1300_udc_control()
225 r = __raw_readl(base + USB_DWC_CTRL1); __au1300_udc_control()
227 __raw_writel(r, base + USB_DWC_CTRL1); __au1300_udc_control()
230 __au1300_usb_phyctl(base, enable); __au1300_udc_control()
234 static inline void __au1300_otg_control(void __iomem *base, int enable) __au1300_otg_control() argument
238 r = __raw_readl(base + USB_DWC_CTRL3); __au1300_otg_control()
240 __raw_writel(r, base + USB_DWC_CTRL3); __au1300_otg_control()
243 r = __raw_readl(base + USB_DWC_CTRL1); __au1300_otg_control()
245 __raw_writel(r, base + USB_DWC_CTRL1); __au1300_otg_control()
248 __au1300_usb_phyctl(base, enable); __au1300_otg_control()
250 r = __raw_readl(base + USB_DWC_CTRL1); __au1300_otg_control()
252 __raw_writel(r, base + USB_DWC_CTRL1); __au1300_otg_control()
255 r = __raw_readl(base + USB_DWC_CTRL3); __au1300_otg_control()
257 __raw_writel(r, base + USB_DWC_CTRL3); __au1300_otg_control()
260 __au1300_usb_phyctl(base, enable); __au1300_otg_control()
266 void __iomem *base = au1300_usb_control() local
272 __au1300_ohci_control(base, enable, 0); au1300_usb_control()
275 __au1300_ohci_control(base, enable, 1); au1300_usb_control()
278 __au1300_ehci_control(base, enable); au1300_usb_control()
281 __au1300_udc_control(base, enable); au1300_usb_control()
284 __au1300_otg_control(base, enable); au1300_usb_control()
294 void __iomem *base = au1300_usb_init() local
302 __raw_writel(0, base + USB_INT_ENABLE); /* disable all USB irqs */ au1300_usb_init()
304 __raw_writel(0, base + USB_DWC_CTRL3); /* disable all clocks */ au1300_usb_init()
306 __raw_writel(~0, base + USB_MSR_ERR); /* clear all errors */ au1300_usb_init()
308 __raw_writel(~0, base + USB_INT_STATUS); /* clear int status */ au1300_usb_init()
311 __raw_writel(USB_SBUS_CTRL_SBCA, base + USB_SBUS_CTRL); au1300_usb_init()
315 static inline void __au1200_ohci_control(void __iomem *base, int enable) __au1200_ohci_control() argument
317 unsigned long r = __raw_readl(base + AU1200_USBCFG); __au1200_ohci_control()
319 __raw_writel(r | USBCFG_OCE, base + AU1200_USBCFG); __au1200_ohci_control()
323 __raw_writel(r & ~USBCFG_OCE, base + AU1200_USBCFG); __au1200_ohci_control()
329 static inline void __au1200_ehci_control(void __iomem *base, int enable) __au1200_ehci_control() argument
331 unsigned long r = __raw_readl(base + AU1200_USBCFG); __au1200_ehci_control()
333 __raw_writel(r | USBCFG_ECE | USBCFG_PPE, base + AU1200_USBCFG); __au1200_ehci_control()
339 __raw_writel(r & ~USBCFG_ECE, base + AU1200_USBCFG); __au1200_ehci_control()
345 static inline void __au1200_udc_control(void __iomem *base, int enable) __au1200_udc_control() argument
347 unsigned long r = __raw_readl(base + AU1200_USBCFG); __au1200_udc_control()
349 __raw_writel(r | USBCFG_UCE | USBCFG_PPE, base + AU1200_USBCFG); __au1200_udc_control()
354 __raw_writel(r & ~USBCFG_UCE, base + AU1200_USBCFG); __au1200_udc_control()
361 void __iomem *base = au1200_usb_control() local
366 __au1200_ohci_control(base, enable); au1200_usb_control()
369 __au1200_udc_control(base, enable); au1200_usb_control()
372 __au1200_ehci_control(base, enable); au1200_usb_control()
384 void __iomem *base = au1200_usb_init() local
386 __raw_writel(USBCFG_INIT_AU1200, base + AU1200_USBCFG); au1200_usb_init()
393 void __iomem *base = (void __iomem *)KSEG1ADDR(rb + reg); au1000_usb_init() local
394 unsigned long r = __raw_readl(base); au1000_usb_init()
416 __raw_writel(r, base); au1000_usb_init()
426 void __iomem *base = (void __iomem *)KSEG1ADDR(rb); __au1xx0_ohci_control() local
427 unsigned long r = __raw_readl(base + creg); __au1xx0_ohci_control()
437 __raw_writel(r | USBHEN_CE, base + creg); __au1xx0_ohci_control()
440 __raw_writel(r | USBHEN_CE | USBHEN_E, base + creg); __au1xx0_ohci_control()
445 while (__raw_readl(base + creg), __au1xx0_ohci_control()
446 !(__raw_readl(base + creg) & USBHEN_RD)) __au1xx0_ohci_control()
449 __raw_writel(r & ~(USBHEN_CE | USBHEN_E), base + creg); __au1xx0_ohci_control()
513 void __iomem *base = (void __iomem *)KSEG1ADDR(br); au1000_usb_pm() local
516 alchemy_usb_pmdata[0] = __raw_readl(base + creg); au1000_usb_pm()
518 __raw_writel(0, base + 0x04); au1000_usb_pm()
520 __raw_writel(0, base + creg); au1000_usb_pm()
523 __raw_writel(alchemy_usb_pmdata[0], base + creg); au1000_usb_pm()
530 void __iomem *base = au1200_usb_pm() local
535 alchemy_usb_pmdata[0] = __raw_readl(base + 0x00); au1200_usb_pm()
536 alchemy_usb_pmdata[1] = __raw_readl(base + 0x04); au1200_usb_pm()
542 __raw_writel(alchemy_usb_pmdata[0], base + 0x00); au1200_usb_pm()
543 __raw_writel(alchemy_usb_pmdata[1], base + 0x04); au1200_usb_pm()
550 void __iomem *base = au1300_usb_pm() local
554 alchemy_usb_pmdata[0] = __raw_readl(base + USB_DWC_CTRL4); au1300_usb_pm()
557 __raw_writel(alchemy_usb_pmdata[0], base + USB_DWC_CTRL4); au1300_usb_pm()
|
| H A D | irq.c | 291 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR); au1x_ic0_unmask() local
293 __raw_writel(1 << bit, base + IC_MASKSET); au1x_ic0_unmask()
294 __raw_writel(1 << bit, base + IC_WAKESET); au1x_ic0_unmask()
301 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR); au1x_ic1_unmask() local
303 __raw_writel(1 << bit, base + IC_MASKSET); au1x_ic1_unmask()
304 __raw_writel(1 << bit, base + IC_WAKESET); au1x_ic1_unmask()
311 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR); au1x_ic0_mask() local
313 __raw_writel(1 << bit, base + IC_MASKCLR); au1x_ic0_mask()
314 __raw_writel(1 << bit, base + IC_WAKECLR); au1x_ic0_mask()
321 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR); au1x_ic1_mask() local
323 __raw_writel(1 << bit, base + IC_MASKCLR); au1x_ic1_mask()
324 __raw_writel(1 << bit, base + IC_WAKECLR); au1x_ic1_mask()
331 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR); au1x_ic0_ack() local
337 __raw_writel(1 << bit, base + IC_FALLINGCLR); au1x_ic0_ack()
338 __raw_writel(1 << bit, base + IC_RISINGCLR); au1x_ic0_ack()
345 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR); au1x_ic1_ack() local
351 __raw_writel(1 << bit, base + IC_FALLINGCLR); au1x_ic1_ack()
352 __raw_writel(1 << bit, base + IC_RISINGCLR); au1x_ic1_ack()
359 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR); au1x_ic0_maskack() local
361 __raw_writel(1 << bit, base + IC_WAKECLR); au1x_ic0_maskack()
362 __raw_writel(1 << bit, base + IC_MASKCLR); au1x_ic0_maskack()
363 __raw_writel(1 << bit, base + IC_RISINGCLR); au1x_ic0_maskack()
364 __raw_writel(1 << bit, base + IC_FALLINGCLR); au1x_ic0_maskack()
371 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR); au1x_ic1_maskack() local
373 __raw_writel(1 << bit, base + IC_WAKECLR); au1x_ic1_maskack()
374 __raw_writel(1 << bit, base + IC_MASKCLR); au1x_ic1_maskack()
375 __raw_writel(1 << bit, base + IC_RISINGCLR); au1x_ic1_maskack()
376 __raw_writel(1 << bit, base + IC_FALLINGCLR); au1x_ic1_maskack()
432 void __iomem *base; au1x_ic_settype() local
438 base = (void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR); au1x_ic_settype()
442 base = (void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR); au1x_ic_settype()
452 __raw_writel(1 << bit, base + IC_CFG2CLR); au1x_ic_settype()
453 __raw_writel(1 << bit, base + IC_CFG1CLR); au1x_ic_settype()
454 __raw_writel(1 << bit, base + IC_CFG0SET); au1x_ic_settype()
459 __raw_writel(1 << bit, base + IC_CFG2CLR); au1x_ic_settype()
460 __raw_writel(1 << bit, base + IC_CFG1SET); au1x_ic_settype()
461 __raw_writel(1 << bit, base + IC_CFG0CLR); au1x_ic_settype()
466 __raw_writel(1 << bit, base + IC_CFG2CLR); au1x_ic_settype()
467 __raw_writel(1 << bit, base + IC_CFG1SET); au1x_ic_settype()
468 __raw_writel(1 << bit, base + IC_CFG0SET); au1x_ic_settype()
473 __raw_writel(1 << bit, base + IC_CFG2SET); au1x_ic_settype()
474 __raw_writel(1 << bit, base + IC_CFG1CLR); au1x_ic_settype()
475 __raw_writel(1 << bit, base + IC_CFG0SET); au1x_ic_settype()
480 __raw_writel(1 << bit, base + IC_CFG2SET); au1x_ic_settype()
481 __raw_writel(1 << bit, base + IC_CFG1SET); au1x_ic_settype()
482 __raw_writel(1 << bit, base + IC_CFG0CLR); au1x_ic_settype()
487 __raw_writel(1 << bit, base + IC_CFG2CLR); au1x_ic_settype()
488 __raw_writel(1 << bit, base + IC_CFG1CLR); au1x_ic_settype()
489 __raw_writel(1 << bit, base + IC_CFG0CLR); au1x_ic_settype()
715 static inline void ic_init(void __iomem *base) ic_init() argument
718 __raw_writel(0xffffffff, base + IC_CFG0CLR); ic_init()
719 __raw_writel(0xffffffff, base + IC_CFG1CLR); ic_init()
720 __raw_writel(0xffffffff, base + IC_CFG2CLR); ic_init()
721 __raw_writel(0xffffffff, base + IC_MASKCLR); ic_init()
722 __raw_writel(0xffffffff, base + IC_ASSIGNCLR); ic_init()
723 __raw_writel(0xffffffff, base + IC_WAKECLR); ic_init()
724 __raw_writel(0xffffffff, base + IC_SRCSET); ic_init()
725 __raw_writel(0xffffffff, base + IC_FALLINGCLR); ic_init()
726 __raw_writel(0xffffffff, base + IC_RISINGCLR); ic_init()
727 __raw_writel(0x00000000, base + IC_TESTBIT); ic_init()
733 static inline void alchemy_ic_suspend_one(void __iomem *base, unsigned long *d) alchemy_ic_suspend_one() argument
735 d[0] = __raw_readl(base + IC_CFG0RD); alchemy_ic_suspend_one()
736 d[1] = __raw_readl(base + IC_CFG1RD); alchemy_ic_suspend_one()
737 d[2] = __raw_readl(base + IC_CFG2RD); alchemy_ic_suspend_one()
738 d[3] = __raw_readl(base + IC_SRCRD); alchemy_ic_suspend_one()
739 d[4] = __raw_readl(base + IC_ASSIGNRD); alchemy_ic_suspend_one()
740 d[5] = __raw_readl(base + IC_WAKERD); alchemy_ic_suspend_one()
741 d[6] = __raw_readl(base + IC_MASKRD); alchemy_ic_suspend_one()
742 ic_init(base); /* shut it up too while at it */ alchemy_ic_suspend_one()
745 static inline void alchemy_ic_resume_one(void __iomem *base, unsigned long *d) alchemy_ic_resume_one() argument
747 ic_init(base); alchemy_ic_resume_one()
749 __raw_writel(d[0], base + IC_CFG0SET); alchemy_ic_resume_one()
750 __raw_writel(d[1], base + IC_CFG1SET); alchemy_ic_resume_one()
751 __raw_writel(d[2], base + IC_CFG2SET); alchemy_ic_resume_one()
752 __raw_writel(d[3], base + IC_SRCSET); alchemy_ic_resume_one()
753 __raw_writel(d[4], base + IC_ASSIGNSET); alchemy_ic_resume_one()
754 __raw_writel(d[5], base + IC_WAKESET); alchemy_ic_resume_one()
757 __raw_writel(d[6], base + IC_MASKSET); alchemy_ic_resume_one()
780 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1300_GPIC_PHYS_ADDR); alchemy_gpic_suspend() local
784 alchemy_gpic_pmdata[0] = __raw_readl(base + AU1300_GPIC_IEN + 0x0); alchemy_gpic_suspend()
785 alchemy_gpic_pmdata[1] = __raw_readl(base + AU1300_GPIC_IEN + 0x4); alchemy_gpic_suspend()
786 alchemy_gpic_pmdata[2] = __raw_readl(base + AU1300_GPIC_IEN + 0x8); alchemy_gpic_suspend()
787 alchemy_gpic_pmdata[3] = __raw_readl(base + AU1300_GPIC_IEN + 0xc); alchemy_gpic_suspend()
790 alchemy_gpic_pmdata[4] = __raw_readl(base + AU1300_GPIC_DMASEL); alchemy_gpic_suspend()
793 __raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0x0); alchemy_gpic_suspend()
794 __raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0x4); alchemy_gpic_suspend()
795 __raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0x8); alchemy_gpic_suspend()
796 __raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0xc); alchemy_gpic_suspend()
800 base += AU1300_GPIC_PINCFG; alchemy_gpic_suspend()
802 alchemy_gpic_pmdata[i + 5] = __raw_readl(base + (i << 2)); alchemy_gpic_suspend()
811 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1300_GPIC_PHYS_ADDR); alchemy_gpic_resume() local
815 __raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0x0); alchemy_gpic_resume()
816 __raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0x4); alchemy_gpic_resume()
817 __raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0x8); alchemy_gpic_resume()
818 __raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0xc); alchemy_gpic_resume()
822 base += AU1300_GPIC_PINCFG; alchemy_gpic_resume()
824 __raw_writel(alchemy_gpic_pmdata[i + 5], base + (i << 2)); alchemy_gpic_resume()
828 base = (void __iomem *)KSEG1ADDR(AU1300_GPIC_PHYS_ADDR); alchemy_gpic_resume()
829 __raw_writel(alchemy_gpic_pmdata[4], base + AU1300_GPIC_DMASEL); alchemy_gpic_resume()
833 __raw_writel(alchemy_gpic_pmdata[0], base + AU1300_GPIC_IEN + 0x0); alchemy_gpic_resume()
834 __raw_writel(alchemy_gpic_pmdata[1], base + AU1300_GPIC_IEN + 0x4); alchemy_gpic_resume()
835 __raw_writel(alchemy_gpic_pmdata[2], base + AU1300_GPIC_IEN + 0x8); alchemy_gpic_resume()
836 __raw_writel(alchemy_gpic_pmdata[3], base + AU1300_GPIC_IEN + 0xc); alchemy_gpic_resume()
853 #define DISP(name, base, addr) \
858 generic_handle_irq(base + __ffs(r)); \
879 void __iomem *base; au1000_init_irq() local
905 base = (void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR); au1000_init_irq()
908 base = (void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR); au1000_init_irq()
911 __raw_writel(1 << bit, base + IC_ASSIGNSET); au1000_init_irq()
|
| /linux-4.4.14/drivers/net/ethernet/broadcom/bnx2x/ |
| H A D | bnx2x_fw_defs.h | 15 #define CSTORM_ASSERT_LIST_INDEX_OFFSET (IRO[152].base)
17 (IRO[151].base + ((assertListEntry) * IRO[151].m1))
19 (IRO[157].base + (((pfId)>>1) * IRO[157].m1) + (((pfId)&1) * \
22 (IRO[158].base + (((pfId)>>1) * IRO[158].m1) + (((pfId)&1) * \
25 (IRO[163].base + ((funcId) * IRO[163].m1))
27 (IRO[153].base + ((funcId) * IRO[153].m1))
29 (IRO[143].base + ((hcIndex) * IRO[143].m1) + ((sbId) * IRO[143].m2))
31 (IRO[142].base + (((hcIndex)>>2) * IRO[142].m1) + (((hcIndex)&3) \
33 #define CSTORM_IGU_MODE_OFFSET (IRO[161].base)
35 (IRO[323].base + ((pfId) * IRO[323].m1))
37 (IRO[324].base + ((pfId) * IRO[324].m1))
39 (IRO[316].base + ((pfId) * IRO[316].m1) + ((iscsiEqId) * IRO[316].m2))
41 (IRO[318].base + ((pfId) * IRO[318].m1) + ((iscsiEqId) * IRO[318].m2))
43 (IRO[317].base + ((pfId) * IRO[317].m1) + ((iscsiEqId) * IRO[317].m2))
45 (IRO[319].base + ((pfId) * IRO[319].m1) + ((iscsiEqId) * IRO[319].m2))
47 (IRO[315].base + ((pfId) * IRO[315].m1) + ((iscsiEqId) * IRO[315].m2))
49 (IRO[321].base + ((pfId) * IRO[321].m1) + ((iscsiEqId) * IRO[321].m2))
51 (IRO[320].base + ((pfId) * IRO[320].m1) + ((iscsiEqId) * IRO[320].m2))
53 (IRO[322].base + ((pfId) * IRO[322].m1))
55 (IRO[314].base + ((pfId) * IRO[314].m1))
57 (IRO[313].base + ((pfId) * IRO[313].m1))
59 (IRO[312].base + ((pfId) * IRO[312].m1))
61 (IRO[155].base + ((funcId) * IRO[155].m1))
63 (IRO[146].base + ((pfId) * IRO[146].m1))
65 (IRO[147].base + ((pfId) * IRO[147].m1))
67 (IRO[145].base + ((pfId) * IRO[145].m1))
70 (IRO[148].base + ((pfId) * IRO[148].m1))
73 (IRO[140].base + ((sbId) * IRO[140].m1) + ((hcIndex) * IRO[140].m2))
75 (IRO[137].base + ((sbId) * IRO[137].m1))
77 (IRO[138].base + ((sbId) * IRO[138].m1))
79 (IRO[139].base + ((sbId) * IRO[139].m1) + ((hcIndex) * IRO[139].m2))
81 (IRO[136].base + ((sbId) * IRO[136].m1))
84 (IRO[141].base + ((sbId) * IRO[141].m1))
87 (IRO[159].base + ((vfId) * IRO[159].m1))
89 (IRO[160].base + ((vfId) * IRO[160].m1))
91 (IRO[154].base + ((funcId) * IRO[154].m1))
93 (IRO[207].base + ((pfId) * IRO[207].m1))
94 #define TSTORM_ASSERT_LIST_INDEX_OFFSET (IRO[102].base)
96 (IRO[101].base + ((assertListEntry) * IRO[101].m1))
98 (IRO[205].base + ((pfId) * IRO[205].m1))
100 (IRO[107].base + ((funcId) * IRO[107].m1))
102 (IRO[278].base + ((pfId) * IRO[278].m1))
104 (IRO[279].base + ((pfId) * IRO[279].m1))
106 (IRO[280].base + ((pfId) * IRO[280].m1))
108 (IRO[281].base + ((pfId) * IRO[281].m1))
110 (IRO[277].base + ((pfId) * IRO[277].m1))
112 (IRO[276].base + ((pfId) * IRO[276].m1))
114 (IRO[275].base + ((pfId) * IRO[275].m1))
116 (IRO[274].base + ((pfId) * IRO[274].m1))
118 (IRO[284].base + ((pfId) * IRO[284].m1))
120 (IRO[270].base + ((pfId) * IRO[270].m1))
122 (IRO[271].base + ((pfId) * IRO[271].m1))
124 (IRO[272].base + ((pfId) * IRO[272].m1))
126 (IRO[273].base + ((pfId) * IRO[273].m1))
128 (IRO[206].base + ((pfId) * IRO[206].m1))
130 (IRO[109].base + ((funcId) * IRO[109].m1))
132 (IRO[223].base + ((pfId) * IRO[223].m1))
134 (IRO[108].base + ((funcId) * IRO[108].m1))
135 #define USTORM_AGG_DATA_OFFSET (IRO[212].base)
137 #define USTORM_ASSERT_LIST_INDEX_OFFSET (IRO[181].base)
139 (IRO[180].base + ((assertListEntry) * IRO[180].m1))
141 (IRO[187].base + ((portId) * IRO[187].m1))
143 (IRO[325].base + ((pfId) * IRO[325].m1))
145 (IRO[182].base + ((funcId) * IRO[182].m1))
147 (IRO[289].base + ((pfId) * IRO[289].m1))
149 (IRO[290].base + ((pfId) * IRO[290].m1))
151 (IRO[294].base + ((pfId) * IRO[294].m1))
153 (IRO[291].base + ((pfId) * IRO[291].m1))
155 (IRO[287].base + ((pfId) * IRO[287].m1))
157 (IRO[286].base + ((pfId) * IRO[286].m1))
159 (IRO[285].base + ((pfId) * IRO[285].m1))
161 (IRO[288].base + ((pfId) * IRO[288].m1))
163 (IRO[292].base + ((pfId) * IRO[292].m1))
165 (IRO[293].base + ((pfId) * IRO[293].m1))
167 (IRO[186].base + ((pfId) * IRO[186].m1))
169 (IRO[184].base + ((funcId) * IRO[184].m1))
171 (IRO[215].base + ((portId) * IRO[215].m1) + ((clientId) * \
174 (IRO[216].base + ((qzoneId) * IRO[216].m1))
175 #define USTORM_TPA_BTR_OFFSET (IRO[213].base)
178 (IRO[183].base + ((funcId) * IRO[183].m1))
179 #define XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE (IRO[67].base)
180 #define XSTORM_AGG_INT_FINAL_CLEANUP_INDEX (IRO[66].base)
181 #define XSTORM_ASSERT_LIST_INDEX_OFFSET (IRO[51].base)
183 (IRO[50].base + ((assertListEntry) * IRO[50].m1))
185 (IRO[43].base + ((portId) * IRO[43].m1))
187 (IRO[45].base + ((pfId) * IRO[45].m1))
189 (IRO[47].base + ((funcId) * IRO[47].m1))
191 (IRO[302].base + ((pfId) * IRO[302].m1))
193 (IRO[305].base + ((pfId) * IRO[305].m1))
195 (IRO[306].base + ((pfId) * IRO[306].m1))
197 (IRO[307].base + ((pfId) * IRO[307].m1))
199 (IRO[308].base + ((pfId) * IRO[308].m1))
201 (IRO[309].base + ((pfId) * IRO[309].m1))
203 (IRO[310].base + ((pfId) * IRO[310].m1))
205 (IRO[311].base + ((pfId) * IRO[311].m1))
207 (IRO[301].base + ((pfId) * IRO[301].m1))
209 (IRO[300].base + ((pfId) * IRO[300].m1))
211 (IRO[299].base + ((pfId) * IRO[299].m1))
213 (IRO[304].base + ((pfId) * IRO[304].m1))
215 (IRO[303].base + ((pfId) * IRO[303].m1))
217 (IRO[298].base + ((pfId) * IRO[298].m1))
219 (IRO[297].base + ((pfId) * IRO[297].m1))
221 (IRO[296].base + ((pfId) * IRO[296].m1))
223 (IRO[295].base + ((pfId) * IRO[295].m1))
225 (IRO[44].base + ((pfId) * IRO[44].m1))
227 (IRO[49].base + ((funcId) * IRO[49].m1))
229 (IRO[32].base + ((funcId) * IRO[32].m1))
232 (IRO[30].base + ((funcId) * IRO[30].m1))
234 (IRO[31].base + ((funcId) * IRO[31].m1))
236 (IRO[217].base + ((portId) * IRO[217].m1))
238 (IRO[218].base + ((portId) * IRO[218].m1))
240 (IRO[220].base + (((pfId)>>1) * IRO[220].m1) + (((pfId)&1) * \
243 (IRO[48].base + ((funcId) * IRO[48].m1))
|
| /linux-4.4.14/arch/powerpc/boot/ |
| H A D | stdlib.c | 15 /* Not currently supported: leading whitespace, sign, 0x prefix, zero base */ strtoull()
16 unsigned long long int strtoull(const char *ptr, char **end, int base) strtoull() argument
20 if (base > 36) strtoull()
26 if (*ptr >= '0' && *ptr <= '9' && *ptr < '0' + base) strtoull()
28 else if (*ptr >= 'A' && *ptr < 'A' + base - 10) strtoull()
30 else if (*ptr >= 'a' && *ptr < 'a' + base - 10) strtoull()
35 ret *= base; strtoull()
|
| H A D | stdlib.h | 4 unsigned long long int strtoull(const char *ptr, char **end, int base);
|
| /linux-4.4.14/arch/powerpc/include/asm/ |
| H A D | ppc_asm.h | 78 #define SAVE_GPR(n, base) std n,GPR0+8*(n)(base)
79 #define REST_GPR(n, base) ld n,GPR0+8*(n)(base)
80 #define SAVE_NVGPRS(base) SAVE_8GPRS(14, base); SAVE_10GPRS(22, base)
81 #define REST_NVGPRS(base) REST_8GPRS(14, base); REST_10GPRS(22, base)
83 #define SAVE_GPR(n, base) stw n,GPR0+4*(n)(base)
84 #define REST_GPR(n, base) lwz n,GPR0+4*(n)(base)
85 #define SAVE_NVGPRS(base) SAVE_GPR(13, base); SAVE_8GPRS(14, base); \
86 SAVE_10GPRS(22, base)
87 #define REST_NVGPRS(base) REST_GPR(13, base); REST_8GPRS(14, base); \
88 REST_10GPRS(22, base)
91 #define SAVE_2GPRS(n, base) SAVE_GPR(n, base); SAVE_GPR(n+1, base)
92 #define SAVE_4GPRS(n, base) SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base)
93 #define SAVE_8GPRS(n, base) SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base)
94 #define SAVE_10GPRS(n, base) SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base)
95 #define REST_2GPRS(n, base) REST_GPR(n, base); REST_GPR(n+1, base)
96 #define REST_4GPRS(n, base) REST_2GPRS(n, base); REST_2GPRS(n+2, base)
97 #define REST_8GPRS(n, base) REST_4GPRS(n, base); REST_4GPRS(n+4, base)
98 #define REST_10GPRS(n, base) REST_8GPRS(n, base); REST_2GPRS(n+8, base)
100 #define SAVE_FPR(n, base) stfd n,8*TS_FPRWIDTH*(n)(base)
101 #define SAVE_2FPRS(n, base) SAVE_FPR(n, base); SAVE_FPR(n+1, base)
102 #define SAVE_4FPRS(n, base) SAVE_2FPRS(n, base); SAVE_2FPRS(n+2, base)
103 #define SAVE_8FPRS(n, base) SAVE_4FPRS(n, base); SAVE_4FPRS(n+4, base)
104 #define SAVE_16FPRS(n, base) SAVE_8FPRS(n, base); SAVE_8FPRS(n+8, base)
105 #define SAVE_32FPRS(n, base) SAVE_16FPRS(n, base); SAVE_16FPRS(n+16, base)
106 #define REST_FPR(n, base) lfd n,8*TS_FPRWIDTH*(n)(base)
107 #define REST_2FPRS(n, base) REST_FPR(n, base); REST_FPR(n+1, base)
108 #define REST_4FPRS(n, base) REST_2FPRS(n, base); REST_2FPRS(n+2, base)
109 #define REST_8FPRS(n, base) REST_4FPRS(n, base); REST_4FPRS(n+4, base)
110 #define REST_16FPRS(n, base) REST_8FPRS(n, base); REST_8FPRS(n+8, base)
111 #define REST_32FPRS(n, base) REST_16FPRS(n, base); REST_16FPRS(n+16, base)
113 #define SAVE_VR(n,b,base) li b,16*(n); stvx n,base,b
114 #define SAVE_2VRS(n,b,base) SAVE_VR(n,b,base); SAVE_VR(n+1,b,base)
115 #define SAVE_4VRS(n,b,base) SAVE_2VRS(n,b,base); SAVE_2VRS(n+2,b,base)
116 #define SAVE_8VRS(n,b,base) SAVE_4VRS(n,b,base); SAVE_4VRS(n+4,b,base)
117 #define SAVE_16VRS(n,b,base) SAVE_8VRS(n,b,base); SAVE_8VRS(n+8,b,base)
118 #define SAVE_32VRS(n,b,base) SAVE_16VRS(n,b,base); SAVE_16VRS(n+16,b,base)
119 #define REST_VR(n,b,base) li b,16*(n); lvx n,base,b
120 #define REST_2VRS(n,b,base) REST_VR(n,b,base); REST_VR(n+1,b,base)
121 #define REST_4VRS(n,b,base) REST_2VRS(n,b,base); REST_2VRS(n+2,b,base)
122 #define REST_8VRS(n,b,base) REST_4VRS(n,b,base); REST_4VRS(n+4,b,base)
123 #define REST_16VRS(n,b,base) REST_8VRS(n,b,base); REST_8VRS(n+8,b,base)
124 #define REST_32VRS(n,b,base) REST_16VRS(n,b,base); REST_16VRS(n+16,b,base)
127 #define STXVD2X_ROT(n,b,base) STXVD2X(n,b,base)
128 #define LXVD2X_ROT(n,b,base) LXVD2X(n,b,base)
130 #define STXVD2X_ROT(n,b,base) XXSWAPD(n,n); \
131 STXVD2X(n,b,base); \
134 #define LXVD2X_ROT(n,b,base) LXVD2X(n,b,base); \
138 #define SAVE_VSR(n,b,base) li b,16*(n); STXVD2X_ROT(n,R##base,R##b)
139 #define SAVE_2VSRS(n,b,base) SAVE_VSR(n,b,base); SAVE_VSR(n+1,b,base)
140 #define SAVE_4VSRS(n,b,base) SAVE_2VSRS(n,b,base); SAVE_2VSRS(n+2,b,base)
141 #define SAVE_8VSRS(n,b,base) SAVE_4VSRS(n,b,base); SAVE_4VSRS(n+4,b,base)
142 #define SAVE_16VSRS(n,b,base) SAVE_8VSRS(n,b,base); SAVE_8VSRS(n+8,b,base)
143 #define SAVE_32VSRS(n,b,base) SAVE_16VSRS(n,b,base); SAVE_16VSRS(n+16,b,base)
144 #define REST_VSR(n,b,base) li b,16*(n); LXVD2X_ROT(n,R##base,R##b)
145 #define REST_2VSRS(n,b,base) REST_VSR(n,b,base); REST_VSR(n+1,b,base)
146 #define REST_4VSRS(n,b,base) REST_2VSRS(n,b,base); REST_2VSRS(n+2,b,base)
147 #define REST_8VSRS(n,b,base) REST_4VSRS(n,b,base); REST_4VSRS(n+4,b,base)
148 #define REST_16VSRS(n,b,base) REST_8VSRS(n,b,base); REST_8VSRS(n+8,b,base)
149 #define REST_32VSRS(n,b,base) REST_16VSRS(n,b,base); REST_16VSRS(n+16,b,base)
152 * b = base register for addressing, o = base offset from register of 1st EVR
509 * physical base address of RAM at compile time.
|
| /linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/engine/fifo/ |
| H A D | gpfifogf100.c | 52 gf100_fifo_gpfifo_engine_fini(struct nvkm_fifo_chan *base, gf100_fifo_gpfifo_engine_fini() argument
56 struct gf100_fifo_chan *chan = gf100_fifo_chan(base); gf100_fifo_gpfifo_engine_fini()
57 struct nvkm_subdev *subdev = &chan->fifo->base.engine.subdev; gf100_fifo_gpfifo_engine_fini()
59 struct nvkm_gpuobj *inst = chan->base.inst; gf100_fifo_gpfifo_engine_fini()
62 nvkm_wr32(device, 0x002634, chan->base.chid); gf100_fifo_gpfifo_engine_fini()
64 if (nvkm_rd32(device, 0x002634) == chan->base.chid) gf100_fifo_gpfifo_engine_fini()
68 chan->base.chid, chan->base.object.client->name); gf100_fifo_gpfifo_engine_fini()
85 gf100_fifo_gpfifo_engine_init(struct nvkm_fifo_chan *base, gf100_fifo_gpfifo_engine_init() argument
89 struct gf100_fifo_chan *chan = gf100_fifo_chan(base); gf100_fifo_gpfifo_engine_init()
90 struct nvkm_gpuobj *inst = chan->base.inst; gf100_fifo_gpfifo_engine_init()
104 gf100_fifo_gpfifo_engine_dtor(struct nvkm_fifo_chan *base, gf100_fifo_gpfifo_engine_dtor() argument
107 struct gf100_fifo_chan *chan = gf100_fifo_chan(base); gf100_fifo_gpfifo_engine_dtor()
113 gf100_fifo_gpfifo_engine_ctor(struct nvkm_fifo_chan *base, gf100_fifo_gpfifo_engine_ctor() argument
117 struct gf100_fifo_chan *chan = gf100_fifo_chan(base); gf100_fifo_gpfifo_engine_ctor()
133 gf100_fifo_gpfifo_fini(struct nvkm_fifo_chan *base) gf100_fifo_gpfifo_fini() argument
135 struct gf100_fifo_chan *chan = gf100_fifo_chan(base); gf100_fifo_gpfifo_fini()
137 struct nvkm_device *device = fifo->base.engine.subdev.device; gf100_fifo_gpfifo_fini()
138 u32 coff = chan->base.chid * 8; gf100_fifo_gpfifo_fini()
152 gf100_fifo_gpfifo_init(struct nvkm_fifo_chan *base) gf100_fifo_gpfifo_init() argument
154 struct gf100_fifo_chan *chan = gf100_fifo_chan(base); gf100_fifo_gpfifo_init()
156 struct nvkm_device *device = fifo->base.engine.subdev.device; gf100_fifo_gpfifo_init()
157 u32 addr = chan->base.inst->addr >> 12; gf100_fifo_gpfifo_init()
158 u32 coff = chan->base.chid * 8; gf100_fifo_gpfifo_init()
170 gf100_fifo_gpfifo_dtor(struct nvkm_fifo_chan *base) gf100_fifo_gpfifo_dtor() argument
172 struct gf100_fifo_chan *chan = gf100_fifo_chan(base); gf100_fifo_gpfifo_dtor()
191 gf100_fifo_gpfifo_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass, gf100_fifo_gpfifo_new() argument
197 struct gf100_fifo *fifo = gf100_fifo(base); gf100_fifo_gpfifo_new()
198 struct nvkm_device *device = fifo->base.engine.subdev.device; gf100_fifo_gpfifo_new()
216 *pobject = &chan->base.object; gf100_fifo_gpfifo_new()
220 ret = nvkm_fifo_chan_ctor(&gf100_fifo_gpfifo_func, &fifo->base, gf100_fifo_gpfifo_new()
230 oclass, &chan->base); gf100_fifo_gpfifo_new()
234 args->v0.chid = chan->base.chid; gf100_fifo_gpfifo_new()
241 nvkm_kmap(chan->base.inst); gf100_fifo_gpfifo_new()
242 nvkm_wo32(chan->base.inst, 0x0200, lower_32_bits(chan->pgd->addr)); gf100_fifo_gpfifo_new()
243 nvkm_wo32(chan->base.inst, 0x0204, upper_32_bits(chan->pgd->addr)); gf100_fifo_gpfifo_new()
244 nvkm_wo32(chan->base.inst, 0x0208, 0xffffffff); gf100_fifo_gpfifo_new()
245 nvkm_wo32(chan->base.inst, 0x020c, 0x000000ff); gf100_fifo_gpfifo_new()
246 nvkm_done(chan->base.inst); gf100_fifo_gpfifo_new()
248 ret = nvkm_vm_ref(chan->base.vm, &chan->vm, chan->pgd); gf100_fifo_gpfifo_new()
254 usermem = chan->base.chid * 0x1000; gf100_fifo_gpfifo_new()
265 nvkm_kmap(chan->base.inst); gf100_fifo_gpfifo_new()
266 nvkm_wo32(chan->base.inst, 0x08, lower_32_bits(usermem)); gf100_fifo_gpfifo_new()
267 nvkm_wo32(chan->base.inst, 0x0c, upper_32_bits(usermem)); gf100_fifo_gpfifo_new()
268 nvkm_wo32(chan->base.inst, 0x10, 0x0000face); gf100_fifo_gpfifo_new()
269 nvkm_wo32(chan->base.inst, 0x30, 0xfffff902); gf100_fifo_gpfifo_new()
270 nvkm_wo32(chan->base.inst, 0x48, lower_32_bits(ioffset)); gf100_fifo_gpfifo_new()
271 nvkm_wo32(chan->base.inst, 0x4c, upper_32_bits(ioffset) | gf100_fifo_gpfifo_new()
273 nvkm_wo32(chan->base.inst, 0x54, 0x00000002); gf100_fifo_gpfifo_new()
274 nvkm_wo32(chan->base.inst, 0x84, 0x20400000); gf100_fifo_gpfifo_new()
275 nvkm_wo32(chan->base.inst, 0x94, 0x30000001); gf100_fifo_gpfifo_new()
276 nvkm_wo32(chan->base.inst, 0x9c, 0x00000100); gf100_fifo_gpfifo_new()
277 nvkm_wo32(chan->base.inst, 0xa4, 0x1f1f1f1f); gf100_fifo_gpfifo_new()
278 nvkm_wo32(chan->base.inst, 0xa8, 0x1f1f1f1f); gf100_fifo_gpfifo_new()
279 nvkm_wo32(chan->base.inst, 0xac, 0x0000001f); gf100_fifo_gpfifo_new()
280 nvkm_wo32(chan->base.inst, 0xb8, 0xf8000000); gf100_fifo_gpfifo_new()
281 nvkm_wo32(chan->base.inst, 0xf8, 0x10003080); /* 0x002310 */ gf100_fifo_gpfifo_new()
282 nvkm_wo32(chan->base.inst, 0xfc, 0x10000010); /* 0x002350 */ gf100_fifo_gpfifo_new()
283 nvkm_done(chan->base.inst); gf100_fifo_gpfifo_new()
289 .base.oclass = FERMI_CHANNEL_GPFIFO,
290 .base.minver = 0,
291 .base.maxver = 0,
|
| H A D | gpfifogk104.c | 39 struct nvkm_subdev *subdev = &fifo->base.engine.subdev; gk104_fifo_gpfifo_kick()
41 struct nvkm_client *client = chan->base.object.client; gk104_fifo_gpfifo_kick()
43 nvkm_wr32(device, 0x002634, chan->base.chid); gk104_fifo_gpfifo_kick()
49 chan->base.chid, client->name); gk104_fifo_gpfifo_kick()
75 gk104_fifo_gpfifo_engine_fini(struct nvkm_fifo_chan *base, gk104_fifo_gpfifo_engine_fini() argument
79 struct gk104_fifo_chan *chan = gk104_fifo_chan(base); gk104_fifo_gpfifo_engine_fini()
80 struct nvkm_gpuobj *inst = chan->base.inst; gk104_fifo_gpfifo_engine_fini()
98 gk104_fifo_gpfifo_engine_init(struct nvkm_fifo_chan *base, gk104_fifo_gpfifo_engine_init() argument
102 struct gk104_fifo_chan *chan = gk104_fifo_chan(base); gk104_fifo_gpfifo_engine_init()
103 struct nvkm_gpuobj *inst = chan->base.inst; gk104_fifo_gpfifo_engine_init()
117 gk104_fifo_gpfifo_engine_dtor(struct nvkm_fifo_chan *base, gk104_fifo_gpfifo_engine_dtor() argument
120 struct gk104_fifo_chan *chan = gk104_fifo_chan(base); gk104_fifo_gpfifo_engine_dtor()
126 gk104_fifo_gpfifo_engine_ctor(struct nvkm_fifo_chan *base, gk104_fifo_gpfifo_engine_ctor() argument
130 struct gk104_fifo_chan *chan = gk104_fifo_chan(base); gk104_fifo_gpfifo_engine_ctor()
146 gk104_fifo_gpfifo_fini(struct nvkm_fifo_chan *base) gk104_fifo_gpfifo_fini() argument
148 struct gk104_fifo_chan *chan = gk104_fifo_chan(base); gk104_fifo_gpfifo_fini()
150 struct nvkm_device *device = fifo->base.engine.subdev.device; gk104_fifo_gpfifo_fini()
151 u32 coff = chan->base.chid * 8; gk104_fifo_gpfifo_fini()
163 gk104_fifo_gpfifo_init(struct nvkm_fifo_chan *base) gk104_fifo_gpfifo_init() argument
165 struct gk104_fifo_chan *chan = gk104_fifo_chan(base); gk104_fifo_gpfifo_init()
167 struct nvkm_device *device = fifo->base.engine.subdev.device; gk104_fifo_gpfifo_init()
168 u32 addr = chan->base.inst->addr >> 12; gk104_fifo_gpfifo_init()
169 u32 coff = chan->base.chid * 8; gk104_fifo_gpfifo_init()
183 gk104_fifo_gpfifo_dtor(struct nvkm_fifo_chan *base) gk104_fifo_gpfifo_dtor() argument
185 struct gk104_fifo_chan *chan = gk104_fifo_chan(base); gk104_fifo_gpfifo_dtor()
204 gk104_fifo_gpfifo_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass, gk104_fifo_gpfifo_new() argument
210 struct gk104_fifo *fifo = gk104_fifo(base); gk104_fifo_gpfifo_new()
211 struct nvkm_device *device = fifo->base.engine.subdev.device; gk104_fifo_gpfifo_new()
254 *pobject = &chan->base.object; gk104_fifo_gpfifo_new()
259 ret = nvkm_fifo_chan_ctor(&gk104_fifo_gpfifo_func, &fifo->base, gk104_fifo_gpfifo_new()
263 oclass, &chan->base); gk104_fifo_gpfifo_new()
267 args->v0.chid = chan->base.chid; gk104_fifo_gpfifo_new()
274 nvkm_kmap(chan->base.inst); gk104_fifo_gpfifo_new()
275 nvkm_wo32(chan->base.inst, 0x0200, lower_32_bits(chan->pgd->addr)); gk104_fifo_gpfifo_new()
276 nvkm_wo32(chan->base.inst, 0x0204, upper_32_bits(chan->pgd->addr)); gk104_fifo_gpfifo_new()
277 nvkm_wo32(chan->base.inst, 0x0208, 0xffffffff); gk104_fifo_gpfifo_new()
278 nvkm_wo32(chan->base.inst, 0x020c, 0x000000ff); gk104_fifo_gpfifo_new()
279 nvkm_done(chan->base.inst); gk104_fifo_gpfifo_new()
281 ret = nvkm_vm_ref(chan->base.vm, &chan->vm, chan->pgd); gk104_fifo_gpfifo_new()
286 usermem = chan->base.chid * 0x200; gk104_fifo_gpfifo_new()
297 nvkm_kmap(chan->base.inst); gk104_fifo_gpfifo_new()
298 nvkm_wo32(chan->base.inst, 0x08, lower_32_bits(usermem)); gk104_fifo_gpfifo_new()
299 nvkm_wo32(chan->base.inst, 0x0c, upper_32_bits(usermem)); gk104_fifo_gpfifo_new()
300 nvkm_wo32(chan->base.inst, 0x10, 0x0000face); gk104_fifo_gpfifo_new()
301 nvkm_wo32(chan->base.inst, 0x30, 0xfffff902); gk104_fifo_gpfifo_new()
302 nvkm_wo32(chan->base.inst, 0x48, lower_32_bits(ioffset)); gk104_fifo_gpfifo_new()
303 nvkm_wo32(chan->base.inst, 0x4c, upper_32_bits(ioffset) | gk104_fifo_gpfifo_new()
305 nvkm_wo32(chan->base.inst, 0x84, 0x20400000); gk104_fifo_gpfifo_new()
306 nvkm_wo32(chan->base.inst, 0x94, 0x30000001); gk104_fifo_gpfifo_new()
307 nvkm_wo32(chan->base.inst, 0x9c, 0x00000100); gk104_fifo_gpfifo_new()
308 nvkm_wo32(chan->base.inst, 0xac, 0x0000001f); gk104_fifo_gpfifo_new()
309 nvkm_wo32(chan->base.inst, 0xe8, chan->base.chid); gk104_fifo_gpfifo_new()
310 nvkm_wo32(chan->base.inst, 0xb8, 0xf8000000); gk104_fifo_gpfifo_new()
311 nvkm_wo32(chan->base.inst, 0xf8, 0x10003080); /* 0x002310 */ gk104_fifo_gpfifo_new()
312 nvkm_wo32(chan->base.inst, 0xfc, 0x10000010); /* 0x002350 */ gk104_fifo_gpfifo_new()
313 nvkm_done(chan->base.inst); gk104_fifo_gpfifo_new()
319 .base.oclass = KEPLER_CHANNEL_GPFIFO_A,
320 .base.minver = 0,
321 .base.maxver = 0,
|
| H A D | dmanv04.c | 35 nv04_fifo_dma_object_dtor(struct nvkm_fifo_chan *base, int cookie) nv04_fifo_dma_object_dtor() argument
37 struct nv04_fifo_chan *chan = nv04_fifo_chan(base); nv04_fifo_dma_object_dtor()
38 struct nvkm_instmem *imem = chan->fifo->base.engine.subdev.device->imem; nv04_fifo_dma_object_dtor()
43 nv04_fifo_dma_object_ctor(struct nvkm_fifo_chan *base, nv04_fifo_dma_object_ctor() argument
46 struct nv04_fifo_chan *chan = nv04_fifo_chan(base); nv04_fifo_dma_object_ctor()
47 struct nvkm_instmem *imem = chan->fifo->base.engine.subdev.device->imem; nv04_fifo_dma_object_ctor()
48 u32 context = 0x80000000 | chan->base.chid << 24; nv04_fifo_dma_object_ctor()
62 mutex_lock(&chan->fifo->base.engine.subdev.mutex); nv04_fifo_dma_object_ctor()
63 hash = nvkm_ramht_insert(imem->ramht, object, chan->base.chid, 4, nv04_fifo_dma_object_ctor()
65 mutex_unlock(&chan->fifo->base.engine.subdev.mutex); nv04_fifo_dma_object_ctor()
70 nv04_fifo_dma_fini(struct nvkm_fifo_chan *base) nv04_fifo_dma_fini() argument
72 struct nv04_fifo_chan *chan = nv04_fifo_chan(base); nv04_fifo_dma_fini()
74 struct nvkm_device *device = fifo->base.engine.subdev.device; nv04_fifo_dma_fini()
78 u32 mask = fifo->base.nr - 1; nv04_fifo_dma_fini()
83 spin_lock_irqsave(&fifo->base.lock, flags); nv04_fifo_dma_fini()
88 if (chid == chan->base.chid) { nv04_fifo_dma_fini()
115 nvkm_mask(device, NV04_PFIFO_MODE, 1 << chan->base.chid, 0); nv04_fifo_dma_fini()
117 spin_unlock_irqrestore(&fifo->base.lock, flags); nv04_fifo_dma_fini()
121 nv04_fifo_dma_init(struct nvkm_fifo_chan *base) nv04_fifo_dma_init() argument
123 struct nv04_fifo_chan *chan = nv04_fifo_chan(base); nv04_fifo_dma_init()
125 struct nvkm_device *device = fifo->base.engine.subdev.device; nv04_fifo_dma_init()
126 u32 mask = 1 << chan->base.chid; nv04_fifo_dma_init()
128 spin_lock_irqsave(&fifo->base.lock, flags); nv04_fifo_dma_init()
130 spin_unlock_irqrestore(&fifo->base.lock, flags); nv04_fifo_dma_init()
134 nv04_fifo_dma_dtor(struct nvkm_fifo_chan *base) nv04_fifo_dma_dtor() argument
136 struct nv04_fifo_chan *chan = nv04_fifo_chan(base); nv04_fifo_dma_dtor()
138 struct nvkm_instmem *imem = fifo->base.engine.subdev.device->imem; nv04_fifo_dma_dtor()
159 nv04_fifo_dma_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass, nv04_fifo_dma_new() argument
166 struct nv04_fifo *fifo = nv04_fifo(base); nv04_fifo_dma_new()
168 struct nvkm_device *device = fifo->base.engine.subdev.device; nv04_fifo_dma_new()
184 *pobject = &chan->base.object; nv04_fifo_dma_new()
186 ret = nvkm_fifo_chan_ctor(&nv04_fifo_dma_func, &fifo->base, nv04_fifo_dma_new()
191 0, 0x800000, 0x10000, oclass, &chan->base); nv04_fifo_dma_new()
196 args->v0.chid = chan->base.chid; nv04_fifo_dma_new()
197 chan->ramfc = chan->base.chid * 32; nv04_fifo_dma_new()
202 nvkm_wo32(imem->ramfc, chan->ramfc + 0x08, chan->base.push->addr >> 4); nv04_fifo_dma_new()
216 .base.oclass = NV03_CHANNEL_DMA,
217 .base.minver = 0,
218 .base.maxver = 0,
|
| H A D | dmanv40.c | 56 nv40_fifo_dma_engine_fini(struct nvkm_fifo_chan *base, nv40_fifo_dma_engine_fini() argument
59 struct nv04_fifo_chan *chan = nv04_fifo_chan(base); nv40_fifo_dma_engine_fini()
61 struct nvkm_device *device = fifo->base.engine.subdev.device; nv40_fifo_dma_engine_fini()
70 spin_lock_irqsave(&fifo->base.lock, flags); nv40_fifo_dma_engine_fini()
73 chid = nvkm_rd32(device, 0x003204) & (fifo->base.nr - 1); nv40_fifo_dma_engine_fini()
74 if (chid == chan->base.chid) nv40_fifo_dma_engine_fini()
81 spin_unlock_irqrestore(&fifo->base.lock, flags); nv40_fifo_dma_engine_fini()
86 nv40_fifo_dma_engine_init(struct nvkm_fifo_chan *base, nv40_fifo_dma_engine_init() argument
89 struct nv04_fifo_chan *chan = nv04_fifo_chan(base); nv40_fifo_dma_engine_init()
91 struct nvkm_device *device = fifo->base.engine.subdev.device; nv40_fifo_dma_engine_init()
101 spin_lock_irqsave(&fifo->base.lock, flags); nv40_fifo_dma_engine_init()
104 chid = nvkm_rd32(device, 0x003204) & (fifo->base.nr - 1); nv40_fifo_dma_engine_init()
105 if (chid == chan->base.chid) nv40_fifo_dma_engine_init()
112 spin_unlock_irqrestore(&fifo->base.lock, flags); nv40_fifo_dma_engine_init()
117 nv40_fifo_dma_engine_dtor(struct nvkm_fifo_chan *base, nv40_fifo_dma_engine_dtor() argument
120 struct nv04_fifo_chan *chan = nv04_fifo_chan(base); nv40_fifo_dma_engine_dtor()
125 nv40_fifo_dma_engine_ctor(struct nvkm_fifo_chan *base, nv40_fifo_dma_engine_ctor() argument
129 struct nv04_fifo_chan *chan = nv04_fifo_chan(base); nv40_fifo_dma_engine_ctor()
140 nv40_fifo_dma_object_ctor(struct nvkm_fifo_chan *base, nv40_fifo_dma_object_ctor() argument
143 struct nv04_fifo_chan *chan = nv04_fifo_chan(base); nv40_fifo_dma_object_ctor()
144 struct nvkm_instmem *imem = chan->fifo->base.engine.subdev.device->imem; nv40_fifo_dma_object_ctor()
145 u32 context = chan->base.chid << 23; nv40_fifo_dma_object_ctor()
159 mutex_lock(&chan->fifo->base.engine.subdev.mutex); nv40_fifo_dma_object_ctor()
160 hash = nvkm_ramht_insert(imem->ramht, object, chan->base.chid, 4, nv40_fifo_dma_object_ctor()
162 mutex_unlock(&chan->fifo->base.engine.subdev.mutex); nv40_fifo_dma_object_ctor()
180 nv40_fifo_dma_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass, nv40_fifo_dma_new() argument
187 struct nv04_fifo *fifo = nv04_fifo(base); nv40_fifo_dma_new()
189 struct nvkm_device *device = fifo->base.engine.subdev.device; nv40_fifo_dma_new()
205 *pobject = &chan->base.object; nv40_fifo_dma_new()
207 ret = nvkm_fifo_chan_ctor(&nv40_fifo_dma_func, &fifo->base, nv40_fifo_dma_new()
213 0, 0xc00000, 0x1000, oclass, &chan->base); nv40_fifo_dma_new()
218 args->v0.chid = chan->base.chid; nv40_fifo_dma_new()
219 chan->ramfc = chan->base.chid * 128; nv40_fifo_dma_new()
224 nvkm_wo32(imem->ramfc, chan->ramfc + 0x0c, chan->base.push->addr >> 4); nv40_fifo_dma_new()
239 .base.oclass = NV40_CHANNEL_DMA,
240 .base.minver = 0,
241 .base.maxver = 0,
|
| H A D | channv50.c | 46 nv50_fifo_chan_engine_fini(struct nvkm_fifo_chan *base, nv50_fifo_chan_engine_fini() argument
49 struct nv50_fifo_chan *chan = nv50_fifo_chan(base); nv50_fifo_chan_engine_fini()
51 struct nvkm_subdev *subdev = &fifo->base.engine.subdev; nv50_fifo_chan_engine_fini()
75 nvkm_wr32(device, 0x0032fc, chan->base.inst->addr >> 12); nv50_fifo_chan_engine_fini()
81 chan->base.chid, chan->base.object.client->name); nv50_fifo_chan_engine_fini()
102 nv50_fifo_chan_engine_init(struct nvkm_fifo_chan *base, nv50_fifo_chan_engine_init() argument
105 struct nv50_fifo_chan *chan = nv50_fifo_chan(base); nv50_fifo_chan_engine_init()
129 nv50_fifo_chan_engine_dtor(struct nvkm_fifo_chan *base, nv50_fifo_chan_engine_dtor() argument
132 struct nv50_fifo_chan *chan = nv50_fifo_chan(base); nv50_fifo_chan_engine_dtor()
137 nv50_fifo_chan_engine_ctor(struct nvkm_fifo_chan *base, nv50_fifo_chan_engine_ctor() argument
141 struct nv50_fifo_chan *chan = nv50_fifo_chan(base); nv50_fifo_chan_engine_ctor()
151 nv50_fifo_chan_object_dtor(struct nvkm_fifo_chan *base, int cookie) nv50_fifo_chan_object_dtor() argument
153 struct nv50_fifo_chan *chan = nv50_fifo_chan(base); nv50_fifo_chan_object_dtor()
158 nv50_fifo_chan_object_ctor(struct nvkm_fifo_chan *base, nv50_fifo_chan_object_ctor() argument
161 struct nv50_fifo_chan *chan = nv50_fifo_chan(base); nv50_fifo_chan_object_ctor()
179 nv50_fifo_chan_fini(struct nvkm_fifo_chan *base) nv50_fifo_chan_fini() argument
181 struct nv50_fifo_chan *chan = nv50_fifo_chan(base); nv50_fifo_chan_fini()
183 struct nvkm_device *device = fifo->base.engine.subdev.device; nv50_fifo_chan_fini()
184 u32 chid = chan->base.chid; nv50_fifo_chan_fini()
193 nv50_fifo_chan_init(struct nvkm_fifo_chan *base) nv50_fifo_chan_init() argument
195 struct nv50_fifo_chan *chan = nv50_fifo_chan(base); nv50_fifo_chan_init()
197 struct nvkm_device *device = fifo->base.engine.subdev.device; nv50_fifo_chan_init()
199 u32 chid = chan->base.chid; nv50_fifo_chan_init()
206 nv50_fifo_chan_dtor(struct nvkm_fifo_chan *base) nv50_fifo_chan_dtor() argument
208 struct nv50_fifo_chan *chan = nv50_fifo_chan(base); nv50_fifo_chan_dtor()
236 struct nvkm_device *device = fifo->base.engine.subdev.device; nv50_fifo_chan_ctor()
239 ret = nvkm_fifo_chan_ctor(&nv50_fifo_chan_func, &fifo->base, nv50_fifo_chan_ctor()
245 0, 0xc00000, 0x2000, oclass, &chan->base); nv50_fifo_chan_ctor()
250 ret = nvkm_gpuobj_new(device, 0x0200, 0x1000, true, chan->base.inst, nv50_fifo_chan_ctor()
255 ret = nvkm_gpuobj_new(device, 0x1200, 0, true, chan->base.inst, nv50_fifo_chan_ctor()
260 ret = nvkm_gpuobj_new(device, 0x4000, 0, false, chan->base.inst, nv50_fifo_chan_ctor()
265 ret = nvkm_ramht_new(device, 0x8000, 16, chan->base.inst, &chan->ramht); nv50_fifo_chan_ctor()
269 return nvkm_vm_ref(chan->base.vm, &chan->vm, chan->pgd); nv50_fifo_chan_ctor()
|
| H A D | changf100.h | 3 #define gf100_fifo_chan(p) container_of((p), struct gf100_fifo_chan, base)
8 struct nvkm_fifo_chan base; member in struct:gf100_fifo_chan
|
| H A D | gf100.h | 3 #define gf100_fifo(p) container_of((p), struct gf100_fifo, base)
9 struct nvkm_fifo base; member in struct:gf100_fifo
|
| H A D | nv04.h | 3 #define nv04_fifo(p) container_of((p), struct nv04_fifo, base)
15 struct nvkm_fifo base; member in struct:nv04_fifo
|
| H A D | nv50.h | 3 #define nv50_fifo(p) container_of((p), struct nv50_fifo, base)
7 struct nvkm_fifo base; member in struct:nv50_fifo
|
| /linux-4.4.14/drivers/gpu/drm/msm/mdp/mdp5/ |
| H A D | mdp5_cfg.c | 29 .base = { 0x00100 },
44 .base = { 0x00600, 0x00700, 0x00800, 0x00900, 0x00a00 },
49 .base = { 0x01200, 0x01600, 0x01a00 },
58 .base = { 0x01e00, 0x02200, 0x02600 },
66 .base = { 0x02a00, 0x02e00 },
73 .base = { 0x03200, 0x03600, 0x03a00, 0x03e00, 0x04200 },
78 .base = { 0x04600, 0x04a00, 0x04e00 },
82 .base = { 0x21b00, 0x21c00, 0x21d00 },
85 .base = { 0x21100, 0x21300, 0x21500, 0x21700 },
100 .base = { 0x00100 },
115 .base = { 0x00600, 0x00700, 0x00800, 0x00900, 0x00a00 },
120 .base = { 0x01200, 0x01600, 0x01a00 },
127 .base = { 0x01e00, 0x02200, 0x02600 },
133 .base = { 0x02a00, 0x02e00 },
138 .base = { 0x03200, 0x03600, 0x03a00, 0x03e00, 0x04200 },
145 .base = { 0x04600, 0x04a00, 0x04e00 },
149 .base = { 0x13100, 0x13300 },
153 .base = { 0x12d00, 0x12e00, 0x12f00 },
156 .base = { 0x12500, 0x12700, 0x12900, 0x12b00 },
171 .base = { 0x00100 },
193 .base = { 0x00600, 0x00700, 0x00800, 0x00900, 0x00a00 },
198 .base = { 0x01200, 0x01600, 0x01a00, 0x01e00 },
205 .base = { 0x02200, 0x02600, 0x02a00, 0x02e00 },
211 .base = { 0x03200, 0x03600 },
216 .base = { 0x03a00, 0x03e00, 0x04200, 0x04600, 0x04a00, 0x04e00 },
223 .base = { 0x05200, 0x05600, 0x05a00, 0x05e00 },
228 .base = { 0x13500, 0x13700, 0x13900 },
232 .base = { 0x12f00, 0x13000, 0x13100, 0x13200 },
235 .base = { 0x12500, 0x12700, 0x12900, 0x12b00, 0x12d00 },
250 .base = { 0x01000 },
264 .base = { 0x02000, 0x02200, 0x02400, 0x02600, 0x02800 },
269 .base = { 0x05000 },
276 .base = { 0x15000, 0x17000 },
282 .base = { 0x25000 },
287 .base = { 0x45000, 0x48000 },
294 .base = { 0x55000 },
298 .base = { 0x00000, 0x6b800 },
311 .base = { 0x01000 },
333 .base = { 0x02000, 0x02200, 0x02400, 0x02600, 0x02800 },
338 .base = { 0x05000, 0x07000, 0x09000, 0x0b000 },
345 .base = { 0x15000, 0x17000, 0x19000, 0x1b000 },
351 .base = { 0x25000, 0x27000 },
356 .base = { 0x45000, 0x46000, 0x47000, 0x48000, 0x49000, 0x4a000 },
363 .base = { 0x55000, 0x57000, 0x59000, 0x5b000 },
368 .base = { 0x79000, 0x79800, 0x7a000 },
372 .base = { 0x71000, 0x71800, 0x72000, 0x72800 },
375 .base = { 0x6b000, 0x6b800, 0x6c000, 0x6c800, 0x6d000 },
390 .base = { 0x01000 },
397 .base = { 0x02000, 0x02200, 0x02400, 0x02600, 0x02800 },
402 .base = { 0x05000, 0x07000, 0x09000, 0x0b000 },
413 .base = { 0x15000, 0x17000, 0x19000, 0x1b000 },
423 .base = { 0x25000, 0x27000 },
431 .base = { 0x45000, 0x46000, 0x47000, 0x48000, 0x49000, 0x4a000 },
438 .base = { 0x55000, 0x57000 },
442 .base = { 0x79000, 0x79800, 0x7a000 },
446 .base = { 0x71000, 0x71800, 0x72000, 0x72800 },
450 .base = { 0x7a200 },
454 .base = { 0x81000, 0x81400 },
457 .base = { 0x6b000, 0x6b800, 0x6c000, 0x6c800, 0x6d000 },
|
| /linux-4.4.14/arch/arm/mach-realview/include/mach/ |
| H A D | uncompress.h | 29 #define AMBA_UART_DR(base) (*(volatile unsigned char *)((base) + 0x00))
30 #define AMBA_UART_LCRH(base) (*(volatile unsigned char *)((base) + 0x2c))
31 #define AMBA_UART_CR(base) (*(volatile unsigned char *)((base) + 0x30))
32 #define AMBA_UART_FR(base) (*(volatile unsigned char *)((base) + 0x18))
35 * Return the UART base address
58 unsigned long base = get_uart_base(); putc() local
60 while (AMBA_UART_FR(base) & (1 << 5)) putc()
63 AMBA_UART_DR(base) = c; putc()
68 unsigned long base = get_uart_base(); flush() local
70 while (AMBA_UART_FR(base) & (1 << 3)) flush()
|
| /linux-4.4.14/drivers/isdn/hardware/avm/ |
| H A D | avmcard.h | 219 static inline unsigned char b1outp(unsigned int base, b1outp() argument
223 outb(value, base + offset); b1outp()
224 return inb(base + B1_ANALYSE); b1outp()
228 static inline int b1_rx_full(unsigned int base) b1_rx_full() argument
230 return inb(base + B1_INSTAT) & 0x1; b1_rx_full()
233 static inline unsigned char b1_get_byte(unsigned int base) b1_get_byte() argument
236 while (!b1_rx_full(base) && time_before(jiffies, stop)); b1_get_byte()
237 if (b1_rx_full(base)) b1_get_byte()
238 return inb(base + B1_READ); b1_get_byte()
239 printk(KERN_CRIT "b1lli(0x%x): rx not full after 1 second\n", base); b1_get_byte()
243 static inline unsigned int b1_get_word(unsigned int base) b1_get_word() argument
246 val |= b1_get_byte(base); b1_get_word()
247 val |= (b1_get_byte(base) << 8); b1_get_word()
248 val |= (b1_get_byte(base) << 16); b1_get_word()
249 val |= (b1_get_byte(base) << 24); b1_get_word()
253 static inline int b1_tx_empty(unsigned int base) b1_tx_empty() argument
255 return inb(base + B1_OUTSTAT) & 0x1; b1_tx_empty()
258 static inline void b1_put_byte(unsigned int base, unsigned char val) b1_put_byte() argument
260 while (!b1_tx_empty(base)); b1_put_byte()
261 b1outp(base, B1_WRITE, val); b1_put_byte()
264 static inline int b1_save_put_byte(unsigned int base, unsigned char val) b1_save_put_byte() argument
267 while (!b1_tx_empty(base) && time_before(jiffies, stop)); b1_save_put_byte()
268 if (!b1_tx_empty(base)) return -1; b1_save_put_byte()
269 b1outp(base, B1_WRITE, val); b1_save_put_byte()
273 static inline void b1_put_word(unsigned int base, unsigned int val) b1_put_word() argument
275 b1_put_byte(base, val & 0xff); b1_put_word()
276 b1_put_byte(base, (val >> 8) & 0xff); b1_put_word()
277 b1_put_byte(base, (val >> 16) & 0xff); b1_put_word()
278 b1_put_byte(base, (val >> 24) & 0xff); b1_put_word()
281 static inline unsigned int b1_get_slice(unsigned int base, b1_get_slice() argument
286 len = i = b1_get_word(base); b1_get_slice()
287 while (i-- > 0) *dp++ = b1_get_byte(base); b1_get_slice()
291 static inline void b1_put_slice(unsigned int base, b1_put_slice() argument
295 b1_put_word(base, i); b1_put_slice()
297 b1_put_byte(base, *dp++); b1_put_slice()
300 static void b1_wr_reg(unsigned int base, b1_wr_reg() argument
304 b1_put_byte(base, WRITE_REGISTER); b1_wr_reg()
305 b1_put_word(base, reg); b1_wr_reg()
306 b1_put_word(base, value); b1_wr_reg()
309 static inline unsigned int b1_rd_reg(unsigned int base, b1_rd_reg() argument
312 b1_put_byte(base, READ_REGISTER); b1_rd_reg()
313 b1_put_word(base, reg); b1_rd_reg()
314 return b1_get_word(base); b1_rd_reg()
318 static inline void b1_reset(unsigned int base) b1_reset() argument
320 b1outp(base, B1_RESET, 0); b1_reset()
323 b1outp(base, B1_RESET, 1); b1_reset()
326 b1outp(base, B1_RESET, 0); b1_reset()
330 static inline unsigned char b1_disable_irq(unsigned int base) b1_disable_irq() argument
332 return b1outp(base, B1_INSTAT, 0x00); b1_disable_irq()
337 static inline void b1_set_test_bit(unsigned int base, b1_set_test_bit() argument
341 b1_wr_reg(base, B1_STAT0(cardtype), onoff ? 0x21 : 0x20); b1_set_test_bit()
344 static inline int b1_get_test_bit(unsigned int base, b1_get_test_bit() argument
347 return (b1_rd_reg(base, B1_STAT0(cardtype)) & 0x01) != 0; b1_get_test_bit()
386 static inline void t1outp(unsigned int base, t1outp() argument
390 outb(value, base + offset); t1outp()
393 static inline unsigned char t1inp(unsigned int base, t1inp() argument
396 return inb(base + offset); t1inp()
399 static inline int t1_isfastlink(unsigned int base) t1_isfastlink() argument
401 return (inb(base + T1_IDENT) & ~0x82) == 1; t1_isfastlink()
404 static inline unsigned char t1_fifostatus(unsigned int base) t1_fifostatus() argument
406 return inb(base + T1_FIFOSTAT); t1_fifostatus()
409 static inline unsigned int t1_get_slice(unsigned int base, t1_get_slice() argument
417 len = i = b1_get_word(base); t1_get_slice()
418 if (t1_isfastlink(base)) { t1_get_slice()
421 status = t1_fifostatus(base) & (T1F_IREADY | T1F_IHALF); t1_get_slice()
426 insb(base + B1_READ, dp, FIFO_INPBSIZE); t1_get_slice()
434 insb(base + B1_READ, dp, i); t1_get_slice()
442 *dp++ = b1_get_byte(base); t1_get_slice()
453 base, len, wcnt, bcnt); t1_get_slice()
457 *dp++ = b1_get_byte(base); t1_get_slice()
462 static inline void t1_put_slice(unsigned int base, t1_put_slice() argument
466 b1_put_word(base, i); t1_put_slice()
467 if (t1_isfastlink(base)) { t1_put_slice()
470 status = t1_fifostatus(base) & (T1F_OREADY | T1F_OHALF); t1_put_slice()
474 outsb(base + B1_WRITE, dp, FIFO_OUTBSIZE); t1_put_slice()
479 outsb(base + B1_WRITE, dp, i); t1_put_slice()
484 b1_put_byte(base, *dp++); t1_put_slice()
491 b1_put_byte(base, *dp++); t1_put_slice()
495 static inline void t1_disable_irq(unsigned int base) t1_disable_irq() argument
497 t1outp(base, T1_IRQMASTER, 0x00); t1_disable_irq()
500 static inline void t1_reset(unsigned int base) t1_reset() argument
503 b1_reset(base); t1_reset()
505 t1outp(base, B1_INSTAT, 0x00); t1_reset()
506 t1outp(base, B1_OUTSTAT, 0x00); t1_reset()
507 t1outp(base, T1_IRQMASTER, 0x00); t1_reset()
509 t1outp(base, T1_RESETBOARD, 0xf); t1_reset()
512 static inline void b1_setinterrupt(unsigned int base, unsigned irq, b1_setinterrupt() argument
517 t1outp(base, B1_INSTAT, 0x00); b1_setinterrupt()
518 t1outp(base, B1_INSTAT, 0x02); b1_setinterrupt()
519 t1outp(base, T1_IRQMASTER, 0x08); b1_setinterrupt()
522 b1outp(base, B1_INSTAT, 0x00); b1_setinterrupt()
523 b1outp(base, B1_RESET, b1_irq_table[irq]); b1_setinterrupt()
524 b1outp(base, B1_INSTAT, 0x02); b1_setinterrupt()
530 b1outp(base, B1_INSTAT, 0x00); b1_setinterrupt()
531 b1outp(base, B1_RESET, 0xf0); b1_setinterrupt()
532 b1outp(base, B1_INSTAT, 0x02); b1_setinterrupt()
536 b1outp(base, B1_RESET, 0xf0); b1_setinterrupt()
544 int b1_detect(unsigned int base, enum avmcardtype cardtype);
|
| /linux-4.4.14/arch/arm/plat-orion/ |
| H A D | pcie.c | 55 u32 orion_pcie_dev_id(void __iomem *base) orion_pcie_dev_id() argument
57 return readl(base + PCIE_DEV_ID_OFF) >> 16; orion_pcie_dev_id()
60 u32 orion_pcie_rev(void __iomem *base) orion_pcie_rev() argument
62 return readl(base + PCIE_DEV_REV_OFF) & 0xff; orion_pcie_rev()
65 int orion_pcie_link_up(void __iomem *base) orion_pcie_link_up() argument
67 return !(readl(base + PCIE_STAT_OFF) & PCIE_STAT_LINK_DOWN); orion_pcie_link_up()
70 int __init orion_pcie_x4_mode(void __iomem *base) orion_pcie_x4_mode() argument
72 return !(readl(base + PCIE_CTRL_OFF) & PCIE_CTRL_X1_MODE); orion_pcie_x4_mode()
75 int orion_pcie_get_local_bus_nr(void __iomem *base) orion_pcie_get_local_bus_nr() argument
77 u32 stat = readl(base + PCIE_STAT_OFF); orion_pcie_get_local_bus_nr()
82 void __init orion_pcie_set_local_bus_nr(void __iomem *base, int nr) orion_pcie_set_local_bus_nr() argument
86 stat = readl(base + PCIE_STAT_OFF); orion_pcie_set_local_bus_nr()
89 writel(stat, base + PCIE_STAT_OFF); orion_pcie_set_local_bus_nr()
92 void __init orion_pcie_reset(void __iomem *base) orion_pcie_reset() argument
103 reg = readl(base + PCIE_DEBUG_CTRL); orion_pcie_reset()
105 writel(reg, base + PCIE_DEBUG_CTRL); orion_pcie_reset()
110 if (orion_pcie_link_up(base)) orion_pcie_reset()
115 writel(reg, base + PCIE_DEBUG_CTRL); orion_pcie_reset()
123 static void __init orion_pcie_setup_wins(void __iomem *base) orion_pcie_setup_wins() argument
135 writel(0, base + PCIE_BAR_CTRL_OFF(i)); orion_pcie_setup_wins()
136 writel(0, base + PCIE_BAR_LO_OFF(i)); orion_pcie_setup_wins()
137 writel(0, base + PCIE_BAR_HI_OFF(i)); orion_pcie_setup_wins()
141 writel(0, base + PCIE_WIN04_CTRL_OFF(i)); orion_pcie_setup_wins()
142 writel(0, base + PCIE_WIN04_BASE_OFF(i)); orion_pcie_setup_wins()
143 writel(0, base + PCIE_WIN04_REMAP_OFF(i)); orion_pcie_setup_wins()
146 writel(0, base + PCIE_WIN5_CTRL_OFF); orion_pcie_setup_wins()
147 writel(0, base + PCIE_WIN5_BASE_OFF); orion_pcie_setup_wins()
148 writel(0, base + PCIE_WIN5_REMAP_OFF); orion_pcie_setup_wins()
157 writel(cs->base & 0xffff0000, base + PCIE_WIN04_BASE_OFF(i)); orion_pcie_setup_wins()
158 writel(0, base + PCIE_WIN04_REMAP_OFF(i)); orion_pcie_setup_wins()
162 base + PCIE_WIN04_CTRL_OFF(i)); orion_pcie_setup_wins()
176 writel(dram->cs[0].base, base + PCIE_BAR_LO_OFF(1)); orion_pcie_setup_wins()
177 writel(0, base + PCIE_BAR_HI_OFF(1)); orion_pcie_setup_wins()
178 writel(((size - 1) & 0xffff0000) | 1, base + PCIE_BAR_CTRL_OFF(1)); orion_pcie_setup_wins()
181 void __init orion_pcie_setup(void __iomem *base) orion_pcie_setup() argument
189 orion_pcie_setup_wins(base); orion_pcie_setup()
194 cmd = readw(base + PCIE_CMD_OFF); orion_pcie_setup()
198 writew(cmd, base + PCIE_CMD_OFF); orion_pcie_setup()
203 mask = readl(base + PCIE_MASK_OFF); orion_pcie_setup()
205 writel(mask, base + PCIE_MASK_OFF); orion_pcie_setup()
208 int orion_pcie_rd_conf(void __iomem *base, struct pci_bus *bus, orion_pcie_rd_conf() argument
215 base + PCIE_CONF_ADDR_OFF); orion_pcie_rd_conf()
217 *val = readl(base + PCIE_CONF_DATA_OFF); orion_pcie_rd_conf()
227 int orion_pcie_rd_conf_tlp(void __iomem *base, struct pci_bus *bus, orion_pcie_rd_conf_tlp() argument
234 base + PCIE_CONF_ADDR_OFF); orion_pcie_rd_conf_tlp()
236 *val = readl(base + PCIE_CONF_DATA_OFF); orion_pcie_rd_conf_tlp()
238 if (bus->number != orion_pcie_get_local_bus_nr(base) || orion_pcie_rd_conf_tlp()
240 *val = readl(base + PCIE_HEADER_LOG_4_OFF); orion_pcie_rd_conf_tlp()
266 int orion_pcie_wr_conf(void __iomem *base, struct pci_bus *bus, orion_pcie_wr_conf() argument
275 base + PCIE_CONF_ADDR_OFF); orion_pcie_wr_conf()
278 writel(val, base + PCIE_CONF_DATA_OFF); orion_pcie_wr_conf()
280 writew(val, base + PCIE_CONF_DATA_OFF + (where & 3)); orion_pcie_wr_conf()
282 writeb(val, base + PCIE_CONF_DATA_OFF + (where & 3)); orion_pcie_wr_conf()
|
| /linux-4.4.14/arch/m68k/amiga/ |
| H A D | cia.c | 51 unsigned char cia_set_irq(struct ciabase *base, unsigned char mask) cia_set_irq() argument
55 old = (base->icr_data |= base->cia->icr); cia_set_irq()
57 base->icr_data |= mask; cia_set_irq()
59 base->icr_data &= ~mask; cia_set_irq()
60 if (base->icr_data & base->icr_mask) cia_set_irq()
61 amiga_custom.intreq = IF_SETCLR | base->int_mask; cia_set_irq()
62 return old & base->icr_mask; cia_set_irq()
69 unsigned char cia_able_irq(struct ciabase *base, unsigned char mask) cia_able_irq() argument
73 old = base->icr_mask; cia_able_irq()
74 base->icr_data |= base->cia->icr; cia_able_irq()
75 base->cia->icr = mask; cia_able_irq()
77 base->icr_mask |= mask; cia_able_irq()
79 base->icr_mask &= ~mask; cia_able_irq()
80 base->icr_mask &= CIA_ICR_ALL; cia_able_irq()
81 if (base->icr_data & base->icr_mask) cia_able_irq()
82 amiga_custom.intreq = IF_SETCLR | base->int_mask; cia_able_irq()
88 struct ciabase *base = dev_id; cia_handler() local
92 mach_irq = base->cia_irq; cia_handler()
93 ints = cia_set_irq(base, CIA_ICR_ALL); cia_handler()
94 amiga_custom.intreq = base->int_mask; cia_handler()
170 void __init cia_init_IRQ(struct ciabase *base) cia_init_IRQ() argument
173 base->cia_irq, CIA_IRQS); cia_init_IRQ()
176 cia_set_irq(base, CIA_ICR_ALL); cia_init_IRQ()
177 cia_able_irq(base, CIA_ICR_ALL); cia_init_IRQ()
181 base->handler_irq, 1); cia_init_IRQ()
182 m68k_irq_startup_irq(base->handler_irq); cia_init_IRQ()
183 if (request_irq(base->handler_irq, cia_handler, IRQF_SHARED, cia_init_IRQ()
184 base->name, base)) cia_init_IRQ()
185 pr_err("Couldn't register %s interrupt\n", base->name); cia_init_IRQ()
|
| /linux-4.4.14/drivers/phy/ |
| H A D | phy-qcom-apq8064-sata.c | 100 void __iomem *base = phy->mmio; qcom_apq8064_sata_phy_init() local
104 writel_relaxed(0x01, base + SATA_PHY_SER_CTRL); qcom_apq8064_sata_phy_init()
105 writel_relaxed(0xB1, base + SATA_PHY_POW_DWN_CTRL0); qcom_apq8064_sata_phy_init()
110 writel_relaxed(0x01, base + SATA_PHY_POW_DWN_CTRL0); qcom_apq8064_sata_phy_init()
111 writel_relaxed(0x3E, base + SATA_PHY_POW_DWN_CTRL1); qcom_apq8064_sata_phy_init()
112 writel_relaxed(0x01, base + SATA_PHY_RX_IMCAL0); qcom_apq8064_sata_phy_init()
113 writel_relaxed(0x01, base + SATA_PHY_TX_IMCAL0); qcom_apq8064_sata_phy_init()
114 writel_relaxed(0x02, base + SATA_PHY_TX_IMCAL2); qcom_apq8064_sata_phy_init()
117 writel_relaxed(0x04, base + UNIPHY_PLL_REFCLK_CFG); qcom_apq8064_sata_phy_init()
118 writel_relaxed(0x00, base + UNIPHY_PLL_PWRGEN_CFG); qcom_apq8064_sata_phy_init()
120 writel_relaxed(0x0A, base + UNIPHY_PLL_CAL_CFG0); qcom_apq8064_sata_phy_init()
121 writel_relaxed(0xF3, base + UNIPHY_PLL_CAL_CFG8); qcom_apq8064_sata_phy_init()
122 writel_relaxed(0x01, base + UNIPHY_PLL_CAL_CFG9); qcom_apq8064_sata_phy_init()
123 writel_relaxed(0xED, base + UNIPHY_PLL_CAL_CFG10); qcom_apq8064_sata_phy_init()
124 writel_relaxed(0x02, base + UNIPHY_PLL_CAL_CFG11); qcom_apq8064_sata_phy_init()
126 writel_relaxed(0x36, base + UNIPHY_PLL_SDM_CFG0); qcom_apq8064_sata_phy_init()
127 writel_relaxed(0x0D, base + UNIPHY_PLL_SDM_CFG1); qcom_apq8064_sata_phy_init()
128 writel_relaxed(0xA3, base + UNIPHY_PLL_SDM_CFG2); qcom_apq8064_sata_phy_init()
129 writel_relaxed(0xF0, base + UNIPHY_PLL_SDM_CFG3); qcom_apq8064_sata_phy_init()
130 writel_relaxed(0x00, base + UNIPHY_PLL_SDM_CFG4); qcom_apq8064_sata_phy_init()
132 writel_relaxed(0x19, base + UNIPHY_PLL_SSC_CFG0); qcom_apq8064_sata_phy_init()
133 writel_relaxed(0xE1, base + UNIPHY_PLL_SSC_CFG1); qcom_apq8064_sata_phy_init()
134 writel_relaxed(0x00, base + UNIPHY_PLL_SSC_CFG2); qcom_apq8064_sata_phy_init()
135 writel_relaxed(0x11, base + UNIPHY_PLL_SSC_CFG3); qcom_apq8064_sata_phy_init()
137 writel_relaxed(0x04, base + UNIPHY_PLL_LKDET_CFG0); qcom_apq8064_sata_phy_init()
138 writel_relaxed(0xFF, base + UNIPHY_PLL_LKDET_CFG1); qcom_apq8064_sata_phy_init()
140 writel_relaxed(0x02, base + UNIPHY_PLL_GLB_CFG); qcom_apq8064_sata_phy_init()
144 writel_relaxed(0x03, base + UNIPHY_PLL_GLB_CFG); qcom_apq8064_sata_phy_init()
145 writel_relaxed(0x05, base + UNIPHY_PLL_LKDET_CFG2); qcom_apq8064_sata_phy_init()
148 ret = read_poll_timeout(base + UNIPHY_PLL_STATUS, UNIPHY_PLL_LOCK); qcom_apq8064_sata_phy_init()
155 ret = read_poll_timeout(base + SATA_PHY_TX_IMCAL_STAT, SATA_PHY_TX_CAL); qcom_apq8064_sata_phy_init()
162 ret = read_poll_timeout(base + SATA_PHY_RX_IMCAL_STAT, SATA_PHY_RX_CAL); qcom_apq8064_sata_phy_init()
169 writel_relaxed(0x3E, base + SATA_PHY_POW_DWN_CTRL1); qcom_apq8064_sata_phy_init()
170 writel_relaxed(0x01, base + SATA_PHY_RX_IMCAL0); qcom_apq8064_sata_phy_init()
171 writel_relaxed(0x01, base + SATA_PHY_TX_IMCAL0); qcom_apq8064_sata_phy_init()
173 writel_relaxed(0x00, base + SATA_PHY_POW_DWN_CTRL1); qcom_apq8064_sata_phy_init()
174 writel_relaxed(0x59, base + SATA_PHY_CDR_CTRL0); qcom_apq8064_sata_phy_init()
175 writel_relaxed(0x04, base + SATA_PHY_CDR_CTRL1); qcom_apq8064_sata_phy_init()
176 writel_relaxed(0x00, base + SATA_PHY_CDR_CTRL2); qcom_apq8064_sata_phy_init()
177 writel_relaxed(0x00, base + SATA_PHY_PI_CTRL0); qcom_apq8064_sata_phy_init()
178 writel_relaxed(0x00, base + SATA_PHY_CDR_CTRL3); qcom_apq8064_sata_phy_init()
179 writel_relaxed(0x01, base + SATA_PHY_POW_DWN_CTRL0); qcom_apq8064_sata_phy_init()
181 writel_relaxed(0x11, base + SATA_PHY_TX_DATA_CTRL); qcom_apq8064_sata_phy_init()
182 writel_relaxed(0x43, base + SATA_PHY_ALIGNP); qcom_apq8064_sata_phy_init()
183 writel_relaxed(0x04, base + SATA_PHY_OOB_TERM); qcom_apq8064_sata_phy_init()
185 writel_relaxed(0x01, base + SATA_PHY_EQUAL); qcom_apq8064_sata_phy_init()
186 writel_relaxed(0x09, base + SATA_PHY_TX_DRIV_CTRL0); qcom_apq8064_sata_phy_init()
187 writel_relaxed(0x09, base + SATA_PHY_TX_DRIV_CTRL1); qcom_apq8064_sata_phy_init()
195 void __iomem *base = phy->mmio; qcom_apq8064_sata_phy_exit() local
198 writel_relaxed(0xF8, base + SATA_PHY_POW_DWN_CTRL0); qcom_apq8064_sata_phy_exit()
199 writel_relaxed(0xFE, base + SATA_PHY_POW_DWN_CTRL1); qcom_apq8064_sata_phy_exit()
202 writel_relaxed(0x00, base + UNIPHY_PLL_GLB_CFG); qcom_apq8064_sata_phy_exit()
|
| H A D | phy-miphy28lp.c | 208 void __iomem *base; member in struct:miphy28lp_phy
370 void __iomem *base = miphy_phy->base; miphy28lp_set_reset() local
374 writeb_relaxed(RST_APPLI_SW, base + MIPHY_CONF_RESET); miphy28lp_set_reset()
377 writeb_relaxed(val, base + MIPHY_CONF_RESET); miphy28lp_set_reset()
379 writeb_relaxed(RST_APPLI_SW, base + MIPHY_CONF_RESET); miphy28lp_set_reset()
384 writeb_relaxed(val, base + MIPHY_CONTROL); miphy28lp_set_reset()
387 writeb_relaxed(val, base + MIPHY_CONTROL); miphy28lp_set_reset()
394 void __iomem *base = miphy_phy->base; miphy28lp_pll_calibration() local
398 writeb_relaxed(0x1d, base + MIPHY_PLL_SPAREIN); miphy28lp_pll_calibration()
399 writeb_relaxed(pll_ratio->clk_ref, base + MIPHY_PLL_CLKREF_FREQ); miphy28lp_pll_calibration()
402 writeb_relaxed(pll_ratio->calset_1, base + MIPHY_PLL_CALSET_1); miphy28lp_pll_calibration()
403 writeb_relaxed(pll_ratio->calset_2, base + MIPHY_PLL_CALSET_2); miphy28lp_pll_calibration()
404 writeb_relaxed(pll_ratio->calset_3, base + MIPHY_PLL_CALSET_3); miphy28lp_pll_calibration()
405 writeb_relaxed(pll_ratio->calset_4, base + MIPHY_PLL_CALSET_4); miphy28lp_pll_calibration()
406 writeb_relaxed(pll_ratio->cal_ctrl, base + MIPHY_PLL_CALSET_CTRL); miphy28lp_pll_calibration()
408 writeb_relaxed(TX_SEL, base + MIPHY_BOUNDARY_SEL); miphy28lp_pll_calibration()
411 writeb_relaxed(val, base + MIPHY_TX_CAL_MAN); miphy28lp_pll_calibration()
418 writeb_relaxed(val, base + MIPHY_RX_CAL_OFFSET_CTRL); miphy28lp_pll_calibration()
421 writeb_relaxed(0x00, base + MIPHY_CONF); miphy28lp_pll_calibration()
422 writeb_relaxed(0x70, base + MIPHY_RX_LOCK_STEP); miphy28lp_pll_calibration()
423 writeb_relaxed(EN_FIRST_HALF, base + MIPHY_RX_SIGDET_SLEEP_OA); miphy28lp_pll_calibration()
424 writeb_relaxed(EN_FIRST_HALF, base + MIPHY_RX_SIGDET_SLEEP_SEL); miphy28lp_pll_calibration()
425 writeb_relaxed(EN_FIRST_HALF, base + MIPHY_RX_SIGDET_WAIT_SEL); miphy28lp_pll_calibration()
428 writeb_relaxed(val, base + MIPHY_RX_SIGDET_DATA_SEL); miphy28lp_pll_calibration()
435 void __iomem *base = miphy_phy->base; miphy28lp_sata_config_gen() local
442 writeb_relaxed(gen->bank, base + MIPHY_CONF); miphy28lp_sata_config_gen()
443 writeb_relaxed(gen->speed, base + MIPHY_SPEED); miphy28lp_sata_config_gen()
444 writeb_relaxed(gen->bias_boost_1, base + MIPHY_BIAS_BOOST_1); miphy28lp_sata_config_gen()
445 writeb_relaxed(gen->bias_boost_2, base + MIPHY_BIAS_BOOST_2); miphy28lp_sata_config_gen()
448 writeb_relaxed(gen->tx_ctrl_2, base + MIPHY_TX_CTRL_2); miphy28lp_sata_config_gen()
449 writeb_relaxed(gen->tx_ctrl_3, base + MIPHY_TX_CTRL_3); miphy28lp_sata_config_gen()
452 writeb_relaxed(gen->rx_buff_ctrl, base + MIPHY_RX_BUFFER_CTRL); miphy28lp_sata_config_gen()
453 writeb_relaxed(gen->rx_vga_gain, base + MIPHY_RX_VGA_GAIN); miphy28lp_sata_config_gen()
454 writeb_relaxed(gen->rx_equ_gain_1, base + MIPHY_RX_EQU_GAIN_1); miphy28lp_sata_config_gen()
455 writeb_relaxed(gen->rx_equ_gain_2, base + MIPHY_RX_EQU_GAIN_2); miphy28lp_sata_config_gen()
456 writeb_relaxed(gen->rx_equ_gain_3, base + MIPHY_RX_EQU_GAIN_3); miphy28lp_sata_config_gen()
462 void __iomem *base = miphy_phy->base; miphy28lp_pcie_config_gen() local
469 writeb_relaxed(gen->bank, base + MIPHY_CONF); miphy28lp_pcie_config_gen()
470 writeb_relaxed(gen->speed, base + MIPHY_SPEED); miphy28lp_pcie_config_gen()
471 writeb_relaxed(gen->bias_boost_1, base + MIPHY_BIAS_BOOST_1); miphy28lp_pcie_config_gen()
472 writeb_relaxed(gen->bias_boost_2, base + MIPHY_BIAS_BOOST_2); miphy28lp_pcie_config_gen()
475 writeb_relaxed(gen->tx_ctrl_1, base + MIPHY_TX_CTRL_1); miphy28lp_pcie_config_gen()
476 writeb_relaxed(gen->tx_ctrl_2, base + MIPHY_TX_CTRL_2); miphy28lp_pcie_config_gen()
477 writeb_relaxed(gen->tx_ctrl_3, base + MIPHY_TX_CTRL_3); miphy28lp_pcie_config_gen()
479 writeb_relaxed(gen->rx_k_gain, base + MIPHY_RX_K_GAIN); miphy28lp_pcie_config_gen()
482 writeb_relaxed(gen->rx_buff_ctrl, base + MIPHY_RX_BUFFER_CTRL); miphy28lp_pcie_config_gen()
483 writeb_relaxed(gen->rx_vga_gain, base + MIPHY_RX_VGA_GAIN); miphy28lp_pcie_config_gen()
484 writeb_relaxed(gen->rx_equ_gain_1, base + MIPHY_RX_EQU_GAIN_1); miphy28lp_pcie_config_gen()
485 writeb_relaxed(gen->rx_equ_gain_2, base + MIPHY_RX_EQU_GAIN_2); miphy28lp_pcie_config_gen()
496 val = readb_relaxed(miphy_phy->base + MIPHY_COMP_FSM_6); miphy28lp_wait_compensation()
510 void __iomem *base = miphy_phy->base; miphy28lp_compensation() local
514 writeb_relaxed(RST_PLL_SW | RST_COMP_SW, base + MIPHY_RESET); miphy28lp_compensation()
516 writeb_relaxed(0x00, base + MIPHY_PLL_COMMON_MISC_2); miphy28lp_compensation()
517 writeb_relaxed(pll_ratio->clk_ref, base + MIPHY_PLL_CLKREF_FREQ); miphy28lp_compensation()
518 writeb_relaxed(COMP_START, base + MIPHY_COMP_FSM_1); miphy28lp_compensation()
521 writeb_relaxed(RST_PLL_SW, base + MIPHY_RESET); miphy28lp_compensation()
523 writeb_relaxed(0x00, base + MIPHY_RESET); miphy28lp_compensation()
524 writeb_relaxed(START_ACT_FILT, base + MIPHY_PLL_COMMON_MISC_2); miphy28lp_compensation()
525 writeb_relaxed(SET_NEW_CHANGE, base + MIPHY_PLL_SBR_1); miphy28lp_compensation()
528 writeb_relaxed(0x00, base + MIPHY_COMP_POSTP); miphy28lp_compensation()
538 void __iomem *base = miphy_phy->base; miphy28_usb3_miphy_reset() local
542 writeb_relaxed(RST_APPLI_SW, base + MIPHY_CONF_RESET); miphy28_usb3_miphy_reset()
543 writeb_relaxed(0x00, base + MIPHY_CONF_RESET); miphy28_usb3_miphy_reset()
544 writeb_relaxed(RST_COMP_SW, base + MIPHY_RESET); miphy28_usb3_miphy_reset()
547 writeb_relaxed(val, base + MIPHY_RESET); miphy28_usb3_miphy_reset()
549 writeb_relaxed(0x00, base + MIPHY_PLL_COMMON_MISC_2); miphy28_usb3_miphy_reset()
550 writeb_relaxed(0x1e, base + MIPHY_PLL_CLKREF_FREQ); miphy28_usb3_miphy_reset()
551 writeb_relaxed(COMP_START, base + MIPHY_COMP_FSM_1); miphy28_usb3_miphy_reset()
552 writeb_relaxed(RST_PLL_SW, base + MIPHY_RESET); miphy28_usb3_miphy_reset()
553 writeb_relaxed(0x00, base + MIPHY_RESET); miphy28_usb3_miphy_reset()
554 writeb_relaxed(START_ACT_FILT, base + MIPHY_PLL_COMMON_MISC_2); miphy28_usb3_miphy_reset()
555 writeb_relaxed(0x00, base + MIPHY_CONF); miphy28_usb3_miphy_reset()
556 writeb_relaxed(0x00, base + MIPHY_BOUNDARY_1); miphy28_usb3_miphy_reset()
557 writeb_relaxed(0x00, base + MIPHY_TST_BIAS_BOOST_2); miphy28_usb3_miphy_reset()
558 writeb_relaxed(0x00, base + MIPHY_CONF); miphy28_usb3_miphy_reset()
559 writeb_relaxed(SET_NEW_CHANGE, base + MIPHY_PLL_SBR_1); miphy28_usb3_miphy_reset()
560 writeb_relaxed(0xa5, base + MIPHY_DEBUG_BUS); miphy28_usb3_miphy_reset()
561 writeb_relaxed(0x00, base + MIPHY_CONF); miphy28_usb3_miphy_reset()
566 void __iomem *base = miphy_phy->base; miphy_sata_tune_ssc() local
574 val = readb_relaxed(base + MIPHY_BOUNDARY_2); miphy_sata_tune_ssc()
576 writeb_relaxed(val, base + MIPHY_BOUNDARY_2); miphy_sata_tune_ssc()
578 val = readb_relaxed(base + MIPHY_BOUNDARY_SEL); miphy_sata_tune_ssc()
580 writeb_relaxed(val, base + MIPHY_BOUNDARY_SEL); miphy_sata_tune_ssc()
583 writeb_relaxed(val, base + MIPHY_CONF); miphy_sata_tune_ssc()
587 writeb_relaxed(0x3c, base + MIPHY_PLL_SBR_2); miphy_sata_tune_ssc()
588 writeb_relaxed(0x6c, base + MIPHY_PLL_SBR_3); miphy_sata_tune_ssc()
589 writeb_relaxed(0x81, base + MIPHY_PLL_SBR_4); miphy_sata_tune_ssc()
592 writeb_relaxed(0x00, base + MIPHY_PLL_SBR_1); miphy_sata_tune_ssc()
595 writeb_relaxed(SET_NEW_CHANGE, base + MIPHY_PLL_SBR_1); miphy_sata_tune_ssc()
598 writeb_relaxed(0x00, base + MIPHY_PLL_SBR_1); miphy_sata_tune_ssc()
604 void __iomem *base = miphy_phy->base; miphy_pcie_tune_ssc() local
612 val = readb_relaxed(base + MIPHY_BOUNDARY_2); miphy_pcie_tune_ssc()
614 writeb_relaxed(val, base + MIPHY_BOUNDARY_2); miphy_pcie_tune_ssc()
616 val = readb_relaxed(base + MIPHY_BOUNDARY_SEL); miphy_pcie_tune_ssc()
618 writeb_relaxed(val, base + MIPHY_BOUNDARY_SEL); miphy_pcie_tune_ssc()
621 writeb_relaxed(val, base + MIPHY_CONF); miphy_pcie_tune_ssc()
624 writeb_relaxed(0x69, base + MIPHY_PLL_SBR_3); miphy_pcie_tune_ssc()
625 writeb_relaxed(0x21, base + MIPHY_PLL_SBR_4); miphy_pcie_tune_ssc()
628 writeb_relaxed(0x3c, base + MIPHY_PLL_SBR_2); miphy_pcie_tune_ssc()
629 writeb_relaxed(0x21, base + MIPHY_PLL_SBR_4); miphy_pcie_tune_ssc()
632 writeb_relaxed(0x00, base + MIPHY_PLL_SBR_1); miphy_pcie_tune_ssc()
635 writeb_relaxed(SET_NEW_CHANGE, base + MIPHY_PLL_SBR_1); miphy_pcie_tune_ssc()
638 writeb_relaxed(0x00, base + MIPHY_PLL_SBR_1); miphy_pcie_tune_ssc()
645 writeb_relaxed(0x02, miphy_phy->base + MIPHY_COMP_POSTP); miphy_tune_tx_impedance()
650 void __iomem *base = miphy_phy->base; miphy28lp_configure_sata() local
665 writeb_relaxed(0x21, base + MIPHY_RX_POWER_CTRL_1); miphy28lp_configure_sata()
668 writeb_relaxed(0x00, base + MIPHY_CONF_RESET); miphy28lp_configure_sata()
678 val = readb_relaxed(miphy_phy->base + MIPHY_CONTROL); miphy28lp_configure_sata()
680 writeb_relaxed(val, miphy_phy->base + MIPHY_CONTROL); miphy28lp_configure_sata()
694 void __iomem *base = miphy_phy->base; miphy28lp_configure_pcie() local
708 writeb_relaxed(0x21, base + MIPHY_RX_POWER_CTRL_1); miphy28lp_configure_pcie()
711 writeb_relaxed(0x00, base + MIPHY_CONF_RESET); miphy28lp_configure_pcie()
731 void __iomem *base = miphy_phy->base; miphy28lp_configure_usb3() local
741 writeb_relaxed(0x00, base + MIPHY_CONF); miphy28lp_configure_usb3()
744 writeb_relaxed(val, base + MIPHY_SPEED); miphy28lp_configure_usb3()
747 writeb_relaxed(0x1c, base + MIPHY_RX_LOCK_SETTINGS_OPT); miphy28lp_configure_usb3()
748 writeb_relaxed(0x51, base + MIPHY_RX_CAL_CTRL_1); miphy28lp_configure_usb3()
749 writeb_relaxed(0x70, base + MIPHY_RX_CAL_CTRL_2); miphy28lp_configure_usb3()
753 writeb_relaxed(val, base + MIPHY_RX_CAL_OFFSET_CTRL); miphy28lp_configure_usb3()
754 writeb_relaxed(0x22, base + MIPHY_RX_CAL_VGA_STEP); miphy28lp_configure_usb3()
755 writeb_relaxed(0x0e, base + MIPHY_RX_CAL_OPT_LENGTH); miphy28lp_configure_usb3()
758 writeb_relaxed(val, base + MIPHY_RX_BUFFER_CTRL); miphy28lp_configure_usb3()
759 writeb_relaxed(0x78, base + MIPHY_RX_EQU_GAIN_1); miphy28lp_configure_usb3()
760 writeb_relaxed(0x1b, base + MIPHY_SYNCHAR_CONTROL); miphy28lp_configure_usb3()
763 writeb_relaxed(0x02, base + MIPHY_COMP_POSTP); miphy28lp_configure_usb3()
768 writeb_relaxed(val, base + MIPHY_BOUNDARY_SEL); miphy28lp_configure_usb3()
771 writeb_relaxed(0x00, base + MIPHY_BIAS_BOOST_1); miphy28lp_configure_usb3()
772 writeb_relaxed(0xa7, base + MIPHY_BIAS_BOOST_2); miphy28lp_configure_usb3()
775 writeb_relaxed(SSC_EN_SW, base + MIPHY_BOUNDARY_2); miphy28lp_configure_usb3()
778 writeb_relaxed(0x00, base + MIPHY_CONF); miphy28lp_configure_usb3()
781 writeb_relaxed(0x5a, base + MIPHY_PLL_SBR_3); miphy28lp_configure_usb3()
782 writeb_relaxed(0xa0, base + MIPHY_PLL_SBR_4); miphy28lp_configure_usb3()
785 writeb_relaxed(0x3c, base + MIPHY_PLL_SBR_2); miphy28lp_configure_usb3()
786 writeb_relaxed(0xa1, base + MIPHY_PLL_SBR_4); miphy28lp_configure_usb3()
789 writeb_relaxed(0x00, base + MIPHY_PLL_SBR_1); miphy28lp_configure_usb3()
792 writeb_relaxed(0x02, base + MIPHY_PLL_SBR_1); miphy28lp_configure_usb3()
795 writeb_relaxed(0x00, base + MIPHY_PLL_SBR_1); miphy28lp_configure_usb3()
798 writeb_relaxed(0xca, base + MIPHY_RX_K_GAIN); miphy28lp_configure_usb3()
802 writeb_relaxed(0x21, base + MIPHY_RX_POWER_CTRL_1); miphy28lp_configure_usb3()
803 writeb_relaxed(0x29, base + MIPHY_RX_POWER_CTRL_1); miphy28lp_configure_usb3()
804 writeb_relaxed(0x1a, base + MIPHY_RX_POWER_CTRL_2); miphy28lp_configure_usb3()
824 val = readb_relaxed(miphy_phy->base + MIPHY_STATUS_1); miphy_is_ready()
873 void __iomem **base) miphy28lp_get_one_addr()
880 *base = devm_ioremap(dev, res.start, resource_size(&res)); miphy28lp_get_one_addr()
881 if (!*base) { miphy28lp_get_one_addr()
929 (!miphy_phy->base)) miphy28lp_init_sata()
932 dev_info(miphy_dev->dev, "sata-up mode, addr 0x%p\n", miphy_phy->base); miphy28lp_init_sata()
965 || (!miphy_phy->base) || (!miphy_phy->pipebase)) miphy28lp_init_pcie()
968 dev_info(miphy_dev->dev, "pcie-up mode, addr 0x%p\n", miphy_phy->base); miphy28lp_init_pcie()
1008 if ((!miphy_phy->base) || (!miphy_phy->pipebase)) miphy28lp_init_usb3()
1011 dev_info(miphy_dev->dev, "usb3-up mode, addr 0x%p\n", miphy_phy->base); miphy28lp_init_usb3()
1087 &miphy_phy->base); miphy28lp_get_addr()
871 miphy28lp_get_one_addr(struct device *dev, struct device_node *child, char *rname, void __iomem **base) miphy28lp_get_one_addr() argument
|
| H A D | phy-pxa-28nm-hsic.c | 52 void __iomem *base; member in struct:mv_hsic_phy
71 void __iomem *base = mv_phy->base; mv_hsic_phy_init() local
79 base + PHY_28NM_HSIC_PLL_CTRL01); mv_hsic_phy_init()
82 writel(readl(base + PHY_28NM_HSIC_PLL_CTRL2) | mv_hsic_phy_init()
84 base + PHY_28NM_HSIC_PLL_CTRL2); mv_hsic_phy_init()
87 if (!wait_for_reg(base + PHY_28NM_HSIC_PLL_CTRL2, mv_hsic_phy_init()
101 void __iomem *base = mv_phy->base; mv_hsic_phy_power_on() local
104 reg = readl(base + PHY_28NM_HSIC_CTRL); mv_hsic_phy_power_on()
108 writel(reg, base + PHY_28NM_HSIC_CTRL); mv_hsic_phy_power_on()
120 if (!wait_for_reg(base + PHY_28NM_HSIC_IMPCAL_CAL, mv_hsic_phy_power_on()
127 if (!wait_for_reg(base + PHY_28NM_HSIC_INT, mv_hsic_phy_power_on()
139 void __iomem *base = mv_phy->base; mv_hsic_phy_power_off() local
141 writel(readl(base + PHY_28NM_HSIC_CTRL) & ~PHY_28NM_HSIC_S2H_HSIC_EN, mv_hsic_phy_power_off()
142 base + PHY_28NM_HSIC_CTRL); mv_hsic_phy_power_off()
150 void __iomem *base = mv_phy->base; mv_hsic_phy_exit() local
153 writel(readl(base + PHY_28NM_HSIC_PLL_CTRL2) & mv_hsic_phy_exit()
155 base + PHY_28NM_HSIC_PLL_CTRL2); mv_hsic_phy_exit()
189 mv_phy->base = devm_ioremap_resource(&pdev->dev, r); mv_hsic_phy_probe()
190 if (IS_ERR(mv_phy->base)) mv_hsic_phy_probe()
191 return PTR_ERR(mv_phy->base); mv_hsic_phy_probe()
|
| H A D | phy-pxa-28nm-usb2.c | 146 void __iomem *base; member in struct:mv_usb2_phy
165 void __iomem *base = mv_phy->base; mv_usb2_phy_28nm_init() local
172 reg = readl(base + PHY_28NM_PLL_REG0) & mv_usb2_phy_28nm_init()
179 base + PHY_28NM_PLL_REG0); mv_usb2_phy_28nm_init()
182 reg = readl(base + PHY_28NM_PLL_REG1); mv_usb2_phy_28nm_init()
184 base + PHY_28NM_PLL_REG1); mv_usb2_phy_28nm_init()
187 reg = readl(base + PHY_28NM_TX_REG0) & ~PHY_28NM_TX_AMP_MASK; mv_usb2_phy_28nm_init()
190 base + PHY_28NM_TX_REG0); mv_usb2_phy_28nm_init()
193 reg = readl(base + PHY_28NM_RX_REG0) & ~PHY_28NM_RX_SQ_THRESH_MASK; mv_usb2_phy_28nm_init()
195 base + PHY_28NM_RX_REG0); mv_usb2_phy_28nm_init()
198 reg = readl(base + PHY_28NM_DIG_REG0) & mv_usb2_phy_28nm_init()
204 base + PHY_28NM_DIG_REG0); mv_usb2_phy_28nm_init()
207 reg = readl(base + PHY_28NM_OTG_REG) | PHY_28NM_OTG_PU_OTG; mv_usb2_phy_28nm_init()
208 writel(reg & ~PHY_28NM_OTG_CONTROL_BY_PIN, base + PHY_28NM_OTG_REG); mv_usb2_phy_28nm_init()
220 if (!wait_for_reg(base + PHY_28NM_CAL_REG, mv_usb2_phy_28nm_init()
227 if (!wait_for_reg(base + PHY_28NM_RX_REG1, mv_usb2_phy_28nm_init()
234 if (!wait_for_reg(base + PHY_28NM_PLL_REG0, mv_usb2_phy_28nm_init()
250 void __iomem *base = mv_phy->base; mv_usb2_phy_28nm_power_on() local
252 writel(readl(base + PHY_28NM_CTRL_REG3) | mv_usb2_phy_28nm_power_on()
255 base + PHY_28NM_CTRL_REG3); mv_usb2_phy_28nm_power_on()
263 void __iomem *base = mv_phy->base; mv_usb2_phy_28nm_power_off() local
265 writel(readl(base + PHY_28NM_CTRL_REG3) | mv_usb2_phy_28nm_power_off()
268 base + PHY_28NM_CTRL_REG3); mv_usb2_phy_28nm_power_off()
276 void __iomem *base = mv_phy->base; mv_usb2_phy_28nm_exit() local
279 val = readw(base + PHY_28NM_PLL_REG1); mv_usb2_phy_28nm_exit()
281 writew(val, base + PHY_28NM_PLL_REG1); mv_usb2_phy_28nm_exit()
284 val = readw(base + PHY_28NM_TX_REG0); mv_usb2_phy_28nm_exit()
286 writew(val, base + PHY_28NM_TX_REG0); mv_usb2_phy_28nm_exit()
289 val = readw(base + PHY_28NM_OTG_REG); mv_usb2_phy_28nm_exit()
291 writew(val, base + PHY_28NM_OTG_REG); mv_usb2_phy_28nm_exit()
324 mv_phy->base = devm_ioremap_resource(&pdev->dev, r); mv_usb2_phy_probe()
325 if (IS_ERR(mv_phy->base)) mv_usb2_phy_probe()
326 return PTR_ERR(mv_phy->base); mv_usb2_phy_probe()
|
| /linux-4.4.14/arch/powerpc/net/ |
| H A D | bpf_jit.h | 104 #define PPC_STD(r, base, i) EMIT(PPC_INST_STD | ___PPC_RS(r) | \
105 ___PPC_RA(base) | ((i) & 0xfffc))
106 #define PPC_STDU(r, base, i) EMIT(PPC_INST_STDU | ___PPC_RS(r) | \
107 ___PPC_RA(base) | ((i) & 0xfffc))
108 #define PPC_STW(r, base, i) EMIT(PPC_INST_STW | ___PPC_RS(r) | \
109 ___PPC_RA(base) | ((i) & 0xfffc))
110 #define PPC_STWU(r, base, i) EMIT(PPC_INST_STWU | ___PPC_RS(r) | \
111 ___PPC_RA(base) | ((i) & 0xfffc))
113 #define PPC_LBZ(r, base, i) EMIT(PPC_INST_LBZ | ___PPC_RT(r) | \
114 ___PPC_RA(base) | IMM_L(i))
115 #define PPC_LD(r, base, i) EMIT(PPC_INST_LD | ___PPC_RT(r) | \
116 ___PPC_RA(base) | IMM_L(i))
117 #define PPC_LWZ(r, base, i) EMIT(PPC_INST_LWZ | ___PPC_RT(r) | \
118 ___PPC_RA(base) | IMM_L(i))
119 #define PPC_LHZ(r, base, i) EMIT(PPC_INST_LHZ | ___PPC_RT(r) | \
120 ___PPC_RA(base) | IMM_L(i))
121 #define PPC_LHBRX(r, base, b) EMIT(PPC_INST_LHBRX | ___PPC_RT(r) | \
122 ___PPC_RA(base) | ___PPC_RB(b))
125 #define PPC_BPF_LL(r, base, i) do { PPC_LD(r, base, i); } while(0)
126 #define PPC_BPF_STL(r, base, i) do { PPC_STD(r, base, i); } while(0)
127 #define PPC_BPF_STLU(r, base, i) do { PPC_STDU(r, base, i); } while(0)
129 #define PPC_BPF_LL(r, base, i) do { PPC_LWZ(r, base, i); } while(0)
130 #define PPC_BPF_STL(r, base, i) do { PPC_STW(r, base, i); } while(0)
131 #define PPC_BPF_STLU(r, base, i) do { PPC_STWU(r, base, i); } while(0)
135 #define PPC_LBZ_OFFS(r, base, i) do { if ((i) < 32768) PPC_LBZ(r, base, i); \
136 else { PPC_ADDIS(r, base, IMM_HA(i)); \
139 #define PPC_LD_OFFS(r, base, i) do { if ((i) < 32768) PPC_LD(r, base, i); \
140 else { PPC_ADDIS(r, base, IMM_HA(i)); \
143 #define PPC_LWZ_OFFS(r, base, i) do { if ((i) < 32768) PPC_LWZ(r, base, i); \
144 else { PPC_ADDIS(r, base, IMM_HA(i)); \
147 #define PPC_LHZ_OFFS(r, base, i) do { if ((i) < 32768) PPC_LHZ(r, base, i); \
148 else { PPC_ADDIS(r, base, IMM_HA(i)); \
152 #define PPC_LL_OFFS(r, base, i) do { PPC_LD_OFFS(r, base, i); } while(0)
154 #define PPC_LL_OFFS(r, base, i) do { PPC_LWZ_OFFS(r, base, i); } while(0)
261 #define PPC_LHBRX_OFFS(r, base, i) \
262 do { PPC_LI32(r, i); PPC_LHBRX(r, r, base); } while(0)
264 #define PPC_NTOHS_OFFS(r, base, i) PPC_LHBRX_OFFS(r, base, i)
266 #define PPC_NTOHS_OFFS(r, base, i) PPC_LHZ_OFFS(r, base, i)
|
| /linux-4.4.14/include/crypto/internal/ |
| H A D | aead.h | 27 char head[offsetof(struct aead_alg, base)];
28 struct crypto_instance base; member in struct:aead_instance::__anon12060::__anon12061
35 struct crypto_spawn base; member in struct:crypto_aead_spawn
39 struct crypto_queue base; member in struct:aead_queue
44 return crypto_tfm_ctx(&tfm->base); crypto_aead_ctx()
50 return container_of(&inst->alg.base, struct crypto_instance, alg); aead_crypto_instance()
55 return container_of(&inst->alg, struct aead_instance, alg.base); aead_instance()
60 return aead_instance(crypto_tfm_alg_instance(&aead->base)); aead_alg_instance()
75 req->base.complete(&req->base, err); aead_request_complete()
80 return req->base.flags; aead_request_flags()
86 crypto_set_spawn(&spawn->base, inst); crypto_set_aead_spawn()
94 crypto_drop_spawn(&spawn->base); crypto_drop_aead()
100 return container_of(spawn->base.alg, struct aead_alg, base); crypto_spawn_aead_alg()
106 return crypto_spawn_tfm2(&spawn->base); crypto_spawn_aead()
128 crypto_init_queue(&queue->base, max_qlen); aead_init_queue()
134 return crypto_enqueue_request(&queue->base, &request->base); aead_enqueue_request()
142 req = crypto_dequeue_request(&queue->base); aead_dequeue_request()
144 return req ? container_of(req, struct aead_request, base) : NULL; aead_dequeue_request()
151 req = crypto_get_backlog(&queue->base); aead_get_backlog()
153 return req ? container_of(req, struct aead_request, base) : NULL; aead_get_backlog()
|
| H A D | skcipher.h | 23 struct crypto_spawn base; member in struct:crypto_skcipher_spawn
31 crypto_set_spawn(&spawn->base, inst); crypto_set_skcipher_spawn()
41 crypto_drop_spawn(&spawn->base); crypto_drop_skcipher()
47 return spawn->base.alg; crypto_skcipher_spawn_alg()
54 crypto_spawn_tfm(&spawn->base, crypto_skcipher_type(0), crypto_spawn_skcipher()
72 return crypto_ablkcipher_crt(geniv)->base; skcipher_geniv_cipher()
96 req->base.complete(&req->base, err); ablkcipher_request_complete()
107 return req->base.flags; ablkcipher_request_flags()
112 return crypto_tfm_ctx(&tfm->base); crypto_skcipher_ctx()
122 return req->base.flags; skcipher_request_flags()
|
| /linux-4.4.14/include/linux/mmc/ |
| H A D | sh_mmcif.h | 102 static inline void sh_mmcif_boot_cmd_send(void __iomem *base, sh_mmcif_boot_cmd_send() argument
105 sh_mmcif_writel(base, MMCIF_CE_INT, 0); sh_mmcif_boot_cmd_send()
106 sh_mmcif_writel(base, MMCIF_CE_ARG, arg); sh_mmcif_boot_cmd_send()
107 sh_mmcif_writel(base, MMCIF_CE_CMD_SET, cmd); sh_mmcif_boot_cmd_send()
110 static inline int sh_mmcif_boot_cmd_poll(void __iomem *base, unsigned long mask) sh_mmcif_boot_cmd_poll() argument
116 tmp = sh_mmcif_readl(base, MMCIF_CE_INT); sh_mmcif_boot_cmd_poll()
118 sh_mmcif_writel(base, MMCIF_CE_INT, tmp & ~mask); sh_mmcif_boot_cmd_poll()
126 static inline int sh_mmcif_boot_cmd(void __iomem *base, sh_mmcif_boot_cmd() argument
129 sh_mmcif_boot_cmd_send(base, cmd, arg); sh_mmcif_boot_cmd()
130 return sh_mmcif_boot_cmd_poll(base, 0x00010000); sh_mmcif_boot_cmd()
133 static inline int sh_mmcif_boot_do_read_single(void __iomem *base, sh_mmcif_boot_do_read_single() argument
140 sh_mmcif_boot_cmd(base, 0x0d400000, 0x00010000); sh_mmcif_boot_do_read_single()
142 if (sh_mmcif_readl(base, MMCIF_CE_RESP0) != 0x0900) sh_mmcif_boot_do_read_single()
146 sh_mmcif_boot_cmd(base, 0x11480000, block_nr * SH_MMCIF_BBS); sh_mmcif_boot_do_read_single()
147 if (sh_mmcif_boot_cmd_poll(base, 0x00100000) < 0) sh_mmcif_boot_do_read_single()
151 buf[k] = sh_mmcif_readl(base, MMCIF_CE_DATA); sh_mmcif_boot_do_read_single()
156 static inline int sh_mmcif_boot_do_read(void __iomem *base, sh_mmcif_boot_do_read() argument
165 sh_mmcif_writel(base, MMCIF_CE_CLK_CTRL, sh_mmcif_boot_do_read()
170 sh_mmcif_boot_cmd(base, 0x09806000, 0x00010000); sh_mmcif_boot_do_read()
173 sh_mmcif_boot_cmd(base, 0x07400000, 0x00010000); sh_mmcif_boot_do_read()
176 sh_mmcif_boot_cmd(base, 0x10400000, SH_MMCIF_BBS); sh_mmcif_boot_do_read()
179 ret = sh_mmcif_boot_do_read_single(base, first_block + k, sh_mmcif_boot_do_read()
185 static inline void sh_mmcif_boot_init(void __iomem *base) sh_mmcif_boot_init() argument
188 sh_mmcif_writel(base, MMCIF_CE_VERSION, SOFT_RST_ON); sh_mmcif_boot_init()
189 sh_mmcif_writel(base, MMCIF_CE_VERSION, SOFT_RST_OFF); sh_mmcif_boot_init()
192 sh_mmcif_writel(base, MMCIF_CE_BUF_ACC, BUF_ACC_ATYP); sh_mmcif_boot_init()
195 sh_mmcif_writel(base, MMCIF_CE_BLOCK_SET, SH_MMCIF_BBS); sh_mmcif_boot_init()
198 sh_mmcif_writel(base, MMCIF_CE_CLK_CTRL, sh_mmcif_boot_init()
203 sh_mmcif_boot_cmd(base, 0x00000040, 0); sh_mmcif_boot_init()
207 sh_mmcif_boot_cmd(base, 0x01405040, 0x40300000); /* CMD1 */ sh_mmcif_boot_init()
208 } while ((sh_mmcif_readl(base, MMCIF_CE_RESP0) & 0x80000000) sh_mmcif_boot_init()
212 sh_mmcif_boot_cmd(base, 0x02806040, 0); sh_mmcif_boot_init()
215 sh_mmcif_boot_cmd(base, 0x03400040, 0x00010000); sh_mmcif_boot_init()
|
| /linux-4.4.14/drivers/ide/ |
| H A D | ide-legacy.c | 9 unsigned long base, ctl; ide_legacy_init_one() local
13 base = 0x1f0; ide_legacy_init_one()
17 base = 0x170; ide_legacy_init_one()
22 if (!request_region(base, 8, d->name)) { ide_legacy_init_one()
24 d->name, base, base + 7); ide_legacy_init_one()
31 release_region(base, 8); ide_legacy_init_one()
35 ide_std_init_ports(hw, base, ctl); ide_legacy_init_one()
|
| H A D | ide-4drives.c | 33 unsigned long base = 0x1f0, ctl = 0x3f6; ide_4drives_init() local
39 if (!request_region(base, 8, DRV_NAME)) { ide_4drives_init()
41 DRV_NAME, base, base + 7); ide_4drives_init()
48 release_region(base, 8); ide_4drives_init()
54 ide_std_init_ports(&hw, base, ctl); ide_4drives_init()
|
| H A D | palm_bk3710.c | 77 static void palm_bk3710_setudmamode(void __iomem *base, unsigned int dev, palm_bk3710_setudmamode() argument
92 val32 = readl(base + BK3710_UDMASTB) & (0xFF << (dev ? 0 : 8)); palm_bk3710_setudmamode()
94 writel(val32, base + BK3710_UDMASTB); palm_bk3710_setudmamode()
97 val32 = readl(base + BK3710_UDMATRP) & (0xFF << (dev ? 0 : 8)); palm_bk3710_setudmamode()
99 writel(val32, base + BK3710_UDMATRP); palm_bk3710_setudmamode()
102 val32 = readl(base + BK3710_UDMAENV) & (0xFF << (dev ? 0 : 8)); palm_bk3710_setudmamode()
104 writel(val32, base + BK3710_UDMAENV); palm_bk3710_setudmamode()
107 val16 = readw(base + BK3710_UDMACTL) | (1 << dev); palm_bk3710_setudmamode()
108 writew(val16, base + BK3710_UDMACTL); palm_bk3710_setudmamode()
111 static void palm_bk3710_setdmamode(void __iomem *base, unsigned int dev, palm_bk3710_setdmamode() argument
130 val32 = readl(base + BK3710_DMASTB) & (0xFF << (dev ? 0 : 8)); palm_bk3710_setdmamode()
132 writel(val32, base + BK3710_DMASTB); palm_bk3710_setdmamode()
134 val32 = readl(base + BK3710_DMARCVR) & (0xFF << (dev ? 0 : 8)); palm_bk3710_setdmamode()
136 writel(val32, base + BK3710_DMARCVR); palm_bk3710_setdmamode()
139 val16 = readw(base + BK3710_UDMACTL) & ~(1 << dev); palm_bk3710_setdmamode()
140 writew(val16, base + BK3710_UDMACTL); palm_bk3710_setdmamode()
143 static void palm_bk3710_setpiomode(void __iomem *base, ide_drive_t *mate, palm_bk3710_setpiomode() argument
160 val32 = readl(base + BK3710_DATSTB) & (0xFF << (dev ? 0 : 8)); palm_bk3710_setpiomode()
162 writel(val32, base + BK3710_DATSTB); palm_bk3710_setpiomode()
164 val32 = readl(base + BK3710_DATRCVR) & (0xFF << (dev ? 0 : 8)); palm_bk3710_setpiomode()
166 writel(val32, base + BK3710_DATRCVR); palm_bk3710_setpiomode()
182 val32 = readl(base + BK3710_REGSTB) & (0xFF << (dev ? 0 : 8)); palm_bk3710_setpiomode()
184 writel(val32, base + BK3710_REGSTB); palm_bk3710_setpiomode()
186 val32 = readl(base + BK3710_REGRCVR) & (0xFF << (dev ? 0 : 8)); palm_bk3710_setpiomode()
188 writel(val32, base + BK3710_REGRCVR); palm_bk3710_setpiomode()
194 void __iomem *base = (void __iomem *)hwif->dma_base; palm_bk3710_set_dma_mode() local
198 palm_bk3710_setudmamode(base, is_slave, palm_bk3710_set_dma_mode()
201 palm_bk3710_setdmamode(base, is_slave, palm_bk3710_set_dma_mode()
212 void __iomem *base = (void __iomem *)hwif->dma_base; palm_bk3710_set_pio_mode() local
220 palm_bk3710_setpiomode(base, mate, is_slave, cycle_time, pio); palm_bk3710_set_pio_mode()
223 static void palm_bk3710_chipinit(void __iomem *base) palm_bk3710_chipinit() argument
242 writew(BIT(15), base + BK3710_IDETIMP); palm_bk3710_chipinit()
250 writew(0, base + BK3710_UDMACTL); palm_bk3710_chipinit()
258 writel(0x001, base + BK3710_MISCCTL); palm_bk3710_chipinit()
264 writel(0xFFFF, base + BK3710_IORDYTMP); palm_bk3710_chipinit()
274 writew(0, base + BK3710_BMISP); palm_bk3710_chipinit()
276 palm_bk3710_setpiomode(base, NULL, 0, 600, 0); palm_bk3710_chipinit()
277 palm_bk3710_setpiomode(base, NULL, 1, 600, 0); palm_bk3710_chipinit()
317 void __iomem *base; palm_bk3710_probe() local
350 base = ioremap(mem->start, mem_size); palm_bk3710_probe()
351 if (!base) { palm_bk3710_probe()
358 palm_bk3710_chipinit(base); palm_bk3710_probe()
363 (base + IDE_PALM_ATA_PRI_REG_OFFSET + i); palm_bk3710_probe()
365 (base + IDE_PALM_ATA_PRI_CTL_OFFSET); palm_bk3710_probe()
|
| H A D | tx4939ide.c | 84 static u16 tx4939ide_readw(void __iomem *base, u32 reg) tx4939ide_readw() argument
86 return __raw_readw(base + tx4939ide_swizzlew(reg)); tx4939ide_readw()
88 static u8 tx4939ide_readb(void __iomem *base, u32 reg) tx4939ide_readb() argument
90 return __raw_readb(base + tx4939ide_swizzleb(reg)); tx4939ide_readb()
92 static void tx4939ide_writel(u32 val, void __iomem *base, u32 reg) tx4939ide_writel() argument
94 __raw_writel(val, base + tx4939ide_swizzlel(reg)); tx4939ide_writel()
96 static void tx4939ide_writew(u16 val, void __iomem *base, u32 reg) tx4939ide_writew() argument
98 __raw_writew(val, base + tx4939ide_swizzlew(reg)); tx4939ide_writew()
100 static void tx4939ide_writeb(u8 val, void __iomem *base, u32 reg) tx4939ide_writeb() argument
102 __raw_writeb(val, base + tx4939ide_swizzleb(reg)); tx4939ide_writeb()
151 void __iomem *base = TX4939IDE_BASE(hwif); tx4939ide_check_error_ints() local
152 u16 ctl = tx4939ide_readw(base, TX4939IDE_Int_Ctl); tx4939ide_check_error_ints()
156 u16 sysctl = tx4939ide_readw(base, TX4939IDE_Sys_Ctl); tx4939ide_check_error_ints()
158 tx4939ide_writew(sysctl | 0x4000, base, TX4939IDE_Sys_Ctl); tx4939ide_check_error_ints()
162 tx4939ide_writew(sysctl, base, TX4939IDE_Sys_Ctl); tx4939ide_check_error_ints()
177 void __iomem *base; tx4939ide_clear_irq() local
187 base = TX4939IDE_BASE(hwif); tx4939ide_clear_irq()
189 tx4939ide_writew(ctl, base, TX4939IDE_Int_Ctl); tx4939ide_clear_irq()
194 void __iomem *base = TX4939IDE_BASE(hwif); tx4939ide_cable_detect() local
196 return tx4939ide_readw(base, TX4939IDE_Sys_Ctl) & 0x2000 ? tx4939ide_cable_detect()
205 void __iomem *base = TX4939IDE_BASE(hwif); tx4939ide_dma_host_set() local
206 u8 dma_stat = tx4939ide_readb(base, TX4939IDE_DMA_Stat); tx4939ide_dma_host_set()
213 tx4939ide_writeb(dma_stat, base, TX4939IDE_DMA_Stat); tx4939ide_dma_host_set()
219 static u8 tx4939ide_clear_dma_status(void __iomem *base) tx4939ide_clear_dma_status() argument
224 dma_stat = tx4939ide_readb(base, TX4939IDE_DMA_Stat); tx4939ide_clear_dma_status()
226 tx4939ide_writeb(dma_stat | ATA_DMA_INTR | ATA_DMA_ERR, base, tx4939ide_clear_dma_status()
229 tx4939ide_writew(TX4939IDE_IGNORE_INTS << 8, base, TX4939IDE_Int_Ctl); tx4939ide_clear_dma_status()
291 void __iomem *base = TX4939IDE_BASE(hwif); tx4939ide_dma_setup() local
299 tx4939ide_writel(hwif->dmatable_dma, base, TX4939IDE_PRD_Ptr); tx4939ide_dma_setup()
302 tx4939ide_writeb(rw, base, TX4939IDE_DMA_Cmd); tx4939ide_dma_setup()
305 tx4939ide_clear_dma_status(base); tx4939ide_dma_setup()
307 tx4939ide_writew(SECTOR_SIZE / 2, base, drive->dn ? tx4939ide_dma_setup()
310 tx4939ide_writew(blk_rq_sectors(cmd->rq), base, TX4939IDE_Sec_Cnt); tx4939ide_dma_setup()
319 void __iomem *base = TX4939IDE_BASE(hwif); tx4939ide_dma_end() local
320 u16 ctl = tx4939ide_readw(base, TX4939IDE_Int_Ctl); tx4939ide_dma_end()
323 dma_cmd = tx4939ide_readb(base, TX4939IDE_DMA_Cmd); tx4939ide_dma_end()
325 tx4939ide_writeb(dma_cmd & ~ATA_DMA_START, base, TX4939IDE_DMA_Cmd); tx4939ide_dma_end()
328 dma_stat = tx4939ide_clear_dma_status(base); tx4939ide_dma_end()
346 void __iomem *base = TX4939IDE_BASE(hwif); tx4939ide_dma_test_irq() local
356 stat = tx4939ide_readb(base, TX4939IDE_AltStat_DevCtl); tx4939ide_dma_test_irq()
365 dma_stat = tx4939ide_readb(base, TX4939IDE_DMA_Stat); tx4939ide_dma_test_irq()
378 tx4939ide_writew(ctl, base, TX4939IDE_Int_Ctl); tx4939ide_dma_test_irq()
385 void __iomem *base = TX4939IDE_BASE(hwif); tx4939ide_dma_sff_read_status() local
387 return tx4939ide_readb(base, TX4939IDE_DMA_Stat); tx4939ide_dma_sff_read_status()
395 void __iomem *base = TX4939IDE_BASE(hwif); tx4939ide_init_hwif() local
398 tx4939ide_writew(0x8000, base, TX4939IDE_Sys_Ctl); tx4939ide_init_hwif()
402 tx4939ide_writew(0x0000, base, TX4939IDE_Sys_Ctl); tx4939ide_init_hwif()
404 tx4939ide_writew((TX4939IDE_IGNORE_INTS << 8) | 0xff, base, tx4939ide_init_hwif()
407 tx4939ide_writew(0x0008, base, TX4939IDE_Lo_Burst_Cnt); tx4939ide_init_hwif()
408 tx4939ide_writew(0, base, TX4939IDE_Up_Burst_Cnt); tx4939ide_init_hwif()
425 void __iomem *base = TX4939IDE_BASE(hwif); tx4939ide_tf_load_fixup() local
434 tx4939ide_writew(sysctl, base, TX4939IDE_Sys_Ctl); tx4939ide_tf_load_fixup()
582 pr_info("TX4939 IDE interface (base %#lx, irq %d)\n", mapbase, irq); tx4939ide_probe()
586 /* use extra_base for base address of the all registers */ tx4939ide_probe()
|
| /linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/engine/pm/ |
| H A D | nv40.h | 3 #define nv40_pm(p) container_of((p), struct nv40_pm, base)
7 struct nvkm_pm base; member in struct:nv40_pm
|
| /linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/engine/sw/ |
| H A D | nv50.h | 3 #define nv50_sw_chan(p) container_of((p), struct nv50_sw_chan, base)
10 struct nvkm_sw_chan base; member in struct:nv50_sw_chan
|
| /linux-4.4.14/drivers/gpu/drm/nouveau/ |
| H A D | nv10_fence.h | 8 struct nouveau_fence_chan base; member in struct:nv10_fence_chan
14 struct nouveau_fence_priv base; member in struct:nv10_fence_priv
|
| H A D | nv04_fence.c | 30 struct nouveau_fence_chan base; member in struct:nv04_fence_chan
34 struct nouveau_fence_priv base; member in struct:nv04_fence_priv
44 OUT_RING (chan, fence->base.seqno); nv04_fence_emit()
70 nouveau_fence_context_del(&fctx->base); nv04_fence_context_del()
72 nouveau_fence_context_free(&fctx->base); nv04_fence_context_del()
80 nouveau_fence_context_new(chan, &fctx->base); nv04_fence_context_new()
81 fctx->base.emit = nv04_fence_emit; nv04_fence_context_new()
82 fctx->base.sync = nv04_fence_sync; nv04_fence_context_new()
83 fctx->base.read = nv04_fence_read; nv04_fence_context_new()
107 priv->base.dtor = nv04_fence_destroy; nv04_fence_create()
108 priv->base.context_new = nv04_fence_context_new; nv04_fence_create()
109 priv->base.context_del = nv04_fence_context_del; nv04_fence_create()
110 priv->base.contexts = 15; nv04_fence_create()
111 priv->base.context_base = fence_context_alloc(priv->base.contexts); nv04_fence_create()
|
| H A D | nv10_fence.c | 36 OUT_RING (chan, fence->base.seqno); nv10_fence_emit()
61 nouveau_fence_context_del(&fctx->base); nv10_fence_context_del()
66 nouveau_fence_context_free(&fctx->base); nv10_fence_context_del()
78 nouveau_fence_context_new(chan, &fctx->base); nv10_fence_context_new()
79 fctx->base.emit = nv10_fence_emit; nv10_fence_context_new()
80 fctx->base.read = nv10_fence_read; nv10_fence_context_new()
81 fctx->base.sync = nv10_fence_sync; nv10_fence_context_new()
106 priv->base.dtor = nv10_fence_destroy; nv10_fence_create()
107 priv->base.context_new = nv10_fence_context_new; nv10_fence_create()
108 priv->base.context_del = nv10_fence_context_del; nv10_fence_create()
109 priv->base.contexts = 31; nv10_fence_create()
110 priv->base.context_base = fence_context_alloc(priv->base.contexts); nv10_fence_create()
|
| /linux-4.4.14/arch/mips/sgi-ip32/ |
| H A D | ip32-memory.c | 24 u64 base, size; prom_meminit() local
31 base = (bankctl & CRIME_MEM_BANK_CONTROL_ADDR) << 25; prom_meminit()
32 if (bank != 0 && base == 0) prom_meminit()
36 if (base + size > (256 << 20)) prom_meminit()
37 base += CRIME_HI_MEM_BASE; prom_meminit()
39 printk("CRIME MC: bank %u base 0x%016Lx size %LuMiB\n", prom_meminit()
40 bank, base, size >> 20); prom_meminit()
41 add_memory_region(base, size, BOOT_MEM_RAM); prom_meminit()
|
| /linux-4.4.14/arch/cris/kernel/ |
| H A D | devicetree.c | 5 void __init early_init_dt_add_memory_arch(u64 base, u64 size) early_init_dt_add_memory_arch() argument
8 __func__, base, size); early_init_dt_add_memory_arch()
|
| /linux-4.4.14/drivers/acpi/apei/ |
| H A D | Makefile | 6 apei-y := apei-base.o hest.o erst.o
|
| /linux-4.4.14/include/asm-generic/ |
| H A D | dma-contiguous.h | 7 dma_contiguous_early_fixup(phys_addr_t base, unsigned long size) { } argument
|
| H A D | div64.h | 9 * uint32_t do_div(uint64_t *n, uint32_t base)
11 * uint32_t remainder = *n % base;
12 * *n = *n / base;
25 # define do_div(n,base) ({ \
26 uint32_t __base = (base); \
40 # define do_div(n,base) ({ \
41 uint32_t __base = (base); \
|
| /linux-4.4.14/drivers/s390/block/ |
| H A D | dasd_ioctl.c | 46 struct dasd_device *base; dasd_ioctl_enable() local
51 base = dasd_device_from_gendisk(bdev->bd_disk); dasd_ioctl_enable()
52 if (!base) dasd_ioctl_enable()
55 dasd_enable_device(base); dasd_ioctl_enable()
59 (loff_t)get_capacity(base->block->gdp) << 9); dasd_ioctl_enable()
61 dasd_put_device(base); dasd_ioctl_enable()
72 struct dasd_device *base; dasd_ioctl_disable() local
77 base = dasd_device_from_gendisk(bdev->bd_disk); dasd_ioctl_disable()
78 if (!base) dasd_ioctl_disable()
88 dasd_set_target_state(base, DASD_STATE_BASIC); dasd_ioctl_disable()
96 dasd_put_device(base); dasd_ioctl_disable()
106 struct dasd_device *base; dasd_ioctl_quiesce() local
108 base = block->base; dasd_ioctl_quiesce()
113 "state\n", dev_name(&base->cdev->dev)); dasd_ioctl_quiesce()
114 spin_lock_irqsave(get_ccwdev_lock(base->cdev), flags); dasd_ioctl_quiesce()
115 dasd_device_set_stop_bits(base, DASD_STOPPED_QUIESCE); dasd_ioctl_quiesce()
116 spin_unlock_irqrestore(get_ccwdev_lock(base->cdev), flags); dasd_ioctl_quiesce()
127 struct dasd_device *base; dasd_ioctl_resume() local
129 base = block->base; dasd_ioctl_resume()
134 "on the DASD\n", dev_name(&base->cdev->dev)); dasd_ioctl_resume()
135 spin_lock_irqsave(get_ccwdev_lock(base->cdev), flags); dasd_ioctl_resume()
136 dasd_device_remove_stop_bits(base, DASD_STOPPED_QUIESCE); dasd_ioctl_resume()
137 spin_unlock_irqrestore(get_ccwdev_lock(base->cdev), flags); dasd_ioctl_resume()
149 struct dasd_device *base; dasd_ioctl_abortio() local
152 base = block->base; dasd_ioctl_abortio()
156 if (test_and_set_bit(DASD_FLAG_ABORTALL, &base->flags)) dasd_ioctl_abortio()
158 DBF_DEV_EVENT(DBF_NOTICE, base, "%s", "abortall flag set"); dasd_ioctl_abortio()
184 struct dasd_device *base; dasd_ioctl_allowio() local
186 base = block->base; dasd_ioctl_allowio()
190 if (test_and_clear_bit(DASD_FLAG_ABORTALL, &base->flags)) dasd_ioctl_allowio()
191 DBF_DEV_EVENT(DBF_NOTICE, base, "%s", "abortall flag unset"); dasd_ioctl_allowio()
205 struct dasd_device *base; dasd_format() local
210 base = block->base; dasd_format()
211 if (base->discipline->format_device == NULL) dasd_format()
214 if (base->state != DASD_STATE_BASIC) { dasd_format()
216 dev_name(&base->cdev->dev)); dasd_format()
220 DBF_DEV_EVENT(DBF_NOTICE, base, dasd_format()
241 rc = base->discipline->format_device(base, fdata, enable_pav); dasd_format()
268 struct dasd_device *base; dasd_ioctl_format() local
276 base = dasd_device_from_gendisk(bdev->bd_disk); dasd_ioctl_format()
277 if (!base) dasd_ioctl_format()
279 if (base->features & DASD_FEATURE_READONLY || dasd_ioctl_format()
280 test_bit(DASD_FLAG_DEVICE_RO, &base->flags)) { dasd_ioctl_format()
281 dasd_put_device(base); dasd_ioctl_format()
285 dasd_put_device(base); dasd_ioctl_format()
291 dev_name(&base->cdev->dev)); dasd_ioctl_format()
292 dasd_put_device(base); dasd_ioctl_format()
295 rc = dasd_format(base->block, &fdata); dasd_ioctl_format()
296 dasd_put_device(base); dasd_ioctl_format()
377 struct dasd_device *base; dasd_ioctl_information() local
382 base = block->base; dasd_ioctl_information()
383 if (!base->discipline || !base->discipline->fill_info) dasd_ioctl_information()
390 rc = base->discipline->fill_info(base, dasd_info); dasd_ioctl_information()
396 cdev = base->cdev; dasd_ioctl_information()
406 dasd_info->status = base->state; dasd_ioctl_information()
420 if ((base->state < DASD_STATE_READY) || dasd_ioctl_information()
425 ((base->features & DASD_FEATURE_READONLY) != 0); dasd_ioctl_information()
427 memcpy(dasd_info->type, base->discipline->name, 4); dasd_ioctl_information()
440 spin_lock_irqsave(get_ccwdev_lock(base->cdev), flags); dasd_ioctl_information()
441 list_for_each(l, &base->ccw_queue) dasd_ioctl_information()
443 spin_unlock_irqrestore(get_ccwdev_lock(base->cdev), dasd_ioctl_information()
463 struct dasd_device *base; dasd_ioctl_set_ro() local
473 base = dasd_device_from_gendisk(bdev->bd_disk); dasd_ioctl_set_ro()
474 if (!base) dasd_ioctl_set_ro()
476 if (!intval && test_bit(DASD_FLAG_DEVICE_RO, &base->flags)) { dasd_ioctl_set_ro()
477 dasd_put_device(base); dasd_ioctl_set_ro()
481 rc = dasd_set_feature(base->cdev, DASD_FEATURE_READONLY, intval); dasd_ioctl_set_ro()
482 dasd_put_device(base); dasd_ioctl_set_ro()
493 ret = cmf_readall(block->base->cdev, &data); dasd_ioctl_readall_cmb()
503 struct dasd_device *base; dasd_ioctl() local
517 base = dasd_device_from_gendisk(bdev->bd_disk); dasd_ioctl()
518 if (!base) dasd_ioctl()
520 block = base->block; dasd_ioctl()
563 rc = enable_cmf(base->cdev); dasd_ioctl()
566 rc = disable_cmf(base->cdev); dasd_ioctl()
574 if (base->discipline->ioctl) dasd_ioctl()
575 rc = base->discipline->ioctl(block, cmd, argp); dasd_ioctl()
577 dasd_put_device(base); dasd_ioctl()
|
| H A D | dasd_genhd.c | 32 struct dasd_device *base; dasd_gendisk_alloc() local
36 base = block->base; dasd_gendisk_alloc()
37 if (base->devindex >= DASD_PER_MAJOR) dasd_gendisk_alloc()
46 gdp->first_minor = base->devindex << DASD_PARTN_BITS; dasd_gendisk_alloc()
48 gdp->driverfs_dev = &base->cdev->dev; dasd_gendisk_alloc()
58 if (base->devindex > 25) { dasd_gendisk_alloc()
59 if (base->devindex > 701) { dasd_gendisk_alloc()
60 if (base->devindex > 18277) dasd_gendisk_alloc()
62 'a'+(((base->devindex-18278) dasd_gendisk_alloc()
65 'a'+(((base->devindex-702)/676)%26)); dasd_gendisk_alloc()
68 'a'+(((base->devindex-26)/26)%26)); dasd_gendisk_alloc()
70 len += sprintf(gdp->disk_name + len, "%c", 'a'+(base->devindex%26)); dasd_gendisk_alloc()
72 if (base->features & DASD_FEATURE_READONLY || dasd_gendisk_alloc()
73 test_bit(DASD_FLAG_DEVICE_RO, &base->flags)) dasd_gendisk_alloc()
75 dasd_add_link_to_gendisk(gdp, base); dasd_gendisk_alloc()
106 DBF_DEV_EVENT(DBF_ERR, block->base, "%s", dasd_scan_partitions()
113 DBF_DEV_EVENT(DBF_ERR, block->base, dasd_scan_partitions()
121 DBF_DEV_EVENT(DBF_ERR, block->base, dasd_scan_partitions()
|
| /linux-4.4.14/sound/soc/txx9/ |
| H A D | txx9aclc-ac97.c | 44 return __raw_readl(drvdata->base + ACINTSTS) & ACINT_REGACCRDY; txx9aclc_regready()
52 void __iomem *base = drvdata->base; txx9aclc_ac97_read() local
55 if (!(__raw_readl(base + ACINTSTS) & ACINT_CODECRDY(ac97->num))) txx9aclc_ac97_read()
59 __raw_writel(dat, base + ACREGACC); txx9aclc_ac97_read()
60 __raw_writel(ACINT_REGACCRDY, base + ACINTEN); txx9aclc_ac97_read()
62 __raw_writel(ACINT_REGACCRDY, base + ACINTDIS); txx9aclc_ac97_read()
67 dat = __raw_readl(base + ACREGACC); txx9aclc_ac97_read()
76 __raw_writel(ACINT_REGACCRDY, base + ACINTDIS); txx9aclc_ac97_read()
85 void __iomem *base = drvdata->base; txx9aclc_ac97_write() local
89 base + ACREGACC); txx9aclc_ac97_write()
90 __raw_writel(ACINT_REGACCRDY, base + ACINTEN); txx9aclc_ac97_write()
95 __raw_writel(ACINT_REGACCRDY, base + ACINTDIS); txx9aclc_ac97_write()
101 void __iomem *base = drvdata->base; txx9aclc_ac97_cold_reset() local
104 __raw_writel(ACCTL_ENLINK, base + ACCTLDIS); txx9aclc_ac97_cold_reset()
107 __raw_writel(ACCTL_ENLINK, base + ACCTLEN); txx9aclc_ac97_cold_reset()
109 __raw_writel(ready, base + ACINTEN); txx9aclc_ac97_cold_reset()
111 (__raw_readl(base + ACINTSTS) & ready) == ready, txx9aclc_ac97_cold_reset()
115 __raw_readl(base + ACINTSTS)); txx9aclc_ac97_cold_reset()
117 __raw_writel(ACINT_REGACCRDY, base + ACINTSTS); txx9aclc_ac97_cold_reset()
118 __raw_writel(ready, base + ACINTDIS); txx9aclc_ac97_cold_reset()
131 void __iomem *base = drvdata->base; txx9aclc_ac97_irq() local
133 __raw_writel(__raw_readl(base + ACINTMSTS), base + ACINTDIS); txx9aclc_ac97_irq()
149 __raw_writel(ACCTL_ENLINK, drvdata->base + ACCTLDIS); txx9aclc_ac97_remove()
192 drvdata->base = devm_ioremap_resource(&pdev->dev, r); txx9aclc_ac97_dev_probe()
193 if (IS_ERR(drvdata->base)) txx9aclc_ac97_dev_probe()
194 return PTR_ERR(drvdata->base); txx9aclc_ac97_dev_probe()
|
| /linux-4.4.14/drivers/clocksource/ |
| H A D | timer-stm32.c | 40 void __iomem *base; member in struct:stm32_clock_event_ddata
47 void *base = data->base; stm32_clock_event_shutdown() local
49 writel_relaxed(0, base + TIM_CR1); stm32_clock_event_shutdown()
57 void *base = data->base; stm32_clock_event_set_periodic() local
59 writel_relaxed(data->periodic_top, base + TIM_ARR); stm32_clock_event_set_periodic()
60 writel_relaxed(TIM_CR1_ARPE | TIM_CR1_CEN, base + TIM_CR1); stm32_clock_event_set_periodic()
70 writel_relaxed(evt, data->base + TIM_ARR); stm32_clock_event_set_next_event()
72 data->base + TIM_CR1); stm32_clock_event_set_next_event()
81 writel_relaxed(0, data->base + TIM_SR); stm32_clock_event_handler()
131 data->base = of_iomap(np, 0); stm32_clockevent_init()
132 if (!data->base) { stm32_clockevent_init()
144 writel_relaxed(~0U, data->base + TIM_ARR); stm32_clockevent_init()
145 max_delta = readl_relaxed(data->base + TIM_ARR); stm32_clockevent_init()
153 writel_relaxed(0, data->base + TIM_ARR); stm32_clockevent_init()
155 writel_relaxed(prescaler - 1, data->base + TIM_PSC); stm32_clockevent_init()
156 writel_relaxed(TIM_EGR_UG, data->base + TIM_EGR); stm32_clockevent_init()
157 writel_relaxed(TIM_DIER_UIE, data->base + TIM_DIER); stm32_clockevent_init()
158 writel_relaxed(0, data->base + TIM_SR); stm32_clockevent_init()
179 iounmap(data->base); stm32_clockevent_init()
|
| H A D | time-efm32.c | 47 void __iomem *base; member in struct:efm32_clock_event_ddata
56 writel_relaxed(TIMERn_CMD_STOP, ddata->base + TIMERn_CMD); efm32_clock_event_shutdown()
65 writel_relaxed(TIMERn_CMD_STOP, ddata->base + TIMERn_CMD); efm32_clock_event_set_oneshot()
70 ddata->base + TIMERn_CTRL); efm32_clock_event_set_oneshot()
79 writel_relaxed(TIMERn_CMD_STOP, ddata->base + TIMERn_CMD); efm32_clock_event_set_periodic()
80 writel_relaxed(ddata->periodic_top, ddata->base + TIMERn_TOP); efm32_clock_event_set_periodic()
84 ddata->base + TIMERn_CTRL); efm32_clock_event_set_periodic()
85 writel_relaxed(TIMERn_CMD_START, ddata->base + TIMERn_CMD); efm32_clock_event_set_periodic()
95 writel_relaxed(TIMERn_CMD_STOP, ddata->base + TIMERn_CMD); efm32_clock_event_set_next_event()
96 writel_relaxed(evt, ddata->base + TIMERn_CNT); efm32_clock_event_set_next_event()
97 writel_relaxed(TIMERn_CMD_START, ddata->base + TIMERn_CMD); efm32_clock_event_set_next_event()
106 writel_relaxed(TIMERn_IRQ_UF, ddata->base + TIMERn_IFC); efm32_clock_event_handler()
135 void __iomem *base; efm32_clocksource_init() local
154 base = of_iomap(np, 0); efm32_clocksource_init()
155 if (!base) { efm32_clocksource_init()
163 TIMERn_CTRL_MODE_UP, base + TIMERn_CTRL); efm32_clocksource_init()
164 writel_relaxed(TIMERn_CMD_START, base + TIMERn_CMD); efm32_clocksource_init()
166 ret = clocksource_mmio_init(base + TIMERn_CNT, "efm32 timer", efm32_clocksource_init()
178 iounmap(base); efm32_clocksource_init()
193 void __iomem *base; efm32_clockevent_init() local
213 base = of_iomap(np, 0); efm32_clockevent_init()
214 if (!base) { efm32_clockevent_init()
227 writel_relaxed(TIMERn_IRQ_UF, base + TIMERn_IEN); efm32_clockevent_init()
229 clock_event_ddata.base = base; efm32_clockevent_init()
242 iounmap(base); efm32_clockevent_init()
|
| H A D | moxart_timer.c | 58 static void __iomem *base; variable
63 writel(TIMER1_DISABLE, base + TIMER_CR); moxart_shutdown()
69 writel(TIMER1_DISABLE, base + TIMER_CR); moxart_set_oneshot()
70 writel(~0, base + TIMER1_BASE + REG_LOAD); moxart_set_oneshot()
76 writel(clock_count_per_tick, base + TIMER1_BASE + REG_LOAD); moxart_set_periodic()
77 writel(TIMER1_ENABLE, base + TIMER_CR); moxart_set_periodic()
86 writel(TIMER1_DISABLE, base + TIMER_CR); moxart_clkevt_next_event()
88 u = readl(base + TIMER1_BASE + REG_COUNT) - cycles; moxart_clkevt_next_event()
89 writel(u, base + TIMER1_BASE + REG_MATCH1); moxart_clkevt_next_event()
91 writel(TIMER1_ENABLE, base + TIMER_CR); moxart_clkevt_next_event()
128 base = of_iomap(node, 0); moxart_timer_init()
129 if (!base) moxart_timer_init()
146 if (clocksource_mmio_init(base + TIMER2_BASE + REG_COUNT, moxart_timer_init()
153 writel(~0, base + TIMER2_BASE + REG_LOAD); moxart_timer_init()
154 writel(TIMEREG_CR_2_ENABLE, base + TIMER_CR); moxart_timer_init()
|
| H A D | armv7m_systick.c | 27 void __iomem *base; system_timer_of_register() local
31 base = of_iomap(np, 0); system_timer_of_register()
32 if (!base) { system_timer_of_register()
33 pr_warn("system-timer: invalid base address\n"); system_timer_of_register()
52 writel_relaxed(SYSTICK_LOAD_RELOAD_MASK, base + SYST_RVR); system_timer_of_register()
53 writel_relaxed(SYST_CSR_ENABLE, base + SYST_CSR); system_timer_of_register()
55 ret = clocksource_mmio_init(base + SYST_CVR, "arm_system_timer", rate, system_timer_of_register()
74 iounmap(base); system_timer_of_register()
|
| H A D | timer-sp804.c | 75 void __init sp804_timer_disable(void __iomem *base) sp804_timer_disable() argument
77 writel(0, base + TIMER_CTRL); sp804_timer_disable()
80 void __init __sp804_clocksource_and_sched_clock_init(void __iomem *base, __sp804_clocksource_and_sched_clock_init() argument
102 writel(0, base + TIMER_CTRL); __sp804_clocksource_and_sched_clock_init()
103 writel(0xffffffff, base + TIMER_LOAD); __sp804_clocksource_and_sched_clock_init()
104 writel(0xffffffff, base + TIMER_VALUE); __sp804_clocksource_and_sched_clock_init()
106 base + TIMER_CTRL); __sp804_clocksource_and_sched_clock_init()
108 clocksource_mmio_init(base + TIMER_VALUE, name, __sp804_clocksource_and_sched_clock_init()
112 sched_clock_base = base; __sp804_clocksource_and_sched_clock_init()
189 void __init __sp804_clockevents_init(void __iomem *base, unsigned int irq, struct clk *clk, const char *name) __sp804_clockevents_init() argument
206 clkevt_base = base; __sp804_clockevents_init()
212 writel(0, base + TIMER_CTRL); __sp804_clockevents_init()
221 void __iomem *base; sp804_of_init() local
227 base = of_iomap(np, 0); sp804_of_init()
228 if (WARN_ON(!base)) sp804_of_init()
232 writel(0, base + TIMER_CTRL); sp804_of_init()
233 writel(0, base + TIMER_2_BASE + TIMER_CTRL); sp804_of_init()
259 __sp804_clockevents_init(base + TIMER_2_BASE, irq, clk2, name); sp804_of_init()
260 __sp804_clocksource_and_sched_clock_init(base, name, clk1, 1); sp804_of_init()
262 __sp804_clockevents_init(base, irq, clk1 , name); sp804_of_init()
263 __sp804_clocksource_and_sched_clock_init(base + TIMER_2_BASE, sp804_of_init()
270 iounmap(base); sp804_of_init()
277 void __iomem *base; integrator_cp_of_init() local
282 base = of_iomap(np, 0); integrator_cp_of_init()
283 if (WARN_ON(!base)) integrator_cp_of_init()
290 writel(0, base + TIMER_CTRL); integrator_cp_of_init()
296 __sp804_clocksource_and_sched_clock_init(base, name, clk, 0); integrator_cp_of_init()
302 __sp804_clockevents_init(base, irq, clk, name); integrator_cp_of_init()
308 iounmap(base); integrator_cp_of_init()
|
| /linux-4.4.14/arch/x86/mm/ |
| H A D | amdtopology.c | 99 u64 base, limit; amd_numa_init() local
101 base = read_pci_config(0, nb, 1, 0x40 + i*8); amd_numa_init()
105 if ((base & 3) == 0) { amd_numa_init()
112 base, limit); amd_numa_init()
117 pr_info("Skipping node entry %d (base %Lx)\n", amd_numa_init()
118 i, base); amd_numa_init()
121 if ((base >> 8) & 3 || (limit >> 8) & 3) { amd_numa_init()
123 nodeid, (base >> 8) & 3, (limit >> 8) & 3); amd_numa_init()
138 if (limit <= base) amd_numa_init()
141 base >>= 16; amd_numa_init()
142 base <<= 24; amd_numa_init()
144 if (base < start) amd_numa_init()
145 base = start; amd_numa_init()
148 if (limit == base) { amd_numa_init()
152 if (limit < base) { amd_numa_init()
154 nodeid, base, limit); amd_numa_init()
159 if (prevbase > base) { amd_numa_init()
161 prevbase, base); amd_numa_init()
166 nodeid, base, limit); amd_numa_init()
168 prevbase = base; amd_numa_init()
169 numa_add_memblk(nodeid, base, limit); amd_numa_init()
|
| /linux-4.4.14/drivers/block/ |
| H A D | swim.c | 66 #define swim_write(base, reg, v) out_8(&(base)->write_##reg, (v))
67 #define swim_read(base, reg) in_8(&(base)->read_##reg)
90 #define iwm_write(base, reg, v) out_8(&(base)->reg, (v))
91 #define iwm_read(base, reg) in_8(&(base)->reg)
212 struct swim __iomem *base; member in struct:swim_priv
219 extern int swim_read_sector_header(struct swim __iomem *base,
221 extern int swim_read_sector_data(struct swim __iomem *base,
225 static inline void set_swim_mode(struct swim __iomem *base, int enable) set_swim_mode() argument
231 swim_write(base, mode0, 0xf8); set_swim_mode()
235 iwm_base = (struct iwm __iomem *)base; set_swim_mode()
250 static inline int get_swim_mode(struct swim __iomem *base) get_swim_mode() argument
256 swim_write(base, phase, 0xf5); get_swim_mode()
257 if (swim_read(base, phase) != 0xf5) get_swim_mode()
259 swim_write(base, phase, 0xf6); get_swim_mode()
260 if (swim_read(base, phase) != 0xf6) get_swim_mode()
262 swim_write(base, phase, 0xf7); get_swim_mode()
263 if (swim_read(base, phase) != 0xf7) get_swim_mode()
272 static inline void swim_select(struct swim __iomem *base, int sel) swim_select() argument
274 swim_write(base, phase, RELAX); swim_select()
278 swim_write(base, phase, sel & CA_MASK); swim_select()
281 static inline void swim_action(struct swim __iomem *base, int action) swim_action() argument
287 swim_select(base, action); swim_action()
289 swim_write(base, phase, (LSTRB<<4) | LSTRB); swim_action()
291 swim_write(base, phase, (LSTRB<<4) | ((~LSTRB) & 0x0F)); swim_action()
297 static inline int swim_readbit(struct swim __iomem *base, int bit) swim_readbit() argument
301 swim_select(base, bit); swim_readbit()
305 stat = swim_read(base, handshake); swim_readbit()
310 static inline void swim_drive(struct swim __iomem *base, swim_drive() argument
314 swim_write(base, mode0, EXTERNAL_DRIVE); /* clear drive 1 bit */ swim_drive()
315 swim_write(base, mode1, INTERNAL_DRIVE); /* set drive 0 bit */ swim_drive()
317 swim_write(base, mode0, INTERNAL_DRIVE); /* clear drive 0 bit */ swim_drive()
318 swim_write(base, mode1, EXTERNAL_DRIVE); /* set drive 1 bit */ swim_drive()
322 static inline void swim_motor(struct swim __iomem *base, swim_motor() argument
328 swim_action(base, MOTOR_ON); swim_motor()
331 swim_select(base, RELAX); swim_motor()
332 if (swim_readbit(base, MOTOR_ON)) swim_motor()
338 swim_action(base, MOTOR_OFF); swim_motor()
339 swim_select(base, RELAX); swim_motor()
343 static inline void swim_eject(struct swim __iomem *base) swim_eject() argument
347 swim_action(base, EJECT); swim_eject()
350 swim_select(base, RELAX); swim_eject()
351 if (!swim_readbit(base, DISK_IN)) swim_eject()
356 swim_select(base, RELAX); swim_eject()
359 static inline void swim_head(struct swim __iomem *base, enum head head) swim_head() argument
364 swim_select(base, READ_DATA_1); swim_head()
366 swim_select(base, READ_DATA_0); swim_head()
369 static inline int swim_step(struct swim __iomem *base) swim_step() argument
373 swim_action(base, STEP); swim_step()
380 swim_select(base, RELAX); swim_step()
381 if (!swim_readbit(base, STEP)) swim_step()
387 static inline int swim_track00(struct swim __iomem *base) swim_track00() argument
391 swim_action(base, SEEK_NEGATIVE); swim_track00()
395 swim_select(base, RELAX); swim_track00()
396 if (swim_readbit(base, TRACK_ZERO)) swim_track00()
399 if (swim_step(base)) swim_track00()
403 if (swim_readbit(base, TRACK_ZERO)) swim_track00()
409 static inline int swim_seek(struct swim __iomem *base, int step) swim_seek() argument
415 swim_action(base, SEEK_NEGATIVE); swim_seek()
418 swim_action(base, SEEK_POSITIVE); swim_seek()
421 if (swim_step(base)) swim_seek()
430 struct swim __iomem *base = fs->swd->base; swim_track() local
433 ret = swim_seek(base, track - fs->track); swim_track()
438 swim_track00(base); swim_track()
447 struct swim __iomem *base = fs->swd->base; floppy_eject() local
449 swim_drive(base, fs->location); floppy_eject()
450 swim_motor(base, OFF); floppy_eject()
451 swim_eject(base); floppy_eject()
463 struct swim __iomem *base = fs->swd->base; swim_read_sector() local
471 swim_write(base, mode1, MOTON); swim_read_sector()
472 swim_head(base, side); swim_read_sector()
473 swim_write(base, mode0, side); swim_read_sector()
477 ret = swim_read_sector_header(base, &header); swim_read_sector()
481 ret = swim_read_sector_data(base, buffer); swim_read_sector()
487 swim_write(base, mode0, MOTON); swim_read_sector()
500 struct swim __iomem *base = fs->swd->base; floppy_read_sectors() local
506 swim_drive(base, fs->location); floppy_read_sectors()
593 struct swim __iomem *base = fs->swd->base; setup_medium() local
595 if (swim_readbit(base, DISK_IN)) { setup_medium()
598 fs->write_protected = swim_readbit(base, WRITE_PROT); setup_medium()
599 fs->type = swim_readbit(base, ONEMEG_MEDIA); setup_medium()
601 if (swim_track00(base)) setup_medium()
605 swim_track00(base); setup_medium()
620 struct swim __iomem *base = fs->swd->base; floppy_open() local
631 swim_write(base, setup, S_IBM_DRIVE | S_FCLK_DIV2); floppy_open()
633 swim_drive(base, INTERNAL_DRIVE); floppy_open()
634 swim_motor(base, ON); floppy_open()
635 swim_action(base, SETMFM); floppy_open()
661 swim_motor(base, OFF); floppy_open()
679 struct swim __iomem *base = fs->swd->base; floppy_release() local
688 swim_motor(base, OFF); floppy_release()
752 struct swim __iomem *base = fs->swd->base; floppy_revalidate() local
754 swim_drive(base, fs->location); floppy_revalidate()
760 swim_motor(base, OFF); floppy_revalidate()
792 struct swim __iomem *base = swd->base; swim_add_floppy() local
796 swim_drive(base, location); swim_add_floppy()
798 swim_motor(base, OFF); swim_add_floppy()
800 if (swim_readbit(base, SINGLE_SIDED)) swim_add_floppy()
816 struct swim __iomem *base = swd->base; swim_floppy_init() local
820 swim_drive(base, INTERNAL_DRIVE); swim_floppy_init()
821 if (swim_readbit(base, DRIVE_PRESENT)) swim_floppy_init()
823 swim_drive(base, EXTERNAL_DRIVE); swim_floppy_init()
824 if (swim_readbit(base, DRIVE_PRESENT)) swim_floppy_init()
918 swd->base = swim_base; swim_probe()
958 iounmap(swd->base); swim_remove()
|
| /linux-4.4.14/drivers/gpu/drm/msm/edp/ |
| H A D | edp_phy.c | 20 void __iomem *base; member in struct:edp_phy
29 status = edp_read(phy->base + msm_edp_phy_ready()
49 edp_write(phy->base + REG_EDP_PHY_CTRL, msm_edp_phy_ctrl()
54 edp_write(phy->base + REG_EDP_PHY_CTRL, 0x000); msm_edp_phy_ctrl()
55 edp_write(phy->base + REG_EDP_PHY_GLB_PD_CTL, 0x3f); msm_edp_phy_ctrl()
56 edp_write(phy->base + REG_EDP_PHY_GLB_CFG, 0x1); msm_edp_phy_ctrl()
58 edp_write(phy->base + REG_EDP_PHY_GLB_PD_CTL, 0xc0); msm_edp_phy_ctrl()
65 edp_write(phy->base + REG_EDP_PHY_GLB_VM_CFG0, 0x3); msm_edp_phy_vm_pe_init()
66 edp_write(phy->base + REG_EDP_PHY_GLB_VM_CFG1, 0x64); msm_edp_phy_vm_pe_init()
67 edp_write(phy->base + REG_EDP_PHY_GLB_MISC9, 0x6c); msm_edp_phy_vm_pe_init()
72 edp_write(phy->base + REG_EDP_PHY_GLB_VM_CFG0, v0); msm_edp_phy_vm_pe_cfg()
73 edp_write(phy->base + REG_EDP_PHY_GLB_VM_CFG1, v1); msm_edp_phy_vm_pe_cfg()
87 edp_write(phy->base + REG_EDP_PHY_LN_PD_CTL(i) , data); msm_edp_phy_lane_power_ctrl()
92 edp_write(phy->base + REG_EDP_PHY_LN_PD_CTL(i) , data); msm_edp_phy_lane_power_ctrl()
103 phy->base = regbase; msm_edp_phy_init()
|
| /linux-4.4.14/drivers/ata/ |
| H A D | pata_bf54x.c | 77 #define ATAPI_GET_CONTROL(base)\
78 bfin_read16(base + ATAPI_OFFSET_CONTROL)
79 #define ATAPI_SET_CONTROL(base, val)\
80 bfin_write16(base + ATAPI_OFFSET_CONTROL, val)
81 #define ATAPI_GET_STATUS(base)\
82 bfin_read16(base + ATAPI_OFFSET_STATUS)
83 #define ATAPI_GET_DEV_ADDR(base)\
84 bfin_read16(base + ATAPI_OFFSET_DEV_ADDR)
85 #define ATAPI_SET_DEV_ADDR(base, val)\
86 bfin_write16(base + ATAPI_OFFSET_DEV_ADDR, val)
87 #define ATAPI_GET_DEV_TXBUF(base)\
88 bfin_read16(base + ATAPI_OFFSET_DEV_TXBUF)
89 #define ATAPI_SET_DEV_TXBUF(base, val)\
90 bfin_write16(base + ATAPI_OFFSET_DEV_TXBUF, val)
91 #define ATAPI_GET_DEV_RXBUF(base)\
92 bfin_read16(base + ATAPI_OFFSET_DEV_RXBUF)
93 #define ATAPI_SET_DEV_RXBUF(base, val)\
94 bfin_write16(base + ATAPI_OFFSET_DEV_RXBUF, val)
95 #define ATAPI_GET_INT_MASK(base)\
96 bfin_read16(base + ATAPI_OFFSET_INT_MASK)
97 #define ATAPI_SET_INT_MASK(base, val)\
98 bfin_write16(base + ATAPI_OFFSET_INT_MASK, val)
99 #define ATAPI_GET_INT_STATUS(base)\
100 bfin_read16(base + ATAPI_OFFSET_INT_STATUS)
101 #define ATAPI_SET_INT_STATUS(base, val)\
102 bfin_write16(base + ATAPI_OFFSET_INT_STATUS, val)
103 #define ATAPI_GET_XFER_LEN(base)\
104 bfin_read16(base + ATAPI_OFFSET_XFER_LEN)
105 #define ATAPI_SET_XFER_LEN(base, val)\
106 bfin_write16(base + ATAPI_OFFSET_XFER_LEN, val)
107 #define ATAPI_GET_LINE_STATUS(base)\
108 bfin_read16(base + ATAPI_OFFSET_LINE_STATUS)
109 #define ATAPI_GET_SM_STATE(base)\
110 bfin_read16(base + ATAPI_OFFSET_SM_STATE)
111 #define ATAPI_GET_TERMINATE(base)\
112 bfin_read16(base + ATAPI_OFFSET_TERMINATE)
113 #define ATAPI_SET_TERMINATE(base, val)\
114 bfin_write16(base + ATAPI_OFFSET_TERMINATE, val)
115 #define ATAPI_GET_PIO_TFRCNT(base)\
116 bfin_read16(base + ATAPI_OFFSET_PIO_TFRCNT)
117 #define ATAPI_GET_DMA_TFRCNT(base)\
118 bfin_read16(base + ATAPI_OFFSET_DMA_TFRCNT)
119 #define ATAPI_GET_UMAIN_TFRCNT(base)\
120 bfin_read16(base + ATAPI_OFFSET_UMAIN_TFRCNT)
121 #define ATAPI_GET_UDMAOUT_TFRCNT(base)\
122 bfin_read16(base + ATAPI_OFFSET_UDMAOUT_TFRCNT)
123 #define ATAPI_GET_REG_TIM_0(base)\
124 bfin_read16(base + ATAPI_OFFSET_REG_TIM_0)
125 #define ATAPI_SET_REG_TIM_0(base, val)\
126 bfin_write16(base + ATAPI_OFFSET_REG_TIM_0, val)
127 #define ATAPI_GET_PIO_TIM_0(base)\
128 bfin_read16(base + ATAPI_OFFSET_PIO_TIM_0)
129 #define ATAPI_SET_PIO_TIM_0(base, val)\
130 bfin_write16(base + ATAPI_OFFSET_PIO_TIM_0, val)
131 #define ATAPI_GET_PIO_TIM_1(base)\
132 bfin_read16(base + ATAPI_OFFSET_PIO_TIM_1)
133 #define ATAPI_SET_PIO_TIM_1(base, val)\
134 bfin_write16(base + ATAPI_OFFSET_PIO_TIM_1, val)
135 #define ATAPI_GET_MULTI_TIM_0(base)\
136 bfin_read16(base + ATAPI_OFFSET_MULTI_TIM_0)
137 #define ATAPI_SET_MULTI_TIM_0(base, val)\
138 bfin_write16(base + ATAPI_OFFSET_MULTI_TIM_0, val)
139 #define ATAPI_GET_MULTI_TIM_1(base)\
140 bfin_read16(base + ATAPI_OFFSET_MULTI_TIM_1)
141 #define ATAPI_SET_MULTI_TIM_1(base, val)\
142 bfin_write16(base + ATAPI_OFFSET_MULTI_TIM_1, val)
143 #define ATAPI_GET_MULTI_TIM_2(base)\
144 bfin_read16(base + ATAPI_OFFSET_MULTI_TIM_2)
145 #define ATAPI_SET_MULTI_TIM_2(base, val)\
146 bfin_write16(base + ATAPI_OFFSET_MULTI_TIM_2, val)
147 #define ATAPI_GET_ULTRA_TIM_0(base)\
148 bfin_read16(base + ATAPI_OFFSET_ULTRA_TIM_0)
149 #define ATAPI_SET_ULTRA_TIM_0(base, val)\
150 bfin_write16(base + ATAPI_OFFSET_ULTRA_TIM_0, val)
151 #define ATAPI_GET_ULTRA_TIM_1(base)\
152 bfin_read16(base + ATAPI_OFFSET_ULTRA_TIM_1)
153 #define ATAPI_SET_ULTRA_TIM_1(base, val)\
154 bfin_write16(base + ATAPI_OFFSET_ULTRA_TIM_1, val)
155 #define ATAPI_GET_ULTRA_TIM_2(base)\
156 bfin_read16(base + ATAPI_OFFSET_ULTRA_TIM_2)
157 #define ATAPI_SET_ULTRA_TIM_2(base, val)\
158 bfin_write16(base + ATAPI_OFFSET_ULTRA_TIM_2, val)
159 #define ATAPI_GET_ULTRA_TIM_3(base)\
160 bfin_read16(base + ATAPI_OFFSET_ULTRA_TIM_3)
161 #define ATAPI_SET_ULTRA_TIM_3(base, val)\
162 bfin_write16(base + ATAPI_OFFSET_ULTRA_TIM_3, val)
292 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr; bfin_set_piomode() local
339 ATAPI_SET_REG_TIM_0(base, (teoc_reg<<8 | t2_reg)); bfin_set_piomode()
340 ATAPI_SET_PIO_TIM_0(base, (t4_reg<<12 | t2_pio<<4 | t1_reg)); bfin_set_piomode()
341 ATAPI_SET_PIO_TIM_1(base, teoc_pio); bfin_set_piomode()
343 ATAPI_SET_CONTROL(base, bfin_set_piomode()
344 ATAPI_GET_CONTROL(base) | IORDY_EN); bfin_set_piomode()
346 ATAPI_SET_CONTROL(base, bfin_set_piomode()
347 ATAPI_GET_CONTROL(base) & ~IORDY_EN); bfin_set_piomode()
351 ATAPI_SET_INT_MASK(base, ATAPI_GET_INT_MASK(base) bfin_set_piomode()
371 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr; bfin_set_dmamode() local
418 ATAPI_SET_ULTRA_TIM_0(base, (tenv<<8 | tack)); bfin_set_dmamode()
419 ATAPI_SET_ULTRA_TIM_1(base, bfin_set_dmamode()
421 ATAPI_SET_ULTRA_TIM_2(base, (tmli<<8 | tss)); bfin_set_dmamode()
422 ATAPI_SET_ULTRA_TIM_3(base, (trp<<8 | tzah)); bfin_set_dmamode()
464 ATAPI_SET_MULTI_TIM_0(base, (tm<<8 | td)); bfin_set_dmamode()
465 ATAPI_SET_MULTI_TIM_1(base, (tkr<<8 | tkw)); bfin_set_dmamode()
466 ATAPI_SET_MULTI_TIM_2(base, (teoc<<8 | th)); bfin_set_dmamode()
480 static inline void wait_complete(void __iomem *base, unsigned short mask) wait_complete() argument
488 status = ATAPI_GET_INT_STATUS(base) & mask; wait_complete()
493 ATAPI_SET_INT_STATUS(base, mask); wait_complete()
504 static void write_atapi_register(void __iomem *base, write_atapi_register() argument
510 ATAPI_SET_DEV_TXBUF(base, value); write_atapi_register()
515 ATAPI_SET_DEV_ADDR(base, ata_reg); write_atapi_register()
519 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) | XFER_DIR)); write_atapi_register()
522 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) & ~PIO_USE_DMA)); write_atapi_register()
525 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) | PIO_START)); write_atapi_register()
530 wait_complete(base, PIO_DONE_INT); write_atapi_register()
541 static unsigned short read_atapi_register(void __iomem *base, read_atapi_register() argument
547 ATAPI_SET_DEV_ADDR(base, ata_reg); read_atapi_register()
551 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) & ~XFER_DIR)); read_atapi_register()
554 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) & ~PIO_USE_DMA)); read_atapi_register()
557 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) | PIO_START)); read_atapi_register()
563 wait_complete(base, PIO_DONE_INT); read_atapi_register()
568 return ATAPI_GET_DEV_RXBUF(base); read_atapi_register()
579 static void write_atapi_data(void __iomem *base, write_atapi_data() argument
585 ATAPI_SET_XFER_LEN(base, 1); write_atapi_data()
590 ATAPI_SET_DEV_ADDR(base, ATA_REG_DATA); write_atapi_data()
594 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) | XFER_DIR)); write_atapi_data()
597 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) & ~PIO_USE_DMA)); write_atapi_data()
603 ATAPI_SET_DEV_TXBUF(base, buf[i]); write_atapi_data()
606 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) | PIO_START)); write_atapi_data()
612 wait_complete(base, PIO_DONE_INT); write_atapi_data()
624 static void read_atapi_data(void __iomem *base, read_atapi_data() argument
630 ATAPI_SET_XFER_LEN(base, 1); read_atapi_data()
635 ATAPI_SET_DEV_ADDR(base, ATA_REG_DATA); read_atapi_data()
639 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) & ~XFER_DIR)); read_atapi_data()
642 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) & ~PIO_USE_DMA)); read_atapi_data()
646 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) | PIO_START)); read_atapi_data()
652 wait_complete(base, PIO_DONE_INT); read_atapi_data()
657 buf[i] = ATAPI_GET_DEV_RXBUF(base); read_atapi_data()
671 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr; bfin_tf_load() local
675 write_atapi_register(base, ATA_REG_CTRL, tf->ctl); bfin_tf_load()
682 write_atapi_register(base, ATA_REG_FEATURE, bfin_tf_load()
684 write_atapi_register(base, ATA_REG_NSECT, bfin_tf_load()
686 write_atapi_register(base, ATA_REG_LBAL, tf->hob_lbal); bfin_tf_load()
687 write_atapi_register(base, ATA_REG_LBAM, tf->hob_lbam); bfin_tf_load()
688 write_atapi_register(base, ATA_REG_LBAH, tf->hob_lbah); bfin_tf_load()
698 write_atapi_register(base, ATA_REG_FEATURE, tf->feature); bfin_tf_load()
699 write_atapi_register(base, ATA_REG_NSECT, tf->nsect); bfin_tf_load()
700 write_atapi_register(base, ATA_REG_LBAL, tf->lbal); bfin_tf_load()
701 write_atapi_register(base, ATA_REG_LBAM, tf->lbam); bfin_tf_load()
702 write_atapi_register(base, ATA_REG_LBAH, tf->lbah); bfin_tf_load()
712 write_atapi_register(base, ATA_REG_DEVICE, tf->device); bfin_tf_load()
728 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr; bfin_check_status() local
729 return read_atapi_register(base, ATA_REG_STATUS); bfin_check_status()
742 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr; bfin_tf_read() local
745 tf->feature = read_atapi_register(base, ATA_REG_ERR); bfin_tf_read()
746 tf->nsect = read_atapi_register(base, ATA_REG_NSECT); bfin_tf_read()
747 tf->lbal = read_atapi_register(base, ATA_REG_LBAL); bfin_tf_read()
748 tf->lbam = read_atapi_register(base, ATA_REG_LBAM); bfin_tf_read()
749 tf->lbah = read_atapi_register(base, ATA_REG_LBAH); bfin_tf_read()
750 tf->device = read_atapi_register(base, ATA_REG_DEVICE); bfin_tf_read()
753 write_atapi_register(base, ATA_REG_CTRL, tf->ctl | ATA_HOB); bfin_tf_read()
754 tf->hob_feature = read_atapi_register(base, ATA_REG_ERR); bfin_tf_read()
755 tf->hob_nsect = read_atapi_register(base, ATA_REG_NSECT); bfin_tf_read()
756 tf->hob_lbal = read_atapi_register(base, ATA_REG_LBAL); bfin_tf_read()
757 tf->hob_lbam = read_atapi_register(base, ATA_REG_LBAM); bfin_tf_read()
758 tf->hob_lbah = read_atapi_register(base, ATA_REG_LBAH); bfin_tf_read()
773 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr; bfin_exec_command() local
776 write_atapi_register(base, ATA_REG_CMD, tf->command); bfin_exec_command()
787 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr; bfin_check_altstatus() local
788 return read_atapi_register(base, ATA_REG_ALTSTATUS); bfin_check_altstatus()
801 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr; bfin_dev_select() local
809 write_atapi_register(base, ATA_REG_DEVICE, tmp); bfin_dev_select()
821 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr; bfin_set_devctl() local
822 write_atapi_register(base, ATA_REG_CTRL, ctl); bfin_set_devctl()
836 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr; bfin_bmdma_setup() local
886 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) bfin_bmdma_setup()
890 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) bfin_bmdma_setup()
895 ATAPI_SET_CONTROL(base, ATAPI_GET_CONTROL(base) | TFRCNT_RST); bfin_bmdma_setup()
898 ATAPI_SET_CONTROL(base, ATAPI_GET_CONTROL(base) | END_ON_TERM); bfin_bmdma_setup()
901 ATAPI_SET_XFER_LEN(base, size >> 1); bfin_bmdma_setup()
914 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr; bfin_bmdma_start() local
923 ATAPI_SET_CONTROL(base, ATAPI_GET_CONTROL(base) bfin_bmdma_start()
926 ATAPI_SET_CONTROL(base, ATAPI_GET_CONTROL(base) bfin_bmdma_start()
968 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr; bfin_devchk() local
973 write_atapi_register(base, ATA_REG_NSECT, 0x55); bfin_devchk()
974 write_atapi_register(base, ATA_REG_LBAL, 0xaa); bfin_devchk()
976 write_atapi_register(base, ATA_REG_NSECT, 0xaa); bfin_devchk()
977 write_atapi_register(base, ATA_REG_LBAL, 0x55); bfin_devchk()
979 write_atapi_register(base, ATA_REG_NSECT, 0x55); bfin_devchk()
980 write_atapi_register(base, ATA_REG_LBAL, 0xaa); bfin_devchk()
982 nsect = read_atapi_register(base, ATA_REG_NSECT); bfin_devchk()
983 lbal = read_atapi_register(base, ATA_REG_LBAL); bfin_devchk()
999 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr; bfin_bus_post_reset() local
1018 nsect = read_atapi_register(base, ATA_REG_NSECT); bfin_bus_post_reset()
1019 lbal = read_atapi_register(base, ATA_REG_LBAL); bfin_bus_post_reset()
1048 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr; bfin_bus_softreset() local
1051 write_atapi_register(base, ATA_REG_CTRL, ap->ctl); bfin_bus_softreset()
1053 write_atapi_register(base, ATA_REG_CTRL, ap->ctl | ATA_SRST); bfin_bus_softreset()
1055 write_atapi_register(base, ATA_REG_CTRL, ap->ctl); bfin_bus_softreset()
1132 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr; bfin_bmdma_status() local
1134 if (ATAPI_GET_STATUS(base) & (MULTI_XFER_ON | ULTRA_XFER_ON)) bfin_bmdma_status()
1136 if (ATAPI_GET_INT_STATUS(base) & ATAPI_DEV_INT) bfin_bmdma_status()
1158 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr; bfin_data_xfer() local
1164 read_atapi_data(base, words, buf16); bfin_data_xfer()
1166 write_atapi_data(base, words, buf16); bfin_data_xfer()
1174 read_atapi_data(base, 1, align_buf); bfin_data_xfer()
1178 write_atapi_data(base, 1, align_buf); bfin_data_xfer()
1195 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr; bfin_irq_clear() local
1198 ATAPI_SET_INT_STATUS(base, ATAPI_GET_INT_STATUS(base)|ATAPI_DEV_INT bfin_irq_clear()
1228 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr; bfin_postreset() local
1245 write_atapi_register(base, ATA_REG_CTRL, ap->ctl); bfin_postreset()
1464 void __iomem *base = (void __iomem *)host->ports[0]->ioaddr.ctl_addr; bfin_reset_controller() local
1469 ATAPI_SET_INT_MASK(base, 0); bfin_reset_controller()
1473 ATAPI_SET_CONTROL(base, ATAPI_GET_CONTROL(base) | DEV_RST); bfin_reset_controller()
1477 ATAPI_SET_CONTROL(base, ATAPI_GET_CONTROL(base) & ~DEV_RST); bfin_reset_controller()
1483 status = read_atapi_register(base, ATA_REG_STATUS); bfin_reset_controller()
1487 ATAPI_SET_INT_MASK(base, 1); bfin_reset_controller()
1560 * Get the register base first bfin_atapi_probe()
|
| /linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/subdev/volt/ |
| H A D | gk20a.c | 22 #define gk20a_volt(p) container_of((p), struct gk20a_volt, base)
37 struct nvkm_volt base; member in struct:gk20a_volt
104 gk20a_volt_vid_get(struct nvkm_volt *base) gk20a_volt_vid_get() argument
106 struct gk20a_volt *volt = gk20a_volt(base); gk20a_volt_vid_get()
111 for (i = 0; i < volt->base.vid_nr; i++) gk20a_volt_vid_get()
112 if (volt->base.vid[i].uv >= uv) gk20a_volt_vid_get()
119 gk20a_volt_vid_set(struct nvkm_volt *base, u8 vid) gk20a_volt_vid_set() argument
121 struct gk20a_volt *volt = gk20a_volt(base); gk20a_volt_vid_set()
122 struct nvkm_subdev *subdev = &volt->base.subdev; gk20a_volt_vid_set()
124 nvkm_debug(subdev, "set voltage as %duv\n", volt->base.vid[vid].uv); gk20a_volt_vid_set()
125 return regulator_set_voltage(volt->vdd, volt->base.vid[vid].uv, 1200000); gk20a_volt_vid_set()
129 gk20a_volt_set_id(struct nvkm_volt *base, u8 id, int condition) gk20a_volt_set_id() argument
131 struct gk20a_volt *volt = gk20a_volt(base); gk20a_volt_set_id()
132 struct nvkm_subdev *subdev = &volt->base.subdev; gk20a_volt_set_id()
134 int target_uv = volt->base.vid[id].uv; gk20a_volt_set_id()
142 ret = gk20a_volt_vid_set(&volt->base, volt->base.vid[id].vid); gk20a_volt_set_id()
167 nvkm_volt_ctor(&gk20a_volt, device, index, &volt->base); gk20a_volt_new()
168 *pvolt = &volt->base; gk20a_volt_new()
171 nvkm_info(&volt->base.subdev, "The default voltage is %duV\n", uv); gk20a_volt_new()
175 volt->base.vid_nr = ARRAY_SIZE(gk20a_cvb_coef); gk20a_volt_new()
176 nvkm_debug(&volt->base.subdev, "%s - vid_nr = %d\n", __func__, gk20a_volt_new()
177 volt->base.vid_nr); gk20a_volt_new()
178 for (i = 0; i < volt->base.vid_nr; i++) { gk20a_volt_new()
179 volt->base.vid[i].vid = i; gk20a_volt_new()
180 volt->base.vid[i].uv = gk20a_volt_new()
183 nvkm_debug(&volt->base.subdev, "%2d: vid=%d, uv=%d\n", i, gk20a_volt_new()
184 volt->base.vid[i].vid, volt->base.vid[i].uv); gk20a_volt_new()
|
| H A D | gk104.c | 31 #define gk104_volt(p) container_of((p), struct gk104_volt, base)
33 struct nvkm_volt base; member in struct:gk104_volt
38 gk104_volt_get(struct nvkm_volt *base) gk104_volt_get() argument
40 struct nvbios_volt *bios = &gk104_volt(base)->bios; gk104_volt_get()
41 struct nvkm_device *device = base->subdev.device; gk104_volt_get()
47 return bios->base + bios->pwm_range * duty / div; gk104_volt_get()
51 gk104_volt_set(struct nvkm_volt *base, u32 uv) gk104_volt_set() argument
53 struct nvbios_volt *bios = &gk104_volt(base)->bios; gk104_volt_set()
54 struct nvkm_device *device = base->subdev.device; gk104_volt_set()
59 duty = (uv - bios->base) * div / bios->pwm_range; gk104_volt_set()
96 nvkm_volt_ctor(volt_func, device, index, &volt->base); gk104_volt_new()
97 *pvolt = &volt->base; gk104_volt_new()
105 nvkm_error(&volt->base.subdev, gk104_volt_new()
111 nvkm_voltgpio_init(&volt->base); gk104_volt_new()
116 nvkm_debug(&volt->base.subdev, "Using %s mode\n", mode); gk104_volt_new()
|
| /linux-4.4.14/drivers/iommu/ |
| H A D | msm_iommu.c | 119 SET_CTX_TLBIALL(iommu_drvdata->base, ctx_drvdata->num, 0); __flush_iotlb()
126 static void __reset_context(void __iomem *base, int ctx) __reset_context() argument
128 SET_BPRCOSH(base, ctx, 0); __reset_context()
129 SET_BPRCISH(base, ctx, 0); __reset_context()
130 SET_BPRCNSH(base, ctx, 0); __reset_context()
131 SET_BPSHCFG(base, ctx, 0); __reset_context()
132 SET_BPMTCFG(base, ctx, 0); __reset_context()
133 SET_ACTLR(base, ctx, 0); __reset_context()
134 SET_SCTLR(base, ctx, 0); __reset_context()
135 SET_FSRRESTORE(base, ctx, 0); __reset_context()
136 SET_TTBR0(base, ctx, 0); __reset_context()
137 SET_TTBR1(base, ctx, 0); __reset_context()
138 SET_TTBCR(base, ctx, 0); __reset_context()
139 SET_BFBCR(base, ctx, 0); __reset_context()
140 SET_PAR(base, ctx, 0); __reset_context()
141 SET_FAR(base, ctx, 0); __reset_context()
142 SET_CTX_TLBIALL(base, ctx, 0); __reset_context()
143 SET_TLBFLPTER(base, ctx, 0); __reset_context()
144 SET_TLBSLPTER(base, ctx, 0); __reset_context()
145 SET_TLBLKCR(base, ctx, 0); __reset_context()
146 SET_PRRR(base, ctx, 0); __reset_context()
147 SET_NMRR(base, ctx, 0); __reset_context()
150 static void __program_context(void __iomem *base, int ctx, phys_addr_t pgtable) __program_context() argument
153 __reset_context(base, ctx); __program_context()
157 SET_TLBMCFG(base, ctx, 0x3); __program_context()
160 SET_V2PCFG(base, ctx, 0x3); __program_context()
162 SET_TTBCR(base, ctx, 0); __program_context()
163 SET_TTBR0_PA(base, ctx, (pgtable >> 14)); __program_context()
166 SET_CTX_TLBIALL(base, ctx, 0); __program_context()
169 SET_IRPTNDX(base, ctx, 0); __program_context()
172 SET_CFEIE(base, ctx, 1); __program_context()
175 SET_CFCFG(base, ctx, 1); __program_context()
178 SET_RCISH(base, ctx, 1); __program_context()
179 SET_RCOSH(base, ctx, 1); __program_context()
180 SET_RCNSH(base, ctx, 1); __program_context()
183 SET_TRE(base, ctx, 1); __program_context()
188 SET_PRRR(base, ctx, prrr); __program_context()
189 SET_NMRR(base, ctx, nmrr); __program_context()
192 SET_BFBDFE(base, ctx, 1); __program_context()
198 SET_TTBR0_SH(base, ctx, 1); __program_context()
199 SET_TTBR1_SH(base, ctx, 1); __program_context()
201 SET_TTBR0_NOS(base, ctx, 1); __program_context()
202 SET_TTBR1_NOS(base, ctx, 1); __program_context()
204 SET_TTBR0_IRGNH(base, ctx, 0); /* WB, WA */ __program_context()
205 SET_TTBR0_IRGNL(base, ctx, 1); __program_context()
207 SET_TTBR1_IRGNH(base, ctx, 0); /* WB, WA */ __program_context()
208 SET_TTBR1_IRGNL(base, ctx, 1); __program_context()
210 SET_TTBR0_ORGN(base, ctx, 1); /* WB, WA */ __program_context()
211 SET_TTBR1_ORGN(base, ctx, 1); /* WB, WA */ __program_context()
215 SET_M(base, ctx, 1); __program_context()
316 __program_context(iommu_drvdata->base, ctx_dev->num, msm_iommu_attach_dev()
359 __reset_context(iommu_drvdata->base, ctx_dev->num); msm_iommu_detach_dev()
562 void __iomem *base; msm_iommu_iova_to_phys() local
576 base = iommu_drvdata->base; msm_iommu_iova_to_phys()
584 SET_CTX_TLBIALL(base, ctx, 0); msm_iommu_iova_to_phys()
585 SET_V2PPR(base, ctx, va & V2Pxx_VA); msm_iommu_iova_to_phys()
587 par = GET_PAR(base, ctx); msm_iommu_iova_to_phys()
590 if (GET_NOFAULT_SS(base, ctx)) msm_iommu_iova_to_phys()
595 if (GET_FAULT(base, ctx)) msm_iommu_iova_to_phys()
609 static void print_ctx_regs(void __iomem *base, int ctx) print_ctx_regs() argument
611 unsigned int fsr = GET_FSR(base, ctx); print_ctx_regs()
613 GET_FAR(base, ctx), GET_PAR(base, ctx)); print_ctx_regs()
627 GET_FSYNR0(base, ctx), GET_FSYNR1(base, ctx)); print_ctx_regs()
629 GET_TTBR0(base, ctx), GET_TTBR1(base, ctx)); print_ctx_regs()
631 GET_SCTLR(base, ctx), GET_ACTLR(base, ctx)); print_ctx_regs()
633 GET_PRRR(base, ctx), GET_NMRR(base, ctx)); print_ctx_regs()
639 void __iomem *base; msm_iommu_fault_handler() local
650 base = drvdata->base; msm_iommu_fault_handler()
653 pr_err("base = %08x\n", (unsigned int) base); msm_iommu_fault_handler()
660 fsr = GET_FSR(base, i); msm_iommu_fault_handler()
664 print_ctx_regs(base, i); msm_iommu_fault_handler()
665 SET_FSR(base, i, 0x4000000F); msm_iommu_fault_handler()
|
| H A D | msm_iommu_dev.c | 87 static void msm_iommu_reset(void __iomem *base, int ncb) msm_iommu_reset() argument
91 SET_RPUE(base, 0); msm_iommu_reset()
92 SET_RPUEIE(base, 0); msm_iommu_reset()
93 SET_ESRRESTORE(base, 0); msm_iommu_reset()
94 SET_TBE(base, 0); msm_iommu_reset()
95 SET_CR(base, 0); msm_iommu_reset()
96 SET_SPDMBE(base, 0); msm_iommu_reset()
97 SET_TESTBUSCR(base, 0); msm_iommu_reset()
98 SET_TLBRSW(base, 0); msm_iommu_reset()
99 SET_GLOBAL_TLBIALL(base, 0); msm_iommu_reset()
100 SET_RPU_ACR(base, 0); msm_iommu_reset()
101 SET_TLBLKCRWE(base, 1); msm_iommu_reset()
104 SET_BPRCOSH(base, ctx, 0); msm_iommu_reset()
105 SET_BPRCISH(base, ctx, 0); msm_iommu_reset()
106 SET_BPRCNSH(base, ctx, 0); msm_iommu_reset()
107 SET_BPSHCFG(base, ctx, 0); msm_iommu_reset()
108 SET_BPMTCFG(base, ctx, 0); msm_iommu_reset()
109 SET_ACTLR(base, ctx, 0); msm_iommu_reset()
110 SET_SCTLR(base, ctx, 0); msm_iommu_reset()
111 SET_FSRRESTORE(base, ctx, 0); msm_iommu_reset()
112 SET_TTBR0(base, ctx, 0); msm_iommu_reset()
113 SET_TTBR1(base, ctx, 0); msm_iommu_reset()
114 SET_TTBCR(base, ctx, 0); msm_iommu_reset()
115 SET_BFBCR(base, ctx, 0); msm_iommu_reset()
116 SET_PAR(base, ctx, 0); msm_iommu_reset()
117 SET_FAR(base, ctx, 0); msm_iommu_reset()
118 SET_CTX_TLBIALL(base, ctx, 0); msm_iommu_reset()
119 SET_TLBFLPTER(base, ctx, 0); msm_iommu_reset()
120 SET_TLBSLPTER(base, ctx, 0); msm_iommu_reset()
121 SET_TLBLKCR(base, ctx, 0); msm_iommu_reset()
122 SET_PRRR(base, ctx, 0); msm_iommu_reset()
123 SET_NMRR(base, ctx, 0); msm_iommu_reset()
124 SET_CONTEXTIDR(base, ctx, 0); msm_iommu_reset()
218 drvdata->base = regs_base; msm_iommu_probe()
306 SET_M2VCBR_N(drvdata->base, mid, 0); msm_iommu_ctx_probe()
307 SET_CBACR_N(drvdata->base, c->num, 0); msm_iommu_ctx_probe()
310 SET_VMID(drvdata->base, mid, 0); msm_iommu_ctx_probe()
313 SET_CBNDX(drvdata->base, mid, c->num); msm_iommu_ctx_probe()
316 SET_CBVMID(drvdata->base, c->num, 0); msm_iommu_ctx_probe()
319 SET_CONTEXTIDR_ASID(drvdata->base, c->num, c->num); msm_iommu_ctx_probe()
322 SET_NSCFG(drvdata->base, mid, 3); msm_iommu_ctx_probe()
|
| /linux-4.4.14/arch/arm/mach-mv78xx0/include/mach/ |
| H A D | uncompress.h | 16 unsigned char *base = SERIAL_BASE; putc() local
20 if (base[UART_LSR << 2] & UART_LSR_THRE) putc()
25 base[UART_TX << 2] = c; putc()
30 unsigned char *base = SERIAL_BASE; flush() local
37 if ((base[UART_LSR << 2] & mask) == mask) flush()
|
| /linux-4.4.14/arch/arm/mach-orion5x/include/mach/ |
| H A D | uncompress.h | 18 unsigned char *base = SERIAL_BASE; putc() local
22 if (base[UART_LSR << 2] & UART_LSR_THRE) putc()
27 base[UART_TX << 2] = c; putc()
32 unsigned char *base = SERIAL_BASE; flush() local
39 if ((base[UART_LSR << 2] & mask) == mask) flush()
|
| /linux-4.4.14/arch/arm/mach-ebsa110/include/mach/ |
| H A D | uncompress.h | 20 unsigned char v, *base = SERIAL_BASE; putc() local
23 v = base[UART_LSR << 2]; putc()
27 base[UART_TX << 2] = c; putc()
32 unsigned char v, *base = SERIAL_BASE; flush() local
35 v = base[UART_LSR << 2]; flush()
|
| H A D | entry-macro.S | 15 .macro get_irqnr_preamble, base, tmp
16 mov \base, #IRQ_STAT
19 .macro get_irqnr_and_base, irqnr, stat, base, tmp
20 ldrb \stat, [\base] @ get interrupts
|
| /linux-4.4.14/drivers/usb/host/ |
| H A D | xhci-mvebu.c | 21 static void xhci_mvebu_mbus_config(void __iomem *base, xhci_mvebu_mbus_config() argument
28 writel(0, base + USB3_WIN_CTRL(win)); xhci_mvebu_mbus_config()
29 writel(0, base + USB3_WIN_BASE(win)); xhci_mvebu_mbus_config()
38 base + USB3_WIN_CTRL(win)); xhci_mvebu_mbus_config()
40 writel((cs->base & 0xffff0000), base + USB3_WIN_BASE(win)); xhci_mvebu_mbus_config()
47 void __iomem *base; xhci_mvebu_mbus_init_quirk() local
58 base = ioremap(res->start, resource_size(res)); xhci_mvebu_mbus_init_quirk()
59 if (!base) xhci_mvebu_mbus_init_quirk()
63 xhci_mvebu_mbus_config(base, dram); xhci_mvebu_mbus_init_quirk()
69 iounmap(base); xhci_mvebu_mbus_init_quirk()
|
| /linux-4.4.14/arch/mips/ath79/ |
| H A D | early_printk.c | 38 void __iomem *base = (void __iomem *)(KSEG1ADDR(AR71XX_UART_BASE)); prom_putchar_ar71xx() local
40 prom_putchar_wait(base + UART_LSR * 4, BOTH_EMPTY, BOTH_EMPTY); prom_putchar_ar71xx()
41 __raw_writel(ch, base + UART_TX * 4); prom_putchar_ar71xx()
42 prom_putchar_wait(base + UART_LSR * 4, BOTH_EMPTY, BOTH_EMPTY); prom_putchar_ar71xx()
47 void __iomem *base = (void __iomem *)(KSEG1ADDR(AR933X_UART_BASE)); prom_putchar_ar933x() local
49 prom_putchar_wait(base + AR933X_UART_DATA_REG, AR933X_UART_DATA_TX_CSR, prom_putchar_ar933x()
51 __raw_writel(AR933X_UART_DATA_TX_CSR | ch, base + AR933X_UART_DATA_REG); prom_putchar_ar933x()
52 prom_putchar_wait(base + AR933X_UART_DATA_REG, AR933X_UART_DATA_TX_CSR, prom_putchar_ar933x()
63 void __iomem *base; prom_putchar_init() local
66 base = (void __iomem *)(KSEG1ADDR(AR71XX_RESET_BASE)); prom_putchar_init()
67 id = __raw_readl(base + AR71XX_RESET_REG_REV_ID); prom_putchar_init()
|
| /linux-4.4.14/drivers/watchdog/ |
| H A D | nv_tco.h | 34 #define TCO_RLD(base) ((base) + 0x00) /* TCO Timer Reload and Current Value */
35 #define TCO_TMR(base) ((base) + 0x01) /* TCO Timer Initial Value */
37 #define TCO_STS(base) ((base) + 0x04) /* TCO Status Register */
53 #define TCO_CNT(base) ((base) + 0x08) /* TCO Control Register */
60 * The SMI_EN register is at the base io address + 0x04,
63 #define MCP51_SMI_EN(base) ((base) - 0x40 + 0x04)
|
| H A D | omap_wdt.c | 65 void __iomem *base; /* physical */ member in struct:omap_wdt_dev
74 void __iomem *base = wdev->base; omap_wdt_reload() local
77 while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x08) omap_wdt_reload()
81 writel_relaxed(wdev->wdt_trgr_pattern, (base + OMAP_WATCHDOG_TGR)); omap_wdt_reload()
84 while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x08) omap_wdt_reload()
91 void __iomem *base = wdev->base; omap_wdt_enable() local
94 writel_relaxed(0xBBBB, base + OMAP_WATCHDOG_SPR); omap_wdt_enable()
95 while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x10) omap_wdt_enable()
98 writel_relaxed(0x4444, base + OMAP_WATCHDOG_SPR); omap_wdt_enable()
99 while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x10) omap_wdt_enable()
105 void __iomem *base = wdev->base; omap_wdt_disable() local
108 writel_relaxed(0xAAAA, base + OMAP_WATCHDOG_SPR); /* TIMER_MODE */ omap_wdt_disable()
109 while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x10) omap_wdt_disable()
112 writel_relaxed(0x5555, base + OMAP_WATCHDOG_SPR); /* TIMER_MODE */ omap_wdt_disable()
113 while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x10) omap_wdt_disable()
121 void __iomem *base = wdev->base; omap_wdt_set_timer() local
124 while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x04) omap_wdt_set_timer()
127 writel_relaxed(pre_margin, base + OMAP_WATCHDOG_LDR); omap_wdt_set_timer()
128 while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x04) omap_wdt_set_timer()
135 void __iomem *base = wdev->base; omap_wdt_start() local
151 while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x01) omap_wdt_start()
154 writel_relaxed((1 << 5) | (PTV << 2), base + OMAP_WATCHDOG_CNTRL); omap_wdt_start()
155 while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x01) omap_wdt_start()
209 void __iomem *base = wdev->base; omap_wdt_get_timeleft() local
212 value = readl_relaxed(base + OMAP_WATCHDOG_CRR); omap_wdt_get_timeleft()
248 wdev->base = devm_ioremap_resource(&pdev->dev, res); omap_wdt_probe()
249 if (IS_ERR(wdev->base)) omap_wdt_probe()
250 return PTR_ERR(wdev->base); omap_wdt_probe()
283 readl_relaxed(wdev->base + OMAP_WATCHDOG_REV) & 0xFF, omap_wdt_probe()
|
| H A D | davinci_wdt.c | 61 * @base - base io address of WD device
66 void __iomem *base; member in struct:davinci_wdt_device
81 iowrite32(0, davinci_wdt->base + TCR); davinci_wdt_start()
83 iowrite32(0, davinci_wdt->base + TGCR); davinci_wdt_start()
85 iowrite32(tgcr, davinci_wdt->base + TGCR); davinci_wdt_start()
87 iowrite32(0, davinci_wdt->base + TIM12); davinci_wdt_start()
88 iowrite32(0, davinci_wdt->base + TIM34); davinci_wdt_start()
91 iowrite32(timer_margin, davinci_wdt->base + PRD12); davinci_wdt_start()
93 iowrite32(timer_margin, davinci_wdt->base + PRD34); davinci_wdt_start()
95 iowrite32(ENAMODE12_PERIODIC, davinci_wdt->base + TCR); davinci_wdt_start()
101 iowrite32(WDKEY_SEQ0 | WDEN, davinci_wdt->base + WDTCR); davinci_wdt_start()
103 iowrite32(WDKEY_SEQ1 | WDEN, davinci_wdt->base + WDTCR); davinci_wdt_start()
112 iowrite32(WDKEY_SEQ0, davinci_wdt->base + WDTCR); davinci_wdt_ping()
114 iowrite32(WDKEY_SEQ1, davinci_wdt->base + WDTCR); davinci_wdt_ping()
126 val = ioread32(davinci_wdt->base + WDTCR); davinci_wdt_get_timeleft()
135 timer_counter = ioread32(davinci_wdt->base + TIM12); davinci_wdt_get_timeleft()
136 timer_counter |= ((u64)ioread32(davinci_wdt->base + TIM34) << 32); davinci_wdt_get_timeleft()
192 davinci_wdt->base = devm_ioremap_resource(dev, wdt_mem); davinci_wdt_probe()
193 if (IS_ERR(davinci_wdt->base)) davinci_wdt_probe()
194 return PTR_ERR(davinci_wdt->base); davinci_wdt_probe()
|
| /linux-4.4.14/drivers/usb/phy/ |
| H A D | phy-tegra-usb.c | 208 void __iomem *base = phy->regs; set_pts() local
212 val = readl(base + TEGRA_USB_HOSTPC1_DEVLC); set_pts()
215 writel(val, base + TEGRA_USB_HOSTPC1_DEVLC); set_pts()
217 val = readl(base + TEGRA_USB_PORTSC1) & ~TEGRA_PORTSC1_RWC_BITS; set_pts()
220 writel(val, base + TEGRA_USB_PORTSC1); set_pts()
226 void __iomem *base = phy->regs; set_phcd() local
230 val = readl(base + TEGRA_USB_HOSTPC1_DEVLC); set_phcd()
235 writel(val, base + TEGRA_USB_HOSTPC1_DEVLC); set_phcd()
237 val = readl(base + TEGRA_USB_PORTSC1) & ~PORT_RWC_BITS; set_phcd()
242 writel(val, base + TEGRA_USB_PORTSC1); set_phcd()
260 void __iomem *base = phy->pad_regs; utmip_pad_power_on() local
268 val = readl(base + UTMIP_BIAS_CFG0); utmip_pad_power_on()
280 writel(val, base + UTMIP_BIAS_CFG0); utmip_pad_power_on()
291 void __iomem *base = phy->pad_regs; utmip_pad_power_off() local
303 val = readl(base + UTMIP_BIAS_CFG0); utmip_pad_power_off()
305 writel(val, base + UTMIP_BIAS_CFG0); utmip_pad_power_off()
330 void __iomem *base = phy->regs; utmi_phy_clk_disable() local
333 val = readl(base + USB_SUSP_CTRL); utmi_phy_clk_disable()
335 writel(val, base + USB_SUSP_CTRL); utmi_phy_clk_disable()
339 val = readl(base + USB_SUSP_CTRL); utmi_phy_clk_disable()
341 writel(val, base + USB_SUSP_CTRL); utmi_phy_clk_disable()
345 if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID, 0) < 0) utmi_phy_clk_disable()
352 void __iomem *base = phy->regs; utmi_phy_clk_enable() local
355 val = readl(base + USB_SUSP_CTRL); utmi_phy_clk_enable()
357 writel(val, base + USB_SUSP_CTRL); utmi_phy_clk_enable()
361 val = readl(base + USB_SUSP_CTRL); utmi_phy_clk_enable()
363 writel(val, base + USB_SUSP_CTRL); utmi_phy_clk_enable()
367 if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID, utmi_phy_clk_enable()
375 void __iomem *base = phy->regs; utmi_phy_power_on() local
378 val = readl(base + USB_SUSP_CTRL); utmi_phy_power_on()
380 writel(val, base + USB_SUSP_CTRL); utmi_phy_power_on()
383 val = readl(base + USB1_LEGACY_CTRL); utmi_phy_power_on()
385 writel(val, base + USB1_LEGACY_CTRL); utmi_phy_power_on()
388 val = readl(base + UTMIP_TX_CFG0); utmi_phy_power_on()
390 writel(val, base + UTMIP_TX_CFG0); utmi_phy_power_on()
392 val = readl(base + UTMIP_HSRX_CFG0); utmi_phy_power_on()
396 writel(val, base + UTMIP_HSRX_CFG0); utmi_phy_power_on()
398 val = readl(base + UTMIP_HSRX_CFG1); utmi_phy_power_on()
401 writel(val, base + UTMIP_HSRX_CFG1); utmi_phy_power_on()
403 val = readl(base + UTMIP_DEBOUNCE_CFG0); utmi_phy_power_on()
406 writel(val, base + UTMIP_DEBOUNCE_CFG0); utmi_phy_power_on()
408 val = readl(base + UTMIP_MISC_CFG0); utmi_phy_power_on()
410 writel(val, base + UTMIP_MISC_CFG0); utmi_phy_power_on()
413 val = readl(base + UTMIP_MISC_CFG1); utmi_phy_power_on()
418 writel(val, base + UTMIP_MISC_CFG1); utmi_phy_power_on()
420 val = readl(base + UTMIP_PLL_CFG1); utmi_phy_power_on()
425 writel(val, base + UTMIP_PLL_CFG1); utmi_phy_power_on()
429 val = readl(base + USB_SUSP_CTRL); utmi_phy_power_on()
431 writel(val, base + USB_SUSP_CTRL); utmi_phy_power_on()
433 val = readl(base + UTMIP_BAT_CHRG_CFG0); utmi_phy_power_on()
435 writel(val, base + UTMIP_BAT_CHRG_CFG0); utmi_phy_power_on()
437 val = readl(base + UTMIP_BAT_CHRG_CFG0); utmi_phy_power_on()
439 writel(val, base + UTMIP_BAT_CHRG_CFG0); utmi_phy_power_on()
444 val = readl(base + UTMIP_XCVR_CFG0); utmi_phy_power_on()
462 writel(val, base + UTMIP_XCVR_CFG0); utmi_phy_power_on()
464 val = readl(base + UTMIP_XCVR_CFG1); utmi_phy_power_on()
468 writel(val, base + UTMIP_XCVR_CFG1); utmi_phy_power_on()
470 val = readl(base + UTMIP_BIAS_CFG1); utmi_phy_power_on()
473 writel(val, base + UTMIP_BIAS_CFG1); utmi_phy_power_on()
475 val = readl(base + UTMIP_SPARE_CFG0); utmi_phy_power_on()
480 writel(val, base + UTMIP_SPARE_CFG0); utmi_phy_power_on()
483 val = readl(base + USB_SUSP_CTRL); utmi_phy_power_on()
485 writel(val, base + USB_SUSP_CTRL); utmi_phy_power_on()
488 val = readl(base + USB_SUSP_CTRL); utmi_phy_power_on()
490 writel(val, base + USB_SUSP_CTRL); utmi_phy_power_on()
493 val = readl(base + USB1_LEGACY_CTRL); utmi_phy_power_on()
496 writel(val, base + USB1_LEGACY_CTRL); utmi_phy_power_on()
498 val = readl(base + USB_SUSP_CTRL); utmi_phy_power_on()
500 writel(val, base + USB_SUSP_CTRL); utmi_phy_power_on()
506 val = readl(base + USB_USBMODE); utmi_phy_power_on()
512 writel(val, base + USB_USBMODE); utmi_phy_power_on()
524 void __iomem *base = phy->regs; utmi_phy_power_off() local
529 val = readl(base + USB_SUSP_CTRL); utmi_phy_power_off()
532 writel(val, base + USB_SUSP_CTRL); utmi_phy_power_off()
535 val = readl(base + USB_SUSP_CTRL); utmi_phy_power_off()
537 writel(val, base + USB_SUSP_CTRL); utmi_phy_power_off()
539 val = readl(base + UTMIP_BAT_CHRG_CFG0); utmi_phy_power_off()
541 writel(val, base + UTMIP_BAT_CHRG_CFG0); utmi_phy_power_off()
543 val = readl(base + UTMIP_XCVR_CFG0); utmi_phy_power_off()
546 writel(val, base + UTMIP_XCVR_CFG0); utmi_phy_power_off()
548 val = readl(base + UTMIP_XCVR_CFG1); utmi_phy_power_off()
551 writel(val, base + UTMIP_XCVR_CFG1); utmi_phy_power_off()
559 void __iomem *base = phy->regs; utmi_phy_preresume() local
561 val = readl(base + UTMIP_TX_CFG0); utmi_phy_preresume()
563 writel(val, base + UTMIP_TX_CFG0); utmi_phy_preresume()
569 void __iomem *base = phy->regs; utmi_phy_postresume() local
571 val = readl(base + UTMIP_TX_CFG0); utmi_phy_postresume()
573 writel(val, base + UTMIP_TX_CFG0); utmi_phy_postresume()
580 void __iomem *base = phy->regs; utmi_phy_restore_start() local
582 val = readl(base + UTMIP_MISC_CFG0); utmi_phy_restore_start()
588 writel(val, base + UTMIP_MISC_CFG0); utmi_phy_restore_start()
591 val = readl(base + UTMIP_MISC_CFG0); utmi_phy_restore_start()
593 writel(val, base + UTMIP_MISC_CFG0); utmi_phy_restore_start()
600 void __iomem *base = phy->regs; utmi_phy_restore_end() local
602 val = readl(base + UTMIP_MISC_CFG0); utmi_phy_restore_end()
604 writel(val, base + UTMIP_MISC_CFG0); utmi_phy_restore_end()
612 void __iomem *base = phy->regs; ulpi_phy_power_on() local
631 val = readl(base + USB_SUSP_CTRL); ulpi_phy_power_on()
633 writel(val, base + USB_SUSP_CTRL); ulpi_phy_power_on()
635 val = readl(base + ULPI_TIMING_CTRL_0); ulpi_phy_power_on()
637 writel(val, base + ULPI_TIMING_CTRL_0); ulpi_phy_power_on()
639 val = readl(base + USB_SUSP_CTRL); ulpi_phy_power_on()
641 writel(val, base + USB_SUSP_CTRL); ulpi_phy_power_on()
644 writel(val, base + ULPI_TIMING_CTRL_1); ulpi_phy_power_on()
649 writel(val, base + ULPI_TIMING_CTRL_1); ulpi_phy_power_on()
655 writel(val, base + ULPI_TIMING_CTRL_1); ulpi_phy_power_on()
670 val = readl(base + USB_SUSP_CTRL); ulpi_phy_power_on()
672 writel(val, base + USB_SUSP_CTRL); ulpi_phy_power_on()
675 val = readl(base + USB_SUSP_CTRL); ulpi_phy_power_on()
677 writel(val, base + USB_SUSP_CTRL); ulpi_phy_power_on()
|
| /linux-4.4.14/arch/x86/platform/scx200/ |
| H A D | scx200_32.c | 18 #define scx200_cb_probe(base) (inw((base) + SCx200_CBA) == (base))
59 unsigned base; scx200_probe() local
63 base = pci_resource_start(pdev, 0); scx200_probe()
64 pr_info("GPIO base 0x%x\n", base); scx200_probe()
66 if (!request_region(base, SCx200_GPIO_SIZE, scx200_probe()
72 scx200_gpio_base = base; scx200_probe()
76 /* find the base of the Configuration Block */ scx200_probe()
80 pci_read_config_dword(pdev, SCx200_CBA_SCRATCH, &base); scx200_probe()
81 if (scx200_cb_probe(base)) { scx200_probe()
82 scx200_cb_base = base; scx200_probe()
88 pr_info("Configuration Block base 0x%x\n", scx200_cb_base); scx200_probe()
|
| /linux-4.4.14/arch/mn10300/proc-mn103e010/ |
| H A D | proc-init.c | 81 * determine the memory size and base from the memory controller regs
85 unsigned long base, size; get_mem_info() local
90 base = SDBASE(0); get_mem_info()
91 if (base & SDBASE_CE) { get_mem_info()
92 size = (base & SDBASE_CBAM) << SDBASE_CBAM_SHIFT; get_mem_info()
94 base &= SDBASE_CBA; get_mem_info()
96 printk(KERN_INFO "SDRAM[0]: %luMb @%08lx\n", size >> 20, base); get_mem_info()
98 *mem_base = base; get_mem_info()
101 base = SDBASE(1); get_mem_info()
102 if (base & SDBASE_CE) { get_mem_info()
103 size = (base & SDBASE_CBAM) << SDBASE_CBAM_SHIFT; get_mem_info()
105 base &= SDBASE_CBA; get_mem_info()
107 printk(KERN_INFO "SDRAM[1]: %luMb @%08lx\n", size >> 20, base); get_mem_info()
110 *mem_base = base; get_mem_info()
|
| /linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/ |
| H A D | busgf119.c | 24 #define gf119_i2c_bus(p) container_of((p), struct gf119_i2c_bus, base)
28 struct nvkm_i2c_bus base; member in struct:gf119_i2c_bus
33 gf119_i2c_bus_drive_scl(struct nvkm_i2c_bus *base, int state) gf119_i2c_bus_drive_scl() argument
35 struct gf119_i2c_bus *bus = gf119_i2c_bus(base); gf119_i2c_bus_drive_scl()
36 struct nvkm_device *device = bus->base.pad->i2c->subdev.device; gf119_i2c_bus_drive_scl()
41 gf119_i2c_bus_drive_sda(struct nvkm_i2c_bus *base, int state) gf119_i2c_bus_drive_sda() argument
43 struct gf119_i2c_bus *bus = gf119_i2c_bus(base); gf119_i2c_bus_drive_sda()
44 struct nvkm_device *device = bus->base.pad->i2c->subdev.device; gf119_i2c_bus_drive_sda()
49 gf119_i2c_bus_sense_scl(struct nvkm_i2c_bus *base) gf119_i2c_bus_sense_scl() argument
51 struct gf119_i2c_bus *bus = gf119_i2c_bus(base); gf119_i2c_bus_sense_scl()
52 struct nvkm_device *device = bus->base.pad->i2c->subdev.device; gf119_i2c_bus_sense_scl()
57 gf119_i2c_bus_sense_sda(struct nvkm_i2c_bus *base) gf119_i2c_bus_sense_sda() argument
59 struct gf119_i2c_bus *bus = gf119_i2c_bus(base); gf119_i2c_bus_sense_sda()
60 struct nvkm_device *device = bus->base.pad->i2c->subdev.device; gf119_i2c_bus_sense_sda()
65 gf119_i2c_bus_init(struct nvkm_i2c_bus *base) gf119_i2c_bus_init() argument
67 struct gf119_i2c_bus *bus = gf119_i2c_bus(base); gf119_i2c_bus_init()
68 struct nvkm_device *device = bus->base.pad->i2c->subdev.device; gf119_i2c_bus_init()
90 *pbus = &bus->base; gf119_i2c_bus_new()
92 nvkm_i2c_bus_ctor(&gf119_i2c_bus_func, pad, id, &bus->base); gf119_i2c_bus_new()
|
| H A D | busnv50.c | 24 #define nv50_i2c_bus(p) container_of((p), struct nv50_i2c_bus, base)
30 struct nvkm_i2c_bus base; member in struct:nv50_i2c_bus
36 nv50_i2c_bus_drive_scl(struct nvkm_i2c_bus *base, int state) nv50_i2c_bus_drive_scl() argument
38 struct nv50_i2c_bus *bus = nv50_i2c_bus(base); nv50_i2c_bus_drive_scl()
39 struct nvkm_device *device = bus->base.pad->i2c->subdev.device; nv50_i2c_bus_drive_scl()
46 nv50_i2c_bus_drive_sda(struct nvkm_i2c_bus *base, int state) nv50_i2c_bus_drive_sda() argument
48 struct nv50_i2c_bus *bus = nv50_i2c_bus(base); nv50_i2c_bus_drive_sda()
49 struct nvkm_device *device = bus->base.pad->i2c->subdev.device; nv50_i2c_bus_drive_sda()
56 nv50_i2c_bus_sense_scl(struct nvkm_i2c_bus *base) nv50_i2c_bus_sense_scl() argument
58 struct nv50_i2c_bus *bus = nv50_i2c_bus(base); nv50_i2c_bus_sense_scl()
59 struct nvkm_device *device = bus->base.pad->i2c->subdev.device; nv50_i2c_bus_sense_scl()
64 nv50_i2c_bus_sense_sda(struct nvkm_i2c_bus *base) nv50_i2c_bus_sense_sda() argument
66 struct nv50_i2c_bus *bus = nv50_i2c_bus(base); nv50_i2c_bus_sense_sda()
67 struct nvkm_device *device = bus->base.pad->i2c->subdev.device; nv50_i2c_bus_sense_sda()
72 nv50_i2c_bus_init(struct nvkm_i2c_bus *base) nv50_i2c_bus_init() argument
74 struct nv50_i2c_bus *bus = nv50_i2c_bus(base); nv50_i2c_bus_init()
75 struct nvkm_device *device = bus->base.pad->i2c->subdev.device; nv50_i2c_bus_init()
107 *pbus = &bus->base; nv50_i2c_bus_new()
109 nvkm_i2c_bus_ctor(&nv50_i2c_bus_func, pad, id, &bus->base); nv50_i2c_bus_new()
|
| H A D | auxg94.c | 24 #define g94_i2c_aux(p) container_of((p), struct g94_i2c_aux, base)
28 struct nvkm_i2c_aux base; member in struct:g94_i2c_aux
35 struct nvkm_device *device = aux->base.pad->i2c->subdev.device; g94_i2c_aux_fini()
42 struct nvkm_device *device = aux->base.pad->i2c->subdev.device; g94_i2c_aux_init()
54 AUX_ERR(&aux->base, "begin idle timeout %08x", ctrl); g94_i2c_aux_init()
66 AUX_ERR(&aux->base, "magic wait %08x", ctrl); g94_i2c_aux_init()
80 struct nvkm_device *device = aux->base.pad->i2c->subdev.device; g94_i2c_aux_xfer()
81 const u32 base = aux->ch * 0x50; g94_i2c_aux_xfer() local
86 AUX_TRACE(&aux->base, "%d: %08x %d", type, addr, size); g94_i2c_aux_xfer()
92 stat = nvkm_rd32(device, 0x00e4e8 + base); g94_i2c_aux_xfer()
94 AUX_TRACE(&aux->base, "sink not detected"); g94_i2c_aux_xfer()
102 AUX_TRACE(&aux->base, "wr %08x", xbuf[i / 4]); g94_i2c_aux_xfer()
103 nvkm_wr32(device, 0x00e4c0 + base + i, xbuf[i / 4]); g94_i2c_aux_xfer()
107 ctrl = nvkm_rd32(device, 0x00e4e4 + base); g94_i2c_aux_xfer()
111 nvkm_wr32(device, 0x00e4e0 + base, addr); g94_i2c_aux_xfer()
116 nvkm_wr32(device, 0x00e4e4 + base, 0x80000000 | ctrl); g94_i2c_aux_xfer()
117 nvkm_wr32(device, 0x00e4e4 + base, 0x00000000 | ctrl); g94_i2c_aux_xfer()
122 nvkm_wr32(device, 0x00e4e4 + base, 0x00010000 | ctrl); g94_i2c_aux_xfer()
126 ctrl = nvkm_rd32(device, 0x00e4e4 + base); g94_i2c_aux_xfer()
129 AUX_ERR(&aux->base, "timeout %08x", ctrl); g94_i2c_aux_xfer()
137 stat = nvkm_mask(device, 0x00e4e8 + base, 0, 0); g94_i2c_aux_xfer()
146 AUX_TRACE(&aux->base, "%02d %08x %08x", retries, ctrl, stat); g94_i2c_aux_xfer()
151 xbuf[i / 4] = nvkm_rd32(device, 0x00e4d0 + base + i); g94_i2c_aux_xfer()
152 AUX_TRACE(&aux->base, "rd %08x", xbuf[i / 4]); g94_i2c_aux_xfer()
175 *paux = &aux->base; g94_i2c_aux_new()
177 nvkm_i2c_aux_ctor(&g94_i2c_aux_func, pad, index, &aux->base); g94_i2c_aux_new()
179 aux->base.intr = 1 << aux->ch; g94_i2c_aux_new()
|
| H A D | auxgm204.c | 24 #define gm204_i2c_aux(p) container_of((p), struct gm204_i2c_aux, base)
28 struct nvkm_i2c_aux base; member in struct:gm204_i2c_aux
35 struct nvkm_device *device = aux->base.pad->i2c->subdev.device; gm204_i2c_aux_fini()
42 struct nvkm_device *device = aux->base.pad->i2c->subdev.device; gm204_i2c_aux_init()
54 AUX_ERR(&aux->base, "begin idle timeout %08x", ctrl); gm204_i2c_aux_init()
66 AUX_ERR(&aux->base, "magic wait %08x", ctrl); gm204_i2c_aux_init()
80 struct nvkm_device *device = aux->base.pad->i2c->subdev.device; gm204_i2c_aux_xfer()
81 const u32 base = aux->ch * 0x50; gm204_i2c_aux_xfer() local
86 AUX_TRACE(&aux->base, "%d: %08x %d", type, addr, size); gm204_i2c_aux_xfer()
92 stat = nvkm_rd32(device, 0x00d958 + base); gm204_i2c_aux_xfer()
94 AUX_TRACE(&aux->base, "sink not detected"); gm204_i2c_aux_xfer()
102 AUX_TRACE(&aux->base, "wr %08x", xbuf[i / 4]); gm204_i2c_aux_xfer()
103 nvkm_wr32(device, 0x00d930 + base + i, xbuf[i / 4]); gm204_i2c_aux_xfer()
107 ctrl = nvkm_rd32(device, 0x00d954 + base); gm204_i2c_aux_xfer()
111 nvkm_wr32(device, 0x00d950 + base, addr); gm204_i2c_aux_xfer()
116 nvkm_wr32(device, 0x00d954 + base, 0x80000000 | ctrl); gm204_i2c_aux_xfer()
117 nvkm_wr32(device, 0x00d954 + base, 0x00000000 | ctrl); gm204_i2c_aux_xfer()
122 nvkm_wr32(device, 0x00d954 + base, 0x00010000 | ctrl); gm204_i2c_aux_xfer()
126 ctrl = nvkm_rd32(device, 0x00d954 + base); gm204_i2c_aux_xfer()
129 AUX_ERR(&aux->base, "timeout %08x", ctrl); gm204_i2c_aux_xfer()
137 stat = nvkm_mask(device, 0x00d958 + base, 0, 0); gm204_i2c_aux_xfer()
146 AUX_TRACE(&aux->base, "%02d %08x %08x", retries, ctrl, stat); gm204_i2c_aux_xfer()
151 xbuf[i / 4] = nvkm_rd32(device, 0x00d940 + base + i); gm204_i2c_aux_xfer()
152 AUX_TRACE(&aux->base, "rd %08x", xbuf[i / 4]); gm204_i2c_aux_xfer()
175 *paux = &aux->base; gm204_i2c_aux_new()
177 nvkm_i2c_aux_ctor(&gm204_i2c_aux_func, pad, index, &aux->base); gm204_i2c_aux_new()
179 aux->base.intr = 1 << aux->ch; gm204_i2c_aux_new()
|
| H A D | busnv04.c | 24 #define nv04_i2c_bus(p) container_of((p), struct nv04_i2c_bus, base)
30 struct nvkm_i2c_bus base; member in struct:nv04_i2c_bus
36 nv04_i2c_bus_drive_scl(struct nvkm_i2c_bus *base, int state) nv04_i2c_bus_drive_scl() argument
38 struct nv04_i2c_bus *bus = nv04_i2c_bus(base); nv04_i2c_bus_drive_scl()
39 struct nvkm_device *device = bus->base.pad->i2c->subdev.device; nv04_i2c_bus_drive_scl()
47 nv04_i2c_bus_drive_sda(struct nvkm_i2c_bus *base, int state) nv04_i2c_bus_drive_sda() argument
49 struct nv04_i2c_bus *bus = nv04_i2c_bus(base); nv04_i2c_bus_drive_sda()
50 struct nvkm_device *device = bus->base.pad->i2c->subdev.device; nv04_i2c_bus_drive_sda()
58 nv04_i2c_bus_sense_scl(struct nvkm_i2c_bus *base) nv04_i2c_bus_sense_scl() argument
60 struct nv04_i2c_bus *bus = nv04_i2c_bus(base); nv04_i2c_bus_sense_scl()
61 struct nvkm_device *device = bus->base.pad->i2c->subdev.device; nv04_i2c_bus_sense_scl()
66 nv04_i2c_bus_sense_sda(struct nvkm_i2c_bus *base) nv04_i2c_bus_sense_sda() argument
68 struct nv04_i2c_bus *bus = nv04_i2c_bus(base); nv04_i2c_bus_sense_sda()
69 struct nvkm_device *device = bus->base.pad->i2c->subdev.device; nv04_i2c_bus_sense_sda()
90 *pbus = &bus->base; nv04_i2c_bus_new()
92 nvkm_i2c_bus_ctor(&nv04_i2c_bus_func, pad, id, &bus->base); nv04_i2c_bus_new()
|
| H A D | busnv4e.c | 24 #define nv4e_i2c_bus(p) container_of((p), struct nv4e_i2c_bus, base)
28 struct nvkm_i2c_bus base; member in struct:nv4e_i2c_bus
33 nv4e_i2c_bus_drive_scl(struct nvkm_i2c_bus *base, int state) nv4e_i2c_bus_drive_scl() argument
35 struct nv4e_i2c_bus *bus = nv4e_i2c_bus(base); nv4e_i2c_bus_drive_scl()
36 struct nvkm_device *device = bus->base.pad->i2c->subdev.device; nv4e_i2c_bus_drive_scl()
41 nv4e_i2c_bus_drive_sda(struct nvkm_i2c_bus *base, int state) nv4e_i2c_bus_drive_sda() argument
43 struct nv4e_i2c_bus *bus = nv4e_i2c_bus(base); nv4e_i2c_bus_drive_sda()
44 struct nvkm_device *device = bus->base.pad->i2c->subdev.device; nv4e_i2c_bus_drive_sda()
49 nv4e_i2c_bus_sense_scl(struct nvkm_i2c_bus *base) nv4e_i2c_bus_sense_scl() argument
51 struct nv4e_i2c_bus *bus = nv4e_i2c_bus(base); nv4e_i2c_bus_sense_scl()
52 struct nvkm_device *device = bus->base.pad->i2c->subdev.device; nv4e_i2c_bus_sense_scl()
57 nv4e_i2c_bus_sense_sda(struct nvkm_i2c_bus *base) nv4e_i2c_bus_sense_sda() argument
59 struct nv4e_i2c_bus *bus = nv4e_i2c_bus(base); nv4e_i2c_bus_sense_sda()
60 struct nvkm_device *device = bus->base.pad->i2c->subdev.device; nv4e_i2c_bus_sense_sda()
81 *pbus = &bus->base; nv4e_i2c_bus_new()
83 nvkm_i2c_bus_ctor(&nv4e_i2c_bus_func, pad, id, &bus->base); nv4e_i2c_bus_new()
|
| H A D | anx9805.c | 24 #define anx9805_pad(p) container_of((p), struct anx9805_pad, base)
25 #define anx9805_bus(p) container_of((p), struct anx9805_bus, base)
26 #define anx9805_aux(p) container_of((p), struct anx9805_aux, base)
31 struct nvkm_i2c_pad base; member in struct:anx9805_pad
37 struct nvkm_i2c_bus base; member in struct:anx9805_bus
43 anx9805_bus_xfer(struct nvkm_i2c_bus *base, struct i2c_msg *msgs, int num) anx9805_bus_xfer() argument
45 struct anx9805_bus *bus = anx9805_bus(base); anx9805_bus_xfer()
103 anx9805_bus_new(struct nvkm_i2c_pad *base, int id, u8 drive, anx9805_bus_new() argument
106 struct anx9805_pad *pad = anx9805_pad(base); anx9805_bus_new()
112 *pbus = &bus->base; anx9805_bus_new()
115 ret = nvkm_i2c_bus_ctor(&anx9805_bus_func, &pad->base, id, &bus->base); anx9805_bus_new()
130 struct nvkm_i2c_aux base; member in struct:anx9805_aux
136 anx9805_aux_xfer(struct nvkm_i2c_aux *base, bool retry, anx9805_aux_xfer() argument
139 struct anx9805_aux *aux = anx9805_aux(base); anx9805_aux_xfer()
146 AUX_DBG(&aux->base, "%02x %05x %d", type, addr, size); anx9805_aux_xfer()
156 AUX_DBG(&aux->base, "%16ph", buf); anx9805_aux_xfer()
181 AUX_DBG(&aux->base, "%16ph", buf); anx9805_aux_xfer()
192 anx9805_aux_lnk_ctl(struct nvkm_i2c_aux *base, anx9805_aux_lnk_ctl() argument
195 struct anx9805_aux *aux = anx9805_aux(base); anx9805_aux_lnk_ctl()
200 AUX_DBG(&aux->base, "ANX9805 train %d %02x %d", anx9805_aux_lnk_ctl()
212 AUX_ERR(&aux->base, "link training timeout"); anx9805_aux_lnk_ctl()
218 AUX_ERR(&aux->base, "link training failed"); anx9805_aux_lnk_ctl()
232 anx9805_aux_new(struct nvkm_i2c_pad *base, int id, u8 drive, anx9805_aux_new() argument
235 struct anx9805_pad *pad = anx9805_pad(base); anx9805_aux_new()
241 *pbus = &aux->base; anx9805_aux_new()
244 ret = nvkm_i2c_aux_ctor(&anx9805_aux_func, &pad->base, id, &aux->base); anx9805_aux_new()
272 *ppad = &pad->base; anx9805_pad_new()
274 nvkm_i2c_pad_ctor(&anx9805_pad_func, bus->pad->i2c, id, &pad->base); anx9805_pad_new()
|
| /linux-4.4.14/drivers/atm/ |
| H A D | nicstarmac.c | 110 writel((val),(base)+(reg))
112 readl((base)+(reg))
121 u_int32_t nicstar_read_eprom_status(virt_addr_t base)
128 val = NICSTAR_REG_READ(base, NICSTAR_REG_GENERAL_PURPOSE) & 0xFFFFFFF0;
131 NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE,
141 NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE,
143 rbyte |= (((NICSTAR_REG_READ(base, NICSTAR_REG_GENERAL_PURPOSE)
145 NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE,
149 NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE, 2);
161 static u_int8_t read_eprom_byte(virt_addr_t base, u_int8_t offset) read_eprom_byte() argument
167 val = NICSTAR_REG_READ(base, NICSTAR_REG_GENERAL_PURPOSE) & 0xFFFFFFF0; read_eprom_byte()
171 NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE, read_eprom_byte()
178 NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE, read_eprom_byte()
181 NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE, read_eprom_byte()
190 NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE, read_eprom_byte()
194 (((NICSTAR_REG_READ(base, NICSTAR_REG_GENERAL_PURPOSE) read_eprom_byte()
196 NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE, read_eprom_byte()
201 NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE, 2); read_eprom_byte()
206 static void nicstar_init_eprom(virt_addr_t base) nicstar_init_eprom() argument
213 val = NICSTAR_REG_READ(base, NICSTAR_REG_GENERAL_PURPOSE) & 0xFFFFFFF0; nicstar_init_eprom()
215 NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE, nicstar_init_eprom()
219 NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE, nicstar_init_eprom()
223 NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE, nicstar_init_eprom()
227 NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE, nicstar_init_eprom()
238 nicstar_read_eprom(virt_addr_t base, nicstar_read_eprom() argument
244 buffer[i] = read_eprom_byte(base, prom_offset); nicstar_read_eprom()
|
| /linux-4.4.14/drivers/scsi/pcmcia/ |
| H A D | nsp_io.h | 15 static inline void nsp_write(unsigned int base,
18 static inline unsigned char nsp_read(unsigned int base,
30 static inline void nsp_write(unsigned int base, nsp_write() argument
34 outb(val, (base + index)); nsp_write()
37 static inline unsigned char nsp_read(unsigned int base, nsp_read() argument
40 return inb(base + index); nsp_read()
75 static inline void nsp_fifo8_read(unsigned int base, nsp_fifo8_read() argument
80 nsp_multi_read_1(base, FIFODATA, buf, count); nsp_fifo8_read()
94 static inline void nsp_fifo16_read(unsigned int base, nsp_fifo16_read() argument
99 nsp_multi_read_2(base, FIFODATA, buf, count); nsp_fifo16_read()
113 static inline void nsp_fifo32_read(unsigned int base, nsp_fifo32_read() argument
118 nsp_multi_read_4(base, FIFODATA, buf, count); nsp_fifo32_read()
132 static inline void nsp_fifo8_write(unsigned int base, nsp_fifo8_write() argument
136 nsp_multi_write_1(base, FIFODATA, buf, count); nsp_fifo8_write()
150 static inline void nsp_fifo16_write(unsigned int base, nsp_fifo16_write() argument
154 nsp_multi_write_2(base, FIFODATA, buf, count); nsp_fifo16_write()
168 static inline void nsp_fifo32_write(unsigned int base, nsp_fifo32_write() argument
172 nsp_multi_write_4(base, FIFODATA, buf, count); nsp_fifo32_write()
178 static inline void nsp_mmio_write(unsigned long base, nsp_mmio_write() argument
182 unsigned char *ptr = (unsigned char *)(base + NSP_MMIO_OFFSET + index); nsp_mmio_write()
187 static inline unsigned char nsp_mmio_read(unsigned long base, nsp_mmio_read() argument
190 unsigned char *ptr = (unsigned char *)(base + NSP_MMIO_OFFSET + index); nsp_mmio_read()
197 static inline unsigned char nsp_mmio_index_read(unsigned long base, nsp_mmio_index_read() argument
200 unsigned char *index_ptr = (unsigned char *)(base + NSP_MMIO_OFFSET + INDEXREG); nsp_mmio_index_read()
201 unsigned char *data_ptr = (unsigned char *)(base + NSP_MMIO_OFFSET + DATAREG); nsp_mmio_index_read()
207 static inline void nsp_mmio_index_write(unsigned long base, nsp_mmio_index_write() argument
211 unsigned char *index_ptr = (unsigned char *)(base + NSP_MMIO_OFFSET + INDEXREG); nsp_mmio_index_write()
212 unsigned char *data_ptr = (unsigned char *)(base + NSP_MMIO_OFFSET + DATAREG); nsp_mmio_index_write()
219 static inline void nsp_mmio_multi_read_4(unsigned long base, nsp_mmio_multi_read_4() argument
224 unsigned long *ptr = (unsigned long *)(base + Register); nsp_mmio_multi_read_4()
228 //nsp_dbg(NSP_DEBUG_DATA_IO, "base 0x%0lx ptr 0x%p",base,ptr); nsp_mmio_multi_read_4()
237 static inline void nsp_mmio_fifo32_read(unsigned int base, nsp_mmio_fifo32_read() argument
242 nsp_mmio_multi_read_4(base, FIFODATA, buf, count); nsp_mmio_fifo32_read()
245 static inline void nsp_mmio_multi_write_4(unsigned long base, nsp_mmio_multi_write_4() argument
250 unsigned long *ptr = (unsigned long *)(base + Register); nsp_mmio_multi_write_4()
254 //nsp_dbg(NSP_DEBUG_DATA_IO, "base 0x%0lx ptr 0x%p",base,ptr); nsp_mmio_multi_write_4()
263 static inline void nsp_mmio_fifo32_write(unsigned int base, nsp_mmio_fifo32_write() argument
268 nsp_mmio_multi_write_4(base, FIFODATA, buf, count); nsp_mmio_fifo32_write()
|
| /linux-4.4.14/drivers/dma/ |
| H A D | ste_dma40.c | 327 * @base: Pointer to memory area when the pre_alloc_lli's are not large
331 * @size: The size in bytes of the memory at base or the size of pre_alloc_lli.
336 void *base; member in struct:d40_lli_pool
347 * points into the lli_pool, to base if lli_len > 1 or to pre_alloc_lli if
383 * @base: The virtual address of LCLA. 18 bit aligned.
392 void *base; member in struct:d40_lcla_pool
446 * @base: Pointer to the device instance struct.
472 struct d40_base *base; member in struct:d40_chan
522 * @virtbase: The virtual base address of the DMA's register.
616 return chan->base->virtbase + D40_DREG_PCBASE + chan_base()
631 void *base; d40_pool_lli_alloc() local
639 base = d40d->lli_pool.pre_alloc_lli; d40_pool_lli_alloc()
641 d40d->lli_pool.base = NULL; d40_pool_lli_alloc()
645 base = kmalloc(d40d->lli_pool.size + align, GFP_NOWAIT); d40_pool_lli_alloc()
646 d40d->lli_pool.base = base; d40_pool_lli_alloc()
648 if (d40d->lli_pool.base == NULL) d40_pool_lli_alloc()
653 d40d->lli_log.src = PTR_ALIGN(base, align); d40_pool_lli_alloc()
658 d40d->lli_phy.src = PTR_ALIGN(base, align); d40_pool_lli_alloc()
661 d40d->lli_pool.dma_addr = dma_map_single(d40c->base->dev, d40_pool_lli_alloc()
666 if (dma_mapping_error(d40c->base->dev, d40_pool_lli_alloc()
668 kfree(d40d->lli_pool.base); d40_pool_lli_alloc()
669 d40d->lli_pool.base = NULL; d40_pool_lli_alloc()
681 dma_unmap_single(d40c->base->dev, d40d->lli_pool.dma_addr, d40_pool_lli_free()
684 kfree(d40d->lli_pool.base); d40_pool_lli_free()
685 d40d->lli_pool.base = NULL; d40_pool_lli_free()
700 spin_lock_irqsave(&d40c->base->lcla_pool.lock, flags); d40_lcla_alloc_one()
709 if (!d40c->base->lcla_pool.alloc_map[idx]) { d40_lcla_alloc_one()
710 d40c->base->lcla_pool.alloc_map[idx] = d40d; d40_lcla_alloc_one()
717 spin_unlock_irqrestore(&d40c->base->lcla_pool.lock, flags); d40_lcla_alloc_one()
732 spin_lock_irqsave(&d40c->base->lcla_pool.lock, flags); d40_lcla_free_all()
737 if (d40c->base->lcla_pool.alloc_map[idx] == d40d) { d40_lcla_free_all()
738 d40c->base->lcla_pool.alloc_map[idx] = NULL; d40_lcla_free_all()
747 spin_unlock_irqrestore(&d40c->base->lcla_pool.lock, flags); d40_lcla_free_all()
777 desc = kmem_cache_zalloc(d40c->base->desc_slab, GFP_NOWAIT); d40_desc_get()
790 kmem_cache_free(d40c->base->desc_slab, d40d); d40_desc_free()
802 void __iomem *base = chan_base(chan); d40_phy_lli_load() local
804 writel(lli_src->reg_cfg, base + D40_CHAN_REG_SSCFG); d40_phy_lli_load()
805 writel(lli_src->reg_elt, base + D40_CHAN_REG_SSELT); d40_phy_lli_load()
806 writel(lli_src->reg_ptr, base + D40_CHAN_REG_SSPTR); d40_phy_lli_load()
807 writel(lli_src->reg_lnk, base + D40_CHAN_REG_SSLNK); d40_phy_lli_load()
809 writel(lli_dst->reg_cfg, base + D40_CHAN_REG_SDCFG); d40_phy_lli_load()
810 writel(lli_dst->reg_elt, base + D40_CHAN_REG_SDELT); d40_phy_lli_load()
811 writel(lli_dst->reg_ptr, base + D40_CHAN_REG_SDPTR); d40_phy_lli_load()
812 writel(lli_dst->reg_lnk, base + D40_CHAN_REG_SDLNK); d40_phy_lli_load()
822 struct d40_lcla_pool *pool = &chan->base->lcla_pool; d40_log_lli_to_lcxa()
829 bool use_esram_lcla = chan->base->plat_data->use_esram_lcla; d40_log_lli_to_lcxa()
882 struct d40_log_lli *lcla = pool->base + lcla_offset; d40_log_lli_to_lcxa()
916 dma_sync_single_range_for_device(chan->base->dev, d40_log_lli_to_lcxa()
1073 spin_lock_irqsave(&d40c->base->execmd_lock, flags); __d40_execute_command_phy()
1076 active_reg = d40c->base->virtbase + D40_DREG_ACTIVE; __d40_execute_command_phy()
1078 active_reg = d40c->base->virtbase + D40_DREG_ACTIVO; __d40_execute_command_phy()
1123 spin_unlock_irqrestore(&d40c->base->execmd_lock, flags); __d40_execute_command_phy()
1293 active_reg = d40c->base->virtbase + D40_DREG_ACTIVE; __d40_execute_command_log()
1295 active_reg = d40c->base->virtbase + D40_DREG_ACTIVO; __d40_execute_command_log()
1377 writel(var, d40c->base->virtbase + D40_DREG_PRMSE + addr_base); d40_config_write()
1382 writel(var, d40c->base->virtbase + D40_DREG_PRMOE + addr_base); d40_config_write()
1447 pm_runtime_get_sync(d40c->base->dev); d40_pause()
1451 pm_runtime_mark_last_busy(d40c->base->dev); d40_pause()
1452 pm_runtime_put_autosuspend(d40c->base->dev); d40_pause()
1472 pm_runtime_get_sync(d40c->base->dev); d40_resume()
1478 pm_runtime_mark_last_busy(d40c->base->dev); d40_resume()
1479 pm_runtime_put_autosuspend(d40c->base->dev); d40_resume()
1517 pm_runtime_get_sync(d40c->base->dev); d40_queue_start()
1580 pm_runtime_mark_last_busy(d40c->base->dev); dma_tc_handle()
1581 pm_runtime_put_autosuspend(d40c->base->dev); dma_tc_handle()
1669 struct d40_base *base = data; d40_handle_interrupt() local
1670 u32 regs[base->gen_dmac.il_size]; d40_handle_interrupt()
1671 struct d40_interrupt_lookup *il = base->gen_dmac.il; d40_handle_interrupt()
1672 u32 il_size = base->gen_dmac.il_size; d40_handle_interrupt()
1674 spin_lock_irqsave(&base->interrupt_lock, flags); d40_handle_interrupt()
1678 regs[i] = readl(base->virtbase + il[i].src); d40_handle_interrupt()
1693 d40c = base->lookup_phy_chans[idx]; d40_handle_interrupt()
1695 d40c = base->lookup_log_chans[il[row].offset + idx]; d40_handle_interrupt()
1706 writel(BIT(idx), base->virtbase + il[row].clr); d40_handle_interrupt()
1713 d40_err(base->dev, "IRQ chan: %ld offset %d idx %d\n", d40_handle_interrupt()
1719 spin_unlock_irqrestore(&base->interrupt_lock, flags); d40_handle_interrupt()
1735 if ((is_log && conf->dev_type > d40c->base->num_log_chans) || d40_validate_conf()
1736 (!is_log && conf->dev_type > d40c->base->num_phy_chans) || d40_validate_conf()
1870 phys = d40c->base->phy_res; d40_allocate_channel()
1871 num_phy_chans = d40c->base->num_phy_chans; d40_allocate_channel()
1905 for (j = 0; j < d40c->base->num_phy_chans; j += 8) { d40_allocate_channel()
1926 for (j = 0; j < d40c->base->num_phy_chans; j += 8) { d40_allocate_channel()
1976 d40c->base->lookup_log_chans[d40c->log_num] = d40c; d40_allocate_channel()
1978 d40c->base->lookup_phy_chans[d40c->phy_chan->num] = d40c; d40_allocate_channel()
2046 pm_runtime_get_sync(d40c->base->dev); d40_free_dma()
2056 d40c->base->lookup_log_chans[d40c->log_num] = NULL; d40_free_dma()
2058 d40c->base->lookup_phy_chans[phy->num] = NULL; d40_free_dma()
2061 pm_runtime_mark_last_busy(d40c->base->dev); d40_free_dma()
2062 pm_runtime_put_autosuspend(d40c->base->dev); d40_free_dma()
2070 pm_runtime_mark_last_busy(d40c->base->dev); d40_free_dma()
2071 pm_runtime_put_autosuspend(d40c->base->dev); d40_free_dma()
2088 active_reg = d40c->base->virtbase + D40_DREG_ACTIVE; d40_is_paused()
2090 active_reg = d40c->base->virtbase + D40_DREG_ACTIVO; d40_is_paused()
2191 dma_sync_single_for_device(chan->base->dev, desc->lli_pool.dma_addr, d40_prep_sg_phy()
2326 struct d40_gen_dmac *dmac = &d40c->base->gen_dmac; __d40_set_prio_rt()
2346 writel(bit, d40c->base->virtbase + prioreg + group * 4); __d40_set_prio_rt()
2347 writel(bit, d40c->base->virtbase + rtreg + group * 4); __d40_set_prio_rt()
2352 if (d40c->base->rev < 3) d40_set_prio_realtime()
2440 pm_runtime_get_sync(d40c->base->dev); d40_alloc_chan_resources()
2446 d40c->lcpa = d40c->base->lcpa_base + d40_alloc_chan_resources()
2449 d40c->lcpa = d40c->base->lcpa_base + d40_alloc_chan_resources()
2472 pm_runtime_mark_last_busy(d40c->base->dev); d40_alloc_chan_resources()
2473 pm_runtime_put_autosuspend(d40c->base->dev); d40_alloc_chan_resources()
2634 pm_runtime_get_sync(d40c->base->dev); d40_terminate_all()
2640 pm_runtime_mark_last_busy(d40c->base->dev); d40_terminate_all()
2641 pm_runtime_put_autosuspend(d40c->base->dev); d40_terminate_all()
2643 pm_runtime_mark_last_busy(d40c->base->dev); d40_terminate_all()
2644 pm_runtime_put_autosuspend(d40c->base->dev); d40_terminate_all()
2710 dev_dbg(d40c->base->dev, d40_set_runtime_config()
2726 dev_dbg(d40c->base->dev, d40_set_runtime_config()
2738 dev_err(d40c->base->dev, d40_set_runtime_config()
2745 dev_err(d40c->base->dev, "no address supplied\n"); d40_set_runtime_config()
2750 dev_err(d40c->base->dev, d40_set_runtime_config()
2798 dev_dbg(d40c->base->dev, d40_set_runtime_config()
2811 static void __init d40_chan_init(struct d40_base *base, struct dma_device *dma, d40_chan_init() argument
2822 d40c->base = base; d40_chan_init()
2844 static void d40_ops_init(struct d40_base *base, struct dma_device *dev) d40_ops_init() argument
2873 dev->dev = base->dev; d40_ops_init()
2876 static int __init d40_dmaengine_init(struct d40_base *base, d40_dmaengine_init() argument
2881 d40_chan_init(base, &base->dma_slave, base->log_chans, d40_dmaengine_init()
2882 0, base->num_log_chans); d40_dmaengine_init()
2884 dma_cap_zero(base->dma_slave.cap_mask); d40_dmaengine_init()
2885 dma_cap_set(DMA_SLAVE, base->dma_slave.cap_mask); d40_dmaengine_init()
2886 dma_cap_set(DMA_CYCLIC, base->dma_slave.cap_mask); d40_dmaengine_init()
2888 d40_ops_init(base, &base->dma_slave); d40_dmaengine_init()
2890 err = dma_async_device_register(&base->dma_slave); d40_dmaengine_init()
2893 d40_err(base->dev, "Failed to register slave channels\n"); d40_dmaengine_init()
2897 d40_chan_init(base, &base->dma_memcpy, base->log_chans, d40_dmaengine_init()
2898 base->num_log_chans, base->num_memcpy_chans); d40_dmaengine_init()
2900 dma_cap_zero(base->dma_memcpy.cap_mask); d40_dmaengine_init()
2901 dma_cap_set(DMA_MEMCPY, base->dma_memcpy.cap_mask); d40_dmaengine_init()
2902 dma_cap_set(DMA_SG, base->dma_memcpy.cap_mask); d40_dmaengine_init()
2904 d40_ops_init(base, &base->dma_memcpy); d40_dmaengine_init()
2906 err = dma_async_device_register(&base->dma_memcpy); d40_dmaengine_init()
2909 d40_err(base->dev, d40_dmaengine_init()
2914 d40_chan_init(base, &base->dma_both, base->phy_chans, d40_dmaengine_init()
2917 dma_cap_zero(base->dma_both.cap_mask); d40_dmaengine_init()
2918 dma_cap_set(DMA_SLAVE, base->dma_both.cap_mask); d40_dmaengine_init()
2919 dma_cap_set(DMA_MEMCPY, base->dma_both.cap_mask); d40_dmaengine_init()
2920 dma_cap_set(DMA_SG, base->dma_both.cap_mask); d40_dmaengine_init()
2921 dma_cap_set(DMA_CYCLIC, base->dma_slave.cap_mask); d40_dmaengine_init()
2923 d40_ops_init(base, &base->dma_both); d40_dmaengine_init()
2924 err = dma_async_device_register(&base->dma_both); d40_dmaengine_init()
2927 d40_err(base->dev, d40_dmaengine_init()
2933 dma_async_device_unregister(&base->dma_memcpy); d40_dmaengine_init()
2935 dma_async_device_unregister(&base->dma_slave); d40_dmaengine_init()
2945 struct d40_base *base = platform_get_drvdata(pdev); dma40_suspend() local
2952 if (base->lcpa_regulator) dma40_suspend()
2953 ret = regulator_disable(base->lcpa_regulator); dma40_suspend()
2960 struct d40_base *base = platform_get_drvdata(pdev); dma40_resume() local
2963 if (base->lcpa_regulator) { dma40_resume()
2964 ret = regulator_enable(base->lcpa_regulator); dma40_resume()
2989 static void d40_save_restore_registers(struct d40_base *base, bool save) d40_save_restore_registers() argument
2994 for (i = 0; i < base->num_phy_chans; i++) { d40_save_restore_registers()
2998 if (base->phy_res[i].reserved) d40_save_restore_registers()
3001 addr = base->virtbase + D40_DREG_PCBASE + i * D40_DREG_PCDELTA; d40_save_restore_registers()
3004 dma40_backup(addr, &base->reg_val_backup_chan[idx], d40_save_restore_registers()
3011 dma40_backup(base->virtbase, base->reg_val_backup, d40_save_restore_registers()
3016 if (base->gen_dmac.backup) d40_save_restore_registers()
3017 dma40_backup(base->virtbase, base->reg_val_backup_v4, d40_save_restore_registers()
3018 base->gen_dmac.backup, d40_save_restore_registers()
3019 base->gen_dmac.backup_size, d40_save_restore_registers()
3026 struct d40_base *base = platform_get_drvdata(pdev); dma40_runtime_suspend() local
3028 d40_save_restore_registers(base, true); dma40_runtime_suspend()
3031 if (base->rev != 1) dma40_runtime_suspend()
3032 writel_relaxed(base->gcc_pwr_off_mask, dma40_runtime_suspend()
3033 base->virtbase + D40_DREG_GCC); dma40_runtime_suspend()
3041 struct d40_base *base = platform_get_drvdata(pdev); dma40_runtime_resume() local
3043 d40_save_restore_registers(base, false); dma40_runtime_resume()
3046 base->virtbase + D40_DREG_GCC); dma40_runtime_resume()
3060 static int __init d40_phy_res_init(struct d40_base *base) d40_phy_res_init() argument
3068 val[0] = readl(base->virtbase + D40_DREG_PRSME); d40_phy_res_init()
3069 val[1] = readl(base->virtbase + D40_DREG_PRSMO); d40_phy_res_init()
3071 for (i = 0; i < base->num_phy_chans; i++) { d40_phy_res_init()
3072 base->phy_res[i].num = i; d40_phy_res_init()
3076 base->phy_res[i].allocated_src = D40_ALLOC_PHY; d40_phy_res_init()
3077 base->phy_res[i].allocated_dst = D40_ALLOC_PHY; d40_phy_res_init()
3078 base->phy_res[i].reserved = true; d40_phy_res_init()
3086 base->phy_res[i].allocated_src = D40_ALLOC_FREE; d40_phy_res_init()
3087 base->phy_res[i].allocated_dst = D40_ALLOC_FREE; d40_phy_res_init()
3088 base->phy_res[i].reserved = false; d40_phy_res_init()
3091 spin_lock_init(&base->phy_res[i].lock); d40_phy_res_init()
3095 for (i = 0; base->plat_data->disabled_channels[i] != -1; i++) { d40_phy_res_init()
3096 int chan = base->plat_data->disabled_channels[i]; d40_phy_res_init()
3098 base->phy_res[chan].allocated_src = D40_ALLOC_PHY; d40_phy_res_init()
3099 base->phy_res[chan].allocated_dst = D40_ALLOC_PHY; d40_phy_res_init()
3100 base->phy_res[chan].reserved = true; d40_phy_res_init()
3109 for (i = 0; i < base->plat_data->num_of_soft_lli_chans; i++) { d40_phy_res_init()
3110 int chan = base->plat_data->soft_lli_chans[i]; d40_phy_res_init()
3112 base->phy_res[chan].use_soft_lli = true; d40_phy_res_init()
3115 dev_info(base->dev, "%d of %d physical DMA channels available\n", d40_phy_res_init()
3116 num_phy_chans_avail, base->num_phy_chans); d40_phy_res_init()
3119 val[0] = readl(base->virtbase + D40_DREG_PRTYP); d40_phy_res_init()
3121 for (i = 0; i < base->num_phy_chans; i++) { d40_phy_res_init()
3123 if (base->phy_res[i].allocated_src == D40_ALLOC_FREE && d40_phy_res_init()
3125 dev_info(base->dev, d40_phy_res_init()
3138 writel(D40_DREG_GCC_ENABLE_ALL, base->virtbase + D40_DREG_GCC); d40_phy_res_init()
3139 base->gcc_pwr_off_mask = gcc; d40_phy_res_init()
3150 struct d40_base *base = NULL; d40_hw_detect_init() local
3172 /* Get IO for DMAC base address */ d40_hw_detect_init()
3173 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "base"); d40_hw_detect_init()
3178 D40_NAME " I/O base") == NULL) d40_hw_detect_init()
3236 base = kzalloc(ALIGN(sizeof(struct d40_base), 4) + d40_hw_detect_init()
3240 if (base == NULL) { d40_hw_detect_init()
3245 base->rev = rev; d40_hw_detect_init()
3246 base->clk = clk; d40_hw_detect_init()
3247 base->num_memcpy_chans = num_memcpy_chans; d40_hw_detect_init()
3248 base->num_phy_chans = num_phy_chans; d40_hw_detect_init()
3249 base->num_log_chans = num_log_chans; d40_hw_detect_init()
3250 base->phy_start = res->start; d40_hw_detect_init()
3251 base->phy_size = resource_size(res); d40_hw_detect_init()
3252 base->virtbase = virtbase; d40_hw_detect_init()
3253 base->plat_data = plat_data; d40_hw_detect_init()
3254 base->dev = &pdev->dev; d40_hw_detect_init()
3255 base->phy_chans = ((void *)base) + ALIGN(sizeof(struct d40_base), 4); d40_hw_detect_init()
3256 base->log_chans = &base->phy_chans[num_phy_chans]; d40_hw_detect_init()
3258 if (base->plat_data->num_of_phy_chans == 14) { d40_hw_detect_init()
3259 base->gen_dmac.backup = d40_backup_regs_v4b; d40_hw_detect_init()
3260 base->gen_dmac.backup_size = BACKUP_REGS_SZ_V4B; d40_hw_detect_init()
3261 base->gen_dmac.interrupt_en = D40_DREG_CPCMIS; d40_hw_detect_init()
3262 base->gen_dmac.interrupt_clear = D40_DREG_CPCICR; d40_hw_detect_init()
3263 base->gen_dmac.realtime_en = D40_DREG_CRSEG1; d40_hw_detect_init()
3264 base->gen_dmac.realtime_clear = D40_DREG_CRCEG1; d40_hw_detect_init()
3265 base->gen_dmac.high_prio_en = D40_DREG_CPSEG1; d40_hw_detect_init()
3266 base->gen_dmac.high_prio_clear = D40_DREG_CPCEG1; d40_hw_detect_init()
3267 base->gen_dmac.il = il_v4b; d40_hw_detect_init()
3268 base->gen_dmac.il_size = ARRAY_SIZE(il_v4b); d40_hw_detect_init()
3269 base->gen_dmac.init_reg = dma_init_reg_v4b; d40_hw_detect_init()
3270 base->gen_dmac.init_reg_size = ARRAY_SIZE(dma_init_reg_v4b); d40_hw_detect_init()
3272 if (base->rev >= 3) { d40_hw_detect_init()
3273 base->gen_dmac.backup = d40_backup_regs_v4a; d40_hw_detect_init()
3274 base->gen_dmac.backup_size = BACKUP_REGS_SZ_V4A; d40_hw_detect_init()
3276 base->gen_dmac.interrupt_en = D40_DREG_PCMIS; d40_hw_detect_init()
3277 base->gen_dmac.interrupt_clear = D40_DREG_PCICR; d40_hw_detect_init()
3278 base->gen_dmac.realtime_en = D40_DREG_RSEG1; d40_hw_detect_init()
3279 base->gen_dmac.realtime_clear = D40_DREG_RCEG1; d40_hw_detect_init()
3280 base->gen_dmac.high_prio_en = D40_DREG_PSEG1; d40_hw_detect_init()
3281 base->gen_dmac.high_prio_clear = D40_DREG_PCEG1; d40_hw_detect_init()
3282 base->gen_dmac.il = il_v4a; d40_hw_detect_init()
3283 base->gen_dmac.il_size = ARRAY_SIZE(il_v4a); d40_hw_detect_init()
3284 base->gen_dmac.init_reg = dma_init_reg_v4a; d40_hw_detect_init()
3285 base->gen_dmac.init_reg_size = ARRAY_SIZE(dma_init_reg_v4a); d40_hw_detect_init()
3288 base->phy_res = kzalloc(num_phy_chans * sizeof(struct d40_phy_res), d40_hw_detect_init()
3290 if (!base->phy_res) d40_hw_detect_init()
3293 base->lookup_phy_chans = kzalloc(num_phy_chans * d40_hw_detect_init()
3296 if (!base->lookup_phy_chans) d40_hw_detect_init()
3299 base->lookup_log_chans = kzalloc(num_log_chans * d40_hw_detect_init()
3302 if (!base->lookup_log_chans) d40_hw_detect_init()
3305 base->reg_val_backup_chan = kmalloc(base->num_phy_chans * d40_hw_detect_init()
3308 if (!base->reg_val_backup_chan) d40_hw_detect_init()
3311 base->lcla_pool.alloc_map = d40_hw_detect_init()
3314 if (!base->lcla_pool.alloc_map) d40_hw_detect_init()
3317 base->desc_slab = kmem_cache_create(D40_NAME, sizeof(struct d40_desc), d40_hw_detect_init()
3320 if (base->desc_slab == NULL) d40_hw_detect_init()
3323 return base; d40_hw_detect_init()
3338 if (base) { d40_hw_detect_init()
3339 kfree(base->lcla_pool.alloc_map); d40_hw_detect_init()
3340 kfree(base->reg_val_backup_chan); d40_hw_detect_init()
3341 kfree(base->lookup_log_chans); d40_hw_detect_init()
3342 kfree(base->lookup_phy_chans); d40_hw_detect_init()
3343 kfree(base->phy_res); d40_hw_detect_init()
3344 kfree(base); d40_hw_detect_init()
3350 static void __init d40_hw_init(struct d40_base *base) d40_hw_init() argument
3358 struct d40_reg_val *dma_init_reg = base->gen_dmac.init_reg; d40_hw_init()
3359 u32 reg_size = base->gen_dmac.init_reg_size; d40_hw_init()
3363 base->virtbase + dma_init_reg[i].reg); d40_hw_init()
3366 for (i = 0; i < base->num_phy_chans; i++) { d40_hw_init()
3370 if (base->phy_res[base->num_phy_chans - i - 1].allocated_src d40_hw_init()
3388 writel(prmseo[1], base->virtbase + D40_DREG_PRMSE); d40_hw_init()
3389 writel(prmseo[0], base->virtbase + D40_DREG_PRMSO); d40_hw_init()
3390 writel(activeo[1], base->virtbase + D40_DREG_ACTIVE); d40_hw_init()
3391 writel(activeo[0], base->virtbase + D40_DREG_ACTIVO); d40_hw_init()
3394 writel(pcmis, base->virtbase + base->gen_dmac.interrupt_en); d40_hw_init()
3397 writel(pcicr, base->virtbase + base->gen_dmac.interrupt_clear); d40_hw_init()
3400 base->gen_dmac.init_reg = NULL; d40_hw_init()
3401 base->gen_dmac.init_reg_size = 0; d40_hw_init()
3404 static int __init d40_lcla_allocate(struct d40_base *base) d40_lcla_allocate() argument
3406 struct d40_lcla_pool *pool = &base->lcla_pool; d40_lcla_allocate()
3425 base->lcla_pool.pages = SZ_1K * base->num_phy_chans / PAGE_SIZE; d40_lcla_allocate()
3429 base->lcla_pool.pages); d40_lcla_allocate()
3432 d40_err(base->dev, "Failed to allocate %d pages.\n", d40_lcla_allocate()
3433 base->lcla_pool.pages); d40_lcla_allocate()
3437 free_pages(page_list[j], base->lcla_pool.pages); d40_lcla_allocate()
3447 free_pages(page_list[j], base->lcla_pool.pages); d40_lcla_allocate()
3450 base->lcla_pool.base = (void *)page_list[i]; d40_lcla_allocate()
3456 dev_warn(base->dev, d40_lcla_allocate()
3458 __func__, base->lcla_pool.pages); d40_lcla_allocate()
3459 base->lcla_pool.base_unaligned = kmalloc(SZ_1K * d40_lcla_allocate()
3460 base->num_phy_chans + d40_lcla_allocate()
3463 if (!base->lcla_pool.base_unaligned) { d40_lcla_allocate()
3468 base->lcla_pool.base = PTR_ALIGN(base->lcla_pool.base_unaligned, d40_lcla_allocate()
3472 pool->dma_addr = dma_map_single(base->dev, pool->base, d40_lcla_allocate()
3473 SZ_1K * base->num_phy_chans, d40_lcla_allocate()
3475 if (dma_mapping_error(base->dev, pool->dma_addr)) { d40_lcla_allocate()
3481 writel(virt_to_phys(base->lcla_pool.base), d40_lcla_allocate()
3482 base->virtbase + D40_DREG_LCLA); d40_lcla_allocate()
3546 struct d40_base *base = NULL; d40_probe() local
3563 base = d40_hw_detect_init(pdev); d40_probe()
3564 if (!base) d40_probe()
3567 num_reserved_chans = d40_phy_res_init(base); d40_probe()
3569 platform_set_drvdata(pdev, base); d40_probe()
3571 spin_lock_init(&base->interrupt_lock); d40_probe()
3572 spin_lock_init(&base->execmd_lock); d40_probe()
3581 base->lcpa_size = resource_size(res); d40_probe()
3582 base->phy_lcpa = res->start; d40_probe()
3592 val = readl(base->virtbase + D40_DREG_LCPA); d40_probe()
3598 writel(res->start, base->virtbase + D40_DREG_LCPA); d40_probe()
3600 base->lcpa_base = ioremap(res->start, resource_size(res)); d40_probe()
3601 if (!base->lcpa_base) { d40_probe()
3607 if (base->plat_data->use_esram_lcla) { d40_probe()
3616 base->lcla_pool.base = ioremap(res->start, d40_probe()
3618 if (!base->lcla_pool.base) { d40_probe()
3623 writel(res->start, base->virtbase + D40_DREG_LCLA); d40_probe()
3626 ret = d40_lcla_allocate(base); d40_probe()
3633 spin_lock_init(&base->lcla_pool.lock); d40_probe()
3635 base->irq = platform_get_irq(pdev, 0); d40_probe()
3637 ret = request_irq(base->irq, d40_handle_interrupt, 0, D40_NAME, base); d40_probe()
3643 if (base->plat_data->use_esram_lcla) { d40_probe()
3645 base->lcpa_regulator = regulator_get(base->dev, "lcla_esram"); d40_probe()
3646 if (IS_ERR(base->lcpa_regulator)) { d40_probe()
3648 ret = PTR_ERR(base->lcpa_regulator); d40_probe()
3649 base->lcpa_regulator = NULL; d40_probe()
3653 ret = regulator_enable(base->lcpa_regulator); d40_probe()
3657 regulator_put(base->lcpa_regulator); d40_probe()
3658 base->lcpa_regulator = NULL; d40_probe()
3663 writel_relaxed(D40_DREG_GCC_ENABLE_ALL, base->virtbase + D40_DREG_GCC); d40_probe()
3665 pm_runtime_irq_safe(base->dev); d40_probe()
3666 pm_runtime_set_autosuspend_delay(base->dev, DMA40_AUTOSUSPEND_DELAY); d40_probe()
3667 pm_runtime_use_autosuspend(base->dev); d40_probe()
3668 pm_runtime_mark_last_busy(base->dev); d40_probe()
3669 pm_runtime_set_active(base->dev); d40_probe()
3670 pm_runtime_enable(base->dev); d40_probe()
3672 ret = d40_dmaengine_init(base, num_reserved_chans); d40_probe()
3676 base->dev->dma_parms = &base->dma_parms; d40_probe()
3677 ret = dma_set_max_seg_size(base->dev, STEDMA40_MAX_SEG_SIZE); d40_probe()
3683 d40_hw_init(base); d40_probe()
3692 dev_info(base->dev, "initialized\n"); d40_probe()
3696 if (base) { d40_probe()
3697 if (base->desc_slab) d40_probe()
3698 kmem_cache_destroy(base->desc_slab); d40_probe()
3699 if (base->virtbase) d40_probe()
3700 iounmap(base->virtbase); d40_probe()
3702 if (base->lcla_pool.base && base->plat_data->use_esram_lcla) { d40_probe()
3703 iounmap(base->lcla_pool.base); d40_probe()
3704 base->lcla_pool.base = NULL; d40_probe()
3707 if (base->lcla_pool.dma_addr) d40_probe()
3708 dma_unmap_single(base->dev, base->lcla_pool.dma_addr, d40_probe()
3709 SZ_1K * base->num_phy_chans, d40_probe()
3712 if (!base->lcla_pool.base_unaligned && base->lcla_pool.base) d40_probe()
3713 free_pages((unsigned long)base->lcla_pool.base, d40_probe()
3714 base->lcla_pool.pages); d40_probe()
3716 kfree(base->lcla_pool.base_unaligned); d40_probe()
3718 if (base->phy_lcpa) d40_probe()
3719 release_mem_region(base->phy_lcpa, d40_probe()
3720 base->lcpa_size); d40_probe()
3721 if (base->phy_start) d40_probe()
3722 release_mem_region(base->phy_start, d40_probe()
3723 base->phy_size); d40_probe()
3724 if (base->clk) { d40_probe()
3725 clk_disable_unprepare(base->clk); d40_probe()
3726 clk_put(base->clk); d40_probe()
3729 if (base->lcpa_regulator) { d40_probe()
3730 regulator_disable(base->lcpa_regulator); d40_probe()
3731 regulator_put(base->lcpa_regulator); d40_probe()
3734 kfree(base->lcla_pool.alloc_map); d40_probe()
3735 kfree(base->lookup_log_chans); d40_probe()
3736 kfree(base->lookup_phy_chans); d40_probe()
3737 kfree(base->phy_res); d40_probe()
3738 kfree(base); d40_probe()
|
| /linux-4.4.14/drivers/gpu/drm/msm/dsi/pll/ |
| H A D | dsi_pll_28nm.c | 78 struct msm_dsi_pll base; member in struct:dsi_pll_28nm
97 #define to_pll_28nm(x) container_of(x, struct dsi_pll_28nm, base)
121 void __iomem *base = pll_28nm->mmio; pll_28nm_software_reset() local
127 pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_TEST_CFG, pll_28nm_software_reset()
129 pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_TEST_CFG, 0x00, 1); pll_28nm_software_reset()
141 void __iomem *base = pll_28nm->mmio; dsi_pll_28nm_clk_set_rate() local
152 pll_write(base + REG_DSI_28nm_PHY_PLL_POSTDIV2_CFG, 3); dsi_pll_28nm_clk_set_rate()
163 pll_write(base + REG_DSI_28nm_PHY_PLL_LPFR_CFG, lpfr_lut[i].resistance); dsi_pll_28nm_clk_set_rate()
166 pll_write(base + REG_DSI_28nm_PHY_PLL_LPFC1_CFG, 0x70); dsi_pll_28nm_clk_set_rate()
167 pll_write(base + REG_DSI_28nm_PHY_PLL_LPFC2_CFG, 0x15); dsi_pll_28nm_clk_set_rate()
192 sdm_cfg1 = pll_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG1); dsi_pll_28nm_clk_set_rate()
219 pll_write(base + REG_DSI_28nm_PHY_PLL_CHGPUMP_CFG, 0x02); dsi_pll_28nm_clk_set_rate()
220 pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG3, 0x2b); dsi_pll_28nm_clk_set_rate()
221 pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG4, 0x06); dsi_pll_28nm_clk_set_rate()
222 pll_write(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, 0x0d); dsi_pll_28nm_clk_set_rate()
224 pll_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG1, sdm_cfg1); dsi_pll_28nm_clk_set_rate()
225 pll_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG2, dsi_pll_28nm_clk_set_rate()
227 pll_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG3, dsi_pll_28nm_clk_set_rate()
229 pll_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG4, 0x00); dsi_pll_28nm_clk_set_rate()
235 pll_write(base + REG_DSI_28nm_PHY_PLL_REFCLK_CFG, refclk_cfg); dsi_pll_28nm_clk_set_rate()
236 pll_write(base + REG_DSI_28nm_PHY_PLL_PWRGEN_CFG, 0x00); dsi_pll_28nm_clk_set_rate()
237 pll_write(base + REG_DSI_28nm_PHY_PLL_VCOLPF_CFG, 0x31); dsi_pll_28nm_clk_set_rate()
238 pll_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG0, sdm_cfg0); dsi_pll_28nm_clk_set_rate()
239 pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG0, 0x12); dsi_pll_28nm_clk_set_rate()
240 pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG6, 0x30); dsi_pll_28nm_clk_set_rate()
241 pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG7, 0x00); dsi_pll_28nm_clk_set_rate()
242 pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG8, 0x60); dsi_pll_28nm_clk_set_rate()
243 pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG9, 0x00); dsi_pll_28nm_clk_set_rate()
244 pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG10, cal_cfg10 & 0xff); dsi_pll_28nm_clk_set_rate()
245 pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG11, cal_cfg11 & 0xff); dsi_pll_28nm_clk_set_rate()
246 pll_write(base + REG_DSI_28nm_PHY_PLL_EFUSE_CFG, 0x20); dsi_pll_28nm_clk_set_rate()
265 void __iomem *base = pll_28nm->mmio; dsi_pll_28nm_clk_recalc_rate() local
274 doubler = pll_read(base + REG_DSI_28nm_PHY_PLL_REFCLK_CFG) & dsi_pll_28nm_clk_recalc_rate()
279 sdm0 = pll_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG0); dsi_pll_28nm_clk_recalc_rate()
283 pll_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG0), dsi_pll_28nm_clk_recalc_rate()
289 pll_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG1), dsi_pll_28nm_clk_recalc_rate()
292 sdm2 = FIELD(pll_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG2), dsi_pll_28nm_clk_recalc_rate()
294 sdm3 = FIELD(pll_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG3), dsi_pll_28nm_clk_recalc_rate()
325 void __iomem *base = pll_28nm->mmio; dsi_pll_28nm_enable_seq_hpm() local
340 pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 1); dsi_pll_28nm_enable_seq_hpm()
343 pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 200); dsi_pll_28nm_enable_seq_hpm()
346 pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 500); dsi_pll_28nm_enable_seq_hpm()
349 pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 600); dsi_pll_28nm_enable_seq_hpm()
353 pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, dsi_pll_28nm_enable_seq_hpm()
355 pll_write(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, 0x0d); dsi_pll_28nm_enable_seq_hpm()
370 pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 1); dsi_pll_28nm_enable_seq_hpm()
373 pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 200); dsi_pll_28nm_enable_seq_hpm()
376 pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 250); dsi_pll_28nm_enable_seq_hpm()
379 pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 200); dsi_pll_28nm_enable_seq_hpm()
382 pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 500); dsi_pll_28nm_enable_seq_hpm()
385 pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 600); dsi_pll_28nm_enable_seq_hpm()
400 void __iomem *base = pll_28nm->mmio; dsi_pll_28nm_enable_seq_lp() local
413 pll_write_ndelay(base + REG_DSI_28nm_PHY_PLL_CAL_CFG1, 0x34, 500); dsi_pll_28nm_enable_seq_lp()
416 pll_write_ndelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 500); dsi_pll_28nm_enable_seq_lp()
419 pll_write_ndelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 500); dsi_pll_28nm_enable_seq_lp()
423 pll_write_ndelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 500); dsi_pll_28nm_enable_seq_lp()
426 pll_write_ndelay(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, 0x04, 500); dsi_pll_28nm_enable_seq_lp()
427 pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, 0x05, 512); dsi_pll_28nm_enable_seq_lp()
451 void __iomem *base = pll_28nm->mmio; dsi_pll_28nm_save_state() local
454 pll_read(base + REG_DSI_28nm_PHY_PLL_POSTDIV3_CFG); dsi_pll_28nm_save_state()
456 pll_read(base + REG_DSI_28nm_PHY_PLL_POSTDIV1_CFG); dsi_pll_28nm_save_state()
457 cached_state->byte_mux = pll_read(base + REG_DSI_28nm_PHY_PLL_VREG_CFG); dsi_pll_28nm_save_state()
465 void __iomem *base = pll_28nm->mmio; dsi_pll_28nm_restore_state() local
476 pll_write(base + REG_DSI_28nm_PHY_PLL_POSTDIV3_CFG, dsi_pll_28nm_restore_state()
478 pll_write(base + REG_DSI_28nm_PHY_PLL_POSTDIV1_CFG, dsi_pll_28nm_restore_state()
480 pll_write(base + REG_DSI_28nm_PHY_PLL_VREG_CFG, dsi_pll_28nm_restore_state()
535 pll_28nm->base.clk_hw.init = &vco_init; pll_28nm_register()
536 clks[num++] = clk_register(dev, &pll_28nm->base.clk_hw); pll_28nm_register()
609 dev_err(&pdev->dev, "%s: failed to map pll base\n", __func__); msm_dsi_pll_28nm_init()
613 pll = &pll_28nm->base; msm_dsi_pll_28nm_init()
|
| /linux-4.4.14/arch/arm/mach-gemini/ |
| H A D | gpio.c | 48 static void _set_gpio_irqenable(void __iomem *base, unsigned int index, _set_gpio_irqenable() argument
53 reg = __raw_readl(base + GPIO_INT_EN); _set_gpio_irqenable()
55 __raw_writel(reg, base + GPIO_INT_EN); _set_gpio_irqenable()
61 void __iomem *base = GPIO_BASE(gpio / 32); gpio_ack_irq() local
63 __raw_writel(1 << (gpio % 32), base + GPIO_INT_CLR); gpio_ack_irq()
69 void __iomem *base = GPIO_BASE(gpio / 32); gpio_mask_irq() local
71 _set_gpio_irqenable(base, gpio % 32, 0); gpio_mask_irq()
77 void __iomem *base = GPIO_BASE(gpio / 32); gpio_unmask_irq() local
79 _set_gpio_irqenable(base, gpio % 32, 1); gpio_unmask_irq()
86 void __iomem *base = GPIO_BASE(gpio / 32); gpio_set_irq_type() local
89 reg_type = __raw_readl(base + GPIO_INT_TYPE); gpio_set_irq_type()
90 reg_level = __raw_readl(base + GPIO_INT_LEVEL); gpio_set_irq_type()
91 reg_both = __raw_readl(base + GPIO_INT_BOTH_EDGE); gpio_set_irq_type()
120 __raw_writel(reg_type, base + GPIO_INT_TYPE); gpio_set_irq_type()
121 __raw_writel(reg_level, base + GPIO_INT_LEVEL); gpio_set_irq_type()
122 __raw_writel(reg_both, base + GPIO_INT_BOTH_EDGE); gpio_set_irq_type()
157 void __iomem *base = GPIO_BASE(offset / 32); _set_gpio_direction() local
160 reg = __raw_readl(base + GPIO_DIR); _set_gpio_direction()
165 __raw_writel(reg, base + GPIO_DIR); _set_gpio_direction()
170 void __iomem *base = GPIO_BASE(offset / 32); gemini_gpio_set() local
173 __raw_writel(1 << (offset % 32), base + GPIO_DATA_SET); gemini_gpio_set()
175 __raw_writel(1 << (offset % 32), base + GPIO_DATA_CLR); gemini_gpio_set()
180 void __iomem *base = GPIO_BASE(offset / 32); gemini_gpio_get() local
182 return (__raw_readl(base + GPIO_DATA_IN) >> (offset % 32)) & 1; gemini_gpio_get()
205 .base = 0,
|
| /linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/ |
| H A D | nv40.c | 24 #define nv40_instmem(p) container_of((p), struct nv40_instmem, base)
32 struct nvkm_instmem base; member in struct:nv40_instmem
96 mutex_lock(&iobj->imem->base.subdev.mutex); nv40_instobj_dtor()
98 mutex_unlock(&iobj->imem->base.subdev.mutex); nv40_instobj_dtor()
115 nv40_instobj_new(struct nvkm_instmem *base, u32 size, u32 align, bool zero, nv40_instobj_new() argument
118 struct nv40_instmem *imem = nv40_instmem(base); nv40_instobj_new()
129 mutex_lock(&imem->base.subdev.mutex); nv40_instobj_new()
132 mutex_unlock(&imem->base.subdev.mutex); nv40_instobj_new()
141 nv40_instmem_rd32(struct nvkm_instmem *base, u32 addr) nv40_instmem_rd32() argument
143 return ioread32_native(nv40_instmem(base)->iomem + addr); nv40_instmem_rd32()
147 nv40_instmem_wr32(struct nvkm_instmem *base, u32 addr, u32 data) nv40_instmem_wr32() argument
149 iowrite32_native(data, nv40_instmem(base)->iomem + addr); nv40_instmem_wr32()
153 nv40_instmem_oneinit(struct nvkm_instmem *base) nv40_instmem_oneinit() argument
155 struct nv40_instmem *imem = nv40_instmem(base); nv40_instmem_oneinit()
156 struct nvkm_device *device = imem->base.subdev.device; nv40_instmem_oneinit()
164 if (device->chipset == 0x40) imem->base.reserved = 0x6aa0 * vs; nv40_instmem_oneinit()
165 else if (device->chipset < 0x43) imem->base.reserved = 0x4f00 * vs; nv40_instmem_oneinit()
166 else if (nv44_gr_class(device)) imem->base.reserved = 0x4980 * vs; nv40_instmem_oneinit()
167 else imem->base.reserved = 0x4a40 * vs; nv40_instmem_oneinit()
168 imem->base.reserved += 16 * 1024; nv40_instmem_oneinit()
169 imem->base.reserved *= 32; /* per-channel */ nv40_instmem_oneinit()
170 imem->base.reserved += 512 * 1024; /* pci(e)gart table */ nv40_instmem_oneinit()
171 imem->base.reserved += 512 * 1024; /* object storage */ nv40_instmem_oneinit()
172 imem->base.reserved = round_up(imem->base.reserved, 4096); nv40_instmem_oneinit()
174 ret = nvkm_mm_init(&imem->heap, 0, imem->base.reserved, 1); nv40_instmem_oneinit()
180 &imem->base.vbios); nv40_instmem_oneinit()
185 ret = nvkm_ramht_new(device, 0x08000, 0, NULL, &imem->base.ramht); nv40_instmem_oneinit()
193 &imem->base.ramro); nv40_instmem_oneinit()
201 &imem->base.ramfc); nv40_instmem_oneinit()
209 nv40_instmem_dtor(struct nvkm_instmem *base) nv40_instmem_dtor() argument
211 struct nv40_instmem *imem = nv40_instmem(base); nv40_instmem_dtor()
212 nvkm_memory_del(&imem->base.ramfc); nv40_instmem_dtor()
213 nvkm_memory_del(&imem->base.ramro); nv40_instmem_dtor()
214 nvkm_ramht_del(&imem->base.ramht); nv40_instmem_dtor()
215 nvkm_memory_del(&imem->base.vbios); nv40_instmem_dtor()
242 nvkm_instmem_ctor(&nv40_instmem, device, index, &imem->base); nv40_instmem_new()
243 *pimem = &imem->base; nv40_instmem_new()
254 nvkm_error(&imem->base.subdev, "unable to map PRAMIN BAR\n"); nv40_instmem_new()
|
| /linux-4.4.14/arch/arm/mach-mmp/ |
| H A D | devices.c | 81 static unsigned int u2o_get(void __iomem *base, unsigned int offset) u2o_get() argument
83 return readl_relaxed(base + offset); u2o_get()
86 static void u2o_set(void __iomem *base, unsigned int offset, u2o_set() argument
91 reg = readl_relaxed(base + offset); u2o_set()
93 writel_relaxed(reg, base + offset); u2o_set()
94 readl_relaxed(base + offset); u2o_set()
97 static void u2o_clear(void __iomem *base, unsigned int offset, u2o_clear() argument
102 reg = readl_relaxed(base + offset); u2o_clear()
104 writel_relaxed(reg, base + offset); u2o_clear()
105 readl_relaxed(base + offset); u2o_clear()
108 static void u2o_write(void __iomem *base, unsigned int offset, u2o_write() argument
111 writel_relaxed(value, base + offset); u2o_write()
112 readl_relaxed(base + offset); u2o_write()
122 static int usb_phy_init_internal(void __iomem *base) usb_phy_init_internal() argument
130 u2o_set(base, UTMI_CTRL, (1<<UTMI_CTRL_INPKT_DELAY_SOF_SHIFT) usb_phy_init_internal()
134 u2o_set(base, UTMI_CTRL, 1<<UTMI_CTRL_PLL_PWR_UP_SHIFT); usb_phy_init_internal()
135 u2o_set(base, UTMI_CTRL, 1<<UTMI_CTRL_PWR_UP_SHIFT); usb_phy_init_internal()
138 u2o_clear(base, UTMI_PLL, UTMI_PLL_PLLVDD18_MASK usb_phy_init_internal()
143 u2o_set(base, UTMI_PLL, 0xee<<UTMI_PLL_FBDIV_SHIFT usb_phy_init_internal()
149 u2o_clear(base, UTMI_TX, UTMI_TX_REG_EXT_FS_RCAL_EN_MASK usb_phy_init_internal()
153 u2o_set(base, UTMI_TX, 3<<UTMI_TX_TXVDD12_SHIFT usb_phy_init_internal()
158 u2o_clear(base, UTMI_RX, UTMI_RX_SQ_THRESH_MASK usb_phy_init_internal()
160 u2o_set(base, UTMI_RX, 7<<UTMI_RX_SQ_THRESH_SHIFT usb_phy_init_internal()
167 u2o_write(base, UTMI_IVREF, 0x4bf); usb_phy_init_internal()
171 u2o_set(base, UTMI_PLL, VCOCAL_START); usb_phy_init_internal()
173 u2o_clear(base, UTMI_PLL, VCOCAL_START); usb_phy_init_internal()
177 u2o_set(base, UTMI_TX, REG_RCAL_START); usb_phy_init_internal()
179 u2o_clear(base, UTMI_TX, REG_RCAL_START); usb_phy_init_internal()
184 while ((u2o_get(base, UTMI_PLL) & PLL_READY) == 0) { usb_phy_init_internal()
189 u2o_get(base, UTMI_PLL)); usb_phy_init_internal()
195 u2o_set(base, UTMI_RESERVE, 1 << 5); usb_phy_init_internal()
197 u2o_write(base, UTMI_OTG_ADDON, 1); usb_phy_init_internal()
203 static int usb_phy_deinit_internal(void __iomem *base) usb_phy_deinit_internal() argument
208 u2o_clear(base, UTMI_OTG_ADDON, UTMI_OTG_ADDON_OTG_ON); usb_phy_deinit_internal()
210 u2o_clear(base, UTMI_CTRL, UTMI_CTRL_RXBUF_PDWN); usb_phy_deinit_internal()
211 u2o_clear(base, UTMI_CTRL, UTMI_CTRL_TXBUF_PDWN); usb_phy_deinit_internal()
212 u2o_clear(base, UTMI_CTRL, UTMI_CTRL_USB_CLK_EN); usb_phy_deinit_internal()
213 u2o_clear(base, UTMI_CTRL, 1<<UTMI_CTRL_PWR_UP_SHIFT); usb_phy_deinit_internal()
214 u2o_clear(base, UTMI_CTRL, 1<<UTMI_CTRL_PLL_PWR_UP_SHIFT); usb_phy_deinit_internal()
|
| /linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/engine/ |
| H A D | xtensa.c | 35 oclass->base = xtensa->func->sclass[index]; nvkm_xtensa_oclass_get()
62 const u32 base = xtensa->addr; nvkm_xtensa_intr() local
63 u32 unk104 = nvkm_rd32(device, base + 0xd04); nvkm_xtensa_intr()
64 u32 intr = nvkm_rd32(device, base + 0xc20); nvkm_xtensa_intr()
65 u32 chan = nvkm_rd32(device, base + 0xc28); nvkm_xtensa_intr()
66 u32 unk10c = nvkm_rd32(device, base + 0xd0c); nvkm_xtensa_intr()
70 nvkm_wr32(device, base + 0xc20, intr); nvkm_xtensa_intr()
71 intr = nvkm_rd32(device, base + 0xc20); nvkm_xtensa_intr()
83 const u32 base = xtensa->addr; nvkm_xtensa_fini() local
85 nvkm_wr32(device, base + 0xd84, 0); /* INTR_EN */ nvkm_xtensa_fini()
86 nvkm_wr32(device, base + 0xd94, 0); /* FIFO_CTRL */ nvkm_xtensa_fini()
99 const u32 base = xtensa->addr; nvkm_xtensa_init() local
140 nvkm_wr32(device, base + 0xd10, 0x1fffffff); /* ?? */ nvkm_xtensa_init()
141 nvkm_wr32(device, base + 0xd08, 0x0fffffff); /* ?? */ nvkm_xtensa_init()
143 nvkm_wr32(device, base + 0xd28, xtensa->func->unkd28); /* ?? */ nvkm_xtensa_init()
144 nvkm_wr32(device, base + 0xc20, 0x3f); /* INTR */ nvkm_xtensa_init()
145 nvkm_wr32(device, base + 0xd84, 0x3f); /* INTR_EN */ nvkm_xtensa_init()
147 nvkm_wr32(device, base + 0xcc0, addr >> 8); /* XT_REGION_BASE */ nvkm_xtensa_init()
148 nvkm_wr32(device, base + 0xcc4, 0x1c); /* XT_REGION_SETUP */ nvkm_xtensa_init()
149 nvkm_wr32(device, base + 0xcc8, size >> 8); /* XT_REGION_LIMIT */ nvkm_xtensa_init()
152 nvkm_wr32(device, base + 0xde0, tmp); /* SCRATCH_H2X */ nvkm_xtensa_init()
154 nvkm_wr32(device, base + 0xce8, 0xf); /* XT_REGION_SETUP */ nvkm_xtensa_init()
156 nvkm_wr32(device, base + 0xc20, 0x3f); /* INTR */ nvkm_xtensa_init()
157 nvkm_wr32(device, base + 0xd84, 0x3f); /* INTR_EN */ nvkm_xtensa_init()
|
| H A D | falcon.c | 36 oclass->base = falcon->func->sclass[index]; nvkm_falcon_oclass_get()
63 const u32 base = falcon->addr; nvkm_falcon_intr() local
64 u32 dest = nvkm_rd32(device, base + 0x01c); nvkm_falcon_intr()
65 u32 intr = nvkm_rd32(device, base + 0x008) & dest & ~(dest >> 16); nvkm_falcon_intr()
66 u32 inst = nvkm_rd32(device, base + 0x050) & 0x3fffffff; nvkm_falcon_intr()
75 nvkm_wr32(device, base + 0x004, 0x00000040); nvkm_falcon_intr()
82 nvkm_wr32(device, base + 0x004, 0x00000010); nvkm_falcon_intr()
88 nvkm_wr32(device, base + 0x004, intr); nvkm_falcon_intr()
99 const u32 base = falcon->addr; nvkm_falcon_fini() local
110 nvkm_mask(device, base + 0x048, 0x00000003, 0x00000000); nvkm_falcon_fini()
111 nvkm_wr32(device, base + 0x014, 0xffffffff); nvkm_falcon_fini()
131 const u32 base = falcon->addr; nvkm_falcon_oneinit() local
140 caps = nvkm_rd32(device, base + 0x12c); nvkm_falcon_oneinit()
145 caps = nvkm_rd32(device, base + 0x108); nvkm_falcon_oneinit()
164 const u32 base = falcon->addr; nvkm_falcon_init() local
171 if (nvkm_rd32(device, base + 0x008) & 0x00000010) nvkm_falcon_init()
176 if (!(nvkm_rd32(device, base + 0x180) & 0x80000000)) nvkm_falcon_init()
180 nvkm_wr32(device, base + 0x004, 0x00000010); nvkm_falcon_init()
184 nvkm_wr32(device, base + 0x014, 0xffffffff); nvkm_falcon_init()
263 nvkm_wr32(device, base + 0x618, 0x04000000); nvkm_falcon_init()
265 nvkm_wr32(device, base + 0x618, 0x00000114); nvkm_falcon_init()
266 nvkm_wr32(device, base + 0x11c, 0); nvkm_falcon_init()
267 nvkm_wr32(device, base + 0x110, addr >> 8); nvkm_falcon_init()
268 nvkm_wr32(device, base + 0x114, 0); nvkm_falcon_init()
269 nvkm_wr32(device, base + 0x118, 0x00006610); nvkm_falcon_init()
278 nvkm_wr32(device, base + 0xff8, 0x00100000); nvkm_falcon_init()
280 nvkm_wr32(device, base + 0xff4, falcon->code.data[i]); nvkm_falcon_init()
282 nvkm_wr32(device, base + 0x180, 0x01000000); nvkm_falcon_init()
285 nvkm_wr32(device, base + 0x188, i >> 6); nvkm_falcon_init()
286 nvkm_wr32(device, base + 0x184, falcon->code.data[i]); nvkm_falcon_init()
293 nvkm_wr32(device, base + 0xff8, 0x00000000); nvkm_falcon_init()
295 nvkm_wr32(device, base + 0xff4, falcon->data.data[i]); nvkm_falcon_init()
297 nvkm_wr32(device, base + 0xff4, 0x00000000); nvkm_falcon_init()
299 nvkm_wr32(device, base + 0x1c0, 0x01000000); nvkm_falcon_init()
301 nvkm_wr32(device, base + 0x1c4, falcon->data.data[i]); nvkm_falcon_init()
303 nvkm_wr32(device, base + 0x1c4, 0x00000000); nvkm_falcon_init()
307 nvkm_wr32(device, base + 0x10c, 0x00000001); /* BLOCK_ON_FIFO */ nvkm_falcon_init()
308 nvkm_wr32(device, base + 0x104, 0x00000000); /* ENTRY */ nvkm_falcon_init()
309 nvkm_wr32(device, base + 0x100, 0x00000002); /* TRIGGER */ nvkm_falcon_init()
310 nvkm_wr32(device, base + 0x048, 0x00000003); /* FIFO | CHSW */ nvkm_falcon_init()
|
| /linux-4.4.14/arch/mips/loongson64/common/ |
| H A D | early_printk.c | 16 #define PORT(base, offset) (u8 *)(base + offset)
18 static inline unsigned int serial_in(unsigned char *base, int offset) serial_in() argument
20 return readb(PORT(base, offset)); serial_in()
23 static inline void serial_out(unsigned char *base, int offset, int value) serial_out() argument
25 writeb(value, PORT(base, offset)); serial_out()
|
| /linux-4.4.14/drivers/gpu/ipu-v3/ |
| H A D | ipu-dp.c | 64 void __iomem *base; member in struct:ipu_flow
71 void __iomem *base; member in struct:ipu_dp_priv
96 reg = readl(flow->base + DP_COM_CONF); ipu_dp_set_global_alpha()
101 writel(reg, flow->base + DP_COM_CONF); ipu_dp_set_global_alpha()
104 reg = readl(flow->base + DP_GRAPH_WIND_CTRL) & 0x00FFFFFFL; ipu_dp_set_global_alpha()
106 flow->base + DP_GRAPH_WIND_CTRL); ipu_dp_set_global_alpha()
108 reg = readl(flow->base + DP_COM_CONF); ipu_dp_set_global_alpha()
109 writel(reg | DP_COM_CONF_GWAM, flow->base + DP_COM_CONF); ipu_dp_set_global_alpha()
111 reg = readl(flow->base + DP_COM_CONF); ipu_dp_set_global_alpha()
112 writel(reg & ~DP_COM_CONF_GWAM, flow->base + DP_COM_CONF); ipu_dp_set_global_alpha()
128 writel((x_pos << 16) | y_pos, flow->base + DP_FG_POS); ipu_dp_set_window_pos()
143 reg = readl(flow->base + DP_COM_CONF); ipu_dp_csc_init()
147 writel(reg, flow->base + DP_COM_CONF); ipu_dp_csc_init()
152 writel(0x099 | (0x12d << 16), flow->base + DP_CSC_A_0); ipu_dp_csc_init()
153 writel(0x03a | (0x3a9 << 16), flow->base + DP_CSC_A_1); ipu_dp_csc_init()
154 writel(0x356 | (0x100 << 16), flow->base + DP_CSC_A_2); ipu_dp_csc_init()
155 writel(0x100 | (0x329 << 16), flow->base + DP_CSC_A_3); ipu_dp_csc_init()
157 flow->base + DP_CSC_0); ipu_dp_csc_init()
159 flow->base + DP_CSC_1); ipu_dp_csc_init()
161 writel(0x095 | (0x000 << 16), flow->base + DP_CSC_A_0); ipu_dp_csc_init()
162 writel(0x0cc | (0x095 << 16), flow->base + DP_CSC_A_1); ipu_dp_csc_init()
163 writel(0x3ce | (0x398 << 16), flow->base + DP_CSC_A_2); ipu_dp_csc_init()
164 writel(0x095 | (0x0ff << 16), flow->base + DP_CSC_A_3); ipu_dp_csc_init()
166 flow->base + DP_CSC_0); ipu_dp_csc_init()
168 flow->base + DP_CSC_1); ipu_dp_csc_init()
173 writel(reg, flow->base + DP_COM_CONF); ipu_dp_csc_init()
246 reg = readl(flow->base + DP_COM_CONF); ipu_dp_enable_channel()
248 writel(reg, flow->base + DP_COM_CONF); ipu_dp_enable_channel()
269 reg = readl(flow->base + DP_COM_CONF); ipu_dp_disable_channel()
275 writel(reg, flow->base + DP_COM_CONF); ipu_dp_disable_channel()
277 writel(0, flow->base + DP_FG_POS); ipu_dp_disable_channel()
333 int ipu_dp_init(struct ipu_soc *ipu, struct device *dev, unsigned long base) ipu_dp_init() argument
346 priv->base = devm_ioremap(dev, base, PAGE_SIZE); ipu_dp_init()
347 if (!priv->base) ipu_dp_init()
354 priv->flow[i].base = priv->base + ipu_dp_flow_base[i]; ipu_dp_init()
|
| /linux-4.4.14/drivers/clk/versatile/ |
| H A D | clk-icst.h | 6 * @vco_offset: offset to the ICST VCO from the provided memory base
8 * memory base
20 void __iomem *base);
|
| /linux-4.4.14/arch/m68k/include/asm/ |
| H A D | div64.h | 10 /* n = n / base; return rem; */
12 #define do_div(n, base) ({ \
18 unsigned long __base = (base); \
|
| /linux-4.4.14/drivers/gpu/drm/bridge/ |
| H A D | dw_hdmi-audio.h | 8 void __iomem *base; member in struct:dw_hdmi_audio_data
|
| /linux-4.4.14/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/ |
| H A D | image.h | 4 u32 base; member in struct:nvbios_image
|
| /linux-4.4.14/kernel/gcov/ |
| H A D | Makefile | 3 obj-y := base.o fs.o
|
| /linux-4.4.14/include/linux/ |
| H A D | sort.h | 6 void sort(void *base, size_t num, size_t size,
|
| H A D | clksrc-dbx500-prcmu.h | 15 void __init clksrc_dbx500_prcmu_init(void __iomem *base);
17 static inline void __init clksrc_dbx500_prcmu_init(void __iomem *base) {} argument
|
| /linux-4.4.14/arch/mips/include/asm/ |
| H A D | bmips-spaces.h | 4 /* Avoid collisions with system base register (SBR) region on BMIPS3300 */
|
| /linux-4.4.14/arch/metag/include/asm/ |
| H A D | hwthread.h | 28 unsigned int base, thread_offset, thread_regnum; __CU_addr() local
32 base = T0UCTREG0; /* Control unit base */ __CU_addr()
37 return (void __iomem *)(base + thread_offset + thread_regnum); __CU_addr()
|
| /linux-4.4.14/arch/mn10300/include/asm/ |
| H A D | page_offset.h | 1 /* MN10300 Kernel base address
|
| /linux-4.4.14/arch/h8300/kernel/ |
| H A D | irq.c | 30 unsigned long base, tmp; get_vector_address() local
33 base = rom_vector[EXT_IRQ0] & ADDR_MASK; get_vector_address()
37 if ((base+(vec_no - EXT_IRQ0)*4) != get_vector_address()
42 /* ramvector base address */ get_vector_address()
43 base -= EXT_IRQ0*4; get_vector_address()
46 tmp = ~(*(volatile unsigned long *)base); get_vector_address()
47 (*(volatile unsigned long *)base) = tmp; get_vector_address()
48 if ((*(volatile unsigned long *)base) != tmp) get_vector_address()
50 return (unsigned long *)base; get_vector_address()
|
| /linux-4.4.14/arch/arm/mach-netx/include/mach/ |
| H A D | uncompress.h | 45 unsigned long base; putc() local
48 base = UART1_BASE; putc()
50 base = UART2_BASE; putc()
54 while (REG(base + UART_FR) & FR_TXFF); putc()
55 REG(base + UART_DR) = c; putc()
60 unsigned long base; flush() local
63 base = UART1_BASE; flush()
65 base = UART2_BASE; flush()
69 while (REG(base + UART_FR) & FR_BUSY); flush()
|
| /linux-4.4.14/net/netlabel/ |
| H A D | Makefile | 5 # base objects
|
| /linux-4.4.14/drivers/i2c/busses/ |
| H A D | i2c-wmt.c | 90 void __iomem *base; member in struct:wmt_i2c_dev
102 while (!(readw(i2c_dev->base + REG_CSR) & CSR_READY_MASK)) { wmt_i2c_wait_bus_not_busy()
147 writew(0, i2c_dev->base + REG_CDR); wmt_i2c_write()
149 writew(pmsg->buf[0] & 0xFF, i2c_dev->base + REG_CDR); wmt_i2c_write()
153 val = readw(i2c_dev->base + REG_CR); wmt_i2c_write()
155 writew(val, i2c_dev->base + REG_CR); wmt_i2c_write()
157 val = readw(i2c_dev->base + REG_CR); wmt_i2c_write()
159 writew(val, i2c_dev->base + REG_CR); wmt_i2c_write()
171 writew(tcr_val, i2c_dev->base + REG_TCR); wmt_i2c_write()
174 val = readw(i2c_dev->base + REG_CR); wmt_i2c_write()
176 writew(val, i2c_dev->base + REG_CR); wmt_i2c_write()
192 val = readw(i2c_dev->base + REG_CSR); wmt_i2c_write()
200 writew(val, i2c_dev->base + REG_CR); wmt_i2c_write()
206 writew(CR_ENABLE, i2c_dev->base + REG_CR); wmt_i2c_write()
208 writew(pmsg->buf[xfer_len] & 0xFF, i2c_dev->base + wmt_i2c_write()
210 writew(CR_CPU_RDY | CR_ENABLE, i2c_dev->base + REG_CR); wmt_i2c_write()
232 val = readw(i2c_dev->base + REG_CR); wmt_i2c_read()
234 writew(val, i2c_dev->base + REG_CR); wmt_i2c_read()
236 val = readw(i2c_dev->base + REG_CR); wmt_i2c_read()
238 writew(val, i2c_dev->base + REG_CR); wmt_i2c_read()
241 val = readw(i2c_dev->base + REG_CR); wmt_i2c_read()
243 writew(val, i2c_dev->base + REG_CR); wmt_i2c_read()
247 val = readw(i2c_dev->base + REG_CR); wmt_i2c_read()
249 writew(val, i2c_dev->base + REG_CR); wmt_i2c_read()
261 writew(tcr_val, i2c_dev->base + REG_TCR); wmt_i2c_read()
264 val = readw(i2c_dev->base + REG_CR); wmt_i2c_read()
266 writew(val, i2c_dev->base + REG_CR); wmt_i2c_read()
280 pmsg->buf[xfer_len] = readw(i2c_dev->base + REG_CDR) >> 8; wmt_i2c_read()
284 val = readw(i2c_dev->base + REG_CR); wmt_i2c_read()
286 writew(val, i2c_dev->base + REG_CR); wmt_i2c_read()
288 val = readw(i2c_dev->base + REG_CR); wmt_i2c_read()
290 writew(val, i2c_dev->base + REG_CR); wmt_i2c_read()
333 i2c_dev->cmd_status = readw(i2c_dev->base + REG_ISR); wmt_i2c_isr()
334 writew(i2c_dev->cmd_status, i2c_dev->base + REG_ISR); wmt_i2c_isr()
358 writew(0, i2c_dev->base + REG_CR); wmt_i2c_reset_hardware()
359 writew(MCR_APB_166M, i2c_dev->base + REG_MCR); wmt_i2c_reset_hardware()
360 writew(ISR_WRITE_ALL, i2c_dev->base + REG_ISR); wmt_i2c_reset_hardware()
361 writew(IMR_ENABLE_ALL, i2c_dev->base + REG_IMR); wmt_i2c_reset_hardware()
362 writew(CR_ENABLE, i2c_dev->base + REG_CR); wmt_i2c_reset_hardware()
363 readw(i2c_dev->base + REG_CSR); /* read clear */ wmt_i2c_reset_hardware()
364 writew(ISR_WRITE_ALL, i2c_dev->base + REG_ISR); wmt_i2c_reset_hardware()
367 writew(SCL_TIMEOUT(128) | TR_STD, i2c_dev->base + REG_TR); wmt_i2c_reset_hardware()
369 writew(SCL_TIMEOUT(128) | TR_HS, i2c_dev->base + REG_TR); wmt_i2c_reset_hardware()
388 i2c_dev->base = devm_ioremap_resource(&pdev->dev, res); wmt_i2c_probe()
389 if (IS_ERR(i2c_dev->base)) wmt_i2c_probe()
390 return PTR_ERR(i2c_dev->base); wmt_i2c_probe()
450 writew(0, i2c_dev->base + REG_IMR); wmt_i2c_remove()
|
| H A D | i2c-pca-isa.c | 36 static unsigned long base; variable
51 base+reg, val); pca_isa_writebyte()
53 outb(val, base+reg); pca_isa_writebyte()
58 int res = inb(base+reg); pca_isa_readbyte()
120 int match = base != 0; pca_isa_match()
126 dev_err(dev, "Please specify I/O base\n"); pca_isa_match()
135 dev_info(dev, "i/o base %#08lx. irq %d\n", base, irq); pca_isa_probe()
138 if (check_legacy_ioport(base)) { pca_isa_probe()
139 dev_err(dev, "I/O address %#08lx is not available\n", base); pca_isa_probe()
144 if (!request_region(base, IO_SIZE, "i2c-pca-isa")) { pca_isa_probe()
145 dev_err(dev, "I/O address %#08lx is in use\n", base); pca_isa_probe()
168 release_region(base, IO_SIZE); pca_isa_probe()
181 release_region(base, IO_SIZE); pca_isa_remove()
207 MODULE_DESCRIPTION("ISA base PCA9564/PCA9665 driver");
210 module_param(base, ulong, 0);
211 MODULE_PARM_DESC(base, "I/O base address");
|
| /linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/engine/disp/ |
| H A D | outpdp.c | 34 nvkm_output_dp_train(struct nvkm_output *base, u32 datarate, bool wait) nvkm_output_dp_train() argument
36 struct nvkm_output_dp *outp = nvkm_output_dp(base); nvkm_output_dp_train()
45 OUTP_DBG(&outp->base, nvkm_output_dp_train()
54 OUTP_DBG(&outp->base, "link not trained at sufficient rate"); nvkm_output_dp_train()
61 OUTP_DBG(&outp->base, nvkm_output_dp_train()
72 OUTP_DBG(&outp->base, nvkm_output_dp_train()
79 OUTP_DBG(&outp->base, "no inter-lane alignment"); nvkm_output_dp_train()
87 outp->base.info.dpconf.link_bw; nvkm_output_dp_train()
89 outp->base.info.dpconf.link_nr; nvkm_output_dp_train()
114 OUTP_DBG(&outp->base, "aux power -> always"); nvkm_output_dp_enable()
121 nvkm_output_dp_train(&outp->base, 0, true); nvkm_output_dp_enable()
127 OUTP_DBG(&outp->base, "aux power -> demand"); nvkm_output_dp_enable()
140 struct nvkm_connector *conn = outp->base.conn; nvkm_output_dp_hpd()
141 struct nvkm_disp *disp = outp->base.disp; nvkm_output_dp_hpd()
144 OUTP_DBG(&outp->base, "HPD: %d", line->mask); nvkm_output_dp_hpd()
161 struct nvkm_connector *conn = outp->base.conn; nvkm_output_dp_irq()
162 struct nvkm_disp *disp = outp->base.disp; nvkm_output_dp_irq()
167 OUTP_DBG(&outp->base, "IRQ: %d", line->mask); nvkm_output_dp_irq()
168 nvkm_output_dp_train(&outp->base, 0, true); nvkm_output_dp_irq()
175 nvkm_output_dp_fini(struct nvkm_output *base) nvkm_output_dp_fini() argument
177 struct nvkm_output_dp *outp = nvkm_output_dp(base); nvkm_output_dp_fini()
185 nvkm_output_dp_init(struct nvkm_output *base) nvkm_output_dp_init() argument
187 struct nvkm_output_dp *outp = nvkm_output_dp(base); nvkm_output_dp_init()
188 nvkm_notify_put(&outp->base.conn->hpd); nvkm_output_dp_init()
194 nvkm_output_dp_dtor(struct nvkm_output *base) nvkm_output_dp_dtor() argument
196 struct nvkm_output_dp *outp = nvkm_output_dp(base); nvkm_output_dp_dtor()
221 nvkm_output_ctor(&nvkm_output_dp_func, disp, index, dcbE, &outp->base); nvkm_output_dp_ctor()
225 OUTP_ERR(&outp->base, "no aux"); nvkm_output_dp_ctor()
230 data = nvbios_dpout_match(bios, outp->base.info.hasht, nvkm_output_dp_ctor()
231 outp->base.info.hashm, &outp->version, nvkm_output_dp_ctor()
234 OUTP_ERR(&outp->base, "no bios dp data"); nvkm_output_dp_ctor()
238 OUTP_DBG(&outp->base, "bios dp %02x %02x %02x %02x", nvkm_output_dp_ctor()
256 OUTP_ERR(&outp->base, "error monitoring aux irq: %d", ret); nvkm_output_dp_ctor()
270 OUTP_ERR(&outp->base, "error monitoring aux hpd: %d", ret); nvkm_output_dp_ctor()
288 *poutp = &outp->base; nvkm_output_dp_new_()
|
| H A D | dmacnv50.c | 41 nv50_disp_dmac_child_del_(struct nvkm_oproxy *base) nv50_disp_dmac_child_del_() argument
44 container_of(base, typeof(*object), oproxy); nv50_disp_dmac_child_del_()
54 nv50_disp_dmac_child_new_(struct nv50_disp_chan *base, nv50_disp_dmac_child_new_() argument
58 struct nv50_disp_dmac *chan = nv50_disp_dmac(base); nv50_disp_dmac_child_new_()
59 struct nv50_disp_root *root = chan->base.root; nv50_disp_dmac_child_new_()
60 struct nvkm_device *device = root->disp->base.engine.subdev.device; nv50_disp_dmac_child_new_()
69 *pobject = &object->oproxy.base; nv50_disp_dmac_child_new_()
84 nv50_disp_dmac_child_get_(struct nv50_disp_chan *base, int index, nv50_disp_dmac_child_get_() argument
87 struct nv50_disp_dmac *chan = nv50_disp_dmac(base); nv50_disp_dmac_child_get_()
88 struct nv50_disp *disp = chan->base.root->disp; nv50_disp_dmac_child_get_()
89 struct nvkm_device *device = disp->base.engine.subdev.device; nv50_disp_dmac_child_get_()
93 if (sclass->engine && sclass->engine->func->base.sclass) { nv50_disp_dmac_child_get_()
94 sclass->engine->func->base.sclass(sclass, index, &oclass); nv50_disp_dmac_child_get_()
105 nv50_disp_dmac_fini_(struct nv50_disp_chan *base) nv50_disp_dmac_fini_() argument
107 struct nv50_disp_dmac *chan = nv50_disp_dmac(base); nv50_disp_dmac_fini_()
112 nv50_disp_dmac_init_(struct nv50_disp_chan *base) nv50_disp_dmac_init_() argument
114 struct nv50_disp_dmac *chan = nv50_disp_dmac(base); nv50_disp_dmac_init_()
119 nv50_disp_dmac_dtor_(struct nv50_disp_chan *base) nv50_disp_dmac_dtor_() argument
121 return nv50_disp_dmac(base); nv50_disp_dmac_dtor_()
140 struct nvkm_device *device = root->disp->base.engine.subdev.device; nv50_disp_dmac_new_()
148 *pobject = &chan->base.object; nv50_disp_dmac_new_()
152 chid, head, oclass, &chan->base); nv50_disp_dmac_new_()
181 return nvkm_ramht_insert(chan->base.root->ramht, object, nv50_disp_dmac_bind()
182 chan->base.chid, -10, handle, nv50_disp_dmac_bind()
183 chan->base.chid << 28 | nv50_disp_dmac_bind()
184 chan->base.chid); nv50_disp_dmac_bind()
190 struct nv50_disp *disp = chan->base.root->disp; nv50_disp_dmac_fini()
191 struct nvkm_subdev *subdev = &disp->base.engine.subdev; nv50_disp_dmac_fini()
193 int chid = chan->base.chid; nv50_disp_dmac_fini()
213 struct nv50_disp *disp = chan->base.root->disp; nv50_disp_dmac_init()
214 struct nvkm_subdev *subdev = &disp->base.engine.subdev; nv50_disp_dmac_init()
216 int chid = chan->base.chid; nv50_disp_dmac_init()
|
| /linux-4.4.14/arch/mips/pci/ |
| H A D | pci-ar724x.c | 75 void __iomem *base; ar724x_pci_local_write() local
84 base = apc->crp_base; ar724x_pci_local_write()
85 data = __raw_readl(base + (where & ~3)); ar724x_pci_local_write()
105 __raw_writel(data, base + (where & ~3)); ar724x_pci_local_write()
107 __raw_readl(base + (where & ~3)); ar724x_pci_local_write()
116 void __iomem *base; ar724x_pci_read() local
126 base = apc->devcfg_base; ar724x_pci_read()
127 data = __raw_readl(base + (where & ~3)); ar724x_pci_read()
163 void __iomem *base; ar724x_pci_write() local
178 * device is set to the proper base address, the ar724x_pci_write()
195 base = apc->devcfg_base; ar724x_pci_write()
196 data = __raw_readl(base + (where & ~3)); ar724x_pci_write()
216 __raw_writel(data, base + (where & ~3)); ar724x_pci_write()
218 __raw_readl(base + (where & ~3)); ar724x_pci_write()
231 void __iomem *base; ar724x_pci_irq_handler() local
235 base = apc->ctrl_base; ar724x_pci_irq_handler()
237 pending = __raw_readl(base + AR724X_PCI_REG_INT_STATUS) & ar724x_pci_irq_handler()
238 __raw_readl(base + AR724X_PCI_REG_INT_MASK); ar724x_pci_irq_handler()
250 void __iomem *base; ar724x_pci_irq_unmask() local
255 base = apc->ctrl_base; ar724x_pci_irq_unmask()
260 t = __raw_readl(base + AR724X_PCI_REG_INT_MASK); ar724x_pci_irq_unmask()
262 base + AR724X_PCI_REG_INT_MASK); ar724x_pci_irq_unmask()
264 __raw_readl(base + AR724X_PCI_REG_INT_MASK); ar724x_pci_irq_unmask()
271 void __iomem *base; ar724x_pci_irq_mask() local
276 base = apc->ctrl_base; ar724x_pci_irq_mask()
281 t = __raw_readl(base + AR724X_PCI_REG_INT_MASK); ar724x_pci_irq_mask()
283 base + AR724X_PCI_REG_INT_MASK); ar724x_pci_irq_mask()
286 __raw_readl(base + AR724X_PCI_REG_INT_MASK); ar724x_pci_irq_mask()
288 t = __raw_readl(base + AR724X_PCI_REG_INT_STATUS); ar724x_pci_irq_mask()
290 base + AR724X_PCI_REG_INT_STATUS); ar724x_pci_irq_mask()
293 __raw_readl(base + AR724X_PCI_REG_INT_STATUS); ar724x_pci_irq_mask()
307 void __iomem *base; ar724x_pci_irq_init() local
310 base = apc->ctrl_base; ar724x_pci_irq_init()
312 __raw_writel(0, base + AR724X_PCI_REG_INT_MASK); ar724x_pci_irq_init()
313 __raw_writel(0, base + AR724X_PCI_REG_INT_STATUS); ar724x_pci_irq_init()
|
| H A D | pci-ar71xx.c | 112 void __iomem *base = apc->cfg_base; ar71xx_pci_check_error() local
116 pci_err = __raw_readl(base + AR71XX_PCI_REG_PCI_ERR) & 3; ar71xx_pci_check_error()
121 addr = __raw_readl(base + AR71XX_PCI_REG_PCI_ERR_ADDR); ar71xx_pci_check_error()
127 __raw_writel(pci_err, base + AR71XX_PCI_REG_PCI_ERR); ar71xx_pci_check_error()
130 ahb_err = __raw_readl(base + AR71XX_PCI_REG_AHB_ERR) & 1; ar71xx_pci_check_error()
135 addr = __raw_readl(base + AR71XX_PCI_REG_AHB_ERR_ADDR); ar71xx_pci_check_error()
141 __raw_writel(ahb_err, base + AR71XX_PCI_REG_AHB_ERR); ar71xx_pci_check_error()
150 void __iomem *base = apc->cfg_base; ar71xx_pci_local_write() local
158 __raw_writel(ad_cbe, base + AR71XX_PCI_REG_CRP_AD_CBE); ar71xx_pci_local_write()
159 __raw_writel(value, base + AR71XX_PCI_REG_CRP_WRDATA); ar71xx_pci_local_write()
167 void __iomem *base = apc->cfg_base; ar71xx_pci_set_cfgaddr() local
172 __raw_writel(addr, base + AR71XX_PCI_REG_CFG_AD); ar71xx_pci_set_cfgaddr()
174 base + AR71XX_PCI_REG_CFG_CBE); ar71xx_pci_set_cfgaddr()
183 void __iomem *base = apc->cfg_base; ar71xx_pci_read_config() local
196 data = __raw_readl(base + AR71XX_PCI_REG_CFG_RDDATA); ar71xx_pci_read_config()
207 void __iomem *base = apc->cfg_base; ar71xx_pci_write_config() local
219 __raw_writel(value, base + AR71XX_PCI_REG_CFG_WRDATA); ar71xx_pci_write_config()
232 void __iomem *base = ath79_reset_base; ar71xx_pci_irq_handler() local
237 pending = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_STATUS) & ar71xx_pci_irq_handler()
238 __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); ar71xx_pci_irq_handler()
260 void __iomem *base = ath79_reset_base; ar71xx_pci_irq_unmask() local
266 t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); ar71xx_pci_irq_unmask()
267 __raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE); ar71xx_pci_irq_unmask()
270 __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); ar71xx_pci_irq_unmask()
277 void __iomem *base = ath79_reset_base; ar71xx_pci_irq_mask() local
283 t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); ar71xx_pci_irq_mask()
284 __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE); ar71xx_pci_irq_mask()
287 __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); ar71xx_pci_irq_mask()
299 void __iomem *base = ath79_reset_base; ar71xx_pci_irq_init() local
302 __raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_ENABLE); ar71xx_pci_irq_init()
303 __raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_STATUS); ar71xx_pci_irq_init()
|
| /linux-4.4.14/drivers/mmc/host/ |
| H A D | mmci_qcom_dml.c | 60 void __iomem *base = host->base + DML_OFFSET; dml_start_xfer() local
65 config = readl_relaxed(base + DML_CONFIG); dml_start_xfer()
68 writel_relaxed(config, base + DML_CONFIG); dml_start_xfer()
71 writel_relaxed(data->blksz, base + DML_PRODUCER_BAM_BLOCK_SIZE); dml_start_xfer()
75 base + DML_PRODUCER_BAM_TRANS_SIZE); dml_start_xfer()
77 config = readl_relaxed(base + DML_CONFIG); dml_start_xfer()
79 writel_relaxed(config, base + DML_CONFIG); dml_start_xfer()
81 writel_relaxed(1, base + DML_PRODUCER_START); dml_start_xfer()
85 config = readl_relaxed(base + DML_CONFIG); dml_start_xfer()
88 writel_relaxed(config, base + DML_CONFIG); dml_start_xfer()
90 config = readl_relaxed(base + DML_CONFIG); dml_start_xfer()
92 writel_relaxed(config, base + DML_CONFIG); dml_start_xfer()
94 writel_relaxed(1, base + DML_CONSUMER_START); dml_start_xfer()
125 void __iomem *base; dml_hw_init() local
134 base = host->base + DML_OFFSET; dml_hw_init()
137 writel_relaxed(1, base + DML_SW_RESET); dml_hw_init()
158 writel_relaxed(config, base + DML_CONFIG); dml_hw_init()
165 base + DML_PRODUCER_PIPE_LOGICAL_SIZE); dml_hw_init()
167 base + DML_CONSUMER_PIPE_LOGICAL_SIZE); dml_hw_init()
171 base + DML_PIPE_ID); dml_hw_init()
|
| /linux-4.4.14/arch/arm/common/ |
| H A D | scoop.c | 36 void __iomem *base; member in struct:scoop_dev
48 iowrite16(0x0100, sdev->base + SCOOP_MCR); /* 00 */ reset_scoop()
49 iowrite16(0x0000, sdev->base + SCOOP_CDR); /* 04 */ reset_scoop()
50 iowrite16(0x0000, sdev->base + SCOOP_CCR); /* 10 */ reset_scoop()
51 iowrite16(0x0000, sdev->base + SCOOP_IMR); /* 18 */ reset_scoop()
52 iowrite16(0x00FF, sdev->base + SCOOP_IRM); /* 14 */ reset_scoop()
53 iowrite16(0x0000, sdev->base + SCOOP_ISR); /* 1C */ reset_scoop()
54 iowrite16(0x0000, sdev->base + SCOOP_IRM); reset_scoop()
62 gpwr = ioread16(sdev->base + SCOOP_GPWR); __scoop_gpio_set()
67 iowrite16(gpwr, sdev->base + SCOOP_GPWR); __scoop_gpio_set()
87 return ioread16(sdev->base + SCOOP_GPRR) & (1 << (offset + 1)); scoop_gpio_get()
99 gpcr = ioread16(sdev->base + SCOOP_GPCR); scoop_gpio_direction_input()
101 iowrite16(gpcr, sdev->base + SCOOP_GPCR); scoop_gpio_direction_input()
119 gpcr = ioread16(sdev->base + SCOOP_GPCR); scoop_gpio_direction_output()
121 iowrite16(gpcr, sdev->base + SCOOP_GPCR); scoop_gpio_direction_output()
131 return ioread16(sdev->base + reg); read_scoop_reg()
137 iowrite16(data, sdev->base + reg); write_scoop_reg()
149 mcr = ioread16(sdev->base + SCOOP_MCR); check_scoop_reg()
151 iowrite16(0x0101, sdev->base + SCOOP_MCR); check_scoop_reg()
159 sdev->scoop_gpwr = ioread16(sdev->base + SCOOP_GPWR); scoop_suspend()
160 iowrite16((sdev->scoop_gpwr & ~sdev->suspend_clr) | sdev->suspend_set, sdev->base + SCOOP_GPWR); scoop_suspend()
170 iowrite16(sdev->scoop_gpwr, sdev->base + SCOOP_GPWR); scoop_resume()
196 devptr->base = ioremap(mem->start, resource_size(mem)); scoop_probe()
198 if (!devptr->base) { scoop_probe()
205 printk("Sharp Scoop Device found at 0x%08x -> 0x%8p\n",(unsigned int)mem->start, devptr->base); scoop_probe()
207 iowrite16(0x0140, devptr->base + SCOOP_MCR); scoop_probe()
209 iowrite16(0x0000, devptr->base + SCOOP_CPR); scoop_probe()
210 iowrite16(inf->io_dir & 0xffff, devptr->base + SCOOP_GPCR); scoop_probe()
211 iowrite16(inf->io_out & 0xffff, devptr->base + SCOOP_GPWR); scoop_probe()
216 devptr->gpio.base = -1; scoop_probe()
220 devptr->gpio.base = inf->gpio_base; scoop_probe()
237 iounmap(devptr->base); scoop_probe()
250 if (sdev->gpio.base != -1) scoop_remove()
254 iounmap(sdev->base); scoop_remove()
|
| H A D | locomo.c | 69 void __iomem *base; member in struct:locomo
84 * locomo_dev will be set to the chip base plus offset. If offset is
150 req = locomo_readl(lchip->base + LOCOMO_ICR) & 0x0f00; locomo_handler()
174 r = locomo_readl(lchip->base + LOCOMO_ICR); locomo_mask_irq()
176 locomo_writel(r, lchip->base + LOCOMO_ICR); locomo_mask_irq()
183 r = locomo_readl(lchip->base + LOCOMO_ICR); locomo_unmask_irq()
185 locomo_writel(r, lchip->base + LOCOMO_ICR); locomo_unmask_irq()
251 dev->mapbase = lchip->base + info->offset; locomo_init_one_child()
291 save->LCM_GPO = locomo_readl(lchip->base + LOCOMO_GPO); /* GPIO */ locomo_suspend()
292 locomo_writel(0x00, lchip->base + LOCOMO_GPO); locomo_suspend()
293 save->LCM_SPICT = locomo_readl(lchip->base + LOCOMO_SPI + LOCOMO_SPICT); /* SPI */ locomo_suspend()
294 locomo_writel(0x40, lchip->base + LOCOMO_SPI + LOCOMO_SPICT); locomo_suspend()
295 save->LCM_GPE = locomo_readl(lchip->base + LOCOMO_GPE); /* GPIO */ locomo_suspend()
296 locomo_writel(0x00, lchip->base + LOCOMO_GPE); locomo_suspend()
297 save->LCM_ASD = locomo_readl(lchip->base + LOCOMO_ASD); /* ADSTART */ locomo_suspend()
298 locomo_writel(0x00, lchip->base + LOCOMO_ASD); locomo_suspend()
299 save->LCM_SPIMD = locomo_readl(lchip->base + LOCOMO_SPI + LOCOMO_SPIMD); /* SPI */ locomo_suspend()
300 locomo_writel(0x3C14, lchip->base + LOCOMO_SPI + LOCOMO_SPIMD); locomo_suspend()
302 locomo_writel(0x00, lchip->base + LOCOMO_PAIF); locomo_suspend()
303 locomo_writel(0x00, lchip->base + LOCOMO_DAC); locomo_suspend()
304 locomo_writel(0x00, lchip->base + LOCOMO_BACKLIGHT + LOCOMO_TC); locomo_suspend()
306 if ((locomo_readl(lchip->base + LOCOMO_LED + LOCOMO_LPT0) & 0x88) && (locomo_readl(lchip->base + LOCOMO_LED + LOCOMO_LPT1) & 0x88)) locomo_suspend()
307 locomo_writel(0x00, lchip->base + LOCOMO_C32K); /* CLK32 off */ locomo_suspend()
310 locomo_writel(0xc1, lchip->base + LOCOMO_C32K); /* CLK32 on */ locomo_suspend()
312 locomo_writel(0x00, lchip->base + LOCOMO_TADC); /* 18MHz clock off*/ locomo_suspend()
313 locomo_writel(0x00, lchip->base + LOCOMO_AUDIO + LOCOMO_ACC); /* 22MHz/24MHz clock off */ locomo_suspend()
314 locomo_writel(0x00, lchip->base + LOCOMO_FRONTLIGHT + LOCOMO_ALS); /* FL */ locomo_suspend()
334 locomo_writel(save->LCM_GPO, lchip->base + LOCOMO_GPO); locomo_resume()
335 locomo_writel(save->LCM_SPICT, lchip->base + LOCOMO_SPI + LOCOMO_SPICT); locomo_resume()
336 locomo_writel(save->LCM_GPE, lchip->base + LOCOMO_GPE); locomo_resume()
337 locomo_writel(save->LCM_ASD, lchip->base + LOCOMO_ASD); locomo_resume()
338 locomo_writel(save->LCM_SPIMD, lchip->base + LOCOMO_SPI + LOCOMO_SPIMD); locomo_resume()
340 locomo_writel(0x00, lchip->base + LOCOMO_C32K); locomo_resume()
341 locomo_writel(0x90, lchip->base + LOCOMO_TADC); locomo_resume()
343 locomo_writel(0, lchip->base + LOCOMO_KEYBOARD + LOCOMO_KSC); locomo_resume()
344 r = locomo_readl(lchip->base + LOCOMO_KEYBOARD + LOCOMO_KIC); locomo_resume()
346 locomo_writel(r, lchip->base + LOCOMO_KEYBOARD + LOCOMO_KIC); locomo_resume()
347 locomo_writel(0x1, lchip->base + LOCOMO_KEYBOARD + LOCOMO_KCMD); locomo_resume()
396 lchip->base = ioremap(mem->start, PAGE_SIZE); __locomo_probe()
397 if (!lchip->base) { __locomo_probe()
403 locomo_writel(0, lchip->base + LOCOMO_ICR); __locomo_probe()
405 locomo_writel(0, lchip->base + LOCOMO_KEYBOARD + LOCOMO_KIC); __locomo_probe()
408 locomo_writel(0, lchip->base + LOCOMO_GPO); __locomo_probe()
410 , lchip->base + LOCOMO_GPE); __locomo_probe()
412 , lchip->base + LOCOMO_GPD); __locomo_probe()
413 locomo_writel(0, lchip->base + LOCOMO_GIE); __locomo_probe()
416 locomo_writel(0, lchip->base + LOCOMO_FRONTLIGHT + LOCOMO_ALS); __locomo_probe()
417 locomo_writel(0, lchip->base + LOCOMO_FRONTLIGHT + LOCOMO_ALD); __locomo_probe()
420 locomo_writel(0, lchip->base + LOCOMO_LTINT); __locomo_probe()
422 locomo_writel(0, lchip->base + LOCOMO_SPI + LOCOMO_SPIIE); __locomo_probe()
424 locomo_writel(6 + 8 + 320 + 30 - 10, lchip->base + LOCOMO_ASD); __locomo_probe()
425 r = locomo_readl(lchip->base + LOCOMO_ASD); __locomo_probe()
427 locomo_writel(r, lchip->base + LOCOMO_ASD); __locomo_probe()
429 locomo_writel(6 + 8 + 320 + 30 - 10 - 128 + 4, lchip->base + LOCOMO_HSD); __locomo_probe()
430 r = locomo_readl(lchip->base + LOCOMO_HSD); __locomo_probe()
432 locomo_writel(r, lchip->base + LOCOMO_HSD); __locomo_probe()
434 locomo_writel(128 / 8, lchip->base + LOCOMO_HSC); __locomo_probe()
437 locomo_writel(0x80, lchip->base + LOCOMO_TADC); __locomo_probe()
440 r = locomo_readl(lchip->base + LOCOMO_TADC); __locomo_probe()
442 locomo_writel(r, lchip->base + LOCOMO_TADC); __locomo_probe()
446 r = locomo_readl(lchip->base + LOCOMO_DAC); __locomo_probe()
448 locomo_writel(r, lchip->base + LOCOMO_DAC); __locomo_probe()
450 r = locomo_readl(lchip->base + LOCOMO_VER); __locomo_probe()
483 iounmap(lchip->base); __locomo_remove()
552 r = locomo_readl(lchip->base + LOCOMO_GPD); locomo_gpio_set_dir()
557 locomo_writel(r, lchip->base + LOCOMO_GPD); locomo_gpio_set_dir()
559 r = locomo_readl(lchip->base + LOCOMO_GPE); locomo_gpio_set_dir()
564 locomo_writel(r, lchip->base + LOCOMO_GPE); locomo_gpio_set_dir()
580 ret = locomo_readl(lchip->base + LOCOMO_GPL); locomo_gpio_read_level()
598 ret = locomo_readl(lchip->base + LOCOMO_GPO); locomo_gpio_read_output()
617 r = locomo_readl(lchip->base + LOCOMO_GPO); locomo_gpio_write()
622 locomo_writel(r, lchip->base + LOCOMO_GPO); locomo_gpio_write()
669 void *mapbase = lchip->base; locomo_m62332_senddata()
808 locomo_writel(bpwf, lchip->base + LOCOMO_FRONTLIGHT + LOCOMO_ALS); locomo_frontlight_set()
810 locomo_writel(duty, lchip->base + LOCOMO_FRONTLIGHT + LOCOMO_ALD); locomo_frontlight_set()
811 locomo_writel(bpwf | LOCOMO_ALC_EN, lchip->base + LOCOMO_FRONTLIGHT + LOCOMO_ALS); locomo_frontlight_set()
|
| /linux-4.4.14/drivers/gpio/ |
| H A D | gpio-zx.c | 42 void __iomem *base; member in struct:zx_gpio
61 gpiodir = readw_relaxed(chip->base + ZX_GPIO_DIR); zx_direction_input()
63 writew_relaxed(gpiodir, chip->base + ZX_GPIO_DIR); zx_direction_input()
80 gpiodir = readw_relaxed(chip->base + ZX_GPIO_DIR); zx_direction_output()
82 writew_relaxed(gpiodir, chip->base + ZX_GPIO_DIR); zx_direction_output()
85 writew_relaxed(BIT(offset), chip->base + ZX_GPIO_DO1); zx_direction_output()
87 writew_relaxed(BIT(offset), chip->base + ZX_GPIO_DO0); zx_direction_output()
97 return !!(readw_relaxed(chip->base + ZX_GPIO_DI) & BIT(offset)); zx_get_value()
105 writew_relaxed(BIT(offset), chip->base + ZX_GPIO_DO1); zx_set_value()
107 writew_relaxed(BIT(offset), chip->base + ZX_GPIO_DO0); zx_set_value()
124 gpioiev = readw_relaxed(chip->base + ZX_GPIO_IV); zx_irq_type()
125 gpiois = readw_relaxed(chip->base + ZX_GPIO_IVE); zx_irq_type()
126 gpioi_epos = readw_relaxed(chip->base + ZX_GPIO_IEP); zx_irq_type()
127 gpioi_eneg = readw_relaxed(chip->base + ZX_GPIO_IEN); zx_irq_type()
151 writew_relaxed(gpiois, chip->base + ZX_GPIO_IVE); zx_irq_type()
152 writew_relaxed(gpioi_epos, chip->base + ZX_GPIO_IEP); zx_irq_type()
153 writew_relaxed(gpioi_eneg, chip->base + ZX_GPIO_IEN); zx_irq_type()
154 writew_relaxed(gpioiev, chip->base + ZX_GPIO_IV); zx_irq_type()
170 pending = readw_relaxed(chip->base + ZX_GPIO_MIS); zx_irq_handler()
171 writew_relaxed(pending, chip->base + ZX_GPIO_IC); zx_irq_handler()
189 gpioie = readw_relaxed(chip->base + ZX_GPIO_IM) | mask; zx_irq_mask()
190 writew_relaxed(gpioie, chip->base + ZX_GPIO_IM); zx_irq_mask()
191 gpioie = readw_relaxed(chip->base + ZX_GPIO_IE) & ~mask; zx_irq_mask()
192 writew_relaxed(gpioie, chip->base + ZX_GPIO_IE); zx_irq_mask()
204 gpioie = readw_relaxed(chip->base + ZX_GPIO_IM) & ~mask; zx_irq_unmask()
205 writew_relaxed(gpioie, chip->base + ZX_GPIO_IM); zx_irq_unmask()
206 gpioie = readw_relaxed(chip->base + ZX_GPIO_IE) | mask; zx_irq_unmask()
207 writew_relaxed(gpioie, chip->base + ZX_GPIO_IE); zx_irq_unmask()
230 chip->base = devm_ioremap_resource(dev, res); zx_gpio_probe()
231 if (IS_ERR(chip->base)) zx_gpio_probe()
232 return PTR_ERR(chip->base); zx_gpio_probe()
245 chip->gc.base = ZX_GPIO_NR * id; zx_gpio_probe()
258 writew_relaxed(0xffff, chip->base + ZX_GPIO_IM); zx_gpio_probe()
259 writew_relaxed(0, chip->base + ZX_GPIO_IE); zx_gpio_probe()
|
| H A D | gpio-samsung.c | 46 void __iomem *reg = chip->base + 0x08; samsung_gpio_setpull_updown()
61 void __iomem *reg = chip->base + 0x08; samsung_gpio_getpull_updown()
115 void __iomem *reg = chip->base + 0x08; s3c24xx_gpio_setpull_1()
133 void __iomem *reg = chip->base + 0x08; s3c24xx_gpio_getpull_1()
181 void __iomem *reg = chip->base; samsung_gpio_setcfg_2bit()
216 con = __raw_readl(chip->base); samsung_gpio_getcfg_2bit()
244 void __iomem *reg = chip->base; samsung_gpio_setcfg_4bit()
279 void __iomem *reg = chip->base; samsung_gpio_getcfg_4bit()
309 void __iomem *reg = chip->base; s3c24xx_gpio_setcfg_abank()
349 con = __raw_readl(chip->base); s3c24xx_gpio_getcfg_abank()
424 * base + 0x00: Control register, 2 bits per gpio
427 * base + 0x04: Data register, 1 bit per gpio
434 void __iomem *base = ourchip->base; samsung_gpiolib_2bit_input() local
440 con = __raw_readl(base + 0x00); samsung_gpiolib_2bit_input()
443 __raw_writel(con, base + 0x00); samsung_gpiolib_2bit_input()
453 void __iomem *base = ourchip->base; samsung_gpiolib_2bit_output() local
460 dat = __raw_readl(base + 0x04); samsung_gpiolib_2bit_output()
464 __raw_writel(dat, base + 0x04); samsung_gpiolib_2bit_output()
466 con = __raw_readl(base + 0x00); samsung_gpiolib_2bit_output()
470 __raw_writel(con, base + 0x00); samsung_gpiolib_2bit_output()
471 __raw_writel(dat, base + 0x04); samsung_gpiolib_2bit_output()
482 * base + 0x00: Control register, 4 bits per gpio
485 * base + 0x04: Data register, 1 bit per gpio
488 * Note, since the data register is one bit per gpio and is at base + 0x4
497 void __iomem *base = ourchip->base; samsung_gpiolib_4bit_input() local
500 con = __raw_readl(base + GPIOCON_OFF); samsung_gpiolib_4bit_input()
505 __raw_writel(con, base + GPIOCON_OFF); samsung_gpiolib_4bit_input()
507 pr_debug("%s: %p: CON now %08lx\n", __func__, base, con); samsung_gpiolib_4bit_input()
516 void __iomem *base = ourchip->base; samsung_gpiolib_4bit_output() local
520 con = __raw_readl(base + GPIOCON_OFF); samsung_gpiolib_4bit_output()
524 dat = __raw_readl(base + GPIODAT_OFF); samsung_gpiolib_4bit_output()
531 __raw_writel(dat, base + GPIODAT_OFF); samsung_gpiolib_4bit_output()
532 __raw_writel(con, base + GPIOCON_OFF); samsung_gpiolib_4bit_output()
533 __raw_writel(dat, base + GPIODAT_OFF); samsung_gpiolib_4bit_output()
535 pr_debug("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat); samsung_gpiolib_4bit_output()
548 * base + 0x00: Control register, 4 bits per gpio (lower 8 GPIOs)
551 * base + 0x04: Control register, 4 bits per gpio (up to 8 additions GPIOs)
554 * base + 0x08: Data register, 1 bit per gpio
558 * routines we store the 'base + 0x4' address so that these routines see
559 * the data register at ourchip->base + 0x04.
566 void __iomem *base = ourchip->base; samsung_gpiolib_4bit2_input() local
567 void __iomem *regcon = base; samsung_gpiolib_4bit2_input()
579 pr_debug("%s: %p: CON %08lx\n", __func__, base, con); samsung_gpiolib_4bit2_input()
588 void __iomem *base = ourchip->base; samsung_gpiolib_4bit2_output() local
589 void __iomem *regcon = base; samsung_gpiolib_4bit2_output()
603 dat = __raw_readl(base + GPIODAT_OFF); samsung_gpiolib_4bit2_output()
610 __raw_writel(dat, base + GPIODAT_OFF); samsung_gpiolib_4bit2_output()
612 __raw_writel(dat, base + GPIODAT_OFF); samsung_gpiolib_4bit2_output()
614 pr_debug("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat); samsung_gpiolib_4bit2_output()
631 void __iomem *base = ourchip->base; s3c24xx_gpiolib_banka_output() local
638 con = __raw_readl(base + 0x00); s3c24xx_gpiolib_banka_output()
639 dat = __raw_readl(base + 0x04); s3c24xx_gpiolib_banka_output()
645 __raw_writel(dat, base + 0x04); s3c24xx_gpiolib_banka_output()
649 __raw_writel(con, base + 0x00); s3c24xx_gpiolib_banka_output()
650 __raw_writel(dat, base + 0x04); s3c24xx_gpiolib_banka_output()
661 void __iomem *base = ourchip->base; samsung_gpiolib_set() local
667 dat = __raw_readl(base + 0x04); samsung_gpiolib_set()
671 __raw_writel(dat, base + 0x04); samsung_gpiolib_set()
681 val = __raw_readl(ourchip->base + 0x04); samsung_gpiolib_get()
708 gpn = chip->chip.base; s3c_gpiolib_track()
731 BUG_ON(!chip->base); samsung_gpiolib_add()
762 int nr_chips, void __iomem *base) s3c24xx_gpiolib_add_chips()
769 if (chip->chip.base >= S3C_GPIO_END) s3c24xx_gpiolib_add_chips()
776 if ((base != NULL) && (chip->base == NULL)) s3c24xx_gpiolib_add_chips()
777 chip->base = base + ((i) * 0x10); s3c24xx_gpiolib_add_chips()
789 int nr_chips, void __iomem *base, samsung_gpiolib_add_2bit_chips()
802 if ((base != NULL) && (chip->base == NULL)) samsung_gpiolib_add_2bit_chips()
803 chip->base = base + ((i) * offset); samsung_gpiolib_add_2bit_chips()
826 int nr_chips, void __iomem *base) samsung_gpiolib_add_4bit_chips()
838 if ((base != NULL) && (chip->base == NULL)) samsung_gpiolib_add_4bit_chips()
839 chip->base = base + ((i) * 0x20); samsung_gpiolib_add_4bit_chips()
904 .base = S3C2410_GPA(0),
913 .base = S3C2410_GPB(0),
920 .base = S3C2410_GPC(0),
927 .base = S3C2410_GPD(0),
934 .base = S3C2410_GPE(0),
941 .base = S3C2410_GPF(0),
950 .base = S3C2410_GPG(0),
958 .base = S3C2410_GPH(0),
966 .base = S3C2440_GPJCON,
968 .base = S3C2410_GPJ(0),
974 .base = S3C2443_GPKCON,
976 .base = S3C2410_GPK(0),
982 .base = S3C2443_GPLCON,
984 .base = S3C2410_GPL(0),
990 .base = S3C2443_GPMCON,
992 .base = S3C2410_GPM(0),
1031 .base = S3C64XX_GPA(0),
1037 .base = S3C64XX_GPB(0),
1043 .base = S3C64XX_GPC(0),
1049 .base = S3C64XX_GPD(0),
1056 .base = S3C64XX_GPE(0),
1061 .base = S3C64XX_GPG_BASE,
1063 .base = S3C64XX_GPG(0),
1068 .base = S3C64XX_GPM_BASE,
1071 .base = S3C64XX_GPM(0),
1083 .base = S3C64XX_GPH_BASE + 0x4,
1085 .base = S3C64XX_GPH(0),
1090 .base = S3C64XX_GPK_BASE + 0x4,
1093 .base = S3C64XX_GPK(0),
1098 .base = S3C64XX_GPL_BASE + 0x4,
1101 .base = S3C64XX_GPL(0),
1113 .base = S3C64XX_GPF_BASE,
1116 .base = S3C64XX_GPF(0),
1123 .base = S3C64XX_GPI(0),
1130 .base = S3C64XX_GPJ(0),
1137 .base = S3C64XX_GPO(0),
1144 .base = S3C64XX_GPP(0),
1151 .base = S3C64XX_GPQ(0),
1156 .base = S3C64XX_GPN_BASE,
1160 .base = S3C64XX_GPN(0),
1214 offset = pin - chip->chip.base; s3c_gpio_cfgpin()
1263 offset = pin - chip->chip.base; s3c_gpio_getcfg()
1283 offset = pin - chip->chip.base; s3c_gpio_setpull()
1301 offset = pin - chip->chip.base; s3c_gpio_getpull()
761 s3c24xx_gpiolib_add_chips(struct samsung_gpio_chip *chip, int nr_chips, void __iomem *base) s3c24xx_gpiolib_add_chips() argument
788 samsung_gpiolib_add_2bit_chips(struct samsung_gpio_chip *chip, int nr_chips, void __iomem *base, unsigned int offset) samsung_gpiolib_add_2bit_chips() argument
825 samsung_gpiolib_add_4bit_chips(struct samsung_gpio_chip *chip, int nr_chips, void __iomem *base) samsung_gpiolib_add_4bit_chips() argument
|
| H A D | gpio-moxart.c | 37 void __iomem *base; moxart_gpio_probe() local
45 base = devm_ioremap_resource(dev, res); moxart_gpio_probe()
46 if (IS_ERR(base)) moxart_gpio_probe()
47 return PTR_ERR(base); moxart_gpio_probe()
49 ret = bgpio_init(bgc, dev, 4, base + GPIO_DATA_IN, moxart_gpio_probe()
50 base + GPIO_DATA_OUT, NULL, moxart_gpio_probe()
51 base + GPIO_PIN_DIRECTION, NULL, moxart_gpio_probe()
62 bgc->gc.base = 0; moxart_gpio_probe()
|
| H A D | gpio-ath79.c | 23 void __iomem *base; member in struct:ath79_gpio_ctrl
35 __raw_writel(BIT(gpio), ctrl->base + AR71XX_GPIO_REG_SET); ath79_gpio_set_value()
37 __raw_writel(BIT(gpio), ctrl->base + AR71XX_GPIO_REG_CLEAR); ath79_gpio_set_value()
44 return (__raw_readl(ctrl->base + AR71XX_GPIO_REG_IN) >> gpio) & 1; ath79_gpio_get_value()
56 __raw_readl(ctrl->base + AR71XX_GPIO_REG_OE) & ~BIT(offset), ath79_gpio_direction_input()
57 ctrl->base + AR71XX_GPIO_REG_OE); ath79_gpio_direction_input()
73 __raw_writel(BIT(offset), ctrl->base + AR71XX_GPIO_REG_SET); ath79_gpio_direction_output()
75 __raw_writel(BIT(offset), ctrl->base + AR71XX_GPIO_REG_CLEAR); ath79_gpio_direction_output()
78 __raw_readl(ctrl->base + AR71XX_GPIO_REG_OE) | BIT(offset), ath79_gpio_direction_output()
79 ctrl->base + AR71XX_GPIO_REG_OE); ath79_gpio_direction_output()
94 __raw_readl(ctrl->base + AR71XX_GPIO_REG_OE) | BIT(offset), ar934x_gpio_direction_input()
95 ctrl->base + AR71XX_GPIO_REG_OE); ar934x_gpio_direction_input()
111 __raw_writel(BIT(offset), ctrl->base + AR71XX_GPIO_REG_SET); ar934x_gpio_direction_output()
113 __raw_writel(BIT(offset), ctrl->base + AR71XX_GPIO_REG_CLEAR); ar934x_gpio_direction_output()
116 __raw_readl(ctrl->base + AR71XX_GPIO_REG_OE) & ~BIT(offset), ar934x_gpio_direction_output()
117 ctrl->base + AR71XX_GPIO_REG_OE); ar934x_gpio_direction_output()
130 .base = 0,
173 ctrl->base = devm_ioremap_nocache( ath79_gpio_probe()
175 if (!ctrl->base) ath79_gpio_probe()
|
| H A D | gpio-pl061.c | 53 void __iomem *base; member in struct:pl061_gpio
71 gpiodir = readb(chip->base + GPIODIR); pl061_direction_input()
73 writeb(gpiodir, chip->base + GPIODIR); pl061_direction_input()
90 writeb(!!value << offset, chip->base + (BIT(offset + 2))); pl061_direction_output()
91 gpiodir = readb(chip->base + GPIODIR); pl061_direction_output()
93 writeb(gpiodir, chip->base + GPIODIR); pl061_direction_output()
99 writeb(!!value << offset, chip->base + (BIT(offset + 2))); pl061_direction_output()
109 return !!readb(chip->base + (BIT(offset + 2))); pl061_get_value()
116 writeb(!!value << offset, chip->base + (BIT(offset + 2))); pl061_set_value()
144 gpioiev = readb(chip->base + GPIOIEV); pl061_irq_type()
145 gpiois = readb(chip->base + GPIOIS); pl061_irq_type()
146 gpioibe = readb(chip->base + GPIOIBE); pl061_irq_type()
198 writeb(gpiois, chip->base + GPIOIS); pl061_irq_type()
199 writeb(gpioibe, chip->base + GPIOIBE); pl061_irq_type()
200 writeb(gpioiev, chip->base + GPIOIEV); pl061_irq_type()
217 pending = readb(chip->base + GPIOMIS); pl061_irq_handler()
235 gpioie = readb(chip->base + GPIOIE) & ~mask; pl061_irq_mask()
236 writeb(gpioie, chip->base + GPIOIE); pl061_irq_mask()
248 gpioie = readb(chip->base + GPIOIE) | mask; pl061_irq_unmask()
249 writeb(gpioie, chip->base + GPIOIE); pl061_irq_unmask()
268 writeb(mask, chip->base + GPIOIC); pl061_irq_ack()
292 chip->gc.base = pdata->gpio_base; pl061_probe()
295 dev_err(&adev->dev, "invalid IRQ base in pdata\n"); pl061_probe()
299 chip->gc.base = -1; pl061_probe()
303 chip->base = devm_ioremap_resource(dev, &adev->res); pl061_probe()
304 if (IS_ERR(chip->base)) pl061_probe()
305 return PTR_ERR(chip->base); pl061_probe()
329 writeb(0, chip->base + GPIOIE); /* disable irqs */ pl061_probe()
370 chip->csave_regs.gpio_dir = readb(chip->base + GPIODIR); pl061_suspend()
371 chip->csave_regs.gpio_is = readb(chip->base + GPIOIS); pl061_suspend()
372 chip->csave_regs.gpio_ibe = readb(chip->base + GPIOIBE); pl061_suspend()
373 chip->csave_regs.gpio_iev = readb(chip->base + GPIOIEV); pl061_suspend()
374 chip->csave_regs.gpio_ie = readb(chip->base + GPIOIE); pl061_suspend()
399 writeb(chip->csave_regs.gpio_is, chip->base + GPIOIS); pl061_resume()
400 writeb(chip->csave_regs.gpio_ibe, chip->base + GPIOIBE); pl061_resume()
401 writeb(chip->csave_regs.gpio_iev, chip->base + GPIOIEV); pl061_resume()
402 writeb(chip->csave_regs.gpio_ie, chip->base + GPIOIE); pl061_resume()
|
| /linux-4.4.14/drivers/leds/ |
| H A D | leds-versatile.c | 17 void __iomem *base; member in struct:versatile_led
45 u32 reg = readl(led->base); versatile_led_set()
51 writel(reg, led->base); versatile_led_set()
58 u32 reg = readl(led->base); versatile_led_get()
67 void __iomem *base; versatile_leds_probe() local
70 base = devm_ioremap_resource(&dev->dev, res); versatile_leds_probe()
71 if (IS_ERR(base)) versatile_leds_probe()
72 return PTR_ERR(base); versatile_leds_probe()
75 writel(0, base); versatile_leds_probe()
83 led->base = base; versatile_leds_probe()
|
| /linux-4.4.14/arch/x86/kernel/cpu/mtrr/ |
| H A D | if.c | 38 mtrr_file_add(unsigned long base, unsigned long size, mtrr_file_add() argument
52 if ((base & (PAGE_SIZE - 1)) || (size & (PAGE_SIZE - 1))) mtrr_file_add()
54 base >>= PAGE_SHIFT; mtrr_file_add()
57 reg = mtrr_add_page(base, size, type, true); mtrr_file_add()
64 mtrr_file_del(unsigned long base, unsigned long size, mtrr_file_del() argument
71 if ((base & (PAGE_SIZE - 1)) || (size & (PAGE_SIZE - 1))) mtrr_file_del()
73 base >>= PAGE_SHIFT; mtrr_file_del()
76 reg = mtrr_del_page(-1, base, size); mtrr_file_del()
91 * "base=%Lx size=%Lx type=%s" or "disable=%d"
98 unsigned long long base, size; mtrr_write() local
134 if (strncmp(line, "base=", 5)) mtrr_write()
137 base = simple_strtoull(line + 5, &ptr, 0); mtrr_write()
144 if ((base & 0xfff) || (size & 0xfff)) mtrr_write()
155 base >>= PAGE_SHIFT; mtrr_write()
157 err = mtrr_add_page((unsigned long)base, (unsigned long)size, i, true); mtrr_write()
170 unsigned long base; mtrr_ioctl() local
205 err = get_user(sentry.base, &s32->base); mtrr_ioctl()
218 err |= get_user(gentry.base, &g32->base); mtrr_ioctl()
238 mtrr_file_add(sentry.base, sentry.size, sentry.type, true, mtrr_ioctl()
247 err = mtrr_add(sentry.base, sentry.size, sentry.type, false); mtrr_ioctl()
255 err = mtrr_file_del(sentry.base, sentry.size, file, 0); mtrr_ioctl()
263 err = mtrr_del(-1, sentry.base, sentry.size); mtrr_ioctl()
271 mtrr_if->get(gentry.regnum, &base, &size, &type); mtrr_ioctl()
274 if (base + size - 1 >= (1UL << (8 * sizeof(gentry.size) - PAGE_SHIFT)) mtrr_ioctl()
276 gentry.base = gentry.size = gentry.type = 0; mtrr_ioctl()
278 gentry.base = base << PAGE_SHIFT; mtrr_ioctl()
291 mtrr_file_add(sentry.base, sentry.size, sentry.type, true, mtrr_ioctl()
301 mtrr_add_page(sentry.base, sentry.size, sentry.type, false); mtrr_ioctl()
309 err = mtrr_file_del(sentry.base, sentry.size, file, 1); mtrr_ioctl()
317 err = mtrr_del_page(-1, sentry.base, sentry.size); mtrr_ioctl()
325 mtrr_if->get(gentry.regnum, &base, &size, &type); mtrr_ioctl()
328 gentry.base = gentry.size = gentry.type = 0; mtrr_ioctl()
330 gentry.base = base; mtrr_ioctl()
352 err = put_user(gentry.base, &g32->base); mtrr_ioctl()
409 unsigned long base, size; mtrr_seq_show() local
413 mtrr_if->get(i, &base, &size, &type); mtrr_seq_show()
427 seq_printf(seq, "reg%02i: base=0x%06lx000 (%5luMB), size=%5lu%cB, count=%d: %s\n", mtrr_seq_show()
428 i, base, base >> (20 - PAGE_SHIFT), mtrr_seq_show()
|
| /linux-4.4.14/drivers/of/ |
| H A D | of_reserved_mem.c | 35 phys_addr_t base; early_init_dt_alloc_reserved_memory_arch() local
41 base = __memblock_alloc_base(size, align, end); early_init_dt_alloc_reserved_memory_arch()
42 if (!base) early_init_dt_alloc_reserved_memory_arch()
48 if (base < start) { early_init_dt_alloc_reserved_memory_arch()
49 memblock_free(base, size); early_init_dt_alloc_reserved_memory_arch()
53 *res_base = base; early_init_dt_alloc_reserved_memory_arch()
55 return memblock_remove(base, size); early_init_dt_alloc_reserved_memory_arch()
73 phys_addr_t base, phys_addr_t size) fdt_reserved_mem_save_node()
84 rmem->base = base; fdt_reserved_mem_save_node()
100 phys_addr_t base = 0, align = 0, size; __reserved_mem_alloc_size() local
142 base = 0; __reserved_mem_alloc_size()
150 align, start, end, nomap, &base); __reserved_mem_alloc_size()
152 pr_debug("Reserved memory: allocated memory for '%s' node: base %pa, size %ld MiB\n", __reserved_mem_alloc_size()
153 uname, &base, __reserved_mem_alloc_size()
162 0, 0, nomap, &base); __reserved_mem_alloc_size()
164 pr_debug("Reserved memory: allocated memory for '%s' node: base %pa, size %ld MiB\n", __reserved_mem_alloc_size()
165 uname, &base, (unsigned long)size / SZ_1M); __reserved_mem_alloc_size()
168 if (base == 0) { __reserved_mem_alloc_size()
174 *res_base = base; __reserved_mem_alloc_size()
211 if (ra->base < rb->base) __rmem_cmp()
214 if (ra->base > rb->base) __rmem_cmp()
234 if (!(this->base && next->base)) __rmem_check_for_overlap()
236 if (this->base + this->size > next->base) { __rmem_check_for_overlap()
239 this_end = this->base + this->size; __rmem_check_for_overlap()
240 next_end = next->base + next->size; __rmem_check_for_overlap()
242 this->name, &this->base, &this_end, __rmem_check_for_overlap()
243 next->name, &next->base, &next_end); __rmem_check_for_overlap()
273 &rmem->base, &rmem->size); fdt_init_reserved_mem()
72 fdt_reserved_mem_save_node(unsigned long node, const char *uname, phys_addr_t base, phys_addr_t size) fdt_reserved_mem_save_node() argument
|
| /linux-4.4.14/drivers/gpu/drm/ttm/ |
| H A D | ttm_object.c | 56 * for fast lookup of ref objects given a base object.
114 * that way, one can easily detect whether a base object is referenced by
116 * multiple ref objects if a ttm_object_file references the same base
158 struct ttm_base_object *base, ttm_base_object_init()
168 base->shareable = shareable; ttm_base_object_init()
169 base->tfile = ttm_object_file_ref(tfile); ttm_base_object_init()
170 base->refcount_release = refcount_release; ttm_base_object_init()
171 base->ref_obj_release = ref_obj_release; ttm_base_object_init()
172 base->object_type = object_type; ttm_base_object_init()
173 kref_init(&base->refcount); ttm_base_object_init()
176 &base->hash, ttm_base_object_init()
177 (unsigned long)base, 31, 0, 0); ttm_base_object_init()
182 ret = ttm_ref_object_add(tfile, base, TTM_REF_USAGE, NULL); ttm_base_object_init()
186 ttm_base_object_unref(&base); ttm_base_object_init()
191 (void)drm_ht_remove_item_rcu(&tdev->object_hash, &base->hash); ttm_base_object_init()
200 struct ttm_base_object *base = ttm_release_base() local
202 struct ttm_object_device *tdev = base->tfile->tdev; ttm_release_base()
205 (void)drm_ht_remove_item_rcu(&tdev->object_hash, &base->hash); ttm_release_base()
214 ttm_object_file_unref(&base->tfile); ttm_release_base()
215 if (base->refcount_release) ttm_release_base()
216 base->refcount_release(&base); ttm_release_base()
221 struct ttm_base_object *base = *p_base; ttm_base_object_unref() local
225 kref_put(&base->refcount, ttm_release_base); ttm_base_object_unref()
232 struct ttm_base_object *base = NULL; ttm_base_object_lookup() local
241 base = drm_hash_entry(hash, struct ttm_ref_object, hash)->obj; ttm_base_object_lookup()
242 if (!kref_get_unless_zero(&base->refcount)) ttm_base_object_lookup()
243 base = NULL; ttm_base_object_lookup()
247 return base; ttm_base_object_lookup()
254 struct ttm_base_object *base = NULL; ttm_base_object_lookup_for_ref() local
263 base = drm_hash_entry(hash, struct ttm_base_object, hash); ttm_base_object_lookup_for_ref()
264 if (!kref_get_unless_zero(&base->refcount)) ttm_base_object_lookup_for_ref()
265 base = NULL; ttm_base_object_lookup_for_ref()
269 return base; ttm_base_object_lookup_for_ref()
275 * (has opened) a base object.
278 * @base: Pointer to a struct base object.
281 * reference object on the base object identified by @base.
284 struct ttm_base_object *base) ttm_ref_object_exists()
291 if (unlikely(drm_ht_find_item_rcu(ht, base->hash.key, &hash) != 0)) ttm_ref_object_exists()
295 * Verify that the ref object is really pointing to our base object. ttm_ref_object_exists()
296 * Our base object could actually be dead, and the ref object pointing ttm_ref_object_exists()
297 * to another base object with the same handle. ttm_ref_object_exists()
300 if (unlikely(base != ref->obj)) ttm_ref_object_exists()
320 struct ttm_base_object *base, ttm_ref_object_add()
329 if (base->tfile != tfile && !base->shareable) ttm_ref_object_add()
337 ret = drm_ht_find_item_rcu(ht, base->hash.key, &hash); ttm_ref_object_add()
358 ref->hash.key = base->hash.key; ttm_ref_object_add()
359 ref->obj = base; ttm_ref_object_add()
369 kref_get(&base->refcount); ttm_ref_object_add()
391 struct ttm_base_object *base = ref->obj; ttm_ref_object_release() local
401 if (ref->ref_type != TTM_REF_USAGE && base->ref_obj_release) ttm_ref_object_release()
402 base->ref_obj_release(base, ref->ref_type); ttm_ref_object_release()
565 * This function is called when all references to the base object we
570 struct ttm_base_object *base = *p_base; ttm_prime_refcount_release() local
574 prime = container_of(base, struct ttm_prime_object, base); ttm_prime_refcount_release()
578 prime->refcount_release(&base); ttm_prime_refcount_release()
588 * and finally releases the reference the dma_buf has on our base
595 struct ttm_base_object *base = &prime->base; ttm_prime_dmabuf_release() local
596 struct ttm_object_device *tdev = base->tfile->tdev; ttm_prime_dmabuf_release()
605 ttm_base_object_unref(&base); ttm_prime_dmabuf_release()
609 * ttm_prime_fd_to_handle - Get a base object handle from a prime fd
625 struct ttm_base_object *base; ttm_prime_fd_to_handle() local
636 base = &prime->base; ttm_prime_fd_to_handle()
637 *handle = base->hash.key; ttm_prime_fd_to_handle()
638 ret = ttm_ref_object_add(tfile, base, TTM_REF_USAGE, NULL); ttm_prime_fd_to_handle()
660 struct ttm_base_object *base; ttm_prime_handle_to_fd() local
665 base = ttm_base_object_lookup(tfile, handle); ttm_prime_handle_to_fd()
666 if (unlikely(base == NULL || ttm_prime_handle_to_fd()
667 base->object_type != ttm_prime_type)) { ttm_prime_handle_to_fd()
672 prime = container_of(base, struct ttm_prime_object, base); ttm_prime_handle_to_fd()
673 if (unlikely(!base->shareable)) { ttm_prime_handle_to_fd()
713 * dma_buf has taken the base object reference ttm_prime_handle_to_fd()
715 base = NULL; ttm_prime_handle_to_fd()
728 if (base) ttm_prime_handle_to_fd()
729 ttm_base_object_unref(&base); ttm_prime_handle_to_fd()
760 return ttm_base_object_init(tfile, &prime->base, shareable, ttm_prime_object_init()
157 ttm_base_object_init(struct ttm_object_file *tfile, struct ttm_base_object *base, bool shareable, enum ttm_object_type object_type, void (*refcount_release) (struct ttm_base_object **), void (*ref_obj_release) (struct ttm_base_object *, enum ttm_ref_type ref_type)) ttm_base_object_init() argument
283 ttm_ref_object_exists(struct ttm_object_file *tfile, struct ttm_base_object *base) ttm_ref_object_exists() argument
319 ttm_ref_object_add(struct ttm_object_file *tfile, struct ttm_base_object *base, enum ttm_ref_type ref_type, bool *existed) ttm_ref_object_add() argument
|
| /linux-4.4.14/net/sunrpc/ |
| H A D | socklib.c | 67 * @base: starting offset
72 ssize_t xdr_partial_copy_from_skb(struct xdr_buf *xdr, unsigned int base, struct xdr_skb_reader *desc, xdr_skb_read_actor copy_actor) xdr_partial_copy_from_skb() argument
80 if (base < len) { xdr_partial_copy_from_skb()
81 len -= base; xdr_partial_copy_from_skb()
82 ret = copy_actor(desc, (char *)xdr->head[0].iov_base + base, len); xdr_partial_copy_from_skb()
86 base = 0; xdr_partial_copy_from_skb()
88 base -= len; xdr_partial_copy_from_skb()
92 if (unlikely(base >= pglen)) { xdr_partial_copy_from_skb()
93 base -= pglen; xdr_partial_copy_from_skb()
96 if (base || xdr->page_base) { xdr_partial_copy_from_skb()
97 pglen -= base; xdr_partial_copy_from_skb()
98 base += xdr->page_base; xdr_partial_copy_from_skb()
99 ppage += base >> PAGE_CACHE_SHIFT; xdr_partial_copy_from_skb()
100 base &= ~PAGE_CACHE_MASK; xdr_partial_copy_from_skb()
118 if (base) { xdr_partial_copy_from_skb()
119 len -= base; xdr_partial_copy_from_skb()
122 ret = copy_actor(desc, kaddr + base, len); xdr_partial_copy_from_skb()
123 base = 0; xdr_partial_copy_from_skb()
138 if (base < len) xdr_partial_copy_from_skb()
139 copied += copy_actor(desc, (char *)xdr->tail[0].iov_base + base, len - base); xdr_partial_copy_from_skb()
|
| /linux-4.4.14/drivers/video/fbdev/matrox/ |
| H A D | matroxfb_crtc2.h | 15 unsigned long base; /* physical */ member in struct:matroxfb_dh_fb_info::__anon11167
24 unsigned long base; member in struct:matroxfb_dh_fb_info::__anon11168
|
| /linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/subdev/bar/ |
| H A D | gf100.h | 3 #define gf100_bar(p) container_of((p), struct gf100_bar, base)
13 struct nvkm_bar base; member in struct:gf100_bar
|
| /linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/ |
| H A D | nv04.h | 3 #define nv04_mmu(p) container_of((p), struct nv04_mmu, base)
7 struct nvkm_mmu base; member in struct:nv04_mmu
|
| /linux-4.4.14/drivers/gpu/drm/nouveau/include/nvkm/core/ |
| H A D | oproxy.h | 3 #define nvkm_oproxy(p) container_of((p), struct nvkm_oproxy, base)
8 struct nvkm_object base; member in struct:nvkm_oproxy
|
| /linux-4.4.14/drivers/clk/mmp/ |
| H A D | clk-apmu.c | 23 void __iomem *base; member in struct:clk_apmu
38 data = readl_relaxed(apmu->base) | apmu->enable_mask; clk_apmu_enable()
39 writel_relaxed(data, apmu->base); clk_apmu_enable()
56 data = readl_relaxed(apmu->base) & ~apmu->enable_mask; clk_apmu_disable()
57 writel_relaxed(data, apmu->base); clk_apmu_disable()
69 void __iomem *base, u32 enable_mask, spinlock_t *lock) mmp_clk_register_apmu()
85 apmu->base = base; mmp_clk_register_apmu()
68 mmp_clk_register_apmu(const char *name, const char *parent_name, void __iomem *base, u32 enable_mask, spinlock_t *lock) mmp_clk_register_apmu() argument
|
| H A D | clk-apbc.c | 29 void __iomem *base; member in struct:clk_apbc
48 data = readl_relaxed(apbc->base); clk_apbc_prepare()
52 writel_relaxed(data, apbc->base); clk_apbc_prepare()
62 data = readl_relaxed(apbc->base); clk_apbc_prepare()
64 writel_relaxed(data, apbc->base); clk_apbc_prepare()
75 data = readl_relaxed(apbc->base); clk_apbc_prepare()
77 writel_relaxed(data, apbc->base); clk_apbc_prepare()
95 data = readl_relaxed(apbc->base); clk_apbc_unprepare()
99 writel_relaxed(data, apbc->base); clk_apbc_unprepare()
109 data = readl_relaxed(apbc->base); clk_apbc_unprepare()
111 writel_relaxed(data, apbc->base); clk_apbc_unprepare()
123 void __iomem *base, unsigned int delay, mmp_clk_register_apbc()
140 apbc->base = base; mmp_clk_register_apbc()
122 mmp_clk_register_apbc(const char *name, const char *parent_name, void __iomem *base, unsigned int delay, unsigned int apbc_flags, spinlock_t *lock) mmp_clk_register_apbc() argument
|
| /linux-4.4.14/arch/c6x/kernel/ |
| H A D | devicetree.c | 15 void __init early_init_dt_add_memory_arch(u64 base, u64 size) early_init_dt_add_memory_arch() argument
17 c6x_add_memory(base, size); early_init_dt_add_memory_arch()
|
| /linux-4.4.14/drivers/spi/ |
| H A D | spi-sirf.c | 256 void __iomem *base; member in struct:sirfsoc_spi
307 writel(readl(sspi->base + sspi->regs->usp_mode1) & sirfsoc_usp_hwinit()
308 ~SIRFSOC_USP_EN, sspi->base + sspi->regs->usp_mode1); sirfsoc_usp_hwinit()
309 writel(readl(sspi->base + sspi->regs->usp_mode1) | sirfsoc_usp_hwinit()
310 SIRFSOC_USP_EN, sspi->base + sspi->regs->usp_mode1); sirfsoc_usp_hwinit()
318 data = readl(sspi->base + sspi->regs->rxfifo_data); spi_sirfsoc_rx_word_u8()
337 writel(data, sspi->base + sspi->regs->txfifo_data); spi_sirfsoc_tx_word_u8()
346 data = readl(sspi->base + sspi->regs->rxfifo_data); spi_sirfsoc_rx_word_u16()
366 writel(data, sspi->base + sspi->regs->txfifo_data); spi_sirfsoc_tx_word_u16()
375 data = readl(sspi->base + sspi->regs->rxfifo_data); spi_sirfsoc_rx_word_u32()
396 writel(data, sspi->base + sspi->regs->txfifo_data); spi_sirfsoc_tx_word_u32()
405 spi_stat = readl(sspi->base + sspi->regs->int_st); spi_sirfsoc_irq()
409 writel(0x0, sspi->base + sspi->regs->int_en); spi_sirfsoc_irq()
410 writel(readl(sspi->base + sspi->regs->int_st), spi_sirfsoc_irq()
411 sspi->base + sspi->regs->int_st); spi_sirfsoc_irq()
422 writel(0x0, sspi->base + sspi->regs->int_en); spi_sirfsoc_irq()
425 writel(~0UL, sspi->base + sspi->regs->usp_int_en_clr); spi_sirfsoc_irq()
428 writel(readl(sspi->base + sspi->regs->int_st), spi_sirfsoc_irq()
429 sspi->base + sspi->regs->int_st); spi_sirfsoc_irq()
434 while (!(readl(sspi->base + sspi->regs->int_st) & spi_sirfsoc_irq()
441 writel(0x0, sspi->base + sspi->regs->int_en); spi_sirfsoc_irq()
444 writel(~0UL, sspi->base + sspi->regs->usp_int_en_clr); spi_sirfsoc_irq()
447 writel(readl(sspi->base + sspi->regs->int_st), spi_sirfsoc_irq()
448 sspi->base + sspi->regs->int_st); spi_sirfsoc_irq()
468 writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + sspi->regs->txfifo_op); spi_sirfsoc_cmd_transfer()
469 writel(SIRFSOC_SPI_FIFO_START, sspi->base + sspi->regs->txfifo_op); spi_sirfsoc_cmd_transfer()
477 writel(cmd, sspi->base + sspi->regs->spi_cmd); spi_sirfsoc_cmd_transfer()
479 sspi->base + sspi->regs->int_en); spi_sirfsoc_cmd_transfer()
481 sspi->base + sspi->regs->tx_rx_en); spi_sirfsoc_cmd_transfer()
497 writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + sspi->regs->rxfifo_op); spi_sirfsoc_dma_transfer()
498 writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + sspi->regs->txfifo_op); spi_sirfsoc_dma_transfer()
502 sspi->base + sspi->regs->rxfifo_op); spi_sirfsoc_dma_transfer()
504 sspi->base + sspi->regs->txfifo_op); spi_sirfsoc_dma_transfer()
505 writel(0, sspi->base + sspi->regs->int_en); spi_sirfsoc_dma_transfer()
508 writel(0x0, sspi->base + sspi->regs->rxfifo_op); spi_sirfsoc_dma_transfer()
509 writel(0x0, sspi->base + sspi->regs->txfifo_op); spi_sirfsoc_dma_transfer()
510 writel(0, sspi->base + sspi->regs->int_en); spi_sirfsoc_dma_transfer()
513 writel(0x0, sspi->base + sspi->regs->rxfifo_op); spi_sirfsoc_dma_transfer()
514 writel(0x0, sspi->base + sspi->regs->txfifo_op); spi_sirfsoc_dma_transfer()
515 writel(~0UL, sspi->base + sspi->regs->usp_int_en_clr); spi_sirfsoc_dma_transfer()
518 writel(readl(sspi->base + sspi->regs->int_st), spi_sirfsoc_dma_transfer()
519 sspi->base + sspi->regs->int_st); spi_sirfsoc_dma_transfer()
523 writel(readl(sspi->base + sspi->regs->spi_ctrl) | spi_sirfsoc_dma_transfer()
526 sspi->base + sspi->regs->spi_ctrl); spi_sirfsoc_dma_transfer()
528 sspi->base + sspi->regs->tx_dma_io_len); spi_sirfsoc_dma_transfer()
530 sspi->base + sspi->regs->rx_dma_io_len); spi_sirfsoc_dma_transfer()
536 sspi->base + sspi->regs->tx_dma_io_len); spi_sirfsoc_dma_transfer()
538 sspi->base + sspi->regs->rx_dma_io_len); spi_sirfsoc_dma_transfer()
543 writel(readl(sspi->base + sspi->regs->spi_ctrl), spi_sirfsoc_dma_transfer()
544 sspi->base + sspi->regs->spi_ctrl); spi_sirfsoc_dma_transfer()
545 writel(0, sspi->base + sspi->regs->tx_dma_io_len); spi_sirfsoc_dma_transfer()
546 writel(0, sspi->base + sspi->regs->rx_dma_io_len); spi_sirfsoc_dma_transfer()
571 sspi->base + sspi->regs->tx_rx_en); spi_sirfsoc_dma_transfer()
575 sspi->base + sspi->regs->rxfifo_op); spi_sirfsoc_dma_transfer()
577 sspi->base + sspi->regs->txfifo_op); spi_sirfsoc_dma_transfer()
593 writel(0, sspi->base + sspi->regs->tx_rx_en); spi_sirfsoc_dma_transfer()
599 writel(0, sspi->base + sspi->regs->rxfifo_op); spi_sirfsoc_dma_transfer()
600 writel(0, sspi->base + sspi->regs->txfifo_op); spi_sirfsoc_dma_transfer()
602 writel(0, sspi->base + sspi->regs->tx_rx_en); spi_sirfsoc_dma_transfer()
605 writel(0, sspi->base + sspi->regs->tx_rx_en); spi_sirfsoc_dma_transfer()
618 sspi->base + sspi->regs->rxfifo_op); spi_sirfsoc_pio_transfer()
620 sspi->base + sspi->regs->txfifo_op); spi_sirfsoc_pio_transfer()
623 writel(0x0, sspi->base + sspi->regs->rxfifo_op); spi_sirfsoc_pio_transfer()
624 writel(0x0, sspi->base + sspi->regs->txfifo_op); spi_sirfsoc_pio_transfer()
625 writel(0, sspi->base + sspi->regs->int_en); spi_sirfsoc_pio_transfer()
626 writel(readl(sspi->base + sspi->regs->int_st), spi_sirfsoc_pio_transfer()
627 sspi->base + sspi->regs->int_st); spi_sirfsoc_pio_transfer()
630 sspi->base + sspi->regs->tx_dma_io_len); spi_sirfsoc_pio_transfer()
633 sspi->base + sspi->regs->rx_dma_io_len); spi_sirfsoc_pio_transfer()
636 writel(0x0, sspi->base + sspi->regs->rxfifo_op); spi_sirfsoc_pio_transfer()
637 writel(0x0, sspi->base + sspi->regs->txfifo_op); spi_sirfsoc_pio_transfer()
638 writel(~0UL, sspi->base + sspi->regs->usp_int_en_clr); spi_sirfsoc_pio_transfer()
639 writel(readl(sspi->base + sspi->regs->int_st), spi_sirfsoc_pio_transfer()
640 sspi->base + sspi->regs->int_st); spi_sirfsoc_pio_transfer()
643 sspi->base + sspi->regs->tx_dma_io_len); spi_sirfsoc_pio_transfer()
646 sspi->base + sspi->regs->rx_dma_io_len); spi_sirfsoc_pio_transfer()
650 sspi->base + sspi->regs->rxfifo_op); spi_sirfsoc_pio_transfer()
652 sspi->base + sspi->regs->txfifo_op); spi_sirfsoc_pio_transfer()
653 writel(0, sspi->base + sspi->regs->int_en); spi_sirfsoc_pio_transfer()
654 writel(readl(sspi->base + sspi->regs->int_st), spi_sirfsoc_pio_transfer()
655 sspi->base + sspi->regs->int_st); spi_sirfsoc_pio_transfer()
656 writel(readl(sspi->base + sspi->regs->spi_ctrl) | spi_sirfsoc_pio_transfer()
659 sspi->base + sspi->regs->spi_ctrl); spi_sirfsoc_pio_transfer()
662 sspi->base + sspi->regs->tx_dma_io_len); spi_sirfsoc_pio_transfer()
664 sspi->base + sspi->regs->rx_dma_io_len); spi_sirfsoc_pio_transfer()
667 while (!((readl(sspi->base + sspi->regs->txfifo_st) spi_sirfsoc_pio_transfer()
675 sspi->base + sspi->regs->int_en); spi_sirfsoc_pio_transfer()
677 sspi->base + sspi->regs->tx_rx_en); spi_sirfsoc_pio_transfer()
681 sspi->base + sspi->regs->rxfifo_op); spi_sirfsoc_pio_transfer()
683 sspi->base + sspi->regs->txfifo_op); spi_sirfsoc_pio_transfer()
690 writel(0, sspi->base + sspi->regs->tx_rx_en); spi_sirfsoc_pio_transfer()
693 while (!((readl(sspi->base + sspi->regs->rxfifo_st) spi_sirfsoc_pio_transfer()
699 writel(0, sspi->base + sspi->regs->tx_rx_en); spi_sirfsoc_pio_transfer()
700 writel(0, sspi->base + sspi->regs->rxfifo_op); spi_sirfsoc_pio_transfer()
701 writel(0, sspi->base + sspi->regs->txfifo_op); spi_sirfsoc_pio_transfer()
739 regval = readl(sspi->base + sspi->regs->spi_ctrl); spi_sirfsoc_chipselect()
754 writel(regval, sspi->base + sspi->regs->spi_ctrl); spi_sirfsoc_chipselect()
758 regval = readl(sspi->base + spi_sirfsoc_chipselect()
775 sspi->base + sspi->regs->usp_pin_io_data); spi_sirfsoc_chipselect()
798 regval = readl(sspi->base + sspi->regs->spi_ctrl); spi_sirfsoc_config_mode()
799 usp_mode1 = readl(sspi->base + sspi->regs->usp_mode1); spi_sirfsoc_config_mode()
841 sspi->base + sspi->regs->txfifo_level_chk); spi_sirfsoc_config_mode()
848 sspi->base + sspi->regs->rxfifo_level_chk); spi_sirfsoc_config_mode()
856 writel(regval, sspi->base + sspi->regs->spi_ctrl); spi_sirfsoc_config_mode()
863 writel(usp_mode1, sspi->base + sspi->regs->usp_mode1); spi_sirfsoc_config_mode()
920 writel(txfifo_ctrl, sspi->base + sspi->regs->txfifo_ctrl); spi_sirfsoc_setup_transfer()
921 writel(rxfifo_ctrl, sspi->base + sspi->regs->rxfifo_ctrl); spi_sirfsoc_setup_transfer()
948 sspi->base + sspi->regs->usp_tx_frame_ctrl); spi_sirfsoc_setup_transfer()
952 sspi->base + sspi->regs->usp_rx_frame_ctrl); spi_sirfsoc_setup_transfer()
953 writel(readl(sspi->base + sspi->regs->usp_mode2) | spi_sirfsoc_setup_transfer()
960 sspi->base + sspi->regs->usp_mode2); spi_sirfsoc_setup_transfer()
963 writel(regval, sspi->base + sspi->regs->spi_ctrl); spi_sirfsoc_setup_transfer()
969 writel(readl(sspi->base + sspi->regs->spi_ctrl) | spi_sirfsoc_setup_transfer()
972 sspi->base + sspi->regs->spi_ctrl); spi_sirfsoc_setup_transfer()
975 writel(readl(sspi->base + sspi->regs->spi_ctrl) & spi_sirfsoc_setup_transfer()
977 sspi->base + sspi->regs->spi_ctrl); spi_sirfsoc_setup_transfer()
982 writel(0, sspi->base + sspi->regs->tx_dma_io_ctrl); spi_sirfsoc_setup_transfer()
984 sspi->base + sspi->regs->rx_dma_io_ctrl); spi_sirfsoc_setup_transfer()
988 sspi->base + sspi->regs->tx_dma_io_ctrl); spi_sirfsoc_setup_transfer()
990 sspi->base + sspi->regs->rx_dma_io_ctrl); spi_sirfsoc_setup_transfer()
1102 sspi->base = devm_ioremap_resource(&pdev->dev, mem_res); spi_sirfsoc_probe()
1103 if (IS_ERR(sspi->base)) { spi_sirfsoc_probe()
1104 ret = PTR_ERR(sspi->base); spi_sirfsoc_probe()
1214 writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + sspi->regs->txfifo_op); spi_sirfsoc_resume()
1215 writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + sspi->regs->rxfifo_op); spi_sirfsoc_resume()
1216 writel(SIRFSOC_SPI_FIFO_START, sspi->base + sspi->regs->txfifo_op); spi_sirfsoc_resume()
1217 writel(SIRFSOC_SPI_FIFO_START, sspi->base + sspi->regs->rxfifo_op); spi_sirfsoc_resume()
|
| /linux-4.4.14/drivers/scsi/arm/ |
| H A D | oak.c | 24 #define NCR5380_setup(host) _base = priv(host)->base
33 void __iomem *base
46 void __iomem *base = priv(instance)->base; NCR5380_pwrite() local
54 while (((status = readw(base + STAT)) & 0x100)==0); NCR5380_pwrite()
61 void __iomem *base = priv(instance)->base; NCR5380_pread() local
70 while (((status = readw(base + STAT)) & 0x100)==0) NCR5380_pread()
82 readsw(base + DATA, addr, 128); NCR5380_pread()
88 b = (unsigned long) readw(base + DATA); NCR5380_pread()
135 priv(host)->base = ioremap(ecard_resource_start(ec, ECARD_RES_MEMC), oakscsi_probe()
137 if (!priv(host)->base) { oakscsi_probe()
155 iounmap(priv(host)->base); oakscsi_probe()
172 iounmap(priv(host)->base); oakscsi_remove()
|
| /linux-4.4.14/drivers/pcmcia/ |
| H A D | rsrc_iodyn.c | 59 unsigned long base, int num, __iodyn_find_io_region()
65 unsigned long min = base; __iodyn_find_io_region()
69 data.offset = base & data.mask; __iodyn_find_io_region()
88 unsigned int *base, unsigned int num, iodyn_find_io()
101 if (!*base) iodyn_find_io()
104 if ((s->io[i].res->start & (align-1)) == *base) iodyn_find_io()
120 res = s->io[i].res = __iodyn_find_io_region(s, *base, iodyn_find_io()
125 *base = res->start; iodyn_find_io()
136 if ((*base == 0) || (*base == try)) { iodyn_find_io()
140 *base = try; iodyn_find_io()
148 if ((*base == 0) || (*base == try)) { iodyn_find_io()
153 *base = try; iodyn_find_io()
58 __iodyn_find_io_region(struct pcmcia_socket *s, unsigned long base, int num, unsigned long align) __iodyn_find_io_region() argument
87 iodyn_find_io(struct pcmcia_socket *s, unsigned int attr, unsigned int *base, unsigned int num, unsigned int align, struct resource **parent) iodyn_find_io() argument
|
| /linux-4.4.14/drivers/pnp/pnpbios/ |
| H A D | rsparser.c | 17 #include "../base.h"
252 resource_size_t base, len; pnpbios_parse_fixed_mem32_option() local
255 base = (p[7] << 24) | (p[6] << 16) | (p[5] << 8) | p[4]; pnpbios_parse_fixed_mem32_option()
258 pnp_register_mem_resource(dev, option_flags, base, base, 0, len, flags); pnpbios_parse_fixed_mem32_option()
307 resource_size_t base, len; pnpbios_parse_fixed_port_option() local
309 base = (p[2] << 8) | p[1]; pnpbios_parse_fixed_port_option()
311 pnp_register_port_resource(dev, option_flags, base, base, 0, len, pnpbios_parse_fixed_port_option()
503 unsigned long base; pnpbios_encode_mem() local
507 base = res->start; pnpbios_encode_mem()
510 base = 0; pnpbios_encode_mem()
514 p[4] = (base >> 8) & 0xff; pnpbios_encode_mem()
515 p[5] = ((base >> 8) >> 8) & 0xff; pnpbios_encode_mem()
516 p[6] = (base >> 8) & 0xff; pnpbios_encode_mem()
517 p[7] = ((base >> 8) >> 8) & 0xff; pnpbios_encode_mem()
521 pnp_dbg(&dev->dev, " encode mem %#lx-%#lx\n", base, base + len - 1); pnpbios_encode_mem()
527 unsigned long base; pnpbios_encode_mem32() local
531 base = res->start; pnpbios_encode_mem32()
534 base = 0; pnpbios_encode_mem32()
538 p[4] = base & 0xff; pnpbios_encode_mem32()
539 p[5] = (base >> 8) & 0xff; pnpbios_encode_mem32()
540 p[6] = (base >> 16) & 0xff; pnpbios_encode_mem32()
541 p[7] = (base >> 24) & 0xff; pnpbios_encode_mem32()
542 p[8] = base & 0xff; pnpbios_encode_mem32()
543 p[9] = (base >> 8) & 0xff; pnpbios_encode_mem32()
544 p[10] = (base >> 16) & 0xff; pnpbios_encode_mem32()
545 p[11] = (base >> 24) & 0xff; pnpbios_encode_mem32()
551 pnp_dbg(&dev->dev, " encode mem32 %#lx-%#lx\n", base, base + len - 1); pnpbios_encode_mem32()
557 unsigned long base; pnpbios_encode_fixed_mem32() local
561 base = res->start; pnpbios_encode_fixed_mem32()
564 base = 0; pnpbios_encode_fixed_mem32()
568 p[4] = base & 0xff; pnpbios_encode_fixed_mem32()
569 p[5] = (base >> 8) & 0xff; pnpbios_encode_fixed_mem32()
570 p[6] = (base >> 16) & 0xff; pnpbios_encode_fixed_mem32()
571 p[7] = (base >> 24) & 0xff; pnpbios_encode_fixed_mem32()
577 pnp_dbg(&dev->dev, " encode fixed_mem32 %#lx-%#lx\n", base, pnpbios_encode_fixed_mem32()
578 base + len - 1); pnpbios_encode_fixed_mem32()
615 unsigned long base; pnpbios_encode_port() local
619 base = res->start; pnpbios_encode_port()
622 base = 0; pnpbios_encode_port()
626 p[2] = base & 0xff; pnpbios_encode_port()
627 p[3] = (base >> 8) & 0xff; pnpbios_encode_port()
628 p[4] = base & 0xff; pnpbios_encode_port()
629 p[5] = (base >> 8) & 0xff; pnpbios_encode_port()
632 pnp_dbg(&dev->dev, " encode io %#lx-%#lx\n", base, base + len - 1); pnpbios_encode_port()
638 unsigned long base = res->start; pnpbios_encode_fixed_port() local
642 base = res->start; pnpbios_encode_fixed_port()
645 base = 0; pnpbios_encode_fixed_port()
649 p[1] = base & 0xff; pnpbios_encode_fixed_port()
650 p[2] = (base >> 8) & 0xff; pnpbios_encode_fixed_port()
653 pnp_dbg(&dev->dev, " encode fixed_io %#lx-%#lx\n", base, pnpbios_encode_fixed_port()
654 base + len - 1); pnpbios_encode_fixed_port()
|
| /linux-4.4.14/drivers/devfreq/event/ |
| H A D | exynos-ppmu.c | 27 void __iomem *base; member in struct:exynos_ppmu_data
122 info->ppmu.base + PPMU_CNTENC); exynos_ppmu_disable()
125 pmnc = __raw_readl(info->ppmu.base + PPMU_PMNC); exynos_ppmu_disable()
127 __raw_writel(pmnc, info->ppmu.base + PPMU_PMNC); exynos_ppmu_disable()
142 cntens = __raw_readl(info->ppmu.base + PPMU_CNTENS); exynos_ppmu_set_event()
144 __raw_writel(cntens, info->ppmu.base + PPMU_CNTENS); exynos_ppmu_set_event()
148 info->ppmu.base + PPMU_BEVTxSEL(id)); exynos_ppmu_set_event()
151 pmnc = __raw_readl(info->ppmu.base + PPMU_PMNC); exynos_ppmu_set_event()
158 __raw_writel(pmnc, info->ppmu.base + PPMU_PMNC); exynos_ppmu_set_event()
174 pmnc = __raw_readl(info->ppmu.base + PPMU_PMNC); exynos_ppmu_get_event()
176 __raw_writel(pmnc, info->ppmu.base + PPMU_PMNC); exynos_ppmu_get_event()
179 edata->total_count = __raw_readl(info->ppmu.base + PPMU_CCNT); exynos_ppmu_get_event()
187 = __raw_readl(info->ppmu.base + PPMU_PMNCT(id)); exynos_ppmu_get_event()
191 ((__raw_readl(info->ppmu.base + PPMU_PMCNT3_HIGH) << 8) exynos_ppmu_get_event()
192 | __raw_readl(info->ppmu.base + PPMU_PMCNT3_LOW)); exynos_ppmu_get_event()
199 cntenc = __raw_readl(info->ppmu.base + PPMU_CNTENC); exynos_ppmu_get_event()
201 __raw_writel(cntenc, info->ppmu.base + PPMU_CNTENC); exynos_ppmu_get_event()
227 __raw_writel(clear, info->ppmu.base + PPMU_V2_FLAG); exynos_ppmu_v2_disable()
228 __raw_writel(clear, info->ppmu.base + PPMU_V2_INTENC); exynos_ppmu_v2_disable()
229 __raw_writel(clear, info->ppmu.base + PPMU_V2_CNTENC); exynos_ppmu_v2_disable()
230 __raw_writel(clear, info->ppmu.base + PPMU_V2_CNT_RESET); exynos_ppmu_v2_disable()
232 __raw_writel(0x0, info->ppmu.base + PPMU_V2_CIG_CFG0); exynos_ppmu_v2_disable()
233 __raw_writel(0x0, info->ppmu.base + PPMU_V2_CIG_CFG1); exynos_ppmu_v2_disable()
234 __raw_writel(0x0, info->ppmu.base + PPMU_V2_CIG_CFG2); exynos_ppmu_v2_disable()
235 __raw_writel(0x0, info->ppmu.base + PPMU_V2_CIG_RESULT); exynos_ppmu_v2_disable()
236 __raw_writel(0x0, info->ppmu.base + PPMU_V2_CNT_AUTO); exynos_ppmu_v2_disable()
237 __raw_writel(0x0, info->ppmu.base + PPMU_V2_CH_EV0_TYPE); exynos_ppmu_v2_disable()
238 __raw_writel(0x0, info->ppmu.base + PPMU_V2_CH_EV1_TYPE); exynos_ppmu_v2_disable()
239 __raw_writel(0x0, info->ppmu.base + PPMU_V2_CH_EV2_TYPE); exynos_ppmu_v2_disable()
240 __raw_writel(0x0, info->ppmu.base + PPMU_V2_CH_EV3_TYPE); exynos_ppmu_v2_disable()
241 __raw_writel(0x0, info->ppmu.base + PPMU_V2_SM_ID_V); exynos_ppmu_v2_disable()
242 __raw_writel(0x0, info->ppmu.base + PPMU_V2_SM_ID_A); exynos_ppmu_v2_disable()
243 __raw_writel(0x0, info->ppmu.base + PPMU_V2_SM_OTHERS_V); exynos_ppmu_v2_disable()
244 __raw_writel(0x0, info->ppmu.base + PPMU_V2_SM_OTHERS_A); exynos_ppmu_v2_disable()
245 __raw_writel(0x0, info->ppmu.base + PPMU_V2_INTERRUPT_RESET); exynos_ppmu_v2_disable()
248 pmnc = __raw_readl(info->ppmu.base + PPMU_V2_PMNC); exynos_ppmu_v2_disable()
250 __raw_writel(pmnc, info->ppmu.base + PPMU_V2_PMNC); exynos_ppmu_v2_disable()
262 cntens = __raw_readl(info->ppmu.base + PPMU_V2_CNTENS); exynos_ppmu_v2_set_event()
264 __raw_writel(cntens, info->ppmu.base + PPMU_V2_CNTENS); exynos_ppmu_v2_set_event()
272 info->ppmu.base + PPMU_V2_CH_EVx_TYPE(id)); exynos_ppmu_v2_set_event()
276 info->ppmu.base + PPMU_V2_CH_EVx_TYPE(id)); exynos_ppmu_v2_set_event()
281 pmnc = __raw_readl(info->ppmu.base + PPMU_V2_PMNC); exynos_ppmu_v2_set_event()
291 __raw_writel(pmnc, info->ppmu.base + PPMU_V2_PMNC); exynos_ppmu_v2_set_event()
306 pmnc = __raw_readl(info->ppmu.base + PPMU_V2_PMNC); exynos_ppmu_v2_get_event()
308 __raw_writel(pmnc, info->ppmu.base + PPMU_V2_PMNC); exynos_ppmu_v2_get_event()
311 edata->total_count = __raw_readl(info->ppmu.base + PPMU_V2_CCNT); exynos_ppmu_v2_get_event()
317 load_count = __raw_readl(info->ppmu.base + PPMU_V2_PMNCT(id)); exynos_ppmu_v2_get_event()
320 pmcnt_high = __raw_readl(info->ppmu.base + PPMU_V2_PMCNT3_HIGH); exynos_ppmu_v2_get_event()
321 pmcnt_low = __raw_readl(info->ppmu.base + PPMU_V2_PMCNT3_LOW); exynos_ppmu_v2_get_event()
329 cntenc = __raw_readl(info->ppmu.base + PPMU_V2_CNTENC); exynos_ppmu_v2_get_event()
331 __raw_writel(cntenc, info->ppmu.base + PPMU_V2_CNTENC); exynos_ppmu_v2_get_event()
431 info->ppmu.base = of_iomap(np, 0); exynos_ppmu_parse_dt()
432 if (IS_ERR_OR_NULL(info->ppmu.base)) { exynos_ppmu_parse_dt()
452 iounmap(info->ppmu.base); exynos_ppmu_parse_dt()
504 iounmap(info->ppmu.base); exynos_ppmu_probe()
514 iounmap(info->ppmu.base); exynos_ppmu_remove()
|
| /linux-4.4.14/arch/x86/platform/intel-quark/ |
| H A D | imr_selftest.c | 58 phys_addr_t base = virt_to_phys(&_text); imr_self_test() local
59 size_t size = virt_to_phys(&__end_rodata) - base; imr_self_test()
68 ret = imr_add_range(base, size, IMR_CPU, IMR_CPU, false); imr_self_test()
69 imr_self_test_result(ret < 0, fmt_over, __va(base), __va(base + size)); imr_self_test()
71 /* Test overlap with base inside of existing. */ imr_self_test()
72 base += size - IMR_ALIGN; imr_self_test()
73 ret = imr_add_range(base, size, IMR_CPU, IMR_CPU, false); imr_self_test()
74 imr_self_test_result(ret < 0, fmt_over, __va(base), __va(base + size)); imr_self_test()
77 base -= size + IMR_ALIGN * 2; imr_self_test()
78 ret = imr_add_range(base, size, IMR_CPU, IMR_CPU, false); imr_self_test()
79 imr_self_test_result(ret < 0, fmt_over, __va(base), __va(base + size)); imr_self_test()
|
| /linux-4.4.14/arch/x86/realmode/ |
| H A D | init.c | 14 unsigned char *base; reserve_real_mode() local
22 base = __va(mem); reserve_real_mode()
24 real_mode_header = (struct real_mode_header *) base; reserve_real_mode()
26 base, (unsigned long long)mem, size); reserve_real_mode()
34 unsigned char *base; setup_real_mode() local
43 base = (unsigned char *)real_mode_header; setup_real_mode()
45 memcpy(base, real_mode_blob, size); setup_real_mode()
47 phys_base = __pa(base); setup_real_mode()
55 u16 *seg = (u16 *) (base + *rel++); setup_real_mode()
62 u32 *ptr = (u32 *) (base + *rel++); setup_real_mode()
102 unsigned char *base = (unsigned char *) real_mode_header; set_real_mode_permissions() local
107 __pa(base); set_real_mode_permissions()
116 set_memory_nx((unsigned long) base, size >> PAGE_SHIFT); set_real_mode_permissions()
117 set_memory_ro((unsigned long) base, ro_size >> PAGE_SHIFT); set_real_mode_permissions()
|
| /linux-4.4.14/samples/bpf/ |
| H A D | trace_output_user.c | 35 void *base; perf_event_mmap() local
41 base = mmap(NULL, mmap_size, PROT_READ | PROT_WRITE, MAP_SHARED, fd, 0); perf_event_mmap()
42 if (base == MAP_FAILED) { perf_event_mmap()
47 header = base; perf_event_mmap()
69 void *base, *begin, *end; perf_event_read() local
76 base = ((char *)header) + page_size; perf_event_read()
78 begin = base + data_tail % buffer_size; perf_event_read()
79 end = base + data_head % buffer_size; perf_event_read()
85 if (begin + e->header.size > base + buffer_size) { perf_event_read()
86 long len = base + buffer_size - begin; perf_event_read()
90 memcpy(buf + len, base, e->header.size - len); perf_event_read()
92 begin = base + e->header.size - len; perf_event_read()
93 } else if (begin + e->header.size == base + buffer_size) { perf_event_read()
94 begin = base; perf_event_read()
|
| /linux-4.4.14/drivers/crypto/ux500/cryp/ |
| H A D | cryp.c | 29 * @device_data: Pointer to the device data struct for base address.
38 peripheralid2 = readl_relaxed(&device_data->base->periphId2); cryp_check()
45 readl_relaxed(&device_data->base->periphId0)) cryp_check()
47 readl_relaxed(&device_data->base->periphId1)) cryp_check()
49 readl_relaxed(&device_data->base->periphId3)) cryp_check()
51 readl_relaxed(&device_data->base->pcellId0)) cryp_check()
53 readl_relaxed(&device_data->base->pcellId1)) cryp_check()
55 readl_relaxed(&device_data->base->pcellId2)) cryp_check()
57 readl_relaxed(&device_data->base->pcellId3))) { cryp_check()
66 * @device_data: Pointer to the device data struct for base address.
72 CRYP_PUT_BITS(&device_data->base->cr, cryp_activity()
80 * @device_data: Pointer to the device data struct for base address.
93 CRYP_SET_BITS(&device_data->base->cr, CRYP_CR_FFLUSH_MASK); cryp_flush_inoutfifo()
99 while (readl_relaxed(&device_data->base->sr) != cryp_flush_inoutfifo()
106 * @device_data: Pointer to the device data struct for base address.
147 writel_relaxed(cr_for_kse, &device_data->base->cr); cryp_set_configuration()
160 * @device_data: Pointer to the device data struct for base address.
170 CRYP_WRITE_BIT(&device_data->base->cr, cryp_configure_protection()
173 CRYP_PUT_BITS(&device_data->base->cr, cryp_configure_protection()
183 * @device_data: Pointer to the device data struct for base address.
187 return CRYP_TEST_BITS(&device_data->base->sr, cryp_is_logic_busy()
193 * @device_data: Pointer to the device data struct for base address.
199 CRYP_SET_BITS(&device_data->base->dmacr, cryp_configure_for_dma()
205 * @device_data: Pointer to the device data struct for base address.
219 &device_data->base->key_1_l); cryp_configure_key_values()
221 &device_data->base->key_1_r); cryp_configure_key_values()
225 &device_data->base->key_2_l); cryp_configure_key_values()
227 &device_data->base->key_2_r); cryp_configure_key_values()
231 &device_data->base->key_3_l); cryp_configure_key_values()
233 &device_data->base->key_3_r); cryp_configure_key_values()
237 &device_data->base->key_4_l); cryp_configure_key_values()
239 &device_data->base->key_4_r); cryp_configure_key_values()
250 * @device_data: Pointer to the device data struct for base address.
266 &device_data->base->init_vect_0_l); cryp_configure_init_vector()
268 &device_data->base->init_vect_0_r); cryp_configure_init_vector()
272 &device_data->base->init_vect_1_l); cryp_configure_init_vector()
274 &device_data->base->init_vect_1_r); cryp_configure_init_vector()
286 * @device_data: Pointer to the device data struct for base address.
294 struct cryp_register __iomem *src_reg = device_data->base; cryp_save_device_context()
346 * @device_data: Pointer to the device data struct for base address.
352 struct cryp_register __iomem *reg = device_data->base; cryp_restore_device_context()
|
| H A D | cryp_irq.c | 26 i = readl_relaxed(&device_data->base->imsc); cryp_enable_irq_src()
28 writel_relaxed(i, &device_data->base->imsc); cryp_enable_irq_src()
37 i = readl_relaxed(&device_data->base->imsc); cryp_disable_irq_src()
39 writel_relaxed(i, &device_data->base->imsc); cryp_disable_irq_src()
44 return (readl_relaxed(&device_data->base->mis) & irq_src) > 0; cryp_pending_irq_src()
|
| /linux-4.4.14/drivers/nvmem/ |
| H A D | rockchip-efuse.c | 40 void __iomem *base; member in struct:rockchip_efuse_context
56 void __iomem *base = _context->base; rockchip_efuse_read() local
67 writel(EFUSE_LOAD | EFUSE_PGENB, base + REG_EFUSE_CTRL); rockchip_efuse_read()
70 writel(readl(base + REG_EFUSE_CTRL) & rockchip_efuse_read()
72 base + REG_EFUSE_CTRL); rockchip_efuse_read()
73 writel(readl(base + REG_EFUSE_CTRL) | rockchip_efuse_read()
75 base + REG_EFUSE_CTRL); rockchip_efuse_read()
77 writel(readl(base + REG_EFUSE_CTRL) | rockchip_efuse_read()
78 EFUSE_STROBE, base + REG_EFUSE_CTRL); rockchip_efuse_read()
80 *buf++ = readb(base + REG_EFUSE_DOUT); rockchip_efuse_read()
81 writel(readl(base + REG_EFUSE_CTRL) & rockchip_efuse_read()
82 (~EFUSE_STROBE), base + REG_EFUSE_CTRL); rockchip_efuse_read()
90 writel(EFUSE_PGENB | EFUSE_CSB, base + REG_EFUSE_CTRL); rockchip_efuse_read()
128 void __iomem *base; rockchip_efuse_probe() local
133 base = devm_ioremap_resource(dev, res); rockchip_efuse_probe()
134 if (IS_ERR(base)) rockchip_efuse_probe()
135 return PTR_ERR(base); rockchip_efuse_probe()
147 context->base = base; rockchip_efuse_probe()
|
| /linux-4.4.14/drivers/clk/st/ |
| H A D | clkgen.h | 20 static inline unsigned long clkgen_read(void __iomem *base, clkgen_read() argument
23 return (readl(base + field->offset) >> field->shift) & field->mask; clkgen_read()
27 static inline void clkgen_write(void __iomem *base, struct clkgen_field *field, clkgen_write() argument
30 writel((readl(base + field->offset) & clkgen_write()
32 base + field->offset); clkgen_write()
|
| /linux-4.4.14/drivers/clk/mxs/ |
| H A D | clk-pll.c | 22 * @base: base address of the pll
31 void __iomem *base; member in struct:clk_pll
42 writel_relaxed(1 << pll->power, pll->base + SET); clk_pll_prepare()
53 writel_relaxed(1 << pll->power, pll->base + CLR); clk_pll_unprepare()
60 writel_relaxed(1 << 31, pll->base + CLR); clk_pll_enable()
69 writel_relaxed(1 << 31, pll->base + SET); clk_pll_disable()
89 void __iomem *base, u8 power, unsigned long rate) mxs_clk_pll()
105 pll->base = base; mxs_clk_pll()
88 mxs_clk_pll(const char *name, const char *parent_name, void __iomem *base, u8 power, unsigned long rate) mxs_clk_pll() argument
|
| /linux-4.4.14/arch/mips/pistachio/ |
| H A D | init.c | 80 void *base; mips_nmi_setup() local
83 base = cpu_has_veic ? mips_nmi_setup()
86 memcpy(base, &except_vec_nmi, 0x80); mips_nmi_setup()
87 flush_icache_range((unsigned long)base, mips_nmi_setup()
88 (unsigned long)base + 0x80); mips_nmi_setup()
93 void *base; mips_ejtag_setup() local
96 base = cpu_has_veic ? mips_ejtag_setup()
99 memcpy(base, &except_vec_ejtag_debug, 0x80); mips_ejtag_setup()
100 flush_icache_range((unsigned long)base, mips_ejtag_setup()
101 (unsigned long)base + 0x80); mips_ejtag_setup()
|
| /linux-4.4.14/drivers/tty/ |
| H A D | isicom.c | 93 * 06/01/05 Alan Cox Merged the ISI and base kernel strands
141 #define InterruptTheCard(base) outw(0, (base) + 0xc)
142 #define ClearInterrupt(base) inw((base) + 0x0a)
189 unsigned long base; member in struct:isi_board
223 static inline int WaitTillCardIsFree(unsigned long base) WaitTillCardIsFree() argument
228 while (!(inw(base + 0xe) & 0x1) && count++ < 100) WaitTillCardIsFree()
234 return !(inw(base + 0xe) & 0x1); WaitTillCardIsFree()
239 unsigned long base = card->base; lock_card() local
245 if (inw(base + 0xe) & 0x1) lock_card()
252 pr_warn("Failed to lock Card (0x%lx)\n", card->base); lock_card()
270 unsigned long base = card->base; raise_dtr() local
273 if (WaitTillCardIsFree(base)) raise_dtr()
276 outw(0x8000 | (channel << card->shift_count) | 0x02, base); raise_dtr()
277 outw(0x0504, base); raise_dtr()
278 InterruptTheCard(base); raise_dtr()
286 unsigned long base = card->base; drop_dtr() local
289 if (WaitTillCardIsFree(base)) drop_dtr()
292 outw(0x8000 | (channel << card->shift_count) | 0x02, base); drop_dtr()
293 outw(0x0404, base); drop_dtr()
294 InterruptTheCard(base); drop_dtr()
302 unsigned long base = card->base; raise_rts() local
305 if (WaitTillCardIsFree(base)) raise_rts()
308 outw(0x8000 | (channel << card->shift_count) | 0x02, base); raise_rts()
309 outw(0x0a04, base); raise_rts()
310 InterruptTheCard(base); raise_rts()
318 unsigned long base = card->base; drop_rts() local
321 if (WaitTillCardIsFree(base)) drop_rts()
324 outw(0x8000 | (channel << card->shift_count) | 0x02, base); drop_rts()
325 outw(0x0804, base); drop_rts()
326 InterruptTheCard(base); drop_rts()
336 unsigned long base = card->base; isicom_dtr_rts() local
343 outw(0x8000 | (channel << card->shift_count) | 0x02, base); isicom_dtr_rts()
344 outw(0x0f04, base); isicom_dtr_rts()
345 InterruptTheCard(base); isicom_dtr_rts()
348 outw(0x8000 | (channel << card->shift_count) | 0x02, base); isicom_dtr_rts()
349 outw(0x0C04, base); isicom_dtr_rts()
350 InterruptTheCard(base); isicom_dtr_rts()
360 unsigned long base = card->base; drop_dtr_rts() local
363 if (WaitTillCardIsFree(base)) drop_dtr_rts()
366 outw(0x8000 | (channel << card->shift_count) | 0x02, base); drop_dtr_rts()
367 outw(0x0c04, base); drop_dtr_rts()
368 InterruptTheCard(base); drop_dtr_rts()
403 unsigned long flags, base; isicom_tx() local
424 base = isi_card[card].base; isicom_tx()
428 if (inw(base + 0xe) & 0x1) isicom_tx()
449 if (!(inw(base + 0x02) & (1 << port->channel))) isicom_tx()
455 base); isicom_tx()
471 outw(wrd, base); isicom_tx()
473 outw(wrd, base); isicom_tx()
480 outsw(base, port->port.xmit_buf+port->xmit_tail, word_count); isicom_tx()
495 InterruptTheCard(base); isicom_tx()
520 unsigned long base; isicom_interrupt() local
528 base = card->base; isicom_interrupt()
531 if (!(inw(base + 0x0e) & 0x02)) isicom_interrupt()
540 outw(0x8000, base+0x04); isicom_interrupt()
541 ClearInterrupt(base); isicom_interrupt()
543 inw(base); /* get the dummy word out */ isicom_interrupt()
544 header = inw(base); isicom_interrupt()
550 __func__, base, channel + 1); isicom_interrupt()
551 outw(0x0000, base+0x04); /* enable interrupts */ isicom_interrupt()
557 outw(0x0000, base+0x04); /* enable interrupts */ isicom_interrupt()
566 inw(base); isicom_interrupt()
570 inw(base); isicom_interrupt()
571 outw(0x0000, base+0x04); /* enable interrupts */ isicom_interrupt()
577 header = inw(base); isicom_interrupt()
658 insw(base, rp, word_count); isicom_interrupt()
661 tty_insert_flip_char(&port->port, inw(base) & 0xff, isicom_interrupt()
667 __func__, base, channel + 1); isicom_interrupt()
670 inw(base); isicom_interrupt()
676 outw(0x0000, base+0x04); /* enable interrupts */ isicom_interrupt()
688 unsigned long base = card->base; isicom_config_port() local
732 if (WaitTillCardIsFree(base) == 0) { isicom_config_port()
733 outw(0x8000 | (channel << shift_count) | 0x03, base); isicom_config_port()
734 outw(linuxb_to_isib[baud] << 8 | 0x03, base); isicom_config_port()
758 outw(channel_setup, base); isicom_config_port()
759 InterruptTheCard(base); isicom_config_port()
778 if (WaitTillCardIsFree(base) == 0) { isicom_config_port()
779 outw(0x8000 | (channel << shift_count) | 0x04, base); isicom_config_port()
780 outw(flow_ctrl << 8 | 0x05, base); isicom_config_port()
781 outw((STOP_CHAR(tty)) << 8 | (START_CHAR(tty)), base); isicom_config_port()
782 InterruptTheCard(base); isicom_config_port()
788 outw(card->port_status, base + 0x02); isicom_config_port()
826 if (WaitTillCardIsFree(card->base) == 0) { isicom_activate()
828 card->base); isicom_activate()
829 outw(((ISICOM_KILLTX | ISICOM_KILLRX) << 8) | 0x06, card->base); isicom_activate()
830 InterruptTheCard(card->base); isicom_activate()
891 __func__, card->base, card->count); isicom_shutdown_port()
925 outw(card->port_status, card->base + 0x02); isicom_shutdown()
1048 unsigned long base = card->base; isicom_send_break() local
1056 outw(0x8000 | ((port->channel) << (card->shift_count)) | 0x3, base); isicom_send_break()
1057 outw((length & 0xff) << 8 | 0x00, base); isicom_send_break()
1058 outw((length & 0xff00u), base); isicom_send_break()
1059 InterruptTheCard(base); isicom_send_break()
1155 out_info.port = port->card->base; isicom_get_serial_info()
1225 outw(card->port_status, card->base + 0x02); isicom_throttle()
1239 outw(card->port_status, card->base + 0x02); isicom_unthrottle()
1314 unsigned long base = board->base; reset_card() local
1319 base); reset_card()
1321 inw(base + 0x8); reset_card()
1325 outw(0, base + 0x8); /* Reset */ reset_card()
1329 sig = inw(base + 0x4) & 0xff; reset_card()
1334 "bad I/O Port Address 0x%lx).\n", card + 1, base); reset_card()
1342 portcount = inw(base + 0x2); reset_card()
1343 if (!(inw(base + 0xe) & 0x1) || (portcount != 0 && portcount != 4 && reset_card()
1376 unsigned long base = board->base; load_firmware() local
1420 if (WaitTillCardIsFree(base)) load_firmware()
1423 outw(0xf0, base); /* start upload sequence */ load_firmware()
1424 outw(0x00, base); load_firmware()
1425 outw(frame->addr, base); /* lsb of address */ load_firmware()
1428 outw(word_count, base); load_firmware()
1429 InterruptTheCard(base); load_firmware()
1433 if (WaitTillCardIsFree(base)) load_firmware()
1436 status = inw(base + 0x4); load_firmware()
1445 outsw(base, frame->data, word_count); load_firmware()
1447 InterruptTheCard(base); load_firmware()
1451 if (WaitTillCardIsFree(base)) load_firmware()
1454 status = inw(base + 0x4); load_firmware()
1468 if (WaitTillCardIsFree(base)) load_firmware()
1471 outw(0xf1, base); /* start download sequence */ load_firmware()
1472 outw(0x00, base); load_firmware()
1473 outw(frame->addr, base); /* lsb of address */ load_firmware()
1476 outw(word_count + 1, base); load_firmware()
1477 InterruptTheCard(base); load_firmware()
1481 if (WaitTillCardIsFree(base)) load_firmware()
1484 status = inw(base + 0x4); load_firmware()
1500 inw(base); load_firmware()
1501 insw(base, data, word_count); load_firmware()
1502 InterruptTheCard(base); load_firmware()
1515 if (WaitTillCardIsFree(base)) load_firmware()
1518 status = inw(base + 0x4); load_firmware()
1527 if (WaitTillCardIsFree(base)) load_firmware()
1530 outw(0xf2, base); load_firmware()
1531 outw(0x800, base); load_firmware()
1532 outw(0x0, base); load_firmware()
1533 outw(0x0, base); load_firmware()
1534 InterruptTheCard(base); load_firmware()
1535 outw(0x0, base + 0x4); /* for ISI4608 cards */ load_firmware()
1571 if (isi_card[index].base == 0) { isicom_probe()
1582 board->base = pci_resource_start(pdev, 3); isicom_probe()
1591 "will be disabled.\n", board->base, board->base + 15, isicom_probe()
1630 board->base = 0; isicom_probe()
1650 board->base = 0; isicom_remove()
1671 isi_card[idx].base = 0; isicom_init()
|
| H A D | goldfish.c | 44 void __iomem *base; member in struct:goldfish_tty
60 void __iomem *base = qtty->base; goldfish_tty_do_write() local
62 gf_write_ptr(buf, base + GOLDFISH_TTY_DATA_PTR, goldfish_tty_do_write()
63 base + GOLDFISH_TTY_DATA_PTR_HIGH); goldfish_tty_do_write()
64 writel(count, base + GOLDFISH_TTY_DATA_LEN); goldfish_tty_do_write()
65 writel(GOLDFISH_TTY_CMD_WRITE_BUFFER, base + GOLDFISH_TTY_CMD); goldfish_tty_do_write()
73 void __iomem *base = qtty->base; goldfish_tty_interrupt() local
78 count = readl(base + GOLDFISH_TTY_BYTES_READY); goldfish_tty_interrupt()
84 gf_write_ptr(buf, base + GOLDFISH_TTY_DATA_PTR, goldfish_tty_interrupt()
85 base + GOLDFISH_TTY_DATA_PTR_HIGH); goldfish_tty_interrupt()
86 writel(count, base + GOLDFISH_TTY_DATA_LEN); goldfish_tty_interrupt()
87 writel(GOLDFISH_TTY_CMD_READ_BUFFER, base + GOLDFISH_TTY_CMD); goldfish_tty_interrupt()
97 writel(GOLDFISH_TTY_CMD_INT_ENABLE, qtty->base + GOLDFISH_TTY_CMD); goldfish_tty_activate()
105 writel(GOLDFISH_TTY_CMD_INT_DISABLE, qtty->base + GOLDFISH_TTY_CMD); goldfish_tty_shutdown()
139 void __iomem *base = qtty->base; goldfish_tty_chars_in_buffer() local
140 return readl(base + GOLDFISH_TTY_BYTES_READY); goldfish_tty_chars_in_buffer()
160 if (!goldfish_ttys[co->index].base) goldfish_tty_console_setup()
234 void __iomem *base; goldfish_tty_probe() local
241 base = ioremap(r->start, 0x1000); goldfish_tty_probe()
242 if (base == NULL) goldfish_tty_probe()
243 pr_err("goldfish_tty: unable to remap base\n"); goldfish_tty_probe()
266 qtty->base = base; goldfish_tty_probe()
269 writel(GOLDFISH_TTY_CMD_INT_DISABLE, base + GOLDFISH_TTY_CMD); goldfish_tty_probe()
304 iounmap(base); goldfish_tty_probe()
317 iounmap(qtty->base); goldfish_tty_remove()
318 qtty->base = NULL; goldfish_tty_remove()
|
| /linux-4.4.14/sound/soc/fsl/ |
| H A D | imx-ssi.c | 67 sccr = readl(ssi->base + SSI_STCCR); imx_ssi_set_dai_tdm_slot()
70 writel(sccr, ssi->base + SSI_STCCR); imx_ssi_set_dai_tdm_slot()
72 sccr = readl(ssi->base + SSI_SRCCR); imx_ssi_set_dai_tdm_slot()
75 writel(sccr, ssi->base + SSI_SRCCR); imx_ssi_set_dai_tdm_slot()
77 writel(~tx_mask, ssi->base + SSI_STMSK); imx_ssi_set_dai_tdm_slot()
78 writel(~rx_mask, ssi->base + SSI_SRMSK); imx_ssi_set_dai_tdm_slot()
92 scr = readl(ssi->base + SSI_SCR) & ~(SSI_SCR_SYN | SSI_SCR_NET); imx_ssi_set_dai_fmt()
152 writel(strcr, ssi->base + SSI_STCR); imx_ssi_set_dai_fmt()
153 writel(strcr, ssi->base + SSI_SRCR); imx_ssi_set_dai_fmt()
154 writel(scr, ssi->base + SSI_SCR); imx_ssi_set_dai_fmt()
169 scr = readl(ssi->base + SSI_SCR); imx_ssi_set_dai_sysclk()
182 writel(scr, ssi->base + SSI_SCR); imx_ssi_set_dai_sysclk()
197 stccr = readl(ssi->base + SSI_STCCR); imx_ssi_set_dai_clkdiv()
198 srccr = readl(ssi->base + SSI_SRCCR); imx_ssi_set_dai_clkdiv()
229 writel(stccr, ssi->base + SSI_STCCR); imx_ssi_set_dai_clkdiv()
230 writel(srccr, ssi->base + SSI_SRCCR); imx_ssi_set_dai_clkdiv()
255 sccr = readl(ssi->base + reg) & ~SSI_STCCR_WL_MASK; imx_ssi_hw_params()
270 writel(sccr, ssi->base + reg); imx_ssi_hw_params()
282 scr = readl(ssi->base + SSI_SCR); imx_ssi_trigger()
283 sier = readl(ssi->base + SSI_SIER); imx_ssi_trigger()
330 writel(scr, ssi->base + SSI_SCR); imx_ssi_trigger()
332 writel(sier, ssi->base + SSI_SIER); imx_ssi_trigger()
355 writel(val, ssi->base + SSI_SFCSR); imx_ssi_dai_probe()
407 void __iomem *base = imx_ssi->base; setup_channel_to_ac97() local
409 writel(0x0, base + SSI_SCR); setup_channel_to_ac97()
410 writel(0x0, base + SSI_STCR); setup_channel_to_ac97()
411 writel(0x0, base + SSI_SRCR); setup_channel_to_ac97()
413 writel(SSI_SCR_SYN | SSI_SCR_NET, base + SSI_SCR); setup_channel_to_ac97()
418 SSI_SFCSR_TFWM1(8), base + SSI_SFCSR); setup_channel_to_ac97()
420 writel(SSI_STCCR_WL(16) | SSI_STCCR_DC(12), base + SSI_STCCR); setup_channel_to_ac97()
421 writel(SSI_STCCR_WL(16) | SSI_STCCR_DC(12), base + SSI_SRCCR); setup_channel_to_ac97()
423 writel(SSI_SCR_SYN | SSI_SCR_NET | SSI_SCR_SSIEN, base + SSI_SCR); setup_channel_to_ac97()
424 writel(SSI_SOR_WAIT(3), base + SSI_SOR); setup_channel_to_ac97()
428 base + SSI_SCR); setup_channel_to_ac97()
430 writel(SSI_SACNT_DEFAULT, base + SSI_SACNT); setup_channel_to_ac97()
431 writel(0xff, base + SSI_SACCDIS); setup_channel_to_ac97()
432 writel(0x300, base + SSI_SACCEN); setup_channel_to_ac97()
441 void __iomem *base = imx_ssi->base; imx_ssi_ac97_write() local
451 writel(lreg, base + SSI_SACADD); imx_ssi_ac97_write()
454 writel(lval , base + SSI_SACDAT); imx_ssi_ac97_write()
456 writel(SSI_SACNT_DEFAULT | SSI_SACNT_WR, base + SSI_SACNT); imx_ssi_ac97_write()
464 void __iomem *base = imx_ssi->base; imx_ssi_ac97_read() local
470 writel(lreg, base + SSI_SACADD); imx_ssi_ac97_read()
471 writel(SSI_SACNT_DEFAULT | SSI_SACNT_RD, base + SSI_SACNT); imx_ssi_ac97_read()
475 val = (readl(base + SSI_SACDAT) >> 4) & 0xffff; imx_ssi_ac97_read()
543 ssi->base = devm_ioremap_resource(&pdev->dev, res); imx_ssi_probe()
544 if (IS_ERR(ssi->base)) { imx_ssi_probe()
545 ret = PTR_ERR(ssi->base); imx_ssi_probe()
561 writel(0x0, ssi->base + SSI_SIER); imx_ssi_probe()
600 ssi->fiq_params.base = ssi->base; imx_ssi_probe()
|
| /linux-4.4.14/drivers/pci/hotplug/ |
| H A D | cpqphp_pci.c | 547 * Saves the length of all base address registers for the
560 u32 base; cpqhp_save_base_addr_length() local
594 * IO and memory base lengths cpqhp_save_base_addr_length()
599 pci_bus_read_config_dword (pci_bus, devfn, cloop, &base); cpqhp_save_base_addr_length()
601 if (base) { cpqhp_save_base_addr_length()
602 if (base & 0x01L) { cpqhp_save_base_addr_length()
603 /* IO base cpqhp_save_base_addr_length()
604 * set base = amount of IO space cpqhp_save_base_addr_length()
607 base = base & 0xFFFFFFFE; cpqhp_save_base_addr_length()
608 base = (~base) + 1; cpqhp_save_base_addr_length()
612 /* memory base */ cpqhp_save_base_addr_length()
613 base = base & 0xFFFFFFF0; cpqhp_save_base_addr_length()
614 base = (~base) + 1; cpqhp_save_base_addr_length()
619 base = 0x0L; cpqhp_save_base_addr_length()
625 base; cpqhp_save_base_addr_length()
628 } /* End of base register loop */ cpqhp_save_base_addr_length()
631 /* Figure out IO and memory base lengths */ cpqhp_save_base_addr_length()
635 pci_bus_read_config_dword (pci_bus, devfn, cloop, &base); cpqhp_save_base_addr_length()
638 if (base) { cpqhp_save_base_addr_length()
639 if (base & 0x01L) { cpqhp_save_base_addr_length()
640 /* IO base cpqhp_save_base_addr_length()
641 * base = amount of IO space cpqhp_save_base_addr_length()
644 base = base & 0xFFFFFFFE; cpqhp_save_base_addr_length()
645 base = (~base) + 1; cpqhp_save_base_addr_length()
649 /* memory base cpqhp_save_base_addr_length()
650 * base = amount of memory cpqhp_save_base_addr_length()
653 base = base & 0xFFFFFFF0; cpqhp_save_base_addr_length()
654 base = (~base) + 1; cpqhp_save_base_addr_length()
659 base = 0x0L; cpqhp_save_base_addr_length()
664 func->base_length[(cloop - 0x10) >> 2] = base; cpqhp_save_base_addr_length()
667 } /* End of base register loop */ cpqhp_save_base_addr_length()
703 u32 base; cpqhp_save_used_resources() local
739 bus_node->base = secondary_bus; cpqhp_save_used_resources()
745 /* Save IO base and Limit registers */ cpqhp_save_used_resources()
754 io_node->base = (b_base & 0xF0) << 8; cpqhp_save_used_resources()
761 /* Save memory base and Limit registers */ cpqhp_save_used_resources()
770 mem_node->base = w_base << 16; cpqhp_save_used_resources()
777 /* Save prefetchable memory base and Limit registers */ cpqhp_save_used_resources()
786 p_mem_node->base = w_base << 16; cpqhp_save_used_resources()
792 /* Figure out IO and memory base lengths */ cpqhp_save_used_resources()
798 pci_bus_read_config_dword(pci_bus, devfn, cloop, &base); cpqhp_save_used_resources()
800 temp_register = base; cpqhp_save_used_resources()
803 if (base) { cpqhp_save_used_resources()
804 if (((base & 0x03L) == 0x01) cpqhp_save_used_resources()
806 /* IO base cpqhp_save_used_resources()
810 temp_register = base & 0xFFFFFFFE; cpqhp_save_used_resources()
818 io_node->base = cpqhp_save_used_resources()
825 if (((base & 0x0BL) == 0x08) cpqhp_save_used_resources()
827 /* prefetchable memory base */ cpqhp_save_used_resources()
828 temp_register = base & 0xFFFFFFF0; cpqhp_save_used_resources()
836 p_mem_node->base = save_base & (~0x0FL); cpqhp_save_used_resources()
842 if (((base & 0x0BL) == 0x00) cpqhp_save_used_resources()
844 /* prefetchable memory base */ cpqhp_save_used_resources()
845 temp_register = base & 0xFFFFFFF0; cpqhp_save_used_resources()
853 mem_node->base = save_base & (~0x0FL); cpqhp_save_used_resources()
861 } /* End of base register loop */ cpqhp_save_used_resources()
864 /* Figure out IO and memory base lengths */ cpqhp_save_used_resources()
870 pci_bus_read_config_dword(pci_bus, devfn, cloop, &base); cpqhp_save_used_resources()
872 temp_register = base; cpqhp_save_used_resources()
875 if (base) { cpqhp_save_used_resources()
876 if (((base & 0x03L) == 0x01) cpqhp_save_used_resources()
878 /* IO base cpqhp_save_used_resources()
882 temp_register = base & 0xFFFFFFFE; cpqhp_save_used_resources()
890 io_node->base = save_base & (~0x01L); cpqhp_save_used_resources()
896 if (((base & 0x0BL) == 0x08) cpqhp_save_used_resources()
898 /* prefetchable memory base */ cpqhp_save_used_resources()
899 temp_register = base & 0xFFFFFFF0; cpqhp_save_used_resources()
907 p_mem_node->base = save_base & (~0x0FL); cpqhp_save_used_resources()
913 if (((base & 0x0BL) == 0x00) cpqhp_save_used_resources()
915 /* prefetchable memory base */ cpqhp_save_used_resources()
916 temp_register = base & 0xFFFFFFF0; cpqhp_save_used_resources()
924 mem_node->base = save_base & (~0x0FL); cpqhp_save_used_resources()
932 } /* End of base register loop */ cpqhp_save_used_resources()
996 /* Check all the base Address Registers to make sure cpqhp_configure_board()
1037 u32 base; cpqhp_valid_replace() local
1108 /* Figure out IO and memory base lengths */ cpqhp_valid_replace()
1112 pci_bus_read_config_dword (pci_bus, devfn, cloop, &base); cpqhp_valid_replace()
1115 if (base) { cpqhp_valid_replace()
1116 if (base & 0x01L) { cpqhp_valid_replace()
1117 /* IO base cpqhp_valid_replace()
1118 * set base = amount of IO cpqhp_valid_replace()
1121 base = base & 0xFFFFFFFE; cpqhp_valid_replace()
1122 base = (~base) + 1; cpqhp_valid_replace()
1126 /* memory base */ cpqhp_valid_replace()
1127 base = base & 0xFFFFFFF0; cpqhp_valid_replace()
1128 base = (~base) + 1; cpqhp_valid_replace()
1133 base = 0x0L; cpqhp_valid_replace()
1138 if (func->base_length[(cloop - 0x10) >> 2] != base) cpqhp_valid_replace()
1144 } /* End of base register loop */ cpqhp_valid_replace()
1245 dbg("dev|IO base|length|Mem base|length|Pre base|length|PB SB MB\n"); cpqhp_find_available_resources()
1302 /* If we've got a valid IO base, use it */ cpqhp_find_available_resources()
1311 io_node->base = io_base; cpqhp_find_available_resources()
1314 dbg("found io_node(base, length) = %x, %x\n", cpqhp_find_available_resources()
1315 io_node->base, io_node->length); cpqhp_find_available_resources()
1326 /* If we've got a valid memory base, use it */ cpqhp_find_available_resources()
1333 mem_node->base = mem_base << 16; cpqhp_find_available_resources()
1337 dbg("found mem_node(base, length) = %x, %x\n", cpqhp_find_available_resources()
1338 mem_node->base, mem_node->length); cpqhp_find_available_resources()
1349 /* If we've got a valid prefetchable memory base, and cpqhp_find_available_resources()
1350 * the base + length isn't greater than 0xFFFF cpqhp_find_available_resources()
1358 p_mem_node->base = pre_mem_base << 16; cpqhp_find_available_resources()
1361 dbg("found p_mem_node(base, length) = %x, %x\n", cpqhp_find_available_resources()
1362 p_mem_node->base, p_mem_node->length); cpqhp_find_available_resources()
1383 bus_node->base = secondary_bus; cpqhp_find_available_resources()
1385 dbg("found bus_node(base, length) = %x, %x\n", cpqhp_find_available_resources()
1386 bus_node->base, bus_node->length); cpqhp_find_available_resources()
|
| /linux-4.4.14/drivers/hwtracing/coresight/ |
| H A D | coresight-replicator-qcom.c | 34 * @base: memory mapped base address for this component.
40 void __iomem *base; member in struct:replicator_state
53 CS_UNLOCK(drvdata->base); replicator_enable()
61 writel_relaxed(0x00, drvdata->base + REPLICATOR_IDFILTER0); replicator_enable()
62 writel_relaxed(0xff, drvdata->base + REPLICATOR_IDFILTER1); replicator_enable()
64 writel_relaxed(0x00, drvdata->base + REPLICATOR_IDFILTER1); replicator_enable()
65 writel_relaxed(0xff, drvdata->base + REPLICATOR_IDFILTER0); replicator_enable()
68 CS_LOCK(drvdata->base); replicator_enable()
79 CS_UNLOCK(drvdata->base); replicator_disable()
83 writel_relaxed(0xff, drvdata->base + REPLICATOR_IDFILTER0); replicator_disable()
85 writel_relaxed(0xff, drvdata->base + REPLICATOR_IDFILTER1); replicator_disable()
87 CS_LOCK(drvdata->base); replicator_disable()
112 void __iomem *base; replicator_probe() local
134 base = devm_ioremap_resource(dev, res); replicator_probe()
135 if (IS_ERR(base)) replicator_probe()
136 return PTR_ERR(base); replicator_probe()
138 drvdata->base = base; replicator_probe()
|
| /linux-4.4.14/include/sound/ |
| H A D | snd_wavefront.h | 22 unsigned long base; /* I/O port address */ member in struct:_snd_wavefront_midi
50 unsigned long base; /* low i/o port address */ member in struct:_snd_wavefront
53 #define mpu_data_port base
54 #define mpu_command_port base + 1 /* write semantics */
55 #define mpu_status_port base + 1 /* read semantics */
56 #define data_port base + 2
57 #define status_port base + 3 /* read semantics */
58 #define control_port base + 3 /* write semantics */
59 #define block_port base + 4 /* 16 bit, writeonly */
60 #define last_block_port base + 6 /* 16 bit, writeonly */
68 #define fx_status base + 8
69 #define fx_op base + 8
70 #define fx_lcr base + 9
71 #define fx_dsp_addr base + 0xa
72 #define fx_dsp_page base + 0xb
73 #define fx_dsp_lsb base + 0xc
74 #define fx_dsp_msb base + 0xd
75 #define fx_mod_addr base + 0xe
76 #define fx_mod_data base + 0xf
|
| /linux-4.4.14/arch/arm/mach-shmobile/ |
| H A D | setup-rcar-gen2.c | 56 void __iomem *base; rcar_gen2_timer_init() local
108 base = ioremap(0xe6080000, PAGE_SIZE); rcar_gen2_timer_init()
117 if ((ioread32(base + CNTCR) & 1) == 0 || rcar_gen2_timer_init()
118 ioread32(base + CNTFID0) != freq) { rcar_gen2_timer_init()
120 iowrite32(freq, base + CNTFID0); rcar_gen2_timer_init()
124 iowrite32(1, base + CNTCR); rcar_gen2_timer_init()
127 iounmap(base); rcar_gen2_timer_init()
136 u64 base, size; member in struct:memory_reserve_config
160 u64 base, size; rcar_gen2_scan_mem() local
162 base = dt_mem_next_cell(dt_root_addr_cells, ®); rcar_gen2_scan_mem()
165 if (base >= lpae_start) rcar_gen2_scan_mem()
168 if ((base + size) >= lpae_start) rcar_gen2_scan_mem()
169 size = lpae_start - base; rcar_gen2_scan_mem()
174 if (base < mrc->base) rcar_gen2_scan_mem()
178 mrc->base = base + size - mrc->reserved; rcar_gen2_scan_mem()
197 if (mrc.size && memblock_is_region_memory(mrc.base, mrc.size)) rcar_gen2_reserve()
198 dma_contiguous_reserve_area(mrc.size, mrc.base, 0, rcar_gen2_reserve()
|
| /linux-4.4.14/arch/arm/plat-samsung/ |
| H A D | pm-gpio.c | 35 chip->pm_save[0] = __raw_readl(chip->base + OFFS_CON); samsung_gpio_pm_1bit_save()
36 chip->pm_save[1] = __raw_readl(chip->base + OFFS_DAT); samsung_gpio_pm_1bit_save()
41 void __iomem *base = chip->base; samsung_gpio_pm_1bit_resume() local
42 u32 old_gpcon = __raw_readl(base + OFFS_CON); samsung_gpio_pm_1bit_resume()
43 u32 old_gpdat = __raw_readl(base + OFFS_DAT); samsung_gpio_pm_1bit_resume()
54 __raw_writel(gpcon, base + OFFS_CON); samsung_gpio_pm_1bit_resume()
58 __raw_writel(gps_gpdat, base + OFFS_DAT); samsung_gpio_pm_1bit_resume()
59 __raw_writel(gps_gpcon, base + OFFS_CON); samsung_gpio_pm_1bit_resume()
72 chip->pm_save[0] = __raw_readl(chip->base + OFFS_CON); samsung_gpio_pm_2bit_save()
73 chip->pm_save[1] = __raw_readl(chip->base + OFFS_DAT); samsung_gpio_pm_2bit_save()
74 chip->pm_save[2] = __raw_readl(chip->base + OFFS_UP); samsung_gpio_pm_2bit_save()
128 void __iomem *base = chip->base; samsung_gpio_pm_2bit_resume() local
129 u32 old_gpcon = __raw_readl(base + OFFS_CON); samsung_gpio_pm_2bit_resume()
130 u32 old_gpdat = __raw_readl(base + OFFS_DAT); samsung_gpio_pm_2bit_resume()
138 __raw_writel(chip->pm_save[2], base + OFFS_UP); samsung_gpio_pm_2bit_resume()
181 __raw_writel(gpcon, base + OFFS_CON); samsung_gpio_pm_2bit_resume()
185 __raw_writel(gps_gpdat, base + OFFS_DAT); samsung_gpio_pm_2bit_resume()
186 __raw_writel(gps_gpcon, base + OFFS_CON); samsung_gpio_pm_2bit_resume()
200 chip->pm_save[1] = __raw_readl(chip->base + OFFS_CON); samsung_gpio_pm_4bit_save()
201 chip->pm_save[2] = __raw_readl(chip->base + OFFS_DAT); samsung_gpio_pm_4bit_save()
202 chip->pm_save[3] = __raw_readl(chip->base + OFFS_UP); samsung_gpio_pm_4bit_save()
205 chip->pm_save[0] = __raw_readl(chip->base - 4); samsung_gpio_pm_4bit_save()
249 void __iomem *con = chip->base + (index * 4); samsung_gpio_pm_4bit_con()
264 void __iomem *base = chip->base; samsung_gpio_pm_4bit_resume() local
266 u32 old_gpdat = __raw_readl(base + OFFS_DAT); samsung_gpio_pm_4bit_resume()
272 old_gpcon[1] = __raw_readl(base + OFFS_CON); samsung_gpio_pm_4bit_resume()
276 old_gpcon[0] = __raw_readl(base - 4); samsung_gpio_pm_4bit_resume()
282 __raw_writel(chip->pm_save[2], base + OFFS_DAT); samsung_gpio_pm_4bit_resume()
283 __raw_writel(chip->pm_save[1], base + OFFS_CON); samsung_gpio_pm_4bit_resume()
285 __raw_writel(chip->pm_save[0], base - 4); samsung_gpio_pm_4bit_resume()
287 __raw_writel(chip->pm_save[2], base + OFFS_DAT); samsung_gpio_pm_4bit_resume()
288 __raw_writel(chip->pm_save[3], base + OFFS_UP); samsung_gpio_pm_4bit_resume()
293 __raw_readl(base - 4), samsung_gpio_pm_4bit_resume()
294 __raw_readl(base + OFFS_CON), samsung_gpio_pm_4bit_resume()
299 __raw_readl(base + OFFS_CON), samsung_gpio_pm_4bit_resume()
|
| /linux-4.4.14/drivers/usb/chipidea/ |
| H A D | usbmisc_imx.c | 93 void __iomem *base; member in struct:imx_usbmisc
110 val = readl(usbmisc->base); usbmisc_imx25_init()
114 writel(val, usbmisc->base); usbmisc_imx25_init()
117 val = readl(usbmisc->base); usbmisc_imx25_init()
123 writel(val, usbmisc->base); usbmisc_imx25_init()
144 reg = usbmisc->base + MX25_USB_PHY_CTRL_OFFSET; usbmisc_imx25_post()
176 val = readl(usbmisc->base) | val; usbmisc_imx27_init()
178 val = readl(usbmisc->base) & ~val; usbmisc_imx27_init()
179 writel(val, usbmisc->base); usbmisc_imx27_init()
196 val = readl(usbmisc->base + MX53_USB_OTG_PHY_CTRL_1_OFFSET); usbmisc_imx53_init()
199 writel(val, usbmisc->base + MX53_USB_OTG_PHY_CTRL_1_OFFSET); usbmisc_imx53_init()
205 reg = usbmisc->base + MX53_USB_OTG_PHY_CTRL_0_OFFSET; usbmisc_imx53_init()
209 reg = usbmisc->base + MX53_USB_OTG_PHY_CTRL_0_OFFSET; usbmisc_imx53_init()
213 reg = usbmisc->base + MX53_USB_UH2_CTRL_OFFSET; usbmisc_imx53_init()
217 reg = usbmisc->base + MX53_USB_UH3_CTRL_OFFSET; usbmisc_imx53_init()
243 val = readl(usbmisc->base + data->index * 4); usbmisc_imx6q_set_wakeup()
246 writel(val, usbmisc->base + data->index * 4); usbmisc_imx6q_set_wakeup()
251 writel(val, usbmisc->base + data->index * 4); usbmisc_imx6q_set_wakeup()
270 reg = readl(usbmisc->base + data->index * 4); usbmisc_imx6q_init()
272 usbmisc->base + data->index * 4); usbmisc_imx6q_init()
276 reg = readl(usbmisc->base + data->index * 4); usbmisc_imx6q_init()
278 usbmisc->base + data->index * 4); usbmisc_imx6q_init()
297 reg = usbmisc->base + MX6_USB_OTG1_PHY_CTRL + data->index * 4; usbmisc_imx6sx_init()
306 val = readl(usbmisc->base + data->index * 4); usbmisc_imx6sx_init()
308 usbmisc->base + data->index * 4); usbmisc_imx6sx_init()
328 reg = readl(usbmisc->base); usbmisc_vf610_init()
329 writel(reg | VF610_OVER_CUR_DIS, usbmisc->base); usbmisc_vf610_init()
345 val = readl(usbmisc->base); usbmisc_imx7d_set_wakeup()
347 writel(val | wakeup_setting, usbmisc->base); usbmisc_imx7d_set_wakeup()
351 writel(val & ~wakeup_setting, usbmisc->base); usbmisc_imx7d_set_wakeup()
369 reg = readl(usbmisc->base); usbmisc_imx7d_init()
370 writel(reg | MX6_BM_OVER_CUR_DIS, usbmisc->base); usbmisc_imx7d_init()
373 reg = readl(usbmisc->base + MX7D_USBNC_USB_CTRL2); usbmisc_imx7d_init()
376 usbmisc->base + MX7D_USBNC_USB_CTRL2); usbmisc_imx7d_init()
516 data->base = devm_ioremap_resource(&pdev->dev, res); usbmisc_imx_probe()
517 if (IS_ERR(data->base)) usbmisc_imx_probe()
518 return PTR_ERR(data->base); usbmisc_imx_probe()
|
| /linux-4.4.14/arch/mips/include/asm/netlogic/xlp-hal/ |
| H A D | pic.h | 62 #define PIC_IPICTRL_IDB 16 /* interrupt destination base */
71 #define PIC_IRT_DB 16 /* Destination base */
228 nlm_9xx_pic_write_irt(uint64_t base, int irt_num, int en, int nmi, nlm_9xx_pic_write_irt() argument
238 nlm_write_pic_reg(base, PIC_9XX_IRT(irt_num), val); nlm_9xx_pic_write_irt()
242 nlm_pic_write_irt(uint64_t base, int irt_num, int en, int nmi, nlm_pic_write_irt() argument
252 nlm_write_pic_reg(base, PIC_IRT(irt_num), val); nlm_pic_write_irt()
256 nlm_pic_write_irt_direct(uint64_t base, int irt_num, int en, int nmi, nlm_pic_write_irt_direct() argument
260 nlm_9xx_pic_write_irt(base, irt_num, en, nmi, sch, vec, nlm_pic_write_irt_direct()
263 nlm_pic_write_irt(base, irt_num, en, nmi, sch, vec, 1, nlm_pic_write_irt_direct()
269 nlm_pic_read_timer(uint64_t base, int timer) nlm_pic_read_timer() argument
271 return nlm_read_pic_reg(base, PIC_TIMER_COUNT(timer)); nlm_pic_read_timer()
275 nlm_pic_read_timer32(uint64_t base, int timer) nlm_pic_read_timer32() argument
277 return (uint32_t)nlm_read_pic_reg(base, PIC_TIMER_COUNT(timer)); nlm_pic_read_timer32()
281 nlm_pic_write_timer(uint64_t base, int timer, uint64_t value) nlm_pic_write_timer() argument
283 nlm_write_pic_reg(base, PIC_TIMER_COUNT(timer), value); nlm_pic_write_timer()
287 nlm_pic_set_timer(uint64_t base, int timer, uint64_t value, int irq, int cpu) nlm_pic_set_timer() argument
289 uint64_t pic_ctrl = nlm_read_pic_reg(base, PIC_CTRL); nlm_pic_set_timer()
293 nlm_write_pic_reg(base, PIC_TIMER_MAXVAL(timer), value); nlm_pic_set_timer()
294 nlm_pic_write_irt_direct(base, PIC_IRT_TIMER_INDEX(timer), nlm_pic_set_timer()
299 nlm_write_pic_reg(base, PIC_CTRL, pic_ctrl); nlm_pic_set_timer()
303 nlm_pic_enable_irt(uint64_t base, int irt) nlm_pic_enable_irt() argument
308 reg = nlm_read_pic_reg(base, PIC_9XX_IRT(irt)); nlm_pic_enable_irt()
309 nlm_write_pic_reg(base, PIC_9XX_IRT(irt), reg | (1 << 22)); nlm_pic_enable_irt()
311 reg = nlm_read_pic_reg(base, PIC_IRT(irt)); nlm_pic_enable_irt()
312 nlm_write_pic_reg(base, PIC_IRT(irt), reg | (1u << 31)); nlm_pic_enable_irt()
317 nlm_pic_disable_irt(uint64_t base, int irt) nlm_pic_disable_irt() argument
322 reg = nlm_read_pic_reg(base, PIC_9XX_IRT(irt)); nlm_pic_disable_irt()
324 nlm_write_pic_reg(base, PIC_9XX_IRT(irt), reg); nlm_pic_disable_irt()
326 reg = nlm_read_pic_reg(base, PIC_IRT(irt)); nlm_pic_disable_irt()
328 nlm_write_pic_reg(base, PIC_IRT(irt), reg); nlm_pic_disable_irt()
333 nlm_pic_send_ipi(uint64_t base, int hwt, int irq, int nmi) nlm_pic_send_ipi() argument
344 nlm_write_pic_reg(base, PIC_IPI_CTL, ipi); nlm_pic_send_ipi()
348 nlm_pic_ack(uint64_t base, int irt_num) nlm_pic_ack() argument
350 nlm_write_pic_reg(base, PIC_INT_ACK, irt_num); nlm_pic_ack()
354 nlm_write_pic_reg(base, PIC_STATUS, (1 << irt_num)); nlm_pic_ack()
358 nlm_pic_init_irt(uint64_t base, int irt, int irq, int hwt, int en) nlm_pic_init_irt() argument
360 nlm_pic_write_irt_direct(base, irt, en, 0, 0, irq, hwt); nlm_pic_init_irt()
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| /linux-4.4.14/drivers/gpu/drm/i915/ |
| H A D | intel_dp_mst.c | 36 struct drm_device *dev = encoder->base.dev; intel_dp_mst_compute_config()
37 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base); intel_dp_mst_compute_config()
43 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; intel_dp_mst_compute_config()
65 state = pipe_config->base.state; intel_dp_mst_compute_config()
70 if (connector_state->best_encoder == &encoder->base) { for_each_connector_in_state()
102 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base); intel_mst_disable_dp()
119 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base); intel_mst_post_disable_dp()
135 intel_dig_port->base.post_disable(&intel_dig_port->base); intel_mst_post_disable_dp()
142 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base); intel_mst_pre_enable_dp()
145 struct drm_device *dev = encoder->base.dev; intel_mst_pre_enable_dp()
152 struct drm_crtc *crtc = encoder->base.crtc; intel_mst_pre_enable_dp()
156 if (connector->base.state->best_encoder == &encoder->base) { for_each_intel_connector()
185 intel_ddi_init_dp_buf_reg(&intel_dig_port->base);
212 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base); intel_mst_enable_dp()
215 struct drm_device *dev = intel_dig_port->base.base.dev; intel_mst_enable_dp()
234 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base); intel_dp_mst_enc_get_hw_state()
244 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base); intel_dp_mst_enc_get_config()
246 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); intel_dp_mst_enc_get_config()
247 struct drm_device *dev = encoder->base.dev; intel_dp_mst_enc_get_config()
280 pipe_config->base.adjusted_mode.flags |= flags; intel_dp_mst_enc_get_config()
287 intel_ddi_clock_get(&intel_dig_port->base, pipe_config); intel_dp_mst_enc_get_config()
373 return &intel_dp->mst_encoders[crtc->pipe]->base.base; intel_mst_atomic_best_encoder()
380 return &intel_dp->mst_encoders[0]->base.base; intel_mst_best_encoder()
404 if (connector->encoder && connector->base.state->crtc) { intel_dp_mst_get_hw_state()
416 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); intel_connector_add_to_fbdev()
417 drm_fb_helper_add_one_connector(&dev_priv->fbdev->helper, &connector->base); intel_connector_add_to_fbdev()
424 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); intel_connector_remove_from_fbdev()
425 drm_fb_helper_remove_one_connector(&dev_priv->fbdev->helper, &connector->base); intel_connector_remove_from_fbdev()
433 struct drm_device *dev = intel_dig_port->base.base.dev; intel_dp_add_mst_connector()
442 connector = &intel_connector->base; intel_dp_add_mst_connector()
452 drm_mode_connector_attach_encoder(&intel_connector->base, intel_dp_add_mst_connector()
453 &intel_dp->mst_encoders[i]->base.base); intel_dp_add_mst_connector()
457 drm_object_attach_property(&connector->base, dev->mode_config.path_property, 0); intel_dp_add_mst_connector()
458 drm_object_attach_property(&connector->base, dev->mode_config.tile_property, 0); intel_dp_add_mst_connector()
471 drm_connector_register(&intel_connector->base); intel_dp_register_mst_connector()
508 struct drm_device *dev = intel_dig_port->base.base.dev; intel_dp_mst_hotplug()
525 struct drm_device *dev = intel_dig_port->base.base.dev; intel_dp_create_fake_mst_encoder()
533 intel_encoder = &intel_mst->base; intel_dp_create_fake_mst_encoder()
536 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_mst_enc_funcs, intel_dp_create_fake_mst_encoder()
570 struct drm_device *dev = intel_dig_port->base.base.dev; intel_dp_mst_encoder_init()
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| /linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/engine/dma/ |
| H A D | usernv04.c | 24 #define nv04_dmaobj(p) container_of((p), struct nv04_dmaobj, base)
34 struct nvkm_dmaobj base; member in struct:nv04_dmaobj
41 nv04_dmaobj_bind(struct nvkm_dmaobj *base, struct nvkm_gpuobj *parent, nv04_dmaobj_bind() argument
44 struct nv04_dmaobj *dmaobj = nv04_dmaobj(base); nv04_dmaobj_bind()
45 struct nvkm_device *device = dmaobj->base.dma->engine.subdev.device; nv04_dmaobj_bind()
46 u64 offset = dmaobj->base.start & 0xfffff000; nv04_dmaobj_bind()
47 u64 adjust = dmaobj->base.start & 0x00000fff; nv04_dmaobj_bind()
48 u32 length = dmaobj->base.limit - dmaobj->base.start; nv04_dmaobj_bind()
54 if (!dmaobj->base.start) nv04_dmaobj_bind()
90 *pdmaobj = &dmaobj->base; nv04_dmaobj_new()
93 &data, &size, &dmaobj->base); nv04_dmaobj_new()
97 if (dmaobj->base.target == NV_MEM_TARGET_VM) { nv04_dmaobj_new()
100 dmaobj->base.target = NV_MEM_TARGET_PCI; nv04_dmaobj_new()
101 dmaobj->base.access = NV_MEM_ACCESS_RW; nv04_dmaobj_new()
104 dmaobj->flags0 = oclass->base.oclass; nv04_dmaobj_new()
105 switch (dmaobj->base.target) { nv04_dmaobj_new()
119 switch (dmaobj->base.access) { nv04_dmaobj_new()
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| /linux-4.4.14/drivers/net/phy/ |
| H A D | mdio-bcm-iproc.c | 46 void __iomem *base; member in struct:iproc_mdio_priv
49 static inline int iproc_mdio_wait_for_idle(void __iomem *base) iproc_mdio_wait_for_idle() argument
55 val = readl(base + MII_CTRL_OFFSET); iproc_mdio_wait_for_idle()
65 static inline void iproc_mdio_config_clk(void __iomem *base) iproc_mdio_config_clk() argument
71 writel(val, base + MII_CTRL_OFFSET); iproc_mdio_config_clk()
80 rc = iproc_mdio_wait_for_idle(priv->base); iproc_mdio_read()
84 iproc_mdio_config_clk(priv->base); iproc_mdio_read()
93 writel(cmd, priv->base + MII_DATA_OFFSET); iproc_mdio_read()
95 rc = iproc_mdio_wait_for_idle(priv->base); iproc_mdio_read()
99 cmd = readl(priv->base + MII_DATA_OFFSET) & MII_DATA_MASK; iproc_mdio_read()
111 rc = iproc_mdio_wait_for_idle(priv->base); iproc_mdio_write()
115 iproc_mdio_config_clk(priv->base); iproc_mdio_write()
125 writel(cmd, priv->base + MII_DATA_OFFSET); iproc_mdio_write()
127 rc = iproc_mdio_wait_for_idle(priv->base); iproc_mdio_write()
146 priv->base = devm_ioremap_resource(&pdev->dev, res); iproc_mdio_probe()
147 if (IS_ERR(priv->base)) { iproc_mdio_probe()
149 return PTR_ERR(priv->base); iproc_mdio_probe()
174 dev_info(&pdev->dev, "Broadcom iProc MDIO bus at 0x%p\n", priv->base); iproc_mdio_probe()
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