140 	void __iomem *base;  member
196 		writeb_relaxed(val, miphy_phy->base + CTRL_REG);  in miphy365x_init_pcie_port()
197 		writeb_relaxed(0x00, miphy_phy->base + PCIE_REG);  in miphy365x_init_pcie_port()
211 		regval = readb_relaxed(miphy_phy->base + STATUS_REG);  in miphy365x_hfc_not_rdy()
230 		regval = readb_relaxed(miphy_phy->base + STATUS_REG);  in miphy365x_rdy()
248 			       miphy_phy->base + COMP_CTRL2_REG);  in miphy365x_set_comp()
251 			       miphy_phy->base + COMP_CTRL2_REG);  in miphy365x_set_comp()
255 			       miphy_phy->base + COMP_CTRL3_REG);  in miphy365x_set_comp()
261 		writeb_relaxed(BYPASS_PLL_CAL, miphy_phy->base + PLL_CTRL2_REG);  in miphy365x_set_comp()
262 		writeb_relaxed(COMZC_IDLL, miphy_phy->base + COMP_IDLL_REG);  in miphy365x_set_comp()
270 	writeb_relaxed(val, miphy_phy->base + COMP_CTRL1_REG);  in miphy365x_set_comp()
273 	while ((readb_relaxed(miphy_phy->base + COMP_CTRL1_REG) & mask)	!= mask)  in miphy365x_set_comp()
288 		       miphy_phy->base + PLL_SSC_STEP_MSB_REG);  in miphy365x_set_ssc()
290 		       miphy_phy->base + PLL_SSC_STEP_LSB_REG);  in miphy365x_set_ssc()
292 		       miphy_phy->base + PLL_SSC_PER_MSB_REG);  in miphy365x_set_ssc()
294 		       miphy_phy->base + PLL_SSC_PER_LSB_REG);  in miphy365x_set_ssc()
299 		writeb_relaxed(val, miphy_phy->base + PLL_CTRL1_REG);  in miphy365x_set_ssc()
302 		writeb_relaxed(val, miphy_phy->base + PLL_CTRL1_REG);  in miphy365x_set_ssc()
317 	writeb_relaxed(val, miphy_phy->base + RESET_REG);  in miphy365x_init_sata_port()
320 		writeb_relaxed(TX_POL, miphy_phy->base + CTRL_REG);  in miphy365x_init_sata_port()
327 	writeb_relaxed(SPDSEL_SEL, miphy_phy->base + BOUNDARY1_REG);  in miphy365x_init_sata_port()
328 	writeb_relaxed(START_CLK_HF, miphy_phy->base + IDLL_TEST_REG);  in miphy365x_init_sata_port()
330 	writeb_relaxed(val, miphy_phy->base + BOUNDARY3_REG);  in miphy365x_init_sata_port()
348 		writeb_relaxed(val, miphy_phy->base + BUF_SEL_REG);  in miphy365x_init_sata_port()
350 		writeb_relaxed(val, miphy_phy->base + TXBUF1_REG);  in miphy365x_init_sata_port()
351 		writeb_relaxed(TXSLEW_VAL, miphy_phy->base + TXBUF2_REG);  in miphy365x_init_sata_port()
352 		writeb_relaxed(0x00, miphy_phy->base + RXBUF_OFFSET_CTRL_REG);  in miphy365x_init_sata_port()
354 		writeb_relaxed(val, miphy_phy->base + RXBUF_REG);  in miphy365x_init_sata_port()
365 			       miphy_phy->base + BUF_SEL_REG);  in miphy365x_init_sata_port()
366 		writeb_relaxed(SWING_VAL, miphy_phy->base + TXBUF1_REG);  in miphy365x_init_sata_port()
367 		writeb_relaxed(TXSLEW_VAL, miphy_phy->base + TXBUF2_REG);  in miphy365x_init_sata_port()
369 		writeb_relaxed(val, miphy_phy->base + RXBUF_REG);  in miphy365x_init_sata_port()
378 		writeb_relaxed(PD_VDDTFILTER, miphy_phy->base + BUF_SEL_REG);  in miphy365x_init_sata_port()
379 		writeb_relaxed(SWING_VAL_GEN1, miphy_phy->base + TXBUF1_REG);  in miphy365x_init_sata_port()
380 		writeb_relaxed(TXSLEW_VAL_GEN1,	miphy_phy->base + TXBUF2_REG);  in miphy365x_init_sata_port()
387 	writeb_relaxed(RST_RX, miphy_phy->base + RESET_REG);  in miphy365x_init_sata_port()
405 	writeb_relaxed(0x00, miphy_phy->base + BOUNDARY1_REG);  in miphy365x_init_sata_port()
406 	writeb_relaxed(0x00, miphy_phy->base + IDLL_TEST_REG);  in miphy365x_init_sata_port()
407 	writeb_relaxed(RST_RX, miphy_phy->base + RESET_REG);  in miphy365x_init_sata_port()
410 	writeb_relaxed(val, miphy_phy->base + CTRL_REG);  in miphy365x_init_sata_port()
413 	writeb_relaxed(val, miphy_phy->base + DES_BITLOCK_REG);  in miphy365x_init_sata_port()
414 	writeb_relaxed(0x00, miphy_phy->base + RESET_REG);  in miphy365x_init_sata_port()
462 	miphy_phy->base = of_iomap(phynode, index);  in miphy365x_get_addr()
463 	if (!miphy_phy->base) {  in miphy365x_get_addr()