77 #define ATAPI_GET_CONTROL(base)\  argument
78 	bfin_read16(base + ATAPI_OFFSET_CONTROL)
79 #define ATAPI_SET_CONTROL(base, val)\  argument
80 	bfin_write16(base + ATAPI_OFFSET_CONTROL, val)
81 #define ATAPI_GET_STATUS(base)\  argument
82 	bfin_read16(base + ATAPI_OFFSET_STATUS)
83 #define ATAPI_GET_DEV_ADDR(base)\  argument
84 	bfin_read16(base + ATAPI_OFFSET_DEV_ADDR)
85 #define ATAPI_SET_DEV_ADDR(base, val)\  argument
86 	bfin_write16(base + ATAPI_OFFSET_DEV_ADDR, val)
87 #define ATAPI_GET_DEV_TXBUF(base)\  argument
88 	bfin_read16(base + ATAPI_OFFSET_DEV_TXBUF)
89 #define ATAPI_SET_DEV_TXBUF(base, val)\  argument
90 	bfin_write16(base + ATAPI_OFFSET_DEV_TXBUF, val)
91 #define ATAPI_GET_DEV_RXBUF(base)\  argument
92 	bfin_read16(base + ATAPI_OFFSET_DEV_RXBUF)
93 #define ATAPI_SET_DEV_RXBUF(base, val)\  argument
94 	bfin_write16(base + ATAPI_OFFSET_DEV_RXBUF, val)
95 #define ATAPI_GET_INT_MASK(base)\  argument
96 	bfin_read16(base + ATAPI_OFFSET_INT_MASK)
97 #define ATAPI_SET_INT_MASK(base, val)\  argument
98 	bfin_write16(base + ATAPI_OFFSET_INT_MASK, val)
99 #define ATAPI_GET_INT_STATUS(base)\  argument
100 	bfin_read16(base + ATAPI_OFFSET_INT_STATUS)
101 #define ATAPI_SET_INT_STATUS(base, val)\  argument
102 	bfin_write16(base + ATAPI_OFFSET_INT_STATUS, val)
103 #define ATAPI_GET_XFER_LEN(base)\  argument
104 	bfin_read16(base + ATAPI_OFFSET_XFER_LEN)
105 #define ATAPI_SET_XFER_LEN(base, val)\  argument
106 	bfin_write16(base + ATAPI_OFFSET_XFER_LEN, val)
107 #define ATAPI_GET_LINE_STATUS(base)\  argument
108 	bfin_read16(base + ATAPI_OFFSET_LINE_STATUS)
109 #define ATAPI_GET_SM_STATE(base)\  argument
110 	bfin_read16(base + ATAPI_OFFSET_SM_STATE)
111 #define ATAPI_GET_TERMINATE(base)\  argument
112 	bfin_read16(base + ATAPI_OFFSET_TERMINATE)
113 #define ATAPI_SET_TERMINATE(base, val)\  argument
114 	bfin_write16(base + ATAPI_OFFSET_TERMINATE, val)
115 #define ATAPI_GET_PIO_TFRCNT(base)\  argument
116 	bfin_read16(base + ATAPI_OFFSET_PIO_TFRCNT)
117 #define ATAPI_GET_DMA_TFRCNT(base)\  argument
118 	bfin_read16(base + ATAPI_OFFSET_DMA_TFRCNT)
119 #define ATAPI_GET_UMAIN_TFRCNT(base)\  argument
120 	bfin_read16(base + ATAPI_OFFSET_UMAIN_TFRCNT)
121 #define ATAPI_GET_UDMAOUT_TFRCNT(base)\  argument
122 	bfin_read16(base + ATAPI_OFFSET_UDMAOUT_TFRCNT)
123 #define ATAPI_GET_REG_TIM_0(base)\  argument
124 	bfin_read16(base + ATAPI_OFFSET_REG_TIM_0)
125 #define ATAPI_SET_REG_TIM_0(base, val)\  argument
126 	bfin_write16(base + ATAPI_OFFSET_REG_TIM_0, val)
127 #define ATAPI_GET_PIO_TIM_0(base)\  argument
128 	bfin_read16(base + ATAPI_OFFSET_PIO_TIM_0)
129 #define ATAPI_SET_PIO_TIM_0(base, val)\  argument
130 	bfin_write16(base + ATAPI_OFFSET_PIO_TIM_0, val)
131 #define ATAPI_GET_PIO_TIM_1(base)\  argument
132 	bfin_read16(base + ATAPI_OFFSET_PIO_TIM_1)
133 #define ATAPI_SET_PIO_TIM_1(base, val)\  argument
134 	bfin_write16(base + ATAPI_OFFSET_PIO_TIM_1, val)
135 #define ATAPI_GET_MULTI_TIM_0(base)\  argument
136 	bfin_read16(base + ATAPI_OFFSET_MULTI_TIM_0)
137 #define ATAPI_SET_MULTI_TIM_0(base, val)\  argument
138 	bfin_write16(base + ATAPI_OFFSET_MULTI_TIM_0, val)
139 #define ATAPI_GET_MULTI_TIM_1(base)\  argument
140 	bfin_read16(base + ATAPI_OFFSET_MULTI_TIM_1)
141 #define ATAPI_SET_MULTI_TIM_1(base, val)\  argument
142 	bfin_write16(base + ATAPI_OFFSET_MULTI_TIM_1, val)
143 #define ATAPI_GET_MULTI_TIM_2(base)\  argument
144 	bfin_read16(base + ATAPI_OFFSET_MULTI_TIM_2)
145 #define ATAPI_SET_MULTI_TIM_2(base, val)\  argument
146 	bfin_write16(base + ATAPI_OFFSET_MULTI_TIM_2, val)
147 #define ATAPI_GET_ULTRA_TIM_0(base)\  argument
148 	bfin_read16(base + ATAPI_OFFSET_ULTRA_TIM_0)
149 #define ATAPI_SET_ULTRA_TIM_0(base, val)\  argument
150 	bfin_write16(base + ATAPI_OFFSET_ULTRA_TIM_0, val)
151 #define ATAPI_GET_ULTRA_TIM_1(base)\  argument
152 	bfin_read16(base + ATAPI_OFFSET_ULTRA_TIM_1)
153 #define ATAPI_SET_ULTRA_TIM_1(base, val)\  argument
154 	bfin_write16(base + ATAPI_OFFSET_ULTRA_TIM_1, val)
155 #define ATAPI_GET_ULTRA_TIM_2(base)\  argument
156 	bfin_read16(base + ATAPI_OFFSET_ULTRA_TIM_2)
157 #define ATAPI_SET_ULTRA_TIM_2(base, val)\  argument
158 	bfin_write16(base + ATAPI_OFFSET_ULTRA_TIM_2, val)
159 #define ATAPI_GET_ULTRA_TIM_3(base)\  argument
160 	bfin_read16(base + ATAPI_OFFSET_ULTRA_TIM_3)
161 #define ATAPI_SET_ULTRA_TIM_3(base, val)\  argument
162 	bfin_write16(base + ATAPI_OFFSET_ULTRA_TIM_3, val)
292 	void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;  in bfin_set_piomode()  local
339 		ATAPI_SET_REG_TIM_0(base, (teoc_reg<<8 | t2_reg));  in bfin_set_piomode()
340 		ATAPI_SET_PIO_TIM_0(base, (t4_reg<<12 | t2_pio<<4 | t1_reg));  in bfin_set_piomode()
341 		ATAPI_SET_PIO_TIM_1(base, teoc_pio);  in bfin_set_piomode()
343 			ATAPI_SET_CONTROL(base,  in bfin_set_piomode()
344 				ATAPI_GET_CONTROL(base) | IORDY_EN);  in bfin_set_piomode()
346 			ATAPI_SET_CONTROL(base,  in bfin_set_piomode()
347 				ATAPI_GET_CONTROL(base) & ~IORDY_EN);  in bfin_set_piomode()
351 		ATAPI_SET_INT_MASK(base, ATAPI_GET_INT_MASK(base)  in bfin_set_piomode()
371 	void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;  in bfin_set_dmamode()  local
418 				ATAPI_SET_ULTRA_TIM_0(base, (tenv<<8 | tack));  in bfin_set_dmamode()
419 				ATAPI_SET_ULTRA_TIM_1(base,  in bfin_set_dmamode()
421 				ATAPI_SET_ULTRA_TIM_2(base, (tmli<<8 | tss));  in bfin_set_dmamode()
422 				ATAPI_SET_ULTRA_TIM_3(base, (trp<<8 | tzah));  in bfin_set_dmamode()
464 			ATAPI_SET_MULTI_TIM_0(base, (tm<<8 | td));  in bfin_set_dmamode()
465 			ATAPI_SET_MULTI_TIM_1(base, (tkr<<8 | tkw));  in bfin_set_dmamode()
466 			ATAPI_SET_MULTI_TIM_2(base, (teoc<<8 | th));  in bfin_set_dmamode()
480 static inline void wait_complete(void __iomem *base, unsigned short mask)  in wait_complete()  argument
488 		status = ATAPI_GET_INT_STATUS(base) & mask;  in wait_complete()
493 	ATAPI_SET_INT_STATUS(base, mask);  in wait_complete()
504 static void write_atapi_register(void __iomem *base,  in write_atapi_register()  argument
510 	ATAPI_SET_DEV_TXBUF(base, value);  in write_atapi_register()
515 	ATAPI_SET_DEV_ADDR(base, ata_reg);  in write_atapi_register()
519 	ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) | XFER_DIR));  in write_atapi_register()
522 	ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) & ~PIO_USE_DMA));  in write_atapi_register()
525 	ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) | PIO_START));  in write_atapi_register()
530 	wait_complete(base, PIO_DONE_INT);  in write_atapi_register()
541 static unsigned short read_atapi_register(void __iomem *base,  in read_atapi_register()  argument
547 	ATAPI_SET_DEV_ADDR(base, ata_reg);  in read_atapi_register()
551 	ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) & ~XFER_DIR));  in read_atapi_register()
554 	ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) & ~PIO_USE_DMA));  in read_atapi_register()
557 	ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) | PIO_START));  in read_atapi_register()
563 	wait_complete(base, PIO_DONE_INT);  in read_atapi_register()
568 	return ATAPI_GET_DEV_RXBUF(base);  in read_atapi_register()
579 static void write_atapi_data(void __iomem *base,  in write_atapi_data()  argument
585 	ATAPI_SET_XFER_LEN(base, 1);  in write_atapi_data()
590 	ATAPI_SET_DEV_ADDR(base, ATA_REG_DATA);  in write_atapi_data()
594 	ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) | XFER_DIR));  in write_atapi_data()
597 	ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) & ~PIO_USE_DMA));  in write_atapi_data()
603 		ATAPI_SET_DEV_TXBUF(base, buf[i]);  in write_atapi_data()
606 		ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) | PIO_START));  in write_atapi_data()
612 		wait_complete(base, PIO_DONE_INT);  in write_atapi_data()
624 static void read_atapi_data(void __iomem *base,  in read_atapi_data()  argument
630 	ATAPI_SET_XFER_LEN(base, 1);  in read_atapi_data()
635 	ATAPI_SET_DEV_ADDR(base, ATA_REG_DATA);  in read_atapi_data()
639 	ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) & ~XFER_DIR));  in read_atapi_data()
642 	ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) & ~PIO_USE_DMA));  in read_atapi_data()
646 		ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) | PIO_START));  in read_atapi_data()
652 		wait_complete(base, PIO_DONE_INT);  in read_atapi_data()
657 		buf[i] = ATAPI_GET_DEV_RXBUF(base);  in read_atapi_data()
671 	void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;  in bfin_tf_load()  local
675 		write_atapi_register(base, ATA_REG_CTRL, tf->ctl);  in bfin_tf_load()
682 			write_atapi_register(base, ATA_REG_FEATURE,  in bfin_tf_load()
684 			write_atapi_register(base, ATA_REG_NSECT,  in bfin_tf_load()
686 			write_atapi_register(base, ATA_REG_LBAL, tf->hob_lbal);  in bfin_tf_load()
687 			write_atapi_register(base, ATA_REG_LBAM, tf->hob_lbam);  in bfin_tf_load()
688 			write_atapi_register(base, ATA_REG_LBAH, tf->hob_lbah);  in bfin_tf_load()
698 		write_atapi_register(base, ATA_REG_FEATURE, tf->feature);  in bfin_tf_load()
699 		write_atapi_register(base, ATA_REG_NSECT, tf->nsect);  in bfin_tf_load()
700 		write_atapi_register(base, ATA_REG_LBAL, tf->lbal);  in bfin_tf_load()
701 		write_atapi_register(base, ATA_REG_LBAM, tf->lbam);  in bfin_tf_load()
702 		write_atapi_register(base, ATA_REG_LBAH, tf->lbah);  in bfin_tf_load()
712 		write_atapi_register(base, ATA_REG_DEVICE, tf->device);  in bfin_tf_load()
728 	void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;  in bfin_check_status()  local
729 	return read_atapi_register(base, ATA_REG_STATUS);  in bfin_check_status()
742 	void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;  in bfin_tf_read()  local
745 	tf->feature = read_atapi_register(base, ATA_REG_ERR);  in bfin_tf_read()
746 	tf->nsect = read_atapi_register(base, ATA_REG_NSECT);  in bfin_tf_read()
747 	tf->lbal = read_atapi_register(base, ATA_REG_LBAL);  in bfin_tf_read()
748 	tf->lbam = read_atapi_register(base, ATA_REG_LBAM);  in bfin_tf_read()
749 	tf->lbah = read_atapi_register(base, ATA_REG_LBAH);  in bfin_tf_read()
750 	tf->device = read_atapi_register(base, ATA_REG_DEVICE);  in bfin_tf_read()
753 		write_atapi_register(base, ATA_REG_CTRL, tf->ctl | ATA_HOB);  in bfin_tf_read()
754 		tf->hob_feature = read_atapi_register(base, ATA_REG_ERR);  in bfin_tf_read()
755 		tf->hob_nsect = read_atapi_register(base, ATA_REG_NSECT);  in bfin_tf_read()
756 		tf->hob_lbal = read_atapi_register(base, ATA_REG_LBAL);  in bfin_tf_read()
757 		tf->hob_lbam = read_atapi_register(base, ATA_REG_LBAM);  in bfin_tf_read()
758 		tf->hob_lbah = read_atapi_register(base, ATA_REG_LBAH);  in bfin_tf_read()
773 	void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;  in bfin_exec_command()  local
776 	write_atapi_register(base, ATA_REG_CMD, tf->command);  in bfin_exec_command()
787 	void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;  in bfin_check_altstatus()  local
788 	return read_atapi_register(base, ATA_REG_ALTSTATUS);  in bfin_check_altstatus()
801 	void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;  in bfin_dev_select()  local
809 	write_atapi_register(base, ATA_REG_DEVICE, tmp);  in bfin_dev_select()
821 	void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;  in bfin_set_devctl()  local
822 	write_atapi_register(base, ATA_REG_CTRL, ctl);  in bfin_set_devctl()
836 	void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;  in bfin_bmdma_setup()  local
886 		ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base)  in bfin_bmdma_setup()
890 		ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base)  in bfin_bmdma_setup()
895 	ATAPI_SET_CONTROL(base, ATAPI_GET_CONTROL(base) | TFRCNT_RST);  in bfin_bmdma_setup()
898 	ATAPI_SET_CONTROL(base, ATAPI_GET_CONTROL(base) | END_ON_TERM);  in bfin_bmdma_setup()
901 	ATAPI_SET_XFER_LEN(base, size >> 1);  in bfin_bmdma_setup()
914 	void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;  in bfin_bmdma_start()  local
923 		ATAPI_SET_CONTROL(base, ATAPI_GET_CONTROL(base)  in bfin_bmdma_start()
926 		ATAPI_SET_CONTROL(base, ATAPI_GET_CONTROL(base)  in bfin_bmdma_start()
968 	void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;  in bfin_devchk()  local
973 	write_atapi_register(base, ATA_REG_NSECT, 0x55);  in bfin_devchk()
974 	write_atapi_register(base, ATA_REG_LBAL, 0xaa);  in bfin_devchk()
976 	write_atapi_register(base, ATA_REG_NSECT, 0xaa);  in bfin_devchk()
977 	write_atapi_register(base, ATA_REG_LBAL, 0x55);  in bfin_devchk()
979 	write_atapi_register(base, ATA_REG_NSECT, 0x55);  in bfin_devchk()
980 	write_atapi_register(base, ATA_REG_LBAL, 0xaa);  in bfin_devchk()
982 	nsect = read_atapi_register(base, ATA_REG_NSECT);  in bfin_devchk()
983 	lbal = read_atapi_register(base, ATA_REG_LBAL);  in bfin_devchk()
999 	void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;  in bfin_bus_post_reset()  local
1018 		nsect = read_atapi_register(base, ATA_REG_NSECT);  in bfin_bus_post_reset()
1019 		lbal = read_atapi_register(base, ATA_REG_LBAL);  in bfin_bus_post_reset()
1048 	void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;  in bfin_bus_softreset()  local
1051 	write_atapi_register(base, ATA_REG_CTRL, ap->ctl);  in bfin_bus_softreset()
1053 	write_atapi_register(base, ATA_REG_CTRL, ap->ctl | ATA_SRST);  in bfin_bus_softreset()
1055 	write_atapi_register(base, ATA_REG_CTRL, ap->ctl);  in bfin_bus_softreset()
1132 	void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;  in bfin_bmdma_status()  local
1134 	if (ATAPI_GET_STATUS(base) & (MULTI_XFER_ON | ULTRA_XFER_ON))  in bfin_bmdma_status()
1136 	if (ATAPI_GET_INT_STATUS(base) & ATAPI_DEV_INT)  in bfin_bmdma_status()
1158 	void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;  in bfin_data_xfer()  local
1164 		read_atapi_data(base, words, buf16);  in bfin_data_xfer()
1166 		write_atapi_data(base, words, buf16);  in bfin_data_xfer()
1174 			read_atapi_data(base, 1, align_buf);  in bfin_data_xfer()
1178 			write_atapi_data(base, 1, align_buf);  in bfin_data_xfer()
1195 	void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;  in bfin_irq_clear()  local
1198 	ATAPI_SET_INT_STATUS(base, ATAPI_GET_INT_STATUS(base)|ATAPI_DEV_INT  in bfin_irq_clear()
1228 	void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;  in bfin_postreset()  local
1245 	write_atapi_register(base, ATA_REG_CTRL, ap->ctl);  in bfin_postreset()
1464 	void __iomem *base = (void __iomem *)host->ports[0]->ioaddr.ctl_addr;  in bfin_reset_controller()  local
1469 	ATAPI_SET_INT_MASK(base, 0);  in bfin_reset_controller()
1473 	ATAPI_SET_CONTROL(base, ATAPI_GET_CONTROL(base) | DEV_RST);  in bfin_reset_controller()
1477 	ATAPI_SET_CONTROL(base, ATAPI_GET_CONTROL(base) & ~DEV_RST);  in bfin_reset_controller()
1483 		status = read_atapi_register(base, ATA_REG_STATUS);  in bfin_reset_controller()
1487 	ATAPI_SET_INT_MASK(base, 1);  in bfin_reset_controller()