35 nv04_fifo_dma_object_dtor(struct nvkm_fifo_chan *base, int cookie)  in nv04_fifo_dma_object_dtor()  argument
37 	struct nv04_fifo_chan *chan = nv04_fifo_chan(base);  in nv04_fifo_dma_object_dtor()
38 	struct nvkm_instmem *imem = chan->fifo->base.engine.subdev.device->imem;  in nv04_fifo_dma_object_dtor()
43 nv04_fifo_dma_object_ctor(struct nvkm_fifo_chan *base,  in nv04_fifo_dma_object_ctor()  argument
46 	struct nv04_fifo_chan *chan = nv04_fifo_chan(base);  in nv04_fifo_dma_object_ctor()
47 	struct nvkm_instmem *imem = chan->fifo->base.engine.subdev.device->imem;  in nv04_fifo_dma_object_ctor()
48 	u32 context = 0x80000000 | chan->base.chid << 24;  in nv04_fifo_dma_object_ctor()
62 	mutex_lock(&chan->fifo->base.engine.subdev.mutex);  in nv04_fifo_dma_object_ctor()
63 	hash = nvkm_ramht_insert(imem->ramht, object, chan->base.chid, 4,  in nv04_fifo_dma_object_ctor()
65 	mutex_unlock(&chan->fifo->base.engine.subdev.mutex);  in nv04_fifo_dma_object_ctor()
70 nv04_fifo_dma_fini(struct nvkm_fifo_chan *base)  in nv04_fifo_dma_fini()  argument
72 	struct nv04_fifo_chan *chan = nv04_fifo_chan(base);  in nv04_fifo_dma_fini()
74 	struct nvkm_device *device = fifo->base.engine.subdev.device;  in nv04_fifo_dma_fini()
78 	u32 mask = fifo->base.nr - 1;  in nv04_fifo_dma_fini()
83 	spin_lock_irqsave(&fifo->base.lock, flags);  in nv04_fifo_dma_fini()
88 	if (chid == chan->base.chid) {  in nv04_fifo_dma_fini()
115 	nvkm_mask(device, NV04_PFIFO_MODE, 1 << chan->base.chid, 0);  in nv04_fifo_dma_fini()
117 	spin_unlock_irqrestore(&fifo->base.lock, flags);  in nv04_fifo_dma_fini()
121 nv04_fifo_dma_init(struct nvkm_fifo_chan *base)  in nv04_fifo_dma_init()  argument
123 	struct nv04_fifo_chan *chan = nv04_fifo_chan(base);  in nv04_fifo_dma_init()
125 	struct nvkm_device *device = fifo->base.engine.subdev.device;  in nv04_fifo_dma_init()
126 	u32 mask = 1 << chan->base.chid;  in nv04_fifo_dma_init()
128 	spin_lock_irqsave(&fifo->base.lock, flags);  in nv04_fifo_dma_init()
130 	spin_unlock_irqrestore(&fifo->base.lock, flags);  in nv04_fifo_dma_init()
134 nv04_fifo_dma_dtor(struct nvkm_fifo_chan *base)  in nv04_fifo_dma_dtor()  argument
136 	struct nv04_fifo_chan *chan = nv04_fifo_chan(base);  in nv04_fifo_dma_dtor()
138 	struct nvkm_instmem *imem = fifo->base.engine.subdev.device->imem;  in nv04_fifo_dma_dtor()
159 nv04_fifo_dma_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass,  in nv04_fifo_dma_new()  argument
166 	struct nv04_fifo *fifo = nv04_fifo(base);  in nv04_fifo_dma_new()
168 	struct nvkm_device *device = fifo->base.engine.subdev.device;  in nv04_fifo_dma_new()
184 	*pobject = &chan->base.object;  in nv04_fifo_dma_new()
186 	ret = nvkm_fifo_chan_ctor(&nv04_fifo_dma_func, &fifo->base,  in nv04_fifo_dma_new()
191 				  0, 0x800000, 0x10000, oclass, &chan->base);  in nv04_fifo_dma_new()
196 	args->v0.chid = chan->base.chid;  in nv04_fifo_dma_new()
197 	chan->ramfc = chan->base.chid * 32;  in nv04_fifo_dma_new()
202 	nvkm_wo32(imem->ramfc, chan->ramfc + 0x08, chan->base.push->addr >> 4);  in nv04_fifo_dma_new()
216 	.base.oclass = NV03_CHANNEL_DMA,
217 	.base.minver = 0,
218 	.base.maxver = 0,