Lines Matching refs:base
291 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR); in au1x_ic0_unmask() local
293 __raw_writel(1 << bit, base + IC_MASKSET); in au1x_ic0_unmask()
294 __raw_writel(1 << bit, base + IC_WAKESET); in au1x_ic0_unmask()
301 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR); in au1x_ic1_unmask() local
303 __raw_writel(1 << bit, base + IC_MASKSET); in au1x_ic1_unmask()
304 __raw_writel(1 << bit, base + IC_WAKESET); in au1x_ic1_unmask()
311 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR); in au1x_ic0_mask() local
313 __raw_writel(1 << bit, base + IC_MASKCLR); in au1x_ic0_mask()
314 __raw_writel(1 << bit, base + IC_WAKECLR); in au1x_ic0_mask()
321 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR); in au1x_ic1_mask() local
323 __raw_writel(1 << bit, base + IC_MASKCLR); in au1x_ic1_mask()
324 __raw_writel(1 << bit, base + IC_WAKECLR); in au1x_ic1_mask()
331 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR); in au1x_ic0_ack() local
337 __raw_writel(1 << bit, base + IC_FALLINGCLR); in au1x_ic0_ack()
338 __raw_writel(1 << bit, base + IC_RISINGCLR); in au1x_ic0_ack()
345 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR); in au1x_ic1_ack() local
351 __raw_writel(1 << bit, base + IC_FALLINGCLR); in au1x_ic1_ack()
352 __raw_writel(1 << bit, base + IC_RISINGCLR); in au1x_ic1_ack()
359 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR); in au1x_ic0_maskack() local
361 __raw_writel(1 << bit, base + IC_WAKECLR); in au1x_ic0_maskack()
362 __raw_writel(1 << bit, base + IC_MASKCLR); in au1x_ic0_maskack()
363 __raw_writel(1 << bit, base + IC_RISINGCLR); in au1x_ic0_maskack()
364 __raw_writel(1 << bit, base + IC_FALLINGCLR); in au1x_ic0_maskack()
371 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR); in au1x_ic1_maskack() local
373 __raw_writel(1 << bit, base + IC_WAKECLR); in au1x_ic1_maskack()
374 __raw_writel(1 << bit, base + IC_MASKCLR); in au1x_ic1_maskack()
375 __raw_writel(1 << bit, base + IC_RISINGCLR); in au1x_ic1_maskack()
376 __raw_writel(1 << bit, base + IC_FALLINGCLR); in au1x_ic1_maskack()
432 void __iomem *base; in au1x_ic_settype() local
438 base = (void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR); in au1x_ic_settype()
442 base = (void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR); in au1x_ic_settype()
452 __raw_writel(1 << bit, base + IC_CFG2CLR); in au1x_ic_settype()
453 __raw_writel(1 << bit, base + IC_CFG1CLR); in au1x_ic_settype()
454 __raw_writel(1 << bit, base + IC_CFG0SET); in au1x_ic_settype()
459 __raw_writel(1 << bit, base + IC_CFG2CLR); in au1x_ic_settype()
460 __raw_writel(1 << bit, base + IC_CFG1SET); in au1x_ic_settype()
461 __raw_writel(1 << bit, base + IC_CFG0CLR); in au1x_ic_settype()
466 __raw_writel(1 << bit, base + IC_CFG2CLR); in au1x_ic_settype()
467 __raw_writel(1 << bit, base + IC_CFG1SET); in au1x_ic_settype()
468 __raw_writel(1 << bit, base + IC_CFG0SET); in au1x_ic_settype()
473 __raw_writel(1 << bit, base + IC_CFG2SET); in au1x_ic_settype()
474 __raw_writel(1 << bit, base + IC_CFG1CLR); in au1x_ic_settype()
475 __raw_writel(1 << bit, base + IC_CFG0SET); in au1x_ic_settype()
480 __raw_writel(1 << bit, base + IC_CFG2SET); in au1x_ic_settype()
481 __raw_writel(1 << bit, base + IC_CFG1SET); in au1x_ic_settype()
482 __raw_writel(1 << bit, base + IC_CFG0CLR); in au1x_ic_settype()
487 __raw_writel(1 << bit, base + IC_CFG2CLR); in au1x_ic_settype()
488 __raw_writel(1 << bit, base + IC_CFG1CLR); in au1x_ic_settype()
489 __raw_writel(1 << bit, base + IC_CFG0CLR); in au1x_ic_settype()
715 static inline void ic_init(void __iomem *base) in ic_init() argument
718 __raw_writel(0xffffffff, base + IC_CFG0CLR); in ic_init()
719 __raw_writel(0xffffffff, base + IC_CFG1CLR); in ic_init()
720 __raw_writel(0xffffffff, base + IC_CFG2CLR); in ic_init()
721 __raw_writel(0xffffffff, base + IC_MASKCLR); in ic_init()
722 __raw_writel(0xffffffff, base + IC_ASSIGNCLR); in ic_init()
723 __raw_writel(0xffffffff, base + IC_WAKECLR); in ic_init()
724 __raw_writel(0xffffffff, base + IC_SRCSET); in ic_init()
725 __raw_writel(0xffffffff, base + IC_FALLINGCLR); in ic_init()
726 __raw_writel(0xffffffff, base + IC_RISINGCLR); in ic_init()
727 __raw_writel(0x00000000, base + IC_TESTBIT); in ic_init()
733 static inline void alchemy_ic_suspend_one(void __iomem *base, unsigned long *d) in alchemy_ic_suspend_one() argument
735 d[0] = __raw_readl(base + IC_CFG0RD); in alchemy_ic_suspend_one()
736 d[1] = __raw_readl(base + IC_CFG1RD); in alchemy_ic_suspend_one()
737 d[2] = __raw_readl(base + IC_CFG2RD); in alchemy_ic_suspend_one()
738 d[3] = __raw_readl(base + IC_SRCRD); in alchemy_ic_suspend_one()
739 d[4] = __raw_readl(base + IC_ASSIGNRD); in alchemy_ic_suspend_one()
740 d[5] = __raw_readl(base + IC_WAKERD); in alchemy_ic_suspend_one()
741 d[6] = __raw_readl(base + IC_MASKRD); in alchemy_ic_suspend_one()
742 ic_init(base); /* shut it up too while at it */ in alchemy_ic_suspend_one()
745 static inline void alchemy_ic_resume_one(void __iomem *base, unsigned long *d) in alchemy_ic_resume_one() argument
747 ic_init(base); in alchemy_ic_resume_one()
749 __raw_writel(d[0], base + IC_CFG0SET); in alchemy_ic_resume_one()
750 __raw_writel(d[1], base + IC_CFG1SET); in alchemy_ic_resume_one()
751 __raw_writel(d[2], base + IC_CFG2SET); in alchemy_ic_resume_one()
752 __raw_writel(d[3], base + IC_SRCSET); in alchemy_ic_resume_one()
753 __raw_writel(d[4], base + IC_ASSIGNSET); in alchemy_ic_resume_one()
754 __raw_writel(d[5], base + IC_WAKESET); in alchemy_ic_resume_one()
757 __raw_writel(d[6], base + IC_MASKSET); in alchemy_ic_resume_one()
780 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1300_GPIC_PHYS_ADDR); in alchemy_gpic_suspend() local
784 alchemy_gpic_pmdata[0] = __raw_readl(base + AU1300_GPIC_IEN + 0x0); in alchemy_gpic_suspend()
785 alchemy_gpic_pmdata[1] = __raw_readl(base + AU1300_GPIC_IEN + 0x4); in alchemy_gpic_suspend()
786 alchemy_gpic_pmdata[2] = __raw_readl(base + AU1300_GPIC_IEN + 0x8); in alchemy_gpic_suspend()
787 alchemy_gpic_pmdata[3] = __raw_readl(base + AU1300_GPIC_IEN + 0xc); in alchemy_gpic_suspend()
790 alchemy_gpic_pmdata[4] = __raw_readl(base + AU1300_GPIC_DMASEL); in alchemy_gpic_suspend()
793 __raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0x0); in alchemy_gpic_suspend()
794 __raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0x4); in alchemy_gpic_suspend()
795 __raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0x8); in alchemy_gpic_suspend()
796 __raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0xc); in alchemy_gpic_suspend()
800 base += AU1300_GPIC_PINCFG; in alchemy_gpic_suspend()
802 alchemy_gpic_pmdata[i + 5] = __raw_readl(base + (i << 2)); in alchemy_gpic_suspend()
811 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1300_GPIC_PHYS_ADDR); in alchemy_gpic_resume() local
815 __raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0x0); in alchemy_gpic_resume()
816 __raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0x4); in alchemy_gpic_resume()
817 __raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0x8); in alchemy_gpic_resume()
818 __raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0xc); in alchemy_gpic_resume()
822 base += AU1300_GPIC_PINCFG; in alchemy_gpic_resume()
824 __raw_writel(alchemy_gpic_pmdata[i + 5], base + (i << 2)); in alchemy_gpic_resume()
828 base = (void __iomem *)KSEG1ADDR(AU1300_GPIC_PHYS_ADDR); in alchemy_gpic_resume()
829 __raw_writel(alchemy_gpic_pmdata[4], base + AU1300_GPIC_DMASEL); in alchemy_gpic_resume()
833 __raw_writel(alchemy_gpic_pmdata[0], base + AU1300_GPIC_IEN + 0x0); in alchemy_gpic_resume()
834 __raw_writel(alchemy_gpic_pmdata[1], base + AU1300_GPIC_IEN + 0x4); in alchemy_gpic_resume()
835 __raw_writel(alchemy_gpic_pmdata[2], base + AU1300_GPIC_IEN + 0x8); in alchemy_gpic_resume()
836 __raw_writel(alchemy_gpic_pmdata[3], base + AU1300_GPIC_IEN + 0xc); in alchemy_gpic_resume()
853 #define DISP(name, base, addr) \ argument
858 generic_handle_irq(base + __ffs(r)); \
879 void __iomem *base; in au1000_init_irq() local
905 base = (void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR); in au1000_init_irq()
908 base = (void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR); in au1000_init_irq()
911 __raw_writel(1 << bit, base + IC_ASSIGNSET); in au1000_init_irq()