157 	void __iomem *base;  member
178 		       dev->base + CS_OFFSET);  in bcm_kona_i2c_send_cmd_to_ctrl()
185 		       dev->base + CS_OFFSET);  in bcm_kona_i2c_send_cmd_to_ctrl()
192 		       dev->base + CS_OFFSET);  in bcm_kona_i2c_send_cmd_to_ctrl()
198 		       dev->base + CS_OFFSET);  in bcm_kona_i2c_send_cmd_to_ctrl()
208 	writel(readl(dev->base + CLKEN_OFFSET) | CLKEN_CLKEN_MASK,  in bcm_kona_i2c_enable_clock()
209 	       dev->base + CLKEN_OFFSET);  in bcm_kona_i2c_enable_clock()
214 	writel(readl(dev->base + CLKEN_OFFSET) & ~CLKEN_CLKEN_MASK,  in bcm_kona_i2c_disable_clock()
215 	       dev->base + CLKEN_OFFSET);  in bcm_kona_i2c_disable_clock()
221 	uint32_t status = readl(dev->base + ISR_OFFSET);  in bcm_kona_i2c_isr()
229 		       dev->base + TXFCR_OFFSET);  in bcm_kona_i2c_isr()
231 	writel(status & ~ISR_RESERVED_MASK, dev->base + ISR_OFFSET);  in bcm_kona_i2c_isr()
242 	while (readl(dev->base + ISR_OFFSET) & ISR_CMDBUSY_MASK)  in bcm_kona_i2c_wait_if_busy()
264 	writel(IER_I2C_INT_EN_MASK, dev->base + IER_OFFSET);  in bcm_kona_send_i2c_cmd()
276 	writel(0, dev->base + IER_OFFSET);  in bcm_kona_send_i2c_cmd()
300 	writel(IER_READ_COMPLETE_INT_MASK, dev->base + IER_OFFSET);  in bcm_kona_i2c_read_fifo_single()
305 		dev->base + RXFCR_OFFSET);  in bcm_kona_i2c_read_fifo_single()
311 	writel(0, dev->base + IER_OFFSET);  in bcm_kona_i2c_read_fifo_single()
320 		*buf = readl(dev->base + RXFIFORDOUT_OFFSET);  in bcm_kona_i2c_read_fifo_single()
368 	writel(ISR_SES_DONE_MASK, dev->base + ISR_OFFSET);  in bcm_kona_i2c_write_byte()
371 	writel(IER_I2C_INT_EN_MASK, dev->base + IER_OFFSET);  in bcm_kona_i2c_write_byte()
377 	writel(data, dev->base + DAT_OFFSET);  in bcm_kona_i2c_write_byte()
383 	writel(0, dev->base + IER_OFFSET);  in bcm_kona_i2c_write_byte()
390 	nak_received = readl(dev->base + CS_OFFSET) & CS_ACK_MASK ? 1 : 0;  in bcm_kona_i2c_write_byte()
413 	       dev->base + IER_OFFSET);  in bcm_kona_i2c_write_fifo_single()
420 		writel(buf[k], (dev->base + DAT_OFFSET));  in bcm_kona_i2c_write_fifo_single()
428 		fifo_status = readl(dev->base + FIFO_STATUS_OFFSET);  in bcm_kona_i2c_write_fifo_single()
432 	writel(0, dev->base + IER_OFFSET);  in bcm_kona_i2c_write_fifo_single()
435 	if (readl(dev->base + CS_OFFSET) & CS_ACK_MASK) {  in bcm_kona_i2c_write_fifo_single()
518 	writel(readl(dev->base + CLKEN_OFFSET) & ~CLKEN_AUTOSENSE_OFF_MASK,  in bcm_kona_i2c_enable_autosense()
519 	       dev->base + CLKEN_OFFSET);  in bcm_kona_i2c_enable_autosense()
524 	writel(readl(dev->base + HSTIM_OFFSET) & ~HSTIM_HS_MODE_MASK,  in bcm_kona_i2c_config_timing()
525 	       dev->base + HSTIM_OFFSET);  in bcm_kona_i2c_config_timing()
531 	       dev->base + TIM_OFFSET);  in bcm_kona_i2c_config_timing()
536 	       dev->base + CLKEN_OFFSET);  in bcm_kona_i2c_config_timing()
545 	       dev->base + TIM_OFFSET);  in bcm_kona_i2c_config_timing_hs()
550 	       dev->base + HSTIM_OFFSET);  in bcm_kona_i2c_config_timing_hs()
552 	writel(readl(dev->base + HSTIM_OFFSET) | HSTIM_HS_MODE_MASK,  in bcm_kona_i2c_config_timing_hs()
553 	       dev->base + HSTIM_OFFSET);  in bcm_kona_i2c_config_timing_hs()
620 	writel(0, dev->base + PADCTL_OFFSET);  in bcm_kona_i2c_xfer()
696 	writel(PADCTL_PAD_OUT_EN_MASK, dev->base + PADCTL_OFFSET);  in bcm_kona_i2c_xfer()
769 	dev->base = devm_ioremap_resource(dev->device, iomem);  in bcm_kona_i2c_probe()
770 	if (IS_ERR(dev->base))  in bcm_kona_i2c_probe()
805 	writel(0, dev->base + TOUT_OFFSET);  in bcm_kona_i2c_probe()
812 	       dev->base + TXFCR_OFFSET);  in bcm_kona_i2c_probe()
815 	writel(0, dev->base + IER_OFFSET);  in bcm_kona_i2c_probe()
824 	       dev->base + ISR_OFFSET);  in bcm_kona_i2c_probe()
846 	writel(PADCTL_PAD_OUT_EN_MASK, dev->base + PADCTL_OFFSET);  in bcm_kona_i2c_probe()