1/*
2 * Copyright (C) 2008, 2009 Provigent Ltd.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * Driver for the ARM PrimeCell(tm) General Purpose Input/Output (PL061)
9 *
10 * Data sheet: ARM DDI 0190B, September 2000
11 */
12#include <linux/spinlock.h>
13#include <linux/errno.h>
14#include <linux/module.h>
15#include <linux/io.h>
16#include <linux/ioport.h>
17#include <linux/irq.h>
18#include <linux/irqchip/chained_irq.h>
19#include <linux/bitops.h>
20#include <linux/gpio.h>
21#include <linux/device.h>
22#include <linux/amba/bus.h>
23#include <linux/amba/pl061.h>
24#include <linux/slab.h>
25#include <linux/pinctrl/consumer.h>
26#include <linux/pm.h>
27
28#define GPIODIR 0x400
29#define GPIOIS  0x404
30#define GPIOIBE 0x408
31#define GPIOIEV 0x40C
32#define GPIOIE  0x410
33#define GPIORIS 0x414
34#define GPIOMIS 0x418
35#define GPIOIC  0x41C
36
37#define PL061_GPIO_NR	8
38
39#ifdef CONFIG_PM
40struct pl061_context_save_regs {
41	u8 gpio_data;
42	u8 gpio_dir;
43	u8 gpio_is;
44	u8 gpio_ibe;
45	u8 gpio_iev;
46	u8 gpio_ie;
47};
48#endif
49
50struct pl061_gpio {
51	spinlock_t		lock;
52
53	void __iomem		*base;
54	struct gpio_chip	gc;
55
56#ifdef CONFIG_PM
57	struct pl061_context_save_regs csave_regs;
58#endif
59};
60
61static int pl061_direction_input(struct gpio_chip *gc, unsigned offset)
62{
63	struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
64	unsigned long flags;
65	unsigned char gpiodir;
66
67	if (offset >= gc->ngpio)
68		return -EINVAL;
69
70	spin_lock_irqsave(&chip->lock, flags);
71	gpiodir = readb(chip->base + GPIODIR);
72	gpiodir &= ~(BIT(offset));
73	writeb(gpiodir, chip->base + GPIODIR);
74	spin_unlock_irqrestore(&chip->lock, flags);
75
76	return 0;
77}
78
79static int pl061_direction_output(struct gpio_chip *gc, unsigned offset,
80		int value)
81{
82	struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
83	unsigned long flags;
84	unsigned char gpiodir;
85
86	if (offset >= gc->ngpio)
87		return -EINVAL;
88
89	spin_lock_irqsave(&chip->lock, flags);
90	writeb(!!value << offset, chip->base + (BIT(offset + 2)));
91	gpiodir = readb(chip->base + GPIODIR);
92	gpiodir |= BIT(offset);
93	writeb(gpiodir, chip->base + GPIODIR);
94
95	/*
96	 * gpio value is set again, because pl061 doesn't allow to set value of
97	 * a gpio pin before configuring it in OUT mode.
98	 */
99	writeb(!!value << offset, chip->base + (BIT(offset + 2)));
100	spin_unlock_irqrestore(&chip->lock, flags);
101
102	return 0;
103}
104
105static int pl061_get_value(struct gpio_chip *gc, unsigned offset)
106{
107	struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
108
109	return !!readb(chip->base + (BIT(offset + 2)));
110}
111
112static void pl061_set_value(struct gpio_chip *gc, unsigned offset, int value)
113{
114	struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
115
116	writeb(!!value << offset, chip->base + (BIT(offset + 2)));
117}
118
119static int pl061_irq_type(struct irq_data *d, unsigned trigger)
120{
121	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
122	struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
123	int offset = irqd_to_hwirq(d);
124	unsigned long flags;
125	u8 gpiois, gpioibe, gpioiev;
126	u8 bit = BIT(offset);
127
128	if (offset < 0 || offset >= PL061_GPIO_NR)
129		return -EINVAL;
130
131	if ((trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) &&
132	    (trigger & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)))
133	{
134		dev_err(gc->dev,
135			"trying to configure line %d for both level and edge "
136			"detection, choose one!\n",
137			offset);
138		return -EINVAL;
139	}
140
141
142	spin_lock_irqsave(&chip->lock, flags);
143
144	gpioiev = readb(chip->base + GPIOIEV);
145	gpiois = readb(chip->base + GPIOIS);
146	gpioibe = readb(chip->base + GPIOIBE);
147
148	if (trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
149		bool polarity = trigger & IRQ_TYPE_LEVEL_HIGH;
150
151		/* Disable edge detection */
152		gpioibe &= ~bit;
153		/* Enable level detection */
154		gpiois |= bit;
155		/* Select polarity */
156		if (polarity)
157			gpioiev |= bit;
158		else
159			gpioiev &= ~bit;
160		irq_set_handler_locked(d, handle_level_irq);
161		dev_dbg(gc->dev, "line %d: IRQ on %s level\n",
162			offset,
163			polarity ? "HIGH" : "LOW");
164	} else if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
165		/* Disable level detection */
166		gpiois &= ~bit;
167		/* Select both edges, setting this makes GPIOEV be ignored */
168		gpioibe |= bit;
169		irq_set_handler_locked(d, handle_edge_irq);
170		dev_dbg(gc->dev, "line %d: IRQ on both edges\n", offset);
171	} else if ((trigger & IRQ_TYPE_EDGE_RISING) ||
172		   (trigger & IRQ_TYPE_EDGE_FALLING)) {
173		bool rising = trigger & IRQ_TYPE_EDGE_RISING;
174
175		/* Disable level detection */
176		gpiois &= ~bit;
177		/* Clear detection on both edges */
178		gpioibe &= ~bit;
179		/* Select edge */
180		if (rising)
181			gpioiev |= bit;
182		else
183			gpioiev &= ~bit;
184		irq_set_handler_locked(d, handle_edge_irq);
185		dev_dbg(gc->dev, "line %d: IRQ on %s edge\n",
186			offset,
187			rising ? "RISING" : "FALLING");
188	} else {
189		/* No trigger: disable everything */
190		gpiois &= ~bit;
191		gpioibe &= ~bit;
192		gpioiev &= ~bit;
193		irq_set_handler_locked(d, handle_bad_irq);
194		dev_warn(gc->dev, "no trigger selected for line %d\n",
195			 offset);
196	}
197
198	writeb(gpiois, chip->base + GPIOIS);
199	writeb(gpioibe, chip->base + GPIOIBE);
200	writeb(gpioiev, chip->base + GPIOIEV);
201
202	spin_unlock_irqrestore(&chip->lock, flags);
203
204	return 0;
205}
206
207static void pl061_irq_handler(struct irq_desc *desc)
208{
209	unsigned long pending;
210	int offset;
211	struct gpio_chip *gc = irq_desc_get_handler_data(desc);
212	struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
213	struct irq_chip *irqchip = irq_desc_get_chip(desc);
214
215	chained_irq_enter(irqchip, desc);
216
217	pending = readb(chip->base + GPIOMIS);
218	if (pending) {
219		for_each_set_bit(offset, &pending, PL061_GPIO_NR)
220			generic_handle_irq(irq_find_mapping(gc->irqdomain,
221							    offset));
222	}
223
224	chained_irq_exit(irqchip, desc);
225}
226
227static void pl061_irq_mask(struct irq_data *d)
228{
229	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
230	struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
231	u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR);
232	u8 gpioie;
233
234	spin_lock(&chip->lock);
235	gpioie = readb(chip->base + GPIOIE) & ~mask;
236	writeb(gpioie, chip->base + GPIOIE);
237	spin_unlock(&chip->lock);
238}
239
240static void pl061_irq_unmask(struct irq_data *d)
241{
242	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
243	struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
244	u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR);
245	u8 gpioie;
246
247	spin_lock(&chip->lock);
248	gpioie = readb(chip->base + GPIOIE) | mask;
249	writeb(gpioie, chip->base + GPIOIE);
250	spin_unlock(&chip->lock);
251}
252
253/**
254 * pl061_irq_ack() - ACK an edge IRQ
255 * @d: IRQ data for this IRQ
256 *
257 * This gets called from the edge IRQ handler to ACK the edge IRQ
258 * in the GPIOIC (interrupt-clear) register. For level IRQs this is
259 * not needed: these go away when the level signal goes away.
260 */
261static void pl061_irq_ack(struct irq_data *d)
262{
263	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
264	struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
265	u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR);
266
267	spin_lock(&chip->lock);
268	writeb(mask, chip->base + GPIOIC);
269	spin_unlock(&chip->lock);
270}
271
272static struct irq_chip pl061_irqchip = {
273	.name		= "pl061",
274	.irq_ack	= pl061_irq_ack,
275	.irq_mask	= pl061_irq_mask,
276	.irq_unmask	= pl061_irq_unmask,
277	.irq_set_type	= pl061_irq_type,
278};
279
280static int pl061_probe(struct amba_device *adev, const struct amba_id *id)
281{
282	struct device *dev = &adev->dev;
283	struct pl061_platform_data *pdata = dev_get_platdata(dev);
284	struct pl061_gpio *chip;
285	int ret, irq, i, irq_base;
286
287	chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
288	if (chip == NULL)
289		return -ENOMEM;
290
291	if (pdata) {
292		chip->gc.base = pdata->gpio_base;
293		irq_base = pdata->irq_base;
294		if (irq_base <= 0) {
295			dev_err(&adev->dev, "invalid IRQ base in pdata\n");
296			return -ENODEV;
297		}
298	} else {
299		chip->gc.base = -1;
300		irq_base = 0;
301	}
302
303	chip->base = devm_ioremap_resource(dev, &adev->res);
304	if (IS_ERR(chip->base))
305		return PTR_ERR(chip->base);
306
307	spin_lock_init(&chip->lock);
308	if (of_property_read_bool(dev->of_node, "gpio-ranges")) {
309		chip->gc.request = gpiochip_generic_request;
310		chip->gc.free = gpiochip_generic_free;
311	}
312
313	chip->gc.direction_input = pl061_direction_input;
314	chip->gc.direction_output = pl061_direction_output;
315	chip->gc.get = pl061_get_value;
316	chip->gc.set = pl061_set_value;
317	chip->gc.ngpio = PL061_GPIO_NR;
318	chip->gc.label = dev_name(dev);
319	chip->gc.dev = dev;
320	chip->gc.owner = THIS_MODULE;
321
322	ret = gpiochip_add(&chip->gc);
323	if (ret)
324		return ret;
325
326	/*
327	 * irq_chip support
328	 */
329	writeb(0, chip->base + GPIOIE); /* disable irqs */
330	irq = adev->irq[0];
331	if (irq < 0) {
332		dev_err(&adev->dev, "invalid IRQ\n");
333		return -ENODEV;
334	}
335
336	ret = gpiochip_irqchip_add(&chip->gc, &pl061_irqchip,
337				   irq_base, handle_bad_irq,
338				   IRQ_TYPE_NONE);
339	if (ret) {
340		dev_info(&adev->dev, "could not add irqchip\n");
341		return ret;
342	}
343	gpiochip_set_chained_irqchip(&chip->gc, &pl061_irqchip,
344				     irq, pl061_irq_handler);
345
346	for (i = 0; i < PL061_GPIO_NR; i++) {
347		if (pdata) {
348			if (pdata->directions & (BIT(i)))
349				pl061_direction_output(&chip->gc, i,
350						pdata->values & (BIT(i)));
351			else
352				pl061_direction_input(&chip->gc, i);
353		}
354	}
355
356	amba_set_drvdata(adev, chip);
357	dev_info(&adev->dev, "PL061 GPIO chip @%pa registered\n",
358		 &adev->res.start);
359
360	return 0;
361}
362
363#ifdef CONFIG_PM
364static int pl061_suspend(struct device *dev)
365{
366	struct pl061_gpio *chip = dev_get_drvdata(dev);
367	int offset;
368
369	chip->csave_regs.gpio_data = 0;
370	chip->csave_regs.gpio_dir = readb(chip->base + GPIODIR);
371	chip->csave_regs.gpio_is = readb(chip->base + GPIOIS);
372	chip->csave_regs.gpio_ibe = readb(chip->base + GPIOIBE);
373	chip->csave_regs.gpio_iev = readb(chip->base + GPIOIEV);
374	chip->csave_regs.gpio_ie = readb(chip->base + GPIOIE);
375
376	for (offset = 0; offset < PL061_GPIO_NR; offset++) {
377		if (chip->csave_regs.gpio_dir & (BIT(offset)))
378			chip->csave_regs.gpio_data |=
379				pl061_get_value(&chip->gc, offset) << offset;
380	}
381
382	return 0;
383}
384
385static int pl061_resume(struct device *dev)
386{
387	struct pl061_gpio *chip = dev_get_drvdata(dev);
388	int offset;
389
390	for (offset = 0; offset < PL061_GPIO_NR; offset++) {
391		if (chip->csave_regs.gpio_dir & (BIT(offset)))
392			pl061_direction_output(&chip->gc, offset,
393					chip->csave_regs.gpio_data &
394					(BIT(offset)));
395		else
396			pl061_direction_input(&chip->gc, offset);
397	}
398
399	writeb(chip->csave_regs.gpio_is, chip->base + GPIOIS);
400	writeb(chip->csave_regs.gpio_ibe, chip->base + GPIOIBE);
401	writeb(chip->csave_regs.gpio_iev, chip->base + GPIOIEV);
402	writeb(chip->csave_regs.gpio_ie, chip->base + GPIOIE);
403
404	return 0;
405}
406
407static const struct dev_pm_ops pl061_dev_pm_ops = {
408	.suspend = pl061_suspend,
409	.resume = pl061_resume,
410	.freeze = pl061_suspend,
411	.restore = pl061_resume,
412};
413#endif
414
415static struct amba_id pl061_ids[] = {
416	{
417		.id	= 0x00041061,
418		.mask	= 0x000fffff,
419	},
420	{ 0, 0 },
421};
422
423MODULE_DEVICE_TABLE(amba, pl061_ids);
424
425static struct amba_driver pl061_gpio_driver = {
426	.drv = {
427		.name	= "pl061_gpio",
428#ifdef CONFIG_PM
429		.pm	= &pl061_dev_pm_ops,
430#endif
431	},
432	.id_table	= pl061_ids,
433	.probe		= pl061_probe,
434};
435
436static int __init pl061_gpio_init(void)
437{
438	return amba_driver_register(&pl061_gpio_driver);
439}
440module_init(pl061_gpio_init);
441
442MODULE_AUTHOR("Baruch Siach <baruch@tkos.co.il>");
443MODULE_DESCRIPTION("PL061 GPIO driver");
444MODULE_LICENSE("GPL");
445